LVT22V10-DD [PHILIPS]
OT PLD, 10ns, PAL-Type, BICMOS, PDSO24,;
| 型号： | LVT22V10-DD |
| 厂家： | 
PHILIPS SEMICONDUCTORS |
| 描述： | OT PLD, 10ns, PAL-Type, BICMOS, PDSO24, 时钟 信息通信管理 光电二极管 可编程逻辑 |
| 文件： | 总20页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
LVT22V10
3V high speed, universal PLD device
Product specification
1998 Feb 10
Supersedes data of 1996 Mar 12
IC13 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
FEATURES
PIN CONFIGURATIONS
• Fastest 3V PLD
D and N Packages
• Supports 3/5V mixed systems
• Low ground bounce (<1.1V worst case)
• Live insertion/extraction permitted
1
2
24
23
22
21
20
19
18
17
16
15
14
13
I0/CLK
I1
V
CC
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
I11
3
I2
• Bus-hold data inputs eliminate the need for external pull-up
4
I3
resistors to hold unused inputs
5
I4
• Metastable hardened device
• High output drive capability: 32mA/–16mA
6
I5
7
I6
• Varied product term distribution with up to 16 product terms per
8
I7
output for complex functions
9
I8
• Programmable output polarity
• Available in 300 mil-wide 24-pin Plastic Small Outline Package
10
11
12
I9
I10
• Design support provided for third party CAD development and
GND
programming hardware
N = Plastic Dual In-Line Package (300mil-wide)
D = Plastic Small Outline Large (300mil-wide) Package
DESCRIPTION
The LVT22V10 is a versatile PAL device fabricated on the Philips
BiCMOS QUBiC process.
A Package (standard)
CLK/
I0
I2 I1
NC
1
V
F9 F8
CC
The QUBiC process produces very high speed 3V devices (7.5ns)
which have excellent noise characteristics. Ground bounce of an
output held low while the remaining 9 outputs switch from high to
4
3
2
28 27 26
I3
I4
5
6
25
24
23
22
F7
F6
low is typically less than 0.7V. V bounce of an output held high
CC
while the remaining 9 outputs switch from low to high is typically less
than 1.0V.
I5
7
F5
NC
NC
I6
8
The LVT22V10 was designed to support mixed 3/5V systems. The
inputs are capable of handling 7V while the outputs can be pulled up
to 7V.
9
21 F4
GND
I8
10
11
20
19
F3
F2
The designer can interface directly from 5V outputs (CMOS full rail
or totem pole) to a 3V LVT input. A 3V LVT output can drive a 5V
TTL input directly, or in the case of a CMOS input, the LVT output
can interface with the use of an external pull-up resistor. Finally, no
external pull-up resistors are needed on unused input pins due to a
bus-hold data structure designed into the LVT input.
12 13 14 15 16 17 18
I9 I10 GND NC I11 F0 F1
A = Plastic Leaded Chip Carrier
A Package (evolutionary)
The LVT22V10 has been designed with high drive outputs (32mA
sink and 16mA source currents), which allows for direct connection
to a backplane bus. This feature eliminates the need for additional,
standalone bus drivers, which are traditionally required to boost the
drive of a standard PLDs.
CLK/
I0
I2 I1
V
V
F9 F8
CC CC
4
3
2
1
28 27 26
I3
I4
5
6
25
24
23
22
F7
F6
The LVT22V10 outputs are designed to support Live
Insertion/Extraction into powered up systems. The output is
I5
7
F5
GND
I6
GND
8
specially designed so that during V ramp, the output remains
CC
9
21 F4
3-Stated until V [ 2.1V. At that time the outputs become fully
CC
functional depending upon device inputs. (See DC Electrical
I7
10
11
20
19
F3
F2
Characteristics, Symbol I
Page 5). In addition when an
PU/PD,
I8
LVT22V10 output is tied to a 5V bus, no bus current is loaded.
12 13 14 15 16 17 18
I9 I10 GNDGND I11 F0 F1
The LVT22V10 uses the familiar AND/OR logic array structure,
which allows direct implementation of sum-of-products equations.
A = Plastic Leaded Chip Carrier
This device has a programmable AND array which drives a fixed OR
array. The OR sum of products feeds an “Output Macro Cell” (OMC)
which can be individually configured as a dedicated input, a
SP00436
combinatorial output, or a registered output with internal feedback.
PAL is a registered trademark of Advanced Micro Devices, Inc.
2
1998 Feb 10
853-1759 18947
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
ORDERING INFORMATION
PACKAGES
ORDER CODE
DWG NUMBER
24-Pin Plastic DIP (300mil)
28-Pin PLCC (standard pinout)
28-Pin PLCC (evolutionary pinout)
24-Pin Plastic SOL
LVT22V10-7N (8.0ns device)
LVT22V10B7A (7.5ns device)
LVT22V10-7A (7.5ns device)
LVT22V10-7D (8.0ns device)
SOT222-1
SOT261-3
SOT261-3
SOT137-1
PIN LABEL DESCRIPTIONS
THERMAL RATINGS
SYMBOL
I1 – I11
F0 – F9
CLK/I0
DESCRIPTION
TEMPERATURE
Dedicated Input
Maximum junction
150°C
75°C
75°C
Macro Cell Input/Output
Clock Input/Dedicated Input
Supply Voltage
Maximum ambient
Allowable thermal rise ambient to junction
V
CC
OPERATING RANGES
GND
NC
Ground
RATINGS
No Connection
SYMBOL
PARAMETER
UNIT
MIN
MAX
V
Supply voltage
+3.0
0
+3.6
V
DC
CC
Operating free-air
temperature
T
amb
+75
°C
1
ABSOLUTE MAXIMUM RATINGS
RATINGS
SYMBOL
PARAMETER
UNIT
MIN
MAX
+4.6
7
2
V
V
V
Supply voltage
–0.5
–0.5
–0.5
–30
V
DC
V
DC
V
DC
CC
2
Input voltage
IN
3
Output voltage
5.5
OUT
I
I
Input currents
+30
+100
+150
mA
mA
°C
IN
OUT
Output currents
T
stg
Storage temperature range
–65
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at
these or any other condition above those indicated in the operational and programming specification of the device is not implied.
2. Except in programming mode.
3. Outputs can be pulled up to 7V via external pull-up resistor.
3
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
TEST CIRCUIT AND WAVEFORMS
6.0V
V
CC
t
W
AMP (V)
90%
OPEN
90%
GND
V
V
M
M
NEGATIVE
PULSE
R
R
L
V
V
OUT
IN
10%
10%
90%
PULSE
GENERATOR
D.U.T.
0V
t
t
(t )
t
t
(t )
R
THL
TLH
F
TLH
R
T
C
L
L
(t
)
(t )
F
R
THL
AMP (V)
90%
M
Test Circuit for 3-State Outputs
SWITCH POSITION
POSITIVE
PULSE
V
V
M
10%
10%
t
W
0V
TEST
/t
SWITCH
Open
6V
V
= 1.5V
M
t
PLH PHL
Input Pulse Definition
t
/t
PLZ PZL
t
/t
GND
PHZ PZH
INPUT PULSE REQUIREMENTS
Amplitude Rep. Rate
3.0V 10MHz
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
FAMILY
L
t
t
t
W
R
F
C = Load capacitance includes jig and probe capacitance;
L
LVT
500ns
2.5ns
2.5ns
see AC CHARACTERISTICS for value.
R = Termination resistance should be equal to Z
T
of pulse
OUT
generators.
SP00385
4
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
DC ELECTRICAL CHARACTERISTICS
Over operating ranges.
LIMITS
MIN MAX
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Input voltage
V
IL
V
IH
V
I
Low
V
= MIN
0.8
V
V
V
CC
High
Clamp
V
= MAX
2.0
CC
V
CC
= MIN, I = –18mA
–1.2
IN
Output voltage
V
CC
V
CC
V
CC
V
CC
= MIN to MAX, V = V or V
I
I
I
I
I
I
= –100 µA
= –16mA
= –5.5 mA
= 100µA
= 32 mA
= 16 mA
V –0.2
CC
V
V
V
V
V
V
I
IH
IL
OH
OH
OH
OL
OL
OL
2.0
2.4
V
OH
V
OL
High-level output voltage
Low-level output voltage
= MIN, V = V or V
IL
I
IH
= MIN to MAX, V = V or V
IL
0.2
0.5
0.4
I
IH
= MIN, V = V or V
I
IH
IL
Input current
I
I
I
I
I
I
I
I
Low
V
= MAX, V = 0.0V
–10
10
µA
µA
µA
µA
µA
µA
µA
µA
IL
CC
IN
High
V
= MAX, V = V
IN CC
IH
CC
CC
CC
Max input current
Pin 1 (program)
V
V
= MAX, V = 5.5V
10
I
IN
= MAX, V = 5.5V
20
I
IN
2
Bus hold low sustaining current
V
= 3V, V = 0.8V
75
–75
500
–500
BHL
BHH
BHLO
BHHO
CC
I
3
Bus hold high sustaining current
V
= 3V, V = 2V
CC I
4, 9
Bus hold low overdrive current
V
= 3.6V
= 3.6V
CC
5, 9
Bus hold high overdrive current
V
CC
Output current
I
Output off current
Current into an output in high state
when V > V
V
CC
= 0V, V or V = 0 to 4.5V
±10
µA
µA
OFF
EX
I
O
I
V
O
= 5.5V, V = 3.0V
±100
CC
O
CC
Power-up/down 3-State output
current
V
<1.2V; V = 0.5V to V
;
CC
I
O
CC
I
100
µA
PU/PD
8
V = GND or V ; OE/OE = X
CC
V
CC
= MAX
6
I
I
I
I
Output leakage
V
= V or V , V = 5.5V
OUT
10
µA
OZH
OZL
SC
IN
IL
IH
6
Output leakage
V
= V or V , V =0V
OUT
–10
–220
170
TYP
µA
mA
IN
IL
IH
7
Short circuit
V
OUT
= 0.5V
–30
V
CC
supply current
V
CC
= 3.6V, Outputs enabled, V = V or GND; I = 0
mA
CC
I
CC
O
Ground/V Bounce
MIN
MAX UNIT
CC
V
= 3.0V, 25°C,
CC
V
Maximum dynamic V
2.2
2.3
V
OHV
OLP
OH
OL
C = 50pF (including jig capacitance)
L
LVT22V10-7
LVT22V10B7
0.7
1.0
1.1
1.1
V
V
V
CC
= 3.3V, 25°C, C = 50pF
L
(including jig capacitance)
V
Maximum dynamic V
NOTES:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. The bus hold circuit can sink at least the minimum low sustaining current at V MAX. I should be measured after lowering V to GND
IL
BHL
IN
and then raising it to V MAX.
IL
3. The bus hold circuit can source at least the minimum high sustaining current at V MIN. I
should be measured after raising V to V
IN CC
IH
BHL
and then lowering it to V
IH MIN.
4. An external driver must source at least I
to switch this node from low to high.
to switch this node from high to low.
BHLO
5. An external driver must sink at least I
BHHO
6. I/O pin leakage is the worst case of I
or I (where X = H or L).
OZX
IX
7. No more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. V
= 0.5V has been
OUT
chosen to avoid test problems caused by tester ground degradation.
8. This parameter is valid for any V between 0V and 1.2 V with a transition time up to 10 mS. From V = 1.2 to V = 3.3V ±0.3V a
CC
CC
CC
transition time of 100 µS is permitted. X = Don’t care.
9. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where input
current may be affected.
5
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
AC ELECTRICAL CHARACTERISTICS
Over commercial operating temperature range.
LIMITS
TYP
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MAX
MIN
Active-LOW
Active-HIGH
Active-LOW
Active-HIGH
7.5
7.5
8.0
8.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
Input or feedback to non-registered output
PLCC package
t
PD
Input or feedback to non-registered output
DIP and SOL packages
t
t
t
t
t
t
t
t
t
t
Setup time from input, feedback or SP to Clock
5.5
0
S
Hold time
H
Clock to output
5.0
3.0
CO
CF
3
Clock to feedback
Asynchronous Reset to registered output
Asynchronous Reset width
12.0
AR
5.0
5.0
5.0
3.0
3.0
ARW
ARR
SPR
WL
WH
Asynchronous Reset recovery time
Synchronous Preset recovery time
Width of Clock LOW
Width of Clock HIGH
Maximum frequency;
External feedback 1/(t + t
95
MHz
MHz
4
)
CO
S
f
MAX
Maximum frequency;
Internal feedback 1/(t + t
118
4
)
CF
S
5
Input to Output Enable
8.5
8.5
ns
ns
t
t
EA
5
Input to Output Disable
ER
6
Capacitance
Input Capacitance (Pin 1)
Input Capacitance (Others)
Output Capacitance
V
V
= 2.0V
6
6
8
pF
pF
pF
IN
V
T
amb
f = 1MHz
= 3.3V,
= 25°C,
CC
C
C
IN
= 2.0V
= 2.0V
IN
V
OUT
OUT
NOTES:
1. Test Conditions: R = 500Ω, R =500Ω
1
2
2. t
is tested with switch S open and C = 50pF (including jig capacitance). V = 3V, V = 0V, V = 1.5V.
PD
1 L IH IL T
3. Calculated from measured f
internal.
MAX
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency
may be affected.
5. For 3-State output; output enable times are tested with C = 50pF to the 1.5V level, and S is open for high-impedance to High tests and
L
1
closed for high-impedance to Low tests. Output disable times are tested with C = 5pF. High-to-High impedance tests are made to an output
L
voltage of V = (V – 0.3V) with S open, and Low-to-High impedance tests are made to the V = (V + 0.3V) level with S closed.
T
OH
1
T
OL
1
6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
6
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
product terms. Programmable polarity allows Boolean expressions
to be written in their most compact form (true or inverted), and the
output can still be of the desired polarity. It can also save
“DeMorganizing” efforts.
PRODUCT FEATURES
Low Ground Bounce
The Philips Semiconductors BiCMOS QUBiC process results in
exceptional noise immunity. Ground bounce is noise that is
generated on a non-switching active low output when other outputs
on the device switch from high to low. The worst case condition
occurs when 9 outputs simultaneously switch from high to low and
the tenth output is active low. The ground bounce on this tenth
output for Philips LVT22V10 is typically less than 0.7V.
Selection is controlled by programmable bit S in the Output Macro
0
Cell, and affects both registered and combinatorial outputs.
Selection is automatic, based on the design specification and pin
definitions. If the pin definition and output equation have the same
polarity, the output is programmed to be Active-HIGH (S = 1).
0
Preset/Reset
V
CC
Bounce
CC
bounce occurs on a non-switching active high output when
For initialization, the LVT22V10 has additional Preset and Reset
product terms. These terms are connected to all registered outputs.
When the Synchronous Preset (SP) product term is asserted high,
the output registers will be loaded with a HIGH on the next
LOW-to-HIGH clock transition. When the Asynchronous Reset (AR)
product term is asserted high, the output registers will be
immediately loaded with a LOW, independent of the clock.
V
other outputs are making a low to high transition. This specification
is important to consider in 3.3V designs because of the reduced
noise margin between V and V of only 1.3V relative to the
CC
OH
traditional 5V system’s noise margin of 3V. The Philips LVT22V10
bounce of an output held high while the remaining 9 outputs
V
CC
switch from low to high is typically less than 1.0V in magnitude.
Note that Preset and Reset control the flip-flop, not the output pin.
The output level is determined by the output polarity selected.
Live Insertion/Extraction Capability
There are some inherent problems associated with inserting or
extracting an unpowered module from a powered-up, active system.
The LVT22V10 outputs have been designed such that any chance of
bus contention, glitching or clamping is eliminated.
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable system
initialization. Outputs of the LVT22V10 will depend on the
programmed output polarity. The V rise must be monotonic and
the reset delay time is 1–10µs maximum.
CC
Detailed information on this feature is provided in an application note
AN051: Philips PLDs Support Live Insertion Applications.
Security Fuse
Bus Hold Input Structure
After programming and verification, LVT22V10 designs can be
secured by programming the security fuse link. Once programmed,
this fuse defeats readback of the internal programmed pattern by a
device programmer, securing proprietary designs from competitors.
When the security fuse is programmed, the array will read as if
every fuse is programmed.
Bus Hold is a feature that maintains the input state of the device by
incorporating a weak latch into the input structure. This latch
maintains the input state until a minimum level of current (called the
overdrive current) is supplied to change the input state. This is
useful in bus applications where the bus is placed into a high
impedance state. The LVT22V10’s inputs, in this high impedance
situation, maintain valid logic levels until the bus is actively driven to
a new state.
Quality and Testability
The LVT22V10 offers a very high level of built-in quality. Extra
programmable fuses provide a means of verifying performance of all
AC and DC parameters. In addition, this verifies programmability
and functionality of the device to provide the highest programming
and post-programming functional yields.
Improved Fuse Verification Circuitry Increases
Reliability
Philips has developed a new means of testing the integrity of fuses,
both blown and intact fuses, which insures that all the fuses have
been correctly programmed and that each and every fuse – whether
“blown” or “intact” – is at the appropriate and optimal fuse
resistance. This dual verify scheme represents a significant
improvement over single reference voltage comparisons schemes
that have been used for bipolar devices since the late 1980s.
Detailed information on this feature is provided in an application note
entitled Dual Verify Technique Increases Reliability of PLDs.
Technology
The BiCMOS LVT22V10 is fabricated with the Philips
Semiconductors process known as QUBiC. QUBiC combines an
advanced, state-of-the-art 1.0µm (drawn feature size) CMOS
process with an ultra fast bipolar process to achieve superior speed
and drive capabilities. QUBiC incorporates three layers of Al/Cu
interconnects for reduced chip size, and our proven Ti-W fuse
technology ensures highest programming yields.
Programmable 3-stage Outputs
Each output has a 3-Stage output buffer with 3-State control. A
product term controls the buffer, allowing enable and disable to be a
function of any product of device inputs or output feedback. The
combinatorial output provides a bidirectional I/O pin, and may be
configured as a dedicated input if the buffer is always disabled.
Programming
The LVT22V10 is fully supported by industry standard (JEDEC
compatible) PLD CAD tools, including Philips Semiconductors
SNAP design software package. ABEL CUPL and PALASM 90
design software packages also support the LVT22V10 architecture.
All packages allow Boolean and state equation entry formats, SNAP,
ABEL and CUPL also accept, as input, schematic capture format.
Programmable Output Polarity
The polarity of each macro cell output can be Active-HIGH or
Active-LOW, either to match output signal needs or to reduce
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
PALASM is a registered trademark of AMD Corp.
7
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
3. Apply the desired value (V /V ) to all registered output pins.
Output Register Preload
ILP IHP
Leave combinatorial output pins floating.
The register on the LVT22V10 can be preloaded from the output
pins to facilitate functional testing of complex state machine designs.
This feature allows direct loading of arbitrary states, making it
unnecessary to cycle through long test vector sequences to reach a
desired state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper recovery. The
procedure for preloading follows:
4. Clock Pin 1 from V to V
.
IHP
ILP
5. Remove V /V
from all registered output pins.
ILP IHP
6. Lower pin 2 or 3 to V
.
ILP
7. Enable the output registers according to the programmed
pattern.
8. Verify V /V at all registered output pins. Note that the output
OL OH
1. Raise V to 3.3V ± 0.3V.
CC
pin signal will depend on the output polarity.
2. Set pin 2 or 3 to V to disable outputs and enable preload.
HH
PRELOAD SET-UP
LIMITS
SYMBOL
PARAMETER
MIN
9.5
0
REC
9.5
0
MAX
10
UNIT
V
V
HH
V
ILP
V
IHP
Super-level input voltage
Low-level input voltage
High-level input voltage
Delay time
0.8
V
2.4
100
100
3.3
200
3.6
V
t
D
1000
ns
ns
t
I/O
I/O valid after Pin 2 or 3 drops from V to V
ILP
HH
V
V
HH
ILP
PINS 2, 3
t
I/O
t
D
t
D
V
V
V
V
IHP
OH
OL
REGISTERED
OUTPUTS
DATA IN
DATA OUT
ILP
t
D
t
D
V
V
IHP
ILP
CLOCK
t
D
SP00373
Output Register Preload Waveform
8
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
LVT22V10 TIMING CHARACTERIZATION
Normalized t vs Temperature
(V = 3.3V, output capacitance = 50pF, 5outputs switching)
Normalized t vs Temperature
PD
(V = 3.3V, output capacitance = 50pF, 5 outputs switching)
CO
CC
CC
1.05
1.00
0.95
0.90
1.10
1.00
0.90
RISE
RISE
FALL
FALL
0.85
0.80
0
25
50
75
0
25
50
75
Temperature (°C)
Temperature (°C)
Normalized t vs V
(temp = 25°C, output capacitance = 50pF, 5 outputs switching)
Normalized t vs V
PD CC
(temp = 25°C, output capacitance = 50pF, 5 outputs switching)
CO
CC
1.20
1.20
1.10
1.00
1.10
1.00
0.90
0.90
RISE
RISE
FALL
FALL
0.80
0.80
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Supply Voltage (V)
Supply Voltage (V)
The timing characterization represents the average values of a representative sample for each parameter.
The data can be used to derate the MAX AC CHARACTERIZATION based upon the specific user design.
Philips guarantees the MAX AC CHARACTERIZATION specifications.
SP00386
9
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
LVT22V10 TIMING CHARACTERIZATION
Delta t vs Number of Outputs Switching
(V = 3.3V, temp = 25°C, output capacitance = 50pF)
Delta t vs Number of Outputs Switching
PD
(V = 3.3V, temp = 25°C, output capacitance = 50pF)
CO
CC
CC
100
0.10
0.00
0
–0.10
–0.20
–100
–0.30
–0.40
–200
–300
–0.50
–0.60
–400
–500
–0.70
–0.80
–0.90
–600
–700
RISE
FALL
RISE
FALL
–1.00
–1.10
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
Number of Outputs Switching
Number of Outputs Switching
Delta t vs Output Capacitance
(V = 3.3V, temp = 25°C, 5 Outputs Switching)
Delta t vs Output Capacitance
PD
(V = 3.3V, temp = 25°C, 5 Outputs Switching)
CO
CC
CC
7.00
6.00
5.00
4.00
3.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
2.00
1.00
0.00
–1.00
–2.00
RISE
FALL
RISE
FALL
–1.00
–2.00
10
50
100
200
400
10
50
100
200
400
Output Capacitance
Output Capacitance
The timing characterization represents the average values of a representative sample for each parameter.
The data can be used to derate the MAX AC CHARACTERIZATION based upon the specific user design.
Philips guarantees the MAX AC CHARACTERIZATION specifications.
SP00387
10
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
LOGIC DIAGRAM
CLK/I0
1
24
V
CC
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
AR
0
1
1
1
0
0
0
1
0
1
AR
D
23 F9
22 F8
21 F7
20 F6
19 F5
18 F4
17 F3
16 F2
15 F1
14 F0
Q
Q
9
SP
0
1
10
20
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
0
1
I1
I2
I3
I4
I5
I6
I7
I8
2
3
4
5
6
7
8
9
21
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
33
34
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
48
49
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
65
66
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
82
83
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
97
98
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
110
0
1
111
121
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
0
1
122
130
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
0
1
I9 10
I10 11
SP
131
13 I11
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
GND 12
NOTE:
Programmable connection.
SP00059
11
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
FUNCTIONAL DIAGRAM
CLK/I0
I1 – I11
1
11
PROGRAMMABLE AND ARRAY
(44 × 132)
8
10
12
14
16
16
14
12
10
8
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
SP00060A
Figure 1. Functional Diagram
registered output or combinatorial I/O, Active-HIGH or Active-LOW
(see Figure 2). The configuration choice is made according to the
user’s design specification and corresponding programming of the
FUNCTIONAL DESCRIPTION
The LVT22V10 allows the systems engineer to implement the
design on-chip, by opening fuse links to configure AND and OR
gates within the device, according to the desired logic function.
configuration bits S –S . Multiplexer controls are connected to
0
1
ground (0) through a programmable fuse link, selecting the “0” path
through the multiplexer. Programming the fuse disconnects the
Product terms with all fuses opened assume the logical HIGH state;
product terms connected to both True and Complement of any
single input assume the logical LOW state.
control line from GND and it floats to V (1), selecting the “1” path.
CC
The LVT22V10 has 12 inputs and 10 I/O Macro Cells (Figure 1). The
Macro Cell allows one of four potential output configurations,
12
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
OUTPUT MACRO CELL
S
1
S
0
OUTPUT CONFIGURATION
1
1
0
0
0
1
0
1
0
0
1
1
0
Registered/Active-LOW
Registered/Active-HIGH
Combinatorial/Active-LOW
Combinatorial/Active-HIGH
AR
1
0
1
D
Q
F
CLK
Q
0 = Unprogrammed fuse
1 = Programmed fuse
SP
S
1
S
0
0
1
SP00375
Figure 2. Output Macro Cell Logic Diagram
S
S
= 0
= 0
S
S
= 0
= 1
0
1
0
1
AR
D
Q
F
F
CLK
Q
SP
a. Registered/Active-LOW
c. Combinatorial/Active-LOW
S
S
= 1
= 0
S
S
= 1
= 1
0
1
0
1
AR
D
Q
Q
F
F
CLK
SP
b. Registered/Active-HIGH
d. Combinatorial/Active-HIGH
SP00376
Figure 3. Output Macro Cell Configurations
Registered Output Configuration
Variable Input/Output Pin Ratio
Each Macro Cell of the LVT22V10 includes a D-type flip-flop for data
storage and synchronization. The flip-flop is loaded on the
LOW-to-HIGH transition of the clock input. In the registered
The LVT22V10 has twelve dedicated input lines, and each Macro
Cell output can be an I/O pin. Buffers for device inputs have
complementary outputs to provide user-programmable input signal
polarity.
configuration (S = 0), the array feedback is from Q of the flip-flop.
1
Combinatorial I/O Configuration
Any Macro Cell can be configured as combinatorial by selecting the
multiplexer path that bypasses the flip-flop (S = 1). In the
1
combinatorial configuration, the feedback is from the pin.
13
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
metastable event occurs within the flop, the only outward
manifestation of the event will be an increased clock-to-Q delay.
This delay is a function of the metastability characteristics of the
INTERFACING IN MIXED 3V/5V SYSTEMS
3V Logic Driving 5V Logic
device, defined by τ and T as described below. Since the outputs
O
The LVT family has outputs that swing virtually between the power
supply rails, thereby allowing direct interfacing with TTL switching
levels.
never glitch, oscillate, or remain in the linear region, the only
metastable failure that can propagate further into the system is when
the next flip-flop in the system samples the LVT22V10’s output at
precisely the same time it is making a logic transition. By allowing
sufficient time for any increased clock-to-Q delay, propagation of
metastable failures can be avoided. The following design example
illustrates this concept.
When interfacing the outputs of any of our 3V logic ICs with
standard TTL-level logic inputs (bipolar or CMOS HCT), the output
levels from the 3V logic are sufficient to directly drive the 5V logic.
When driving CMOS-level devices (such as HC or AC), the output
voltage from the 3V logic is insufficient to ensure reliable operation.
This problem can be easily resolved by using a pull-up resistor at
the interface.
Design Example
Suppose a designer wants to use the LVT22V10 for synchronizing
asynchronous data that is arriving at 2MHz (as measured by a
frequency counter), in a 3.3V system that has a clock frequency of
33MHz, at an ambient temperature of 25°C. She has decided that
she would like to sample the output of the LVT22V10 15ns after the
clock edge to ensure that any clock-to-Q delays that were the result
of the LVT22V10 internal metastability resolution circuitry have
completed and the outputs have transitioned. The MTBF for this
situation can be calculated by using the equation below:
5V Logic Driving 3V Logic
Since the LVT ICs do not have protection diodes between their
inputs and V , the inputs of these devices can therefore withstand
CC
higher levels than the supply voltage, and they can be directly
connected to 5V CMOS logic outputs. For the LVT family, the
combination of low power dissipation with the live insertion feature,
bus hold and full 5V input/output capability make this logic ideal for
3.3V backplane interfacing.
MTBF = e(t’/τ )/T F F
C 1
O
In this formula, F is the frequency of the clock, F is the average
C
1
INTERFACING 3 VOLT AND 5 VOLT LOGIC
input event frequency, and t’ is the time after the clock pulse that the
output is sampled (t’ > T ). T and τ are device parameters
FROM
TO
METHOD
CO
O
provided by the semiconductor manufacturer (refer to the following
3V
to
5V
TTL Inputs
CMOS inputs
Direct
table for the LVT22V10 metastability specifications). T and τ are
O
LVT Output
derived from tests and can be most nearly be defined as follows: τ is
a function of the rate at which a latch in a metastable state resolves
Pull-up
CMOS Rail
Totem-Pole
Open Drain
LVT Input
LVT Input
LVT Input
Direct
Direct
Pull-up
5V
to
3V
that condition. T is a function of the measurement of the propensity
O
of a latch to enter a metastable state. T is also a normalization
O
constant, which is a very strong function of the normal propagation
delay of the device.
In this situation the F will be twice the data frequency, or 4MHz,
1
because input events consist of both of low and high transitions.
LVT22V10 METASTABLE HARDENED
CHARACTERISTICS
Thus, in this case, F is 33MHz, F is 4MHz, τ is 317ps, t’ is 15ns,
C
1
-3
and T is 4.27 × 10 seconds. Using the above formula the actual
MTBF for this situation is 1.26 × 10 seconds or 39 years for the
O
9
LVT22V10.
Metastable Hardened Characteristics
What is metastable hardened? Philips Semiconductors uses the
term “metastable hardened” to describe a combination of two
characteristic features. The first is a patented Philips circuit that
prevents the outputs from glitching, oscillating, or remaining in the
linear region under any circumstances, including setup and hold
time violations. The second is the flip-flops’ inherent ability of
resolving the metastable condition. Philips provides complete data
on the LVT22V10’s metastable characteristics
Summary
The Philips LVT22V10 has on-chip circuitry that completely
eliminates any output glitches, oscillations, or other output
anomalies associated with metastable conditions. For outputs that
are then used to generate clocks, control signals or other
asynchronous data this represents an unparalleled level of reliability
in a PLD. In addition, a complete set of metastability data is
provided, that allows designers the ability to design robust systems
where data is synchronously pipelined.
With the LVT22V10, any tendency towards internal metastability is
resolved by Philips Semiconductors patented circuitry. If a
LVT22V10 VALUES FOR τ AND T
O
0°C
25°C
75°C
V
CC
τ
T
O
τ
T
O
τ
T
O
3.0V
3.3V
3.6V
829.00ps
358.00ps
237.00ps
1.16E–08
2.36E–04
2.66E–01
691.00ps
317.00ps
230.00ps
1.09E–07
4.27E–03
6.47E–01
429.00ps
329.00ps
250.00ps
2.27E–04
5.75E–03
1.13E+00
14
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
SWITCHING WAVEFORMS
INPUT OR
FEEDBACK
INPUT OR
FEEDBACK
V
V
T
T
t
t
t
H
PD
S
COMBINATORIAL
OUTPUT
CLOCK
V
V
T
T
t
CO
REGISTERED
OUTPUT
V
T
Combinatorial Output
Registered Output
CLK
t
+ t
CF
S
t
S
LOGIC
REGISTER
CLOCK
V
T
t
CF
Clock to Feedback (f
Internal)
MAX
(See Path at Right)
Clock to Feedback
INPUT
V
T
t
WH
t
t
ER
EA
CLOCK
V
T
V
– 0.3V
+ 0.3V
OH
OUTPUT
V
T
V
OL
t
WL
Clock Width
Input to Output Disable/Enable
t
ARW
INPUT ASSERTING
ASYNCHRONOUS
RESET
INPUT ASSERTING
SYNCHRONOUS
PRESET
V
T
V
T
t
t
t
t
SPR
AR
S
H
REGISTERED
OUTPUT
CLOCK
V
V
V
T
T
T
t
t
ARR
CO
REGISTERED
OUTPUT
CLOCK
V
T
V
T
Asynchronous Reset
Synchronous Preset
SP00388
NOTES:
1. V = 1.5V.
T
2. Input pulse amplitude 0V to 3.0V.
3. Input rise and fall times 1.5ns max.
15
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
“AND” ARRAY – (I, B)
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
P, D
P, D
P, D
P, D
STATE
CODE
STATE
CODE
STATE
COMPLEMENT
CODE
STATE
DON’T CARE
CODE
1
O
TRUE
H
L
—
INACTIVE
SP00008
NOTE:
1. This is the initial state.
of the power-up reset and the wide range of ways V can rise to its
steady state, two conditions are required to ensure a valid power-up
reset. These conditions are:
POWER-UP RESET
CC
The power-up reset feature ensures that all flip-flops will be reset to
LOW after the device has been powered up. The output state will
depend on the programmed pattern. This feature is valuable in
simplifying state machine initialization. A timing diagram and
parameter table are shown below. Due to the synchronous operation
1. The V rise must be monotonic.
CC
2. Following reset, the clock input must not be driven from LOW to
HIGH until all applicable input and feedback setup times are met.
V
CC
2.7V
POWER
t
PR
REGISTERED
ACTIVE-LOW
OUTPUT
t
S
CLOCK
t
WL
Power-Up Reset Waveform
SP00389
LIMITS
SYMBOL
PARAMETER
MIN
MAX
UNIT
t
t
t
Power-up Reset Time
Input or Feedback Setup Time
Clock Width LOW
1
µs
PR
S
See AC Electrical
Characteristics
WL
16
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
17
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
PLCC28: plastic leaded chip carrer; 28 leads; pedestal
SOT261-3
18
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
19
1998 Feb 10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 02-98
Document order number:
9397 750 03313
Philips
Semiconductors
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