N74F40N [NXP]
Dual 4-input NAND buffer; 双4输入与非缓冲器
| 型号： | N74F40N |
| 厂家： | 
NXP |
| 描述： | Dual 4-input NAND buffer |
| 文件： | 总3页 (文件大小：36K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors FAST Products
Product specification
Dual 4-input NAND buffer
74F40
PIN CONFIGURATION
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
D0a
D0b
NC
1
2
3
4
5
14
V
CC
74F40
3.5ns
6mA
13 D1d
12 D1c
11 NC
10 D1b
ORDERING INFORMATION
D0c
D0d
COMMERCIAL RANGE
DESCRIPTION
V
CC
= 5V ±10%, T
= 0°C to +70°C
amb
Q0
6
7
9
8
D1a
Q1
14-pin plastic DIP
14-pin plastic SO
N74F40N
N74F40D
GND
SF00065
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
Dna, Dnb, Dnc, Dnd
Q0, Q1
DESCRIPTION
74F (U.L.) HIGH/LOW
1.0/2.0
LOAD VALUE HIGH/LOW
20µA/1.2mA
Data inputs
Data outputs
750/106.7
15mA/64mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC DIAGRAM
FUNCTION TABLE
INPUTS
Dnb
OUTPUT
1
2
D0a
Dna
L
Dnc
X
Dnd
X
Qn
H
D0b
D0c
D0d
X
L
6
Q0
4
5
X
X
X
H
X
X
X
H
L
X
H
X
X
X
H
9
D1a
D1b
H
H
H
L
10
NOTES:
8
Q1
1. H = High voltage level
2. L = Low voltage level
3. X = Don’t care
12
13
D1c
D1d
V
= Pin 14
CC
GND = Pin 7
NC = Pin 3, 11
SF00081
LOGIC SYMBOL
IEC/IEEE SYMBOL
1
&
1
2
4
5
9
10 12 13
2
4
6
5
D0a D0b D0c D0d D1a D1b D1c D1d
9
Q0 Q1
10
12
8
6
8
13
V
= Pin 14
CC
GND = Pin 7
NC = Pin 3, 11
SF00083
SF00082
1
April 11, 1989
853–0053 96314
Philips Semiconductors FAST Products
Product specification
Dual 4-input NAND buffer
74F40
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
–0.5 to V
128
OUT
OUT
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
NOM
MAX
V
Supply voltage
5.0
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–15
64
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
OH
OL
T
amb
Operating free-air temperature range
0
+70
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
V
2
MIN
TYP
MAX
±10%V
2.5
2.7
2.0
2.0
CC
I
= –1mA
OH
V
V
V
= MIN,
= MAX,
= MIN
CC
IL
±5%V
3.4
CC
V
OH
High-level output voltage
±10%V
CC
CC
IH
I
= –15mA
V
OH
±5%V
V
V
V
= MIN,
= MAX,
= MIN
±10%V
0.55
0.55
CC
IL
CC
V
OL
Low-level output voltage
I
OL
= MAX
V
±5%V
0.42
CC
IH
V
Input clamp voltage
V
V
= MIN, I = I
–0.73
–1.2
100
V
IK
CC
I
IK
I
I
I
I
Input current at maximum input voltage
= MAX, V = 7.0V
µA
I
CC
I
High-level input current
Low-level input current
V
CC
V
CC
V
CC
= MAX, V = 2.7V
20
–0.6
–225
4.0
µA
mA
mA
IH
IL
I
= MAX, V = 0.5V
I
3
Short-circuit output current
= MAX
–100
OS
I
V
= GND
= 4.5V
IN
1.75
11
CCH
IN
I
Supply current (total)
V
CC
= MAX
mA
CC
I
V
17
CCL
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
2
April 11, 1989
Philips Semiconductors FAST Products
Product specification
Dual 4-input NAND buffer
74F40
AC ELECTRICAL CHARACTERISTICS
LIMITS
V
= +5.0V
= +25°C
V
= +5.0V ± 10%
= 0°C to +70°C
CC
CC
TEST
CONDITION
SYMBOL
PARAMETER
T
amb
T
amb
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
Dna, Dnb, Dnc, Dnd to Qn
2.0
1.5
4.0
3.0
6.0
5.0
1.5
1.0
7.0
5.5
PLH
PHL
Waveform 1
ns
AC WAVEFORMS
Dna, Dnb, Dnc, Dnd
V
V
M
M
t
t
PHL
PLH
V
V
M
M
Qn
SF00069
Waveform 1. Propagation Delay for Inverting Outputs
NOTE:
For all waveforms, V = 1.5V.
M
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
V
CC
90%
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
R
L
C
L
R
T
=
=
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
74F
V
M
rep. rate
t
t
t
THL
amplitude
w
TLH
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
3
April 11, 1989
相关型号：
©2020 ICPDF网 联系我们和版权申明