SA1630 [NXP]
IF quadrature transceiver; 正交IF收发器
| 型号： | SA1630 |
| 厂家： | 
NXP |
| 描述： | IF quadrature transceiver |
| 文件： | 总22页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
SA1630
IF quadrature transceiver
Product specification
IC17 Data Handbook
1998 Jul 21
Philips
Semiconductors
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
DESCRIPTION
• Internal IF PLL for synthesizing the local IF oscillator signal.
The SA1630 is a 70–400 MHz I/Q transceiver for wireless LAN.
The Receive Path contains a digitally gain controlled linear IF
amplifier, a pair of quadrature down conversion mixers and a pair of
baseband amplifiers. The transmit path contains a pair of quadrature
up conversion mixers that transposes a quadrature baseband input
signal up to IF frequency. An external VCO signal is divided
internally and provides quadrature local oscillator signals for the
mixers. Another divider chain, reference divider and phase detector
are provided to avoid the need for an external synthesizer. To keep
power consumption to a minimum the transmit, receive and local
oscillator functions can be powered down under digital control.
• Bandwidth of baseband Tx inputs is 20 MHz and that of baseband
Rx outputs is 8.5MHz.
• Designed for IEEE 802.11 wireless LAN using Direct Sequence
Spread Spectrum modulation.
• Control registers power up in a default state.
• Only a standard reference input frequency required, choice of 8,
11, 22 or 44 MHz.
• Digital gain control of 70 dB in steps of 2 dB.
• Rx Baseband amplifiers are capable of driving 1kW ||15pF
FEATURES
• Rx Baseband o/p’s clamp symmetrically, above 1Vp–p in order to
• Low supply voltage operation of 2.7V for main chip and 2.9V for
prevent dc bias shift under overdrive conditions.
charge pump.
• Package: LQFP–48, PCMCIA compatible
• Low current consumption: 33.5 mA in RX, 26.5 mA in TX, typical
at 3V.
APPLICATIONS
• Flexible power up/down options.
• IF circuitry for IEEE 802.11 DSSS wireless LAN.
• Optional 2.5V regulated reference voltage available during
transmit.
• Applications for high speed wireless data.
• Input IF frequency range of 70–400 MHz.
BE Package
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
GNDCP
CP
V
Rx
1
2
CC
GNDRX
V
CP
CC
V
3
Rx
CC
DATA
4
PLL_ON
Rx_ON
CLOCK
STROBE
LOCK
5
6
GNDHDR
GC0
7
LO_INX
LO_IN
GC1
8
GC2
9
GNDRx
CLK IN
10
11
GC3
GC4
CLK
INX
GC5 12
13 14 15 16 17 18 19 20 21 22 23 24
SR01549
Figure 1.
Pin Configuration
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
48–Pin Plastic Low Profile Quad Flat package
–40 to +85°C
SA1630BE
SOT313–2
2
1998 Jul 21
853–2049 19763
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
(4)
(38)
(1,3)
V
(39)
V
V
2.5
R
T R
CC X X
PLL–ON
REF
CC
X
GND_BB
(13, 14)
(15)
R
XON
(5)
2.5V REGULATOR
V
_BB
CC
MODE
CONTROL
Tx
ON
(23)
I_Tx
I_Tx
IN
(18)
(19)
INX
Tx
IFOUT
(43)
(42)
Tx
IFOUTX
Q_Tx
Q_Tx
IN
(20)
(21)
INX
(7)
GC0
(8)
(9)
GC1
GC2
I_Rx
OUT
(17)
1
1
(46)
Rx
IFIN
(45)
Rx
IFINX
(10)
GC3
GC4
GC5
Q_Rx
(11)
(12)
OUT
(16)
LO IN
(28)
(29)
LO INX
BUFFERS
2
÷
V
CCCP
(34)
N
÷
DAC
CP
(35)
(37)
(30)
I
REF
CHARGE
PHASE
SYNTH
REGISTER
GND HDR
PUMP
DETECTOR
(6)
LOCK
GNDT R
X
X
(40, 41)
SERIAL
INPUT
GNDCP
TEST REGISTER
8, 11, 22, 44
÷
(36)
CLK
CLK
V
GND DIG
(24)
IN
INX
CCDIG
(22)
DATA CLOCK STROBE
(33) (32) (31)
GND RX
(2, 27, 44, 47, 48)
(26)
(25)
SR01551
Figure 2.
Block Diagram
3
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
PIN DESCRIPTIONS
Pin No.
Pin Name
Rx
Description
1, 3
V
Supply Pin for Rx section (IF circuits)
Ground pins for Rx section (IF circuits)
CC
2, 27,
44,47,
48
GNDRx
4
5
PLL_ON
Rx_ON
GNDHDR
GCO
One of the three digital CMOS logic control inputs to the mode control section
One of the three digital CMOS logic control inputs to the mode control section
Substrate ground
6
7
Control bit 0 for IF VGA gain control, CMOS input
Control bit 1 for IF VGA gain control, CMOS input
Control bit 2 for IF VGA gain control, CMOS input
Control bit 3 for IF VGA gain control, CMOS input
Control bit 4 for IF VGA gain control, CMOS input
Control bit 5 for IF VGA gain control, CMOS input
Ground pin for Rx baseband circuits
8
GC1
9
GC2
10
11
12
GC3
GC4
GC5
13, 14 GND_BB
_BB
15
16
17
18
19
20
21
22
23
24
25
26
28
29
30
31
32
33
34
35
36
37
38
39
V
CC
Supply Pin for Rx Baseband circuits
Q_RXOUT
I_RxOUT
I_Tx IN
Quadrature–phase Rx baseband output, single–ended
In–phase Rx baseband output, single–ended
In–phase differential Tx baseband input, positive
In–phase differential Tx baseband input, negative
Quadrature differential Tx baseband input, positive
Quadrature differential Tx baseband input, negative
Supply for digital circuits
I_Tx INX
Q_Tx IN
Q_Tx INX
V
CC
_DIG
Tx_ON
GNDDIG
CLK INX
CLK IN
LO_IN
One of the Three digital CMOS logic control inputs to the mode control section
Digital ground
Differential reference input for synthesizer, negative
Differential reference input for synthesizer, positive
Differential LO input,positive
LO INX
LOCK
Differential LO input, negative
Test control output and synthesizer lock indicator
Serial bus strobe input
STROBE
CLOCK
DATA
Serial bus clock input
Serial bus data input
V
CC
CP
Supply for charge pump circuits
CP
GNDCP
Charge pump output
Ground for charge pump circuits
I
Charge pump reference current
REF
V
V
2.5
Reference voltage of 2.5V available for external use
Supply pin used by Tx circuits
REF
TxRx
CC
40,41 GNDTxRx
Ground pins used by Tx circuits
42
43
45
46
TxIFOUTX
TxIFOUT
RxIF INX
RxIF IN
Differential transmitter IF output (open collector), positive
Differential transmitter IF output (open collector), negative
Differential receiver IF input, negative
Differential receiver IF input, positive
4
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNITS
V
V
CCXX
Supply voltages
-0.3 to +6.0
V
IN
Voltage applied to any other pin
-0.3 to V
+0.3
V
CCXX
∆VG
Any GND pin to any other GND pin
0
V
P
Power dissipation, T = 25°C (still air)
300
mW
°C
D
A
T
Maximum operating junction temperature
Maximum power input/output
150
+20
JMAX
P
dBm
°C
MAX
STG
T
Storage temperature range
–65 to +150
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
RATING
2.7 to 3.6
2.7 to 3.6
-40 to +85
UNITS
V
Supply voltages:
V
V
CCXXXX
V
CC
CP
Charge pump supply voltage
Operating ambient temperature range
T
A
°C
NOTES:
1. There are no ESD protection diodes between pins 42, 43 and V to allow higher AC peak voltage. The ESD protection level has thus been
CC
reduced. Proper ESD handling precautions should be followed.
MODE CONTROL
NO:
PLL_ON
RX_ON
TX_ON
STATE DESCRIPTION
SLEEP mode
MODE
SLEEP
2.5V REF
Off
1
0
1
1
1
1
X
0
1
1
0
X
1
1
0
0
2
Synthesizer ON, Rx STDBY, Tx OFF
Synthesizer ON, Rx STDBY, Tx ON
Synthesizer ON, Rx ON, Tx OFF
Synthesizer ON, Rx OFF, Tx ON
WAIT
Off
3
TRANSMIT
RECEIVE
TRANSMIT
On
4
Off
5
Off
’0’ – LOGIC LOW
’1’ – LOGIC HIGH
’X’ – DON’T CARE
except for the bias and baseband circuits needed to hold the
baseband output voltages in the active state. This mode is useful if
the Rx baseband outputs are AC coupled via a large capacitor and
the application demands quick turn–on for the Rx, from Tx.
1. Sleep mode (PLL OFF, Rx OFF, Tx OFF)
In this mode everything is switched off except the 3–wire digital bus.
As long as the digital supply is still on, the programmed values are
active and the 3–wire bus will continue to be programmable.
4. Receive Mode (Tx Off)
The Transmitter is completely shut–off. The PLL and receiver
sections are operating.
2. Wait Mode (Tx Off, Rx Standby)
PLL is on. Receiver is in the reduced current standby mode and the
transmitter is completely switched off. This mode maybe useful if the
PLL is to be kept on and is waiting for a quick turn–on to either
transmit or receive modes, especially when Rx outputs are AC
coupled.
5. Transmit Mode (Rx OFF)
PLL and Transmit sections are on. However, the Receiver is
completely shut–down. This mode is useful if the Rx baseband
outputs are DC coupled to the external world.
3. Transmit mode (Rx standby)
The PLL and transmitter are on. The receive section is in a reduced
current mode wherein most of the Rx circuitry is powered down
5
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
RX VGA CONTROL TABLE
REDUCTION
FROM Gmax
GC5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
GC4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GC3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
GC2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
GC1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
GC0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
DECIMAL NUMBER
0
0
1
–2
2
–4
3
–6
4
–8
5
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30
–32
–34
–36
–38
–40
–42
–44
–46
–48
–50
–52
–54
–56
–58
–60
–62
–64
–66
–68
–70
6
7
8
9
10
11
12
13
14
15
23
24
25
26
27
28
29
30
31
52
53
54
55
56
57
58
59
60
61
62
6
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
DC ELECTRICAL CHARACTERISTICS
V
CC
XXX=+3V; V XXX = 0V; TA=25°C, unless otherwise stated.
EE
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
UNITS
MAX
MIN
TYP
PLL_ON=Rx_ON=Hi
Tx_ON = Low
I
Supply Current, Receive (mode #4)
33.5
17
41.5
mA
CC–4
CC–2
Wait mode (2)
PLL_ON = Hi
Tx_ON = Hi
I
Supply Current, Wait (mode #2)
23
mA
Rx_ON = Low
PLL_ON = TX_ON = Hi
RX_ON = Hi
I
I
I
Supply Current, Transmit (mode #3)
Supply Current, Sleep mode (mode #1)
Supply current transmit (mode 5)
26.5
0.012
22
34.5
0.1
mA
mA
mA
CC–3
CC–1
CC–5
PLL_ON = Low
RX_ON = DC
TX_ON = DC
PLL_ON = Hi
T _ON = RX_ON = Low
X
28.5
V
_2.5
Reference voltage (mode 3, enabled)
Output impedance of reference voltage
Load = 1.5mA
2.5
15
V
REF
Z
_V
∆I = 1.4 to 1.6mA
W
OUT REF
CMOS LOGIC INPUTS (DATA, CLOCK, STROBE)
V
Input logic 1 level
Input logic 0 level
Input logic current
Input logic capacitance
2.0
0
V
V
V
IH
CCD
V
I
0.8
IL
1
4
µA
pF
I
C
I
CMOS Logic output (LOCK)
V
Output logic 1 level
Output logic 0 level
I
= –2mA
= 2mA
V –0.4
CCD
V
V
OH
O
V
I
0.4
OL
O
CMOS Logic Inputs (PLL_ON, RX_ON, TX_ON)
2.0
0
V
Input logic 1 level
Input logic 0 level
Input logic current
V
V
V
IH
CCTXRX
V
I
0.8
IL
1
µA
I
7
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
AC ELECTRICAL CHARACTERISTICS IF TRANSMIT MODULATOR
(Mode #3, Tx ON Rx Standby) V XXX = +3V; GNDXXX = 0V; LO_in = 100 mV peak at 704 MHz, CLKin = 100mV peak at 22 MHz, T
=
CC
amb
25°C, unless otherwise stated.
LIMITS
TYP
SYMBOL
PARAMETER
TEST CONDITION
UNITS
MIN
MAX
–45
2
4,5
BW
Input modulation bandwidth
500 ohms source impedance
22
MHz
Vpp
1
V
IN
Input signal amplitude, Differential
Voltage common mode = 1 to 2V
1
Input signal amplitude = 1 V
,
PP
5
THD_3
Third harmonic distortion
–55
dBc
kΩ
pF
V
8 MHz, V
= 1.5
CM
Between pins I_T IN, I_T INX
X
X
R
Input resistance
98
INTx
Q_T IN, Q_T INX
X
X
Between pins I_T IN, I_T INX
X
X
4
C
Input Capacitance
INTx
Q_T IN, Q_T INX
X
X
V
IN
= IV
PP
Minimum Tx output DC voltage
Mean output DC current
V
CC
–0.3
V
I = V Q = V /2
CM
CM CC
IO DC
At T IF
and T IF
OUTX
2
2.75
40
mA
µA
X
OUT
X
4
Output current DC offset
Mismatch at T IF
and T IF
OUT X OUTX
X
2
Output current available
At T IF
and T IF
0.475
190
36
mA rms
mV rms
dBc
X
OUT
X
OUTX
2
1,2
Output differential voltage
400 Ω tuned load
1,3
30
CS
Carrier suppression
Differential output
= 352 MHz
1,3
SBS
SB Suppression
f
35
47
dBc
OUT
Noise floor
offset = 10 MHz
156
0.5
dBc/Hz
dB
4
6
nG
Gain stability
2.0
T _ON, R _ON transition
to transmit signal at 90% level
X
X
4
t
Turn–on time
Turn–off time
4
4
µs
µs
ON
T _ON, R _ON transition to transmit
X
X
4
T
OFF
signal at 10% level
NOTES:
1. Tx inputs are differential sine wave, 0.5 V peak, with quadrature relationship between I and Q Tx input. The output spectrum will be SSB.
The tone is at a frequency of 1 MHz.
2. The output current in each arm is the same but 180 degrees out of phase with each other. Also the tuned load of 400 ohms differential, is
assumed. The power delivered to 400 ohms will be –10.4 dBm (typ.). The output current measurement is indirect based on output power
2
measurement according to P = 10 log I rms (400W)/IMV. See typical performance characteristic curve.
3. This is measured with respect to the SSB output.
4. Guaranteed by design and or characterization but not final tested.
5. The input bandwidth may be verified by measuring the output THD and signal level using a DSB spectrum where I = Q.
6. Measured over temperature and supply.
8
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
AC ELECTRICAL CHARACTERISTICS IF RECEIVER DEMODULATOR
(Mode #4, Rx_ON, Tx_OFF) V XXX = +3V = GNDXXX = 0V; LO IN = 100 mV
at 704 MHz, CLKIN = 100mV , at 22 MHz, Ta = 25°C,
CC
peak
peak
unless otherwise stated.
LIMITS
TYP
6.6K||0.7
88
SYMBOL
PARAMETER
TEST CONDITION
UNITS
MIN
81
MAX
f
IN
= 352 MHz
RInRx
VG
Differential input impedance
Voltage gain
kΩ||pF
dB
AGC at maximum gain
VGA at maximum gain
1
NF
Input noise figure
7.5
dB
AGC range
67
70
dB
AGC step size
2
dB
AGC differential error
AGC settling time
2
dB
any AGC step
200
nS
Channel matching
gain
phase
0.1
0.25
dB
deg
Output DC offset between IRx Out and
QRx Out
Maximum Gain, Output at 1 MHz
6
mV
2
AGC G , into load
0.9
1.0
1.15
1.4
1.9
7
Vp–p
MIN
OVS
Output voltage swing
AGC Gain, except G
MIN
Output common mode voltage
Output impedance
V
Ω
3
THD
Total Harmonic Distortion
Rx Bandwidth
Max. Gain, rated output at 1 MHz
3
%
5
BW
7
8.5
10
2
MHz
R _ON, T _ON transition to
X
X
4
t
Turn–on time
Turn–off time
µs
µs
ON
baseband signal out
R _ON, T _ON transition to no
X
X
4
t
2
OFF
baseband signal out
NOTES:
1. The Receive input is to be differential (using a balun or a differential source such as a differential SAW filter) and matched to external
generator’s impedance (ex: 50 ohms). The balun may or may not provide any impedance transformation depending on availability. An
external L–C matching circuit can provide the rest of the impedance transformation and absorb the input capacitance of the receiver input.
Such a differential input scheme is mandatory to avoid pickup, and keep the noise figure low. A shunt resistor across the input (value TBD)
will be used to set the input impedance as a compromise between the matching ease in production versus the noise figure of the receiver.
The system board layout has to keep the isolation between the receive inputs and the LO signal as high as possible. Otherwise the LO
leakage will overload the receiver.
2. The load is 1000 ohms in parallel with 15pF of capacitor.
3. THD is total harmonic distortion. We measure harmonics 2, 3, 4.
4. Guaranteed by design.
5. 3dB bandwidth relative to a passband measurement taken at 1MHz.
9
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
AC ELECTRICAL CHARACTERISTICS IF SYNTHESIZER
V
XXX = RX_ON = TX_ON = PLL_ON = +3V, V XXX = 0V; LO_IN = 100 mV
at 704 MHz, CLKIN = 100mV at 22 MHz, Ta = 25°C,
peak
CC
EE
peak
unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
UNITS
MAX.
MIN
TYP
3
f
Local oscillator input frequency range
140
800
MHz
Ω||pF
mVpk
LO
Z
LOIN
LOIN
Differential input impedance
Between LO_IN and LO_INX
276||0.6
4
V
LO input sensitivity
Single ended Referred to 50Ω
50
64
350
511
Programmable divider:
division range
step size
1
3
f
Reference clock maximum frequency
1
44
MHz
CLK
10||
1.0
kΩ
pF
Z
CLKIN
Differential input impedance
Between Clk and Clk
IN
INX
4
CLK input sensitivity
Referred to 50Ω
50
200
400
mVpk
Phase detector minimum comparison
frequency
f
1
MHz
CMIN
Phase detector maximum comparison
freq
f
Ref Divider = 44
2.5
MHz
CMAX
I
Charge pump reference current
R
= 50KΩ
EXT
31.25
µA
REF
Charge pump output current:
C0...C2 = 000
C0...C2 = 111
I
V
= 31.25 µA
0.160
0.320
0.023
0.200
0.400
0.029
0.240
0.480
0.035
mA
mA
mA
REF
CP
|I
|
CP
= V CP/2
CC
step size
nI
I
CP
CP
1
1.3
Relative output current variation
I
= 31.25 µA
= 31.25 µA
%
"8
REF
REF
I
V
2
nI
CP_M
Output current matching
"12
"15
%
= V CP/2
CP
CC
Output leakage current
0.2
nA
Output current tolerance
with temperature
with output voltage
"1
"5
%
3
Serial Interface
f
Clock frequency
10
MHz
ns
CLOCK
Set–up time; DATA to clock,
CLOCK to STROBE
t
30
SU
t
Hold time: CLOCK to DATA
Pulse width: CLOCK
30
30
30
ns
ns
ns
H
t
W
Pulse width: STROBE
NOTES:
1. The relative output current variation is defined thus:
ǒ
Ǔ
DIOUT
I2 – I1
+ 2 .
; WITH V1 + 0.7V, V2 + VCCCP – 0.8V (see Figure 3).
IOUT
ǒ
Ǔ
I I2 ) 11
2. The output current matching is measured when both (positive current and negative current) sections of the output charge pumps are on
3. Guaranteed by design.
4. Maximum level guaranteed by design.
10
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
The baseband amplifiers can interface directly to the Track/Hold
switch/capacitor combination with capacitance values up to 15 pF.
When sampled at 22MHz the output can settle to within 1/4 LSB
when swinging 1V p–p.
CURRENT
I
2
I
1
The chip has a unique mode in which the Rx is on standby while the
Tx is ON. In this mode the Rx Baseband circuits are idling at
reduced currents and all Rx I/O outputs retain their DC bias
unchanged from their values when the Rx was fully ON. This mode
is very essential if ac coupling through a large capacitor, such as,
10nF is used. From this mode the chip can quickly be switched to
the Rx ON mode (Tx OFF) without worrying about
VOLTAGE
V
1
V
2
charging/discharging the large AC coupling capacitor.
I
2
The VGA can be programmed in 2 ways: 1) Directly programming
external control pins. 2) programming over the serial 3–wire bus.
The former method can switch gain in less than 200 ns.
I
1
SR00526
Figure 3.
Relative Output Current Variation
The Rx baseband section also incorporates simple low pass active
filters of the Sallen key type. The Rx bandwidth is mainly set by
these filters. The function of these filters is twofold: 1) attenuate high
frequency signals from the Rx mixers. 2) act as anti–aliasing filters
for any A to D converters following this chip.
APPLICATION DESCRIPTION
IF synthesizer
General
The SA1630 has an integrated synthesizer that uses an external
VCO operating on twice the IF frequency. It is internally divided by 2
for obtaining quadrature signals. The divided VCO signal is not
externally available. This minimizes the LO feedthrough to the IF
input port and hence minimizes output dc glitches when the IF gain
is switched.
The 1630 performs the IF modulator and demodulator functionality
for high–speed wireless data transceivers. The design is optimized
for IEEE 802.11 wireless LAN using 11 chips/symbol Direct
Sequence Spread Spectrum.
Transmitter
The IF quadrature transmitter baseband modulator input is driven
differentially by the D/A converters in the DSP chip. The baseband
signals are DC coupled for fast turn–on and turn–off and for
constant carrier testing. The typical common–mode input voltage is
VCC/2.
The open collector outputs of the mixers are biased by two
inductors, which are part of an LC tank. The LC tank matches the
output impedance of the mixers to the input impedance of the
upconverter chip (or any filter in between) and suppresses IF
harmonics.
The PLL reference clock is derived from the 22 MHz DSP clock. The
available divider ratios facilitate both 1 and 2 MHz phase
comparison frequency from a 22 MHz and an optional 44 MHz clock
respectively. In essence the reference divider will have
programmable dividers ratios of 8, 11, 22 and 44.
The VCO shall be fed from a stabilized supply. Such a stabilized
supply is necessary in order to prevent oscillator jitters due to Rx/Tx
switching. The effect of oscillator jitters is further minimized when
using a high PLL loop bandwidth, which on its turn requires a high
phase comparison frequency (1 MHz, preferably 2 MHz).
An optional 2.5V reference is available during mode (3) and (5), the
transmit mode with Rx in standby. This reference can be enabled or
disabled via the 3 wire bus (in this mode). This voltage is provided
for use by an external current DAC if needed.
If the IF Synthesizer is not used, the CLK pins should be
IN
terminated to ac ground.
Serial Programming Input
Receiver
The serial input is a 3–wire input (CLOCK, STROBE, DATA) to
program the counter ratios, charge pump current, status– and
DC–offset register, mode select and test register. The programming
data is structured into two 21–bit words; each word includes 4 chip
address bits and 1 subaddress bit. Figure 2 shows the timing
diagram of the serial input. When the STROBE = L, the clock driver
is enabled and on the positive edges of the CLOCK the signal on
DATA input is clocked into a shift register. When the STROBE = H,
the clock is disabled and the data in the shift register remains stable.
Depending on the value of the subaddress bit the data is latched
into different working registers. Table 3 shows the contents of each
word.
The receiver part of the SA1630 consists of an IF Variable gain
amplifier, a quadrature demodulator and a pair of baseband
amplifiers. The IF amplifier has its gain controlled by the DSP chip.
This ensures linear operation of the receiver chain over a wide
dynamic range of input signals. Linear operation is essential for
resolving echo’s due to multipath reception.
The digital controlled AGC is meant for fast level training for the
receiver.
The high gain receiver, which is distributed between the IF and
baseband part facilitates interfacing with the RF front–end chip,
which normally have moderate gains (up to 20 dB), and SAW IF
filters, which mostly have considerable loss (up to 8 dB) without
external amplifiers.
Default States
Upon power up (V DIG is applied) a reset signal is generated,
CC
The baseband amplifiers have a high drive capability (1 Vpp into
1kΩ, 15 pF for VCC = 3V) that facilitates direct interfacing to the A/D
converter without active external elements.
which sets all registers to a default state. The logic level at the
11
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
STROBE pin should be low during power up to guarantee a proper
reset. These default states are shown in Table 2.
The current can be set to zero by connecting the pin I
to V CP.
REF CC
Charge Pumps
Reference Divider
The reference divider can be programmed to four different division
ratios (:8, :11, :22, :44), see registers r0, r1; default setting: divide by
22.
The charge pumps at pin CP are driven by the phase detector and
the current value is determined by the binary value of the charge
pumps register CN = c2, c1, c0, default .4mA. The active charge
pump current is typically:
|ICP| + (c0 ) 2c1 ) 4c2) @ 29mA ) 200mA
Main Divider
The external VCO signal, applied to the LO and LO X inputs, is
IN
IN
divided by two and then fed to the main divider (:N). The main
divider is a programmable 9 bit divider, the minimum division ratio is
divide by 64. The division ratio is binary coded and set in the
registers n0 to n8. The default setting is a divide by 352.
Lock Detect
The output LOCK is H when the phase detector indicates a lock
condition. This condition is defined as a phase difference of less
than ±1 cycle on the reference input CLK , CLK X.
IN
IN
At the completion of a main divider cycle, a main divider output is
generated which will drive the phase detector.
Test Modes (Synthesizer, Transmit Mixer)
The LOCK output is selectable as a test output. Bits x0, x1 control
the selection, the default setting is normal lock output as described
in the Lock detect section. The selection of a Bit x0, x1 combination
has a twofold effect: First it routes a divider output signal to the
LOCK pin, second it disables mixer stages in the transmit path.
Setting x0,1 = 11 disables both transmit path mixers. This mode can
be used to prevent the transmitter from producing an IF output
signal even if the transmit part is powered on. This can be used to
simplify the control timing while commanding the transmit and
receive simultaneously without the transmit part causing
interference.
Phase Detector
The phase detector is a D-type flip-flop phase and frequency
detector shown in Figure 5. The flip-flops are set by the negative
edges of the output signals of the dividers. The rising edge of the
signal L will reset the flip-flops after both flip-flops have been set.
Around zero phase error this has the effect of delaying the reset for
1 reference input cycle. This avoids non-linearity or deadband
around zero phase error. The flip-flops drive on-chip charge pumps.
A source current from the charge pump acts to increase the VCO
frequency; a sink current acts to decrease the VCO frequency.
Table 1. Test Modes
Current Setting
Transmit Mixer
Synthesizer Signal
at LOCK Pin
The charge pump current is defined by the current set between the
x0 x1
pin I
and V CP. The current value to be set there is 31.2µA.
Q-mixer I-mixer
REF
EE
This current can be set by an external resistor to be connected
between the pin I and V CP. The typical value R (current
setting resistor) can be calculated with the formula
0
1
0
1
0
0
1
1
normal lock detect
on
off
on
off
on
on
off
off
REF
EE
EXT
CLK divided by reference
IN
divider ratio
V
CCCP–1.6V
LO ÷ 2 * (main divider ratio)
IN
REXT
+
(44.87K for 3V)
31.2mA
main divider output, that goes to
the phase detector
12
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
Table 2. Definition of SA1630 Serial Registers
First data word: (shown with default values)
Sub
Reference
Divider
Address SA1630
N-Divider
Charge-Pump
Test
Adr
MSB
LSB
a0
a1
a2
a3
sa
n0
n1
n2
n3
n4
n5
n6
n7
n8
r0
r1
c0
c1
c2
x0
x1
1
1
1
0
0
1
0
1
1
0
0
0
0
0
1
0
1
1
1
0
0
Address: 4 bits, a0...a3, fixed to 1110
Sub:Address: 1 bit, sa, fixed to 0 for first data word
9 bits, n0...n8, values 64 (00100 0000) to 511 (11111 1111) allowed for IF choice, default 352 (assuming LO
input frequency is 704 MHz).
N-Divider:
Reference Divider Register: 2 bits, r0...r1, 00 = /8, 01 = 11, 10 = /22, 11 = /44. Default: 10
Charge-Pump Register: 3 bits, c0...c2, Binary setting factor for charge pumps, values 000 = minimum current to 111 = maximum
current, default is maximum charge pump current (111)
Test Register: 2 bits, x0...x1, default 00, see functional description for details
Second data word: (shown with default values)
Misc
Control
bits
Sub LLL Mode
Q Offset
Register
Address SA1630
I Offset Register
VGA Gain Control
Adr
Control
MSB
LSB
a0
a1
a2
a3
sa
s0
s1
i0
i1
i2
q0
q1
q2
b0
b1
b2
b3
b4
b5
bc
vc
1
1
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
Address: 4 bits, a0...a3, fixed to 1110
Sub:Address: 1 bit, sa, fixed to 1 for second data word
LLL Mode control: 2 bits, s0, s1 Not used, always set to 0, 0
I Offset Register: 3 bits, i0...i2 .10 Not used, always set to 0, 0, 0
Q Offset Register: 3 bits, q0...q2. q0. Currently not being used, always set to 0, 0, 0
VGA Gain Control 6 bits, b0...b5. 000 000 corresponds to maximum gain and 111 111 to minimum gain in 2 dB increments.
Check control table contained elsewhere in this document.
VGA Control Enable 1 bit, bc. When bc=0 the VGA is controlled by external pins. When bc=1 then bits b0...b5 control the VGA.
Default bc=0, control by external pins
Regulator Disable 1 bit, Vc. When Vc=0 the 2.5V reference output is completely powered down. When Vc=1 the reference
voltage is enabled (provided Tx_ON=HIGH). Default: Vc = 1, enable the 2.5 reference.
13
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
LSB
MSB
DATA
a
a
0
X
or t
X or t
0 4
1
1
5
t
H
t
t
SU
SU
50%
CLOCK
FIRST CLOCK
LAST CLOCK
FIRST CLOCK
t
SU
STROBE
CLOCK ENABLED
SHIFT IN DATA
CLOCK
DISABLED
STORE DATA
t
W
50%
CLOCK
SR00527
STROBE
Figure 4.
Serial Input Timing Sequence
L
“1”
R
D
C
Q
REFERENCE
DIVIDER
CLK
IN
V
CP
CC
R
R
P
P-TYPE
CHARGE PUMP
C
P
“1”
X
D
C
MAIN
DIVIDER
LO
IN
÷2
N-TYPE
CHARGE PUMP
Q
N
V
SS
CLK
IN
L
R
X
P
N
I
CP
SR00528
Figure 5.
Phase Detector Structure with Timing
14
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
3V
SUPPLY
10m
1
48
GNDRX
GNDRX
V
Rx
CC
100n
47
2
GNDRx
1.8p
5K
3
46
45
V
Rx
RxIF IN
CC
RxIN
100n
44nH
4
PLL_ON
Rx_ON
RxIF INX
PLL_ON
1.8p
17.4
44
43
5
GNDRX
1n
Rx_ON
TxIFOUT
TxOUT
6
1n
GNDHDR
GC0
294
1n
294
7
GC0
42
TxIFOUTX
8
GC1
GC2
GC1
41
40
GNDTxRx
GNDTxRx
9
GC2
10
39
38
37
36
35
34
GC3
GC4
GC5
GC3
V
TXRX
CC
I0n
V
20Ω
REF
11
GC4
V
2.5
REF
12
I
REF
GC5
10n
GNDCP
CP
13
14
15
GND_BB
GND_BB
CP
V
__BB
CC
V
CP
CC
100n
100n
16
DATA
CLOCK
33
32
31
Q_RXOUT
3 WIRE
15P
SERIAL BUS
1K
STROBE
LOCK
30
29
17
LOCK
I_RxOUT
10n
15P
LO INX
LO IN
1K
W
10n
28
27
26
LO_IN
GNDRx
CLK IN
18
I_TX IN
I/Q GEN
1MHZ
FOR SSB
TESTING
10n
10n
19
20
CLKIN
I_Tx INX
50W
25
24
23
CLK INX
GNDDIG
Q_Tx IN
(8MHZ
FOR DSB
TEST-
ING)
Q_Tx INX
21
22
Tx_ON
TX_ON
1n
V
CC DIG
100nF
SR01550
Figure 6.
Typical SA1630 Test Circuit
15
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
Supply Current Wait Mode 2
Vs. Temperature and Supply
Supply Current Sleep Mode 1
Vs. Temperature and Supply
22
20
19
18
17
16
15
14
20
18
16
14
12
10
3.6 V
3 V
2.7 V
3.6 V
3 V
2.7 V
–50
0
50
100
–50
0
50
100
Temperature °C
Temperature °C
Supply Current Transmit Mode 3
Vs. Temperature and Supply
Supply Current Receive Mode 4
Vs. Temperature and Supply
30
40
38
29
28
27
26
25
24
23
22
36
34
3.6 V
3.6 V
2.7 V
3 V
32
30
28
26
2.7 V
–50
0
50
100
–50
0
50
100
Temperature °C
Temperature °C
Supply Current Transmit Mode 5
Vs. Temperature and Supply
Receiver Third Harmonic Distortion
Vs. Temperature and Supply
26
24
22
20
18
16
40
38
36
34
32
30
28
dB below signal with Rx input
IV at maximum gain
PP
2.7 V
3.6 V
3 V
3 V
2.7 V
3.6 V
–50
0
50
100
Temperature °C
–50
0
50
100
Temperature °C
SR01601
Figure 7.
16
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
Receiver AGC Gain Range
Vs. Temperature and Supply
Receiver Maximum Gain
Vs. Temperature and Supply
100
75
70
65
95
90
85
80
2.7 V
3 V
3.6 V
3.6 V
3 V
2.7 V
–50
0
50
100
–50
0
50
100
Temperature °C
Temperature °C
Transmitter Carrier and
Sideband Suppression
Transmitter Third Harmonic Distortion
Vs. Temperature and Supply
Vs. Temperature and Supply
–50
–55
–60
–65
–70
–30
–32
–34
–36
–38
–40
–42
–44
–46
–48
–50
Carrier Suppression
3.6
3
2.7 V
2.7 V
3
3.6
Sideband
Suppression
3.6
3
2.7 V
–50
0
50
100
–50
0
50
100
Temperature °C
Temperature °C
Transmitter AC Output Current
Vs. Temperature and Supply
P Charge Pump Current 000
Vs. Temperature and Supply
0.5
0.4
0.3
0.2
–190
–195
–200
–205
–210
Average output at 353MHz
Input 1V
PP
3.6
3
2.7V to 3,6 V
2.7 V
–50
0
50
Temperature °C
100
–50
0
50
100
Temperature °C
SR01600
Figure 8.
17
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
N Charge Pump Current 000
Vs. Temperature and Supply
P Charge Pump Current 111
Vs. Temperature and Supply
205
200
195
190
–390
–395
–400
–405
–410
–415
–420
3.6
3
3.6
3
2.7 V
2.7 V
–50
0
50
100
–50
0
50
100
Temperature °C
Temperature °C
Charge Pump Match 111
Vs. Temperature and Supply
N Charge Pump Current 111
Vs. Temperature and Supply
5
0
410
405
400
395
390
3.6
V
–5
3
2.7 V
3 V
V
2.7 V
3.6 V
–10
–15
–50
0
50
100
–50
0
50
100
Temperature °C
Temperature °C
N Charge Pump Step Size
Vs. Temperature and Supply
35
33
P Charge Pump Step Size
Vs. Temperature and Supply
–25
–27
–29
–31
–33
–35
31
29
2.7 V
3 V
3.6 V
3.6 V
3 V
2.7 V
27
25
–50
0
50
100
–50
0
50
100
Temperature
C
Temperature °C
SR01599
Figure 9.
18
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
Transmitter Input Modulation
Bandwidth Vs. Frequency
2.5 Reference Voltage Vs. Load
and Temperature
3.0
–21
–22
–23
–24
–25
–26
85°C
25°C
–40°C
2.8
2.6
2.4
–2.0
–1.2
–0.4
0.4
1.2
2.0
0
4
8
12
16
20
24
28
32
36
Load Current mA
Vcc= 3V
Frequency MHz
Vcc = 3V
Transmitter RMS Output Current
Vs. Input Voltage
Receiver Filter Bandwidth Vs.
Frequency and Temperature
0.6
0.5
0.4
0.3
0.2
–14
–16
–18
–20
–22
–24
–26
–40°C
25°C
85°C
0.50
0.70
0.90
1.10
1.30
1.50
0
3
6
9
12
15
Single Ended Input Vpp V
Output Frequency MHz
Vcc= 3V
Vcc= 3V Gain= –70
Charge Pump Relative Variation
Vs. Temperature and Supply
3
2
1
0
Vcm – 0.7V to V –0.8V
CC
2.7 V
P Pump
3 V
3.6 V
N Pump 2.7V to 3.6V
100
–50
0
50
Temperature °C
SR01602
Figure 10.
19
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
20
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
NOTES
21
1998 Jul 21
Philips Semiconductors
Product specification
IF quadrature transceiver
SA1630
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 07-98
9397 750 04166
Document order number:
Philips
Semiconductors
相关型号：
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