SAF1135 [PHILIPS]
Consumer Circuit, CMOS, PDIP14,;
| 型号： | SAF1135 |
| 厂家： | 
PHILIPS SEMICONDUCTORS |
| 描述： | Consumer Circuit, CMOS, PDIP14, 光电二极管 商用集成电路 |
| 文件： | 总15页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAF1135
Data line decoder
August 1986
Product specification
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
Data line decoder
SAF1135
GENERAL DESCRIPTION
The SAF1135 is a data line decoder, designed in CMOS technology, which operates in conjunction with the data line
processor (SAA5235) to form a data line receiver system.
This system receives and decodes binary data that is transmitted in line 16 of every first field of a standard television
signal. The decoded information is accessed via the built-in I2C bus interface. This information can be used to program
a video tape recorder to start and stop the recording of a television program at the correct time, regardless of a delay or
extension in the transmission time of the required television program.
Valid Video Programming System (VPS) data is transmitted in line 16 only. There is no VPS information in line 329.
The data transmission is biphase modulated and the bit transfer rate is 2,5 Mbit/s.
Features
• Field selection
• Line 16 decoding
• Start code check
• Biphase check
• Storage of data line information
• Generation of data reset pulse
• I2C bus transmitter
QUICK REFERENCE DATA
PARAMETER
Supply voltage (pin 14)
SYMBOL
VDD
MIN.
4,5
TYP.
5,0
MAX.
5,5
UNIT
V
Supply current (pin 14)
IDD
−
1
−
mA
Bit transfer rate at input DLD (pin 8)
Clock frequency at input DLCL (pin 11)
Storage temperature range
BRDLD
fDLCL
Tstg
−
2,5
5
−
Mbits/s
MHz
°C
−
−
−65
0
−
+150
70
Operating ambient temperature range
Tamb
−
°C
PACKAGE OUTLINES
14-lead DIL; plastic (SOT27); SOT27-1; 1997 January 07.
August 1986
2
Philips Semiconductors
Product specification
Data line decoder
SAF1135
August 1986
3
Philips Semiconductors
Product specification
Data line decoder
SAF1135
FUNCTIONAL DESCRIPTION
The SAF1135 is designed to receive and decode Video Tape Recorder (VTR) control information which is transmitted in
line 16 of every first field of a standard television signal. The following description refers to the block diagram Fig.1 unless
otherwise stated.
Data line 16
The total information of data line 16 consists of fifteen 8-bit words. The contents of the information is shown in Fig.2, a
timing diagram of the data line in Fig.3 and a survey of VTR control labels in Fig.4.
From the total fifteen 8-bit words, the SAF1135 extracts words 5, 11, 12, 13 and 14. The contents of these words can be
requested via the built-in I2C bus interface (see Fig.9). The circuit is fully transparent, thus each bit is transferred without
modification. Only the sequence of the words is changed; words 11 to 14 being transmitted first followed by word 5.
By evaluation of the Video Composite Sync (VCS) signal at pin 12 the SAF1135 identifies the beginning of line 16 in the
first field. The line 16 decoder stage releases the start code detector. When a correct start code is detected (for timing
of start code detection, see Fig.5) words 5 and 11 to 14 are decoded, checked for biphase errors and stored in register
bank R (Receive). If no biphase error has occurred, the contents of register bank R are transferred to register bank T
(Transmit) by the data valid control signal (DAVID). If the system has been addressed, this transfer is delayed until the
next start or stop condition of the I2C bus has been received.
The last correct data line information remains available until it is read via the I2C bus. After it is read once the stored
information is no longer considered to be valid, the internal new data flag (NWDAT) is reset and if the circuit is addressed,
the only VPS data sent back is “FFF...F”. The same conditions apply after power-up. Then no data can be read out.
New data is available after reception of another error-free line 16.
Power-on Reset
Reset pulses applied externally to pin 5 (RESET; active LOW) are latched internally by the power-on reset circuit.
RESET = LOW influences:
• I2C bus logic to no acknowledge
• NWDAT flag and internal timing to reset
• Data available output (DAV; active LOW) at pin 6 forced to LOW
• Data reset output (DAR) at pin 13 forced to HIGH
• Serial data (SDA) input/output at pin 3 released
When RESET changes to HIGH the reset period is terminated with the next negative-going transition of the data line
clock (DLCL) input at pin 11. Then, the data available (DAV) output at pin 6 will go HIGH.
When an external reset is not used pin 5 is connected to VDD. If an external reset is required, the rise time (tr) of RESET
voltage must be greater than 50 µs. An external 10 kΩ resistor connected between pin 5 and VDD and an external 2,7 nF
capacitor connected to VSS will result in tr ≥ 50 µs.
August 1986
4
Philips Semiconductors
Product specification
Data line decoder
SAF1135
WORD
CONTENT
1
Run in
2
Start code
3
Program source identification (binary coded)
Program source identification (ASCII sequential)
Sound and VTR control information
Program/Test picture identification
4
5
6
7
Internal information exchange
8
Address assignment of signal distribution
Messages/Commands
9
10
11
12
13
14
15
VTR Control Information
Reserve
Fig.2 Total information of data line 16.
Fig.3 Timing diagram of data line 16; modulation depth 71,4%.
August 1986
5
Philips Semiconductors
Product specification
Data line decoder
SAF1135
Where:
X = 0 or 1 (bit)
NC is the Nation Code
PC is the Program Source Code
Fig.4 VTR control information of data line 16.
Fig.5 Timing diagram of start code detection.
August 1986
6
Philips Semiconductors
Product specification
Data line decoder
SAF1135
Fig.6 Timing diagram of the data reset pulse generation.
Fig.7 Timing diagram of the data available output and word latch pulses.
August 1986
7
Philips Semiconductors
Product specification
Data line decoder
SAF1135
Data line data and clock inputs (DLD; DLCL)
The data line data and clock signals from the SAA5235 are input at pins 8 and 11 respectively. The data transmission is
biphase modulated, the bit transfer rate is 2,5 Mbit/s and the clock frequency is 5 MHz.
Input DLD incorporates an internal active clamping circuit. DLCL is internally a.c. coupled.
Video composite sync input (VCS)
The VCS input pulse at pin 12 is used for:
• Generation of the data reset pulse (DAR)
• Identification of the first field
• Selection of line 16
The timing of the data reset pulse generation is shown in Fig.6.
I2C bus address inputs (A0; A1)
The two I2C address inputs at pins 4 and 1 respectively, provide the four different addresses 20H, 22H, 24H and 26H.
Data reset output (DAR)
The DAR output at pin 13 is a line frequency pulse with a 0,88 duty factor derived from the VCS pulse. The DAR pulse
is fed to the SAA5235 to reset the data slicer circuit and the clock phase detector circuit.
Data available output (DAV)
The DAV active LOW output at pin 6 is set to LOW after reception of one error-free data line 16. DAV returns to HIGH
after at the beginning of the next first field.
If no valid data is available DAV remains HIGH. However, a short duration (100 ns) pulse inserted at the beginning of
line 16 ensures that a HIGH-to-LOW transition occurs, which can be used for triggering.
The timing of DAV output and word latch pulses is shown in Fig.7.
I2C bus
The internally latched data from words 5 and 11 to 14 can be clocked out via the I2C interface by a bus master. The lines
are the serial clock input (SCL) at pin 2 and the serial data input/output (SDA) at pin 3.
The SAF1135 can operate only as a slave transmitter on the bus.
Data format is shown in Fig.8.
Fig.8 I2C bus data format.
• The MSB of each word is transmitted first.
• There is no restriction on the number of words to be transmitted, but if more than five words are requested, word 5 will
be repeated.
• Noise pulses less than 200 ns duration are ignored on the bus lines.
August 1986
8
Philips Semiconductors
Product specification
Data line decoder
SAF1135
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage range (pin 14)
Supply current (pin 14)
VDD
IDD
ISS
VI
−0,5 to +7,0
max.
V
20
20
mA
mA
V
Supply current (pin 7)
max.
Input voltage (pins 8 and 11)
Input voltage on all other pins
Input current
−0,5 to +12
−0,5 to VDD +0,5(1)
VI
V
±II
max.
10
mA
mA
mW
mW
°C
Output current
±IO
Ptot
P
max.
10
Power dissipation per package(2)
Power dissipation per output
Storage temperature range
Operating ambient temperature range
max.
400
100
max.
Tstg
Tamb
−65 to +150
0 to +70
°C
Notes
1.
VDD +0,5 not to exceed 7,0 V.
2. Above +60 °C: derate linearly with 8 mW/K.
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see ‘Handling MOS devices’).
August 1986
9
Philips Semiconductors
Product specification
Data line decoder
SAF1135
D.C. CHARACTERISTICS
VDD = 5 V ± 10%; Tamb = 0 to 70 °C; unless otherwise specified
PARAMETER
Supply (pin 14)
CONDITIONS
SYMBOL
MIN.
TYP.
MAX. UNIT
Supply voltage
Supply current
−
VDD
IDD
4,5
5
5,5
10
V
Quiescent at 25 °C
All inputs at VDD or VSS
RESET at VSS
−
−
µA
TEST 1 and TEST 2 at VDD
IO = 0 mA
During normal operation
(without LED at DAV,
IDD
−
1
−
mA
VDD = 5 V)
Inputs
A0, A1, TEST 1, TEST 2,
SCL
Input voltage LOW
Input voltage HIGH
Leakage current
DLCL
VIL
VIH
ILI
−
−
−
−
0,2VDD
V
0,7VDD
−
V
−
1
µA
Input voltage
Leakage current
RESET
Clock internally a.c. coupled VI
−
−
−
−
12
10
V
VI = 0 to 10 V
ILI
µA
During normal operation
pin 5 connected to VDD
Input voltage LOW
Input voltage HIGH
Input current HIGH
Leakage current
VCS
VIL
VIH
IIH
−
−
−
−
−
0,3VDD
V
0,9VDD
−
V
−
−
15
10
µA
µA
ILI
Input voltage LOW
Input voltage HIGH
Leakage current
VIL
VIH
ILI
−
−
−
−
0,8
−
V
2,0
−
V
1
µA
August 1986
10
Philips Semiconductors
Product specification
Data line decoder
SAF1135
PARAMETER
CONDITIONS
SYMBOL
MIN.
TYP.
MAX. UNIT
Inputs/Outputs
DLD
Internal active clamping
circuit, open drain output
Input voltage LOW
Input voltage HIGH
Leakage current
Output voltage LOW
SDA
VIL
−
−
−
−
−
0,9
12
1
V
VIH
ILI
2,0
−
V
µA
V
IOL = 4 mA
VOL
−
0,4
open drain output
Input voltage LOW
Input voltage HIGH
Leakage current
Output voltage LOW
VIL
VIH
ILI
−
−
−
−
−
0,9
−
V
3,15
−
V
VDD = 6 V; VI = 0 or VDD
IOL = 4 mA
6
µA
V
VOL
−
0,4
Outputs
DAR
Output voltage LOW
Output voltage HIGH
DAV
IOL = 1 mA
VOL
VOH
−
−
−
0,4
V
V
−IOH = 400 µA
V
DD−0,5 V
−
Output voltage LOW
Output voltage HIGH
IOL = 10 mA
VOL
VOH
−
−
−
1,0
V
V
−IOH = 400 µA
V
DD−0,5 V
−
August 1986
11
Philips Semiconductors
Product specification
Data line decoder
SAF1135
A.C. CHARACTERISTICS
VDD = 5 V ± 10%; Tamb = 0 to 70 °C; unless otherwise specified
PARAMETER
CONDITIONS
SYMBOL
MIN.
TYP.
MAX. UNIT
Inputs
Input capacitance
A0, A1, TEST 1, TEST 2, SCL
Rise time
CI
tr
−
−
−
10
pF
VIL(max) to VIH(min)
50
−
µs
DLCL
Clock frequency
Input voltage
DLD
sinusoidal input signal
peak-to-peak value
fDLCL
−
5
−
−
MHz
V
VI(p-p)
1
−
Coupling capacitor
Set-up time
CEXT
tSU
−
1
−
−
4,7
−
nF
ns
ns
relative to rising edge of DLCL
relative to rising edge of DLCL
40
40
Hold-up time
tHD
−
Outputs
DAR, DAV
Rise and fall times
DAR-time LOW
SDA
CL = 50 pF
tr, tf
−
−
−
50
ns
tDAR,L
7,8
−
µs
Fall time
CL = 400 pF
tf
−
−
300
ns
I2C bus - Input/Output
For both SDA and SCL valid
Input current HIGH
0,9 VDD, including ILI of
possible output stage
IIH
−
−
10
µA
Input capacitance
Rise time
CI
−
−
−
−
−
−
−
10
1
pF
µs
tr
−
Fall time
tf
−
0,3
100
−
µs
Clock frequency
Pulse duration LOW
Pulse duration HIGH
fCL
tLOW
tHIGH
−
kHz
µs
4,7
4,0
−
µs
August 1986
12
Philips Semiconductors
Product specification
Data line decoder
SAF1135
APPLICATION INFORMATION
Fig.9 Data line receiver.
August 1986
13
Philips Semiconductors
Product specification
Data line decoder
SAF1135
PACKAGE OUTLINE
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
2
(1)
(1)
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.10
7.62
0.30
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.020
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-03-11
SOT27-1
050G04
MO-001AA
August 1986
14
Philips Semiconductors
Product specification
Data line decoder
SAF1135
time of successive solder waves must not exceed
5 seconds.
SOLDERING
Introduction
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Repairing soldered joints
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
August 1986
15
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