TDA1309HB-S [PHILIPS]
Consumer Circuit, PQFP44;
| 型号： | TDA1309HB-S |
| 厂家： | 
PHILIPS SEMICONDUCTORS |
| 描述： | Consumer Circuit, PQFP44 商用集成电路 |
| 文件： | 总24页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA1309H
Low-voltage low-power stereo
bitstream ADC/DAC
1996 Oct 21
Product specification
Supersedes data of 1996 Jun 04
File under Integrated Circuits, IC01
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
FEATURES
• Low power
• Low supply voltage (2.7 V)
• Integrated high-pass filter to cancel DC offset (ADC)
• Analog loop-through function
• Multiple digital input/output formats possible
• 256fs system clock frequency
• Several power-down modes
APPLICATION
• Digital de-emphasis (DAC)
• Portable digital audio equipment.
• Overload detector to enable automatic recording level
adjustment (ADC)
• Input pads suitable for 5.5 V; low supply voltage
GENERAL DESCRIPTION
interfacing
The TDA1309H is a single chip stereo analog-to-digital
and digital-to-analog converter employing bitstream
conversion techniques. The low voltage requirement
makes the device eminently suitable for use in low-voltage
low-power portable digital audio equipment which
incorporates recording and playback functions.
• High dynamic range
• DAC requires only one capacitor for post-filtering
• Small 44-pin quad flat pack with 0.8 mm pitch
• 256fs system clock frequency in Analog-to-Digital (AD)
and Digital-to-Analog (DA) mode
• Choice of three system clock frequencies
(192fs, 256fs or 384fs) in DA mode.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
TDA1309H
QFP44
plastic quad flat package; 44 leads (lead length 1.3 mm);
SOT307-2
body 10 × 10 × 1.75 mm
1996 Oct 21
2
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
QUICK REFERENCE DATA
VDDD = VDDA = VDDO = VDDD(F) = 3 V; VSSD = VSSA = VSSO = VSSD(F) = 0 V; Tamb = 25 °C; full scale sine wave input;
mode 1; fi = 1 kHz; 16-bit input data; conversion rate = 44.1 kHz; measurement bandwidth = 10 Hz to 20 kHz; unless
otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
VDDA(AD)
VDDA(DA)
VDDO
ADC analog supply voltage (pin 8)
DAC analog supply voltage (pin 25)
2.7
2.7
2.7
3.0
3.0
3.0
4.0
4.0
4.0
V
V
V
operational amplifiers supply voltage
(pin 19)
VDDD
ADC and DAC digital supply voltage
(pin 28)
2.7
3.0
4.0
V
VDDD(F)
IDDA(AD)
IDDA(DA)
IDDO
digital filters supply voltage (pin 34)
ADC analog supply current (pin 8)
DAC analog supply current (pin 25)
2.7
−
3.0
8
4.0
V
12.5 mA
−
3.5
12
7
mA
mA
operational amplifiers supply current
(pin 19)
−
18
IDDD
ADC and DAC digital supply current
(pin 28)
−
0.2
0.5
mA
IDDD(F)
IPD(DA)
IPD(AD)
Tamb
digital filters supply current (pin 34)
DAC power-down current
−
20
15
7
30
mA
mA
mA
°C
−
20
ADC power-down current
−
10
operating ambient temperature
−20
−
+75
Analog-to-digital converter
VI(rms)
input voltage (RMS value)
note 1
−
0.5
−85
−35
95
0.54
−80
−30
−
V
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio
at 0 dB
−
dB
dB
dB
dB
at −60 dB; A-weighted
−
S/N
idle channel signal-to-noise ratio
channel separation
VI = 0 V; A-weighted
90
−
αcs
90
−
Digital-to-analog converter
VO(rms)
output voltage (RMS value)
note 2
0.43 0.5
0.57
−82
−34
−
V
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio
at 0 dB
−
−90
−38
−44
104
100
dB
dB
dB
dB
dB
at −60 dB; A-weighted
at −60 dB; A-weighted; note 3
code 0000H; A-weighted
−
−
S/N
idle channel signal-to-noise ratio
channel separation
−
−
αcs
90
−
Notes
1. The input voltage for full scale digital output is a function of VDDA(AD)
.
2. At full scale digital input; no de-emphasis; VO(rms) is a function of VDDA(DA)
3. 18-bit input data.
.
1996 Oct 21
3
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
BLOCK DIAGRAM
GM7E6
o
1996 Oct 21
4
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
PINNING
SYMBOL
ADBCK
PIN
DESCRIPTION
1
ADC input bit clock; 32fs or 64fs
ADC word select input at fs
ADC/DAC mode select input
ADWS
MODE0
ADENB
OVLOAD
ADPON
VSSA(AD)
VDDA(AD)
Vref(neg)
Vref
2
3
4
ADC serial data enable input (active HIGH)
ADC output overload flag (active LOW)
ADC power-on-mode input (active HIGH)
ADC analog ground supply voltage
ADC analog supply voltage
5
6
7
8
9
ADC negative reference voltage input (ground)
ADC decoupling capacitor
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Vref(pos)
BAOL
ADC positive reference voltage decoupling capacitor
ADC input amplifier output left
BAIL
ADC input amplifier virtual ground left
ADC input amplifier virtual ground right
ADC input amplifier output right
BAIR
BAOR
ADref
ADC decoupling capacitor
Iref
ADC/DAC reference current resistor input
DAC decoupling capacitor
DAref
VDDO
ADC/DAC operational amplifier supply voltage
ADC/DAC operational amplifier ground supply voltage
DAC output voltage left
VSSO
VOL
DACL
DAC output current left
DACR
VOR
DAC output current right
DAC output voltage right
VDDA(DA)
VSSA(DA)
VSSD
DAC analog supply voltage
DAC analog ground supply voltage
ADC/DAC digital ground supply voltage
ADC/DAC digital supply voltage
VDDD
DAPON
DADEM
DABCK
DAWS
VSSD(F)
VDDD(F)
DASDA
ANLPTR
TEST0
TEST1
VSS(I/O)
SYSCLK
DAC power-on-mode input (active HIGH)
DAC digital de-emphasis input (active HIGH)
DAC input bit clock; 32fs, 48fs or 64fs
DAC word select input at fs
ADC/DAC digital filters ground supply voltage
ADC/DAC digital filters supply voltage
DAC serial data input
ADC/DAC analog loop-through input (active HIGH)
ADC/DAC enable test mode 0 input (LOW is normal mode)
ADC/DAC enable test mode 1 input (LOW is normal mode)
ADC/DAC digital input/output ground supply voltage
ADC/DAC system clock input (fsys = 256fs; DAC also 192fs and 384fs)
1996 Oct 21
5
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
SYMBOL
ADSDA
PIN
41
42
43
44
DESCRIPTION
ADC serial data output
MODE1
ADC/DAC mode 1 select input
ADC/DAC mode 2 select input
MODE2
CLKEDGE
ADC/DAC input bit clock rising/falling edge
V
1
2
33
32
ADBCK
SSD(F)
ADWS
MODE0
ADENB
DAWS
3
31 DABCK
30 DADEM
29 DAPON
V
4
OVLOAD
ADPON
5
6
28
27
26
25
24
DDD
TDA1309H
V
V
V
V
V
7
SSA(AD)
SSD
V
8
DDA(AD)
SSA(DA)
DDA(DA)
OR
V
9
ref(neg)
V
10
11
ref
V
23 DACR
ref(pos)
MGE765
Fig.2 Pin configuration.
1996 Oct 21
6
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
The digital interfaces accommodates, 16 and 18-bit,
FUNCTIONAL DESCRIPTION
I2S-bus and LSB justified formats. The ADC digital output
can be made 3-state by means of the ADENB signal, this
enables the use of a digital bus.
Figure 1 illustrates the various components of the
TDA1309H.
The analog-to-digital converter is a bitstream type
converter, both channels are sampled simultaneously.
The digital-to-analog converter is a BCC (Bitstream
Continuous Calibration) type converter. The digital filter for
the ADC is a bit serial IIR filter that produces a fairly linear
phase response up to 15 kHz. A high-pass filter is
incorporated in the down-sampling path to remove DC
offsets. An overload detection circuit is incorporated to
facilitate automatic recording level adjustment.
The TDA1309H interface accommodates slave mode only,
therefore, the system ICs must provide the system clock,
bit clock and word clock signals. For the DAC, the
TDA1309H accepts the data together with these clocks,
for the ADC it delivers the data in response to these clocks.
Within one stereo frame, the first sample always
represents the left channel. When sending data the
unused bit positions are set to zero, when receiving data
these bit positions are don't cares.
The digital up-sample filter for the DAC is partly IIR, with
virtual linear phase response up to 15 kHz, and partly FIR.
A switchable digital de-emphasis circuit is also
incorporated. Due to the BCC principle used, the DAC
needs only single pole post-filtering (one external
capacitor) to meet the out-of-band suppression
requirement.
To accommodate the various interface formats and
system clock frequencies four control pins are provided,
MODE0 to MODE2 for mode selection and CLKEDGE
which selects the active edge of the BCK signal. Table 1
gives the interface mode selection, Fig.3 illustrates the
ADC/DAC data formats and Fig.5 the operating modes.
The section of the TDA1309H is designed to
accommodate two main modes:
The ADC and DAC channels have separate power-down
modes, to reduce power if one of them is not in use.
An analog loop-through function enables analog-input
analog-output mode without using the ADC and DAC
converters or filters, thereby switching them off to reduce
power consumption.
1. The 256fs mode in which analog-to-digital and
digital-to-analog can be used
2. The 192fs or 384fs mode (digital-to-analog only).
Table 1 Interface mode selection
DEVICE PIN
ADC/DAC FORMATS
MODE 2
MODE 1
MODE 0
TYPE
BITS
BCK
SYS; fsys
256fs
FIGURE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
LSB justified
LSB justified
LSB justified
LSB justified
I2S-bus
16
16
16
18
16
16
16
18
32fs
64fs
48fs
64fs
32fs
64fs
48fs
64fs
3(a)
3(b)
4(a)
3(c)
3(d)
3(e)
4(b)
3(f)
256fs
(1)
192fs
256fs
256fs
256fs
I2S-bus
I2S-bus
I2S-bus
(1)
384fs
256fs
Note
1. Only digital-to-analog.
Table 2 Clock edge mode
VALID EDGE OF BCK
CLKEDGE
ADC
DAC
0
1
falling
rising
rising
falling
1996 Oct 21
7
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
LSB JUSTIFIED 32f 16-BIT
s
BCK
WS
RIGHT
LEFT
SDA
LSB MSB
LSB MSB
(a)
LSB MSB
LSB JUSTIFIED 64f 16-BIT
s
BCK
WS
RIGHT
MSB
LEFT
MSB
SDA
LSB
LSB
(b)
LSB
LSB JUSTIFIED 64f 18-BIT
s
BCK
WS
RIGHT
LEFT
SDA
LSB
MSB
MSB
LSB
LSB
(c)
2
I S 32f 16-BIT
s
BCK
WS
LEFT
RIGHT
SDA
LSB MSB
LSB MSB
(d)
LSB
2
I S 64f 16-BIT
s
BCK
WS
LEFT
LSB
RIGHT
LSB
SDA
MSB
MSB
(e)
MSB
2
I S 64f 18-BIT
s
BCK
WS
LEFT
RIGHT
SDA
MSB
LSB
MSB
(f)
LSB
MSB
MGE767
Fig.3 DAC and ADC data formats (continued in Fig.4).
8
1996 Oct 21
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
LSB JUSTIFIED 48f 16-BIT
s
BCK
WS
RIGHT
MSB
LEFT
MSB
SDA
LSB
LSB
(a)
LSB
2
I S 48 16-BIT
fs
BCK
WS
LEFT
LSB
RIGHT
LSB
SDA
MSB
MSB
(b)
MSB
MGE768
Fig.4 DAC and ADC data formats (continued from Fig.3).
There are different modes in which the TDA1309H can operate. These modes can be selected as shown in Table 3 and
Fig.5. In mode a, the digital filters clock is switched off. Switching over to one of the ADC active modes (b, c or d) initiates
a reset sequence of the digital filters. This mode should be activated immediately after power-on for at least 2 clock
periods.
Table 3 Operating mode selection
DEVICE PIN LOGIC
MODE
DESCRIPTION
ANLPTR
ADPON
DAPON
a
not used
0
0
0
1
1
0
1
0
0
1
0
0
0
1
1
b
record and playback
record only
1
c
1
d
record and analog loop-through
analog loop-through
playback only
1
e
0
f
0
X(1)
g and h
reserved
Note
1. X = don’t care.
1996 Oct 21
9
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
ADC
DAC
DIGITAL
FILTER
analog
input
analog
output
ADC
DAC
ANALOG
DIGITAL
FILTER
MODE b
MODE c
MODE d
MODE e
MODE f
ANALOG
digital
output
digital
input
ADC
DIGITAL
FILTER
analog
input
digital
output
ADC
ANALOG
ADC
DIGITAL
FILTER
analog
input
digital
output
analog
output
ADC
ANALOG
analog
input
analog
output
DAC
DIGITAL
FILTER
digital
input
analog
output
DAC
ANALOG
MGE771
Fig.5 Schematic diagram of operating modes.
1996 Oct 21
10
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDDA(AD)
VDDA(DA)
VDDO
PARAMETER
analog supply voltage (pin 8)
analog supply voltage (pin 25)
CONDITIONS
MIN.
MAX.
4.5
UNIT
−
−
−
V
V
V
4.5
4.5
operational amplifiers supply voltage
(pin 19)
VDDD
digital supply voltage (pin 28)
−
−
−
−
4.5
4.5
100
100
V
V
VDDD(F)
∆VDD
∆VSS
digital filters supply voltage (pin 34)
maximum supply voltage difference
mV
mV
maximum ground supply voltage
difference
VI
maximum input voltage
−0.5
VDD + 0.5
V
IIK
DC clamp input diode current
VI < −0.5 V or
−
±10
mA
VI > VDD + 0.5 V
IOK
DC output clamp diode current;
(output type 2 mA)
VO < −0.5 V or
VO > VDD + 0.5 V
−
±10
mA
Tstg
Tamb
Ves
storage temperature
−65
+150
+75
°C
°C
V
operating ambient temperature
electrostatic handling
−20
note 1
note 2
−1500
−300
+1500
+300
V
Notes
1. Human body model: C = 100 pF; R = 1.5 kΩ; 3 zaps positive and 3 zaps negative.
2. Machine model: C = 200 pF; L = 0.5 µH; R = 10 Ω; 3 zaps positive and 3 zaps negative.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
60
K/W
QUALITY SPECIFICATION
In accordance with “SNW-FQ-611E”. The number of this quality specification can be found in the “Quality Reference
Handbook”. The handbook can be ordered using the code 9397 750 00192.
1996 Oct 21
11
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
CHARACTERISTICS
VDDD = VDDA = VDDO = VDDD(F) = 3 V; VSSD = VSSA = VSSO = VSSD(F) = 0 V; Tamb = 25 °C; full scale sine wave input;
mode 1; fi = 1 kHz; 16-bit input data; conversion rate = 44.1 kHz; measurement bandwidth = 10 Hz to 20 kHz; unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDDA(AD)
ADC analog supply
voltage (pin 8)
2.7
2.7
2.7
2.7
2.7
3.0
4.0
V
VDDA(DA)
VDDO
DAC analog supply
voltage (pin 25)
3.0
3.0
3.0
3.0
4.0
4.0
4.0
4.0
V
V
V
V
operational amplifiers
supply voltage (pin 19)
VDDD
ADC/DAC digital supply
voltage (pin 28)
VDDD(F)
IDDA(AD)
digital filters supply voltage
(pin 34)
ADC analog supply current
(pin 8)
−
−
−
−
−
−
−
−
−
8
12.5
1
mA
mA
mA
mA
mA
mA
mA
mA
mA
ADC power-down
DAC power-down
0.3
3.5
1.4
12
5.5
7
IDDA(DA)
DAC analog supply current
(pin 25)
7
2
IDDO
operational amplifiers
supply current (pin 19)
18
9
DAC power-down
ADC power-down
11
−
ADC/DAC power-down
0
IDDD
ADC/DAC digital supply
current (pin 28)
0.2
0.5
IDDD(F)
digital filters supply current
(pin 34)
−
−
−
−
20
15
7
30
mA
mA
mA
µA
DAC power-down
ADC power-down
20
10
IDDD(F)q
digital filters quiescent
current
−
100
1996 Oct 21
12
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
SYMBOL
Analog-to-digital converter
VI(rms) input voltage (RMS value) note 1
II
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
−
−
0.5
0.54
V
input current
−
10
nA
(pins 13 and 14)
∆VO
unbalance between
channels
−
−
0.3
dB
RES
resolution
16-bit format
−
16
−
bits
bits
dB
dB
dB
dB
18-bit format
−
18
−
(THD + N)/S total harmonic distortion
plus noise-to-signal ratio
at 0 dB
−
−85
−75
−35
95
−80
−
at −20 dB
−
at −60 dB; A-weighted
Vi = 0 V; A-weighted
−
−30
−
S/N
idle channel
90
signal-to-noise ratio
αcs
channel separation
−
−
90
−
−
dB
dB
PSRR
power supply rejection ratio note 2
−30
Digital-to-analog converter
VO(rms)
output voltage
(RMS value)
note 3
0.43
0.5
0.1
0.57
V
∆VO
unbalance between
channels
−
−
dB
RL
load resistance
load capacitance
resolution
5
−
−
−
−
−
−
−
−
−
kΩ
pF
CL
note 4
−
200
−
RES
16-bit format
18-bit format
at 0 dB
16
bits
bits
dB
dB
dB
dB
18
−
(THD + N)/S total harmonic distortion
plus noise-to-signal ratio
−90
−75
−38
−44
−82
−
at −20 dB
at −60 dB; A-weighted
−34
−
at −60 dB; A-weighted;
note 5
S/N
idle channel
code 0000H; A-weighted
−
104
−
dB
signal-to-noise ratio
αcs
channel separation
90
100
−
−
dB
dB
PSRR
power supply rejection ratio note 2
−
−30
Analog loop-through (mode e)
(THD + N)/S total harmonic distortion
plus noise-to-signal ratio
at 0 dB
−
−
−85
−
−
dB
dB
S/N
idle channel
VI = 0 V; A-weighted
note 1
95
signal-to-noise ratio
Gltr
Eos
loop-through gain
DC offset error
−
−
−1.1
−
−
dB
1.0
mV
1996 Oct 21
13
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog-to-digital decimation filter
fs(o)
fs(i)
fsys
B
output sample frequency
input sample frequency
system clock frequency
signal bandwidth
28
44.1
54
kHz
−
128fs
−
256fs
0.02
60
−
−
−
256fs
20
fs(o) = 44.1 kHz
s(o) − B < fi < 2fs(o) − B;
kHz
dB
Asup
aliasing suppression
f
−
note 6
fi > 2fs(o) − B; note 6
fi = 20 Hz to 20 kHz
note 7
80
−0.2
−
−
−
dB
dB
dB
α
frequency response
−
+0.2
−
OLdet
overload detection level
0.11
Digital-to-analog interpolation filter
fs(o)
fs(i)
fsys
B
output sample frequency
input sample frequency
system clock frequency
signal bandwidth
−
64fs
44.1
−
−
28
54
kHz
256fs
0.02
−0.2
40
256fs
20
fs(i) = 44.1 kHz
−
kHz
dB
α
frequency response
fi = 20 Hz to 20 kHz
−
+0.2
−
SUP
out-of-band suppression
50
dB
Digital part; note 8
INPUTS (PINS 1 TO 4, 6, 29 TO 32, 35 TO 38, 40 AND 42 TO 44)
VIL
LOW level input voltage
LOW level input current
HIGH level input current
−0.5
−
−
−
−
0.3VDDD
10
V
IIL
VI = VSSD
VI = VDDD
−
−
−
µA
µA
pF
IIH
10
CI(max)
maximum input
capacitance
10
INPUTS (PINS 1 TO 4, 6, 29 TO 32, 35 TO 38, 40 AND 42)
VIH HIGH level input voltage
0.7VDDD
0.7VDDD
−
−
−
5.5
V
V
INPUTS (PINS 43 AND 44)
VIH
HIGH level input voltage
VDDD + 0.5
OUTPUTS (PINS 5 AND 41)
VOL
VOH
IOZ
LOW level output voltage
IOL = 2 mA
−
−
−
0.5
−
V
HIGH level output voltage
3-state leakage current
IOH = −2 mA
VDDD − 0.5
V
VO = VDDD or VSSD
−
10
µA
1996 Oct 21
14
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
SYMBOL
Timing
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
BIT CLOCK (BCK) RELATED SIGNALS (see Fig.6); CLKEDGE = 0
Tcy
tHC
tLC
tr
clock period
clock HIGH time
clock LOW time
rise time
300
100
100
−
−
−
−
−
−
−
−
ns
−
ns
ns
ns
ns
ns
−
20
20
−
tf
fall time
−
tsuWS
set-up time WS to rising
edge of BCK
20
thWS
tsuDA
thDA
thAD
tdAD
hold time WS to rising edge
of BCK
0
−
−
−
−
−
−
ns
ns
ns
ns
ns
set-up time SDA (DAC) to
rising edge of BCK
20
0
−
hold time SDA (DAC) to
rising edge of BCK
−
hold time SDA (ADC) to
falling edge of BCK
0
−
delay time SDA (ADC) to
falling edge of BCK
−
80
SYSTEM CLOCK (SYSCLK) RELATED SIGNALS (see Fig.7)
Tcy
tHC
tLC
tr
clock period
clock HIGH time
clock LOW time
rise time
72
22
22
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
−
−
10
10
tf
fall time
−
Notes
1. VI for full scale digital output is a function of VDDA(AD), 0.5 V (RMS) (at 3 V the digital voltages are equivalent to
−1.1 dB in the digital domain).
2. Vripple = 1% of the supply voltage and fripple = 100 Hz.
3. At full scale digital input; no de-emphasis; VO(rms) is a function of VDDA(DA)
.
4. For a load capacitance greater than 33 pF a series resistor of 200 Ω is recommended.
5. 18 bits input data.
6. The aliasing suppression frequency is mirrored around 128fs.
7. VDDA = 3 V; indicated digital level is with respect to −1.1 dB (no overload).
8. All digital voltages = 2.7 to 4.0 V; all ground supply voltages = 0 V; Tamb = −20 to +75 °C.
1996 Oct 21
15
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
T
cy
t
t
LC
HC
CLKEDGE = 1
V
H
BCK
V
L
CLKEDGE = 0
t
t
t
t
hWS
f
r
suWS
WS (LRCK)
t
t
suDA
hDA
SDA (DAC)
t
dAD
t
hAD
SDA (ADC)
MGE769
Fig.6 Serial timing of BCK related signals.
1996 Oct 21
16
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
T
cy
t
t
LC
HC
SYSCLK
t
t
f
MGE770
r
Fig.7 Serial timing of SYSCLK related signals.
1996 Oct 21
17
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
PACKAGE OUTLINE
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
y
X
A
33
23
34
22
Z
E
e
Q
H
E
E
A
2
A
(A )
3
A
1
w M
θ
b
p
L
p
pin 1 index
L
12
44
detail X
1
11
w M
Z
v
M
A
D
b
p
e
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
10o
0o
0.25 1.85
0.05 1.65
0.40 0.25 10.1 10.1
0.20 0.14 9.9 9.9
12.9 12.9
12.3 12.3
0.95 0.85
0.55 0.75
1.2
0.8
1.2
0.8
mm
2.10
0.25
0.8
1.3
0.15 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT307-2
1996 Oct 21
18
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
SOLDERING
Introduction
Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• The footprint must be at an angle of 45° to the
board direction and must incorporate solder
thieves downstream and at the side corners.
Reflow soldering
Even with these conditions, do not consider wave
soldering the following packages:
QFP52 (SOT379-1), QFP100 (SOT317-1),
QFP100 (SOT317-2), QFP100 (SOT382-1) or
QFP160 (SOT322-1).
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9398 510 63011).
During placement and before soldering, the package
must be fixed with a droplet of adhesive. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C. When using a dedicated tool, all other leads can
be soldered in one operation within 2 to 5 seconds
between 270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1996 Oct 21
19
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.2
1996 Oct 21
20
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
NOTES
1996 Oct 21
21
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
NOTES
1996 Oct 21
22
Philips Semiconductors
Productspecification
Low-voltage low-power stereo bitstream
ADC/DAC
TDA1309H
NOTES
1996 Oct 21
23
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
517021/1200/04/pp24
Date of release: 1996 Oct 21
Document order number: 9397 750 00879
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