TEA1752T/1791/DB/9_技术文档

TEA1752T

HV start-up DCM/QR flyback controller with integrated

DCM/QR PFC controller

Rev. 2 — 16 November 2012

Product data sheet

1. General description

The TEA1752T is the third generation of green Switched Mode Power Supply (SMPS)

controller ICs. The TEA1752T combines a controller for Power Factor Correction (PFC)

and a flyback controller. Its high level of integration allows the design of a cost-effective

power supply with a very low number of external components.

The special built-in green functions provide high efficiency at all power levels. This

efficiency applies to quasi-resonant operation at high-power levels, quasi-resonant

operation with valley skipping, as well as reduced frequency operation at lower power

levels. At low-power levels, the PFC switches off to maintain high efficiency.

During low-power conditions, the flyback controller switches to frequency reduction mode

and limits the peak current to an adjustable minimum value. This mode ensures high

efficiency at low-power and good standby power performance while minimizing audible

noise from the transformer.

The TEA1752T is a Multi-Chip Module, (MCM), containing 2 chips. The proprietary

high-voltage BCD800 process which makes direct start-up possible from the rectified

universal mains voltage in an effective and green way. The second low voltage

Silicon On Insulator (SOI) is used for accurate, high speed protection functions and

control.

The TEA1752T enables the design of highly efficient and reliable supplies with power

requirements of up to 250 W with a minimum number of external components.

Remark: All values provided throughout the running text, are typical values unless

otherwise stated.

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

2. Features and benefits

2.1 Distinctive features

 Integrated PFC and flyback controller

 Universal mains supply operation (70 V AC to 276 V AC)

 Dual boost PFC with accurate maximum output voltage (NXP patented)

 High level of integration, resulting in a very low external component count and a

cost-effective design

 Adjustable PFC switch-off delay

2.2 Green features

 On-chip start-up current source

2.3 PFC green features

 Valley/zero voltage switching for minimum switching losses (NXP patented)

 Frequency limitation to reduce switching losses

 PFC is switched off when a low load is detected at the flyback output

2.4 Flyback green features

 Valley switching for minimum switching losses (NXP patented)

 Frequency reduction with adjustable minimum peak current at low-power operation to

maintain high efficiency at low output power levels

2.5 Protection features

 Safe restart mode for system fault conditions

 Continuous mode protection with demagnetization detection for both converters (NXP

patented)

 UnderVoltage Protection (UVP) (foldback during overload)

 Accurate OverVoltage Protection (OVP) for both converters (adjustable for flyback

converter)

 Mains voltage independent OverPower Protection (OPP)

 Open control loop protection for both converters. The open-loop protection on the

flyback converter is a safe restart

 OverTemperature Protection (OTP)

 Low and adjustable OverCurrent Protection (OCP) trip level for both converters

 General-purpose input for latched protection, for system OverTemperature Protection

(OTP) for example

3. Applications

 The device is used in all applications that require an efficient and cost-effective power

supply solution for up to 250 W. Notebook adapters in particular can benefit from the

high level of integration

TEA1752T

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 November 2012

2 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

TEA1752T

SO16

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

TEA1752T

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 November 2012

3 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

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Fig 1. Block diagram

TEA1752T

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 November 2012

4 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

6. Pinning information

6.1 Pinning

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Fig 2. Pin configuration: TEA1752T (SOT109-1)

6.2 Pin description

Table 2.

Pin description

Symbol

V_CC

1

Description

supply voltage

ground

GND

2

FBCTRL

FBAUX

3

flyback control input

4

auxiliary winding input for demagnetization timing and flyback OVP

general-purpose protection input

LATCH

5

PFCCOMP

VINSENSE

PFCAUX

VOSENSE

FBSENSE

PFCSENSE

PFCDRIVER

FBDRIVER

PFCTIMER

HVS

6

frequency compensation pin for PFC

mains voltage sense input

7

8

auxiliary winding input for demagnetization timing for PFC

sense input for PFC output voltage

flyback current sense input

9

10

11

12

13

14

15

16

PFC current sense input

PFC gate-driver output

flyback gate-driver output

delay timer pin for PFC on/off control

high-voltage safety spacer, not connected

high-voltage start-up / flyback valley sensing

HV

TEA1752T

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 November 2012

5 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

7. Functional description

7.1 General control

The TEA1752T contains a controller for a power factor correction circuit as well as a

controller for a flyback circuit. A typical configuration is shown in Figure 3.

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Fig 3. A typical configuration of the TEA1752T IC

7.1.1 Start-up and UnderVoltage LockOut (UVLO)

Initially the capacitor on the V_CCpin is charged from the high-voltage mains from the HV

pin.

When V_CCis less than V_trip, the charge current is low. This low current protects the IC if

the V_CCpin is shorted to ground. To ensure a short start-up time, the charge current

greater than V_tripis increased until V_CCreaches V_th(UVLO). When V_CCis between V_th(UVLO)

and V_startup, the charge current goes low again to ensure a low safe restart duty cycle

during fault conditions.

The control logic activates the internal circuitry and switches off the HV charge current

when the voltage on the V_CCpin passes the V_startuplevel. First, the LATCH pin current

source is activated and the soft-start capacitors on the PFCSENSE and FBSENSE pins

are charged. The clamp circuit on the PFCCOMP pin is also activated.

The PFC circuit is activated when the following conditions are met:

• the LATCH pin voltage exceeds the V_en(LATCH)voltage

• the PFCCOMP pin voltage reaches the V_en(PFCCOMP)voltage

• the soft-start capacitor on the PFCSENSE pin is charged

TEA1752T

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 November 2012

6 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

If the soft-start capacitor on the FBSENSE pin is charged, the flyback converter is also

activated. The flyback converter output voltage is then regulated to its nominal output

voltage. The auxiliary winding of the flyback converter takes over the IC supply (see

Figure 4).

If during start-up the LATCH pin does not reach the V_en(LATCH)level before V_CCreaches

V_th(UVLO), it is deactivated. The charge current is then switched on again.

When the flyback converter starts, V_FBCTRLis monitored. If this output voltage does not

reach its intended regulation level within a specified time, the voltage on the FBCTRL pin

reaches the V_to(FBCTRL)level. An error is then assumed and a safe restart is initiated.

When one of the protection functions is activated, both converters stop switching and the

V_CCvoltage drops to V_th(UVLO). A latched protection recharges the capacitor C_VCCusing

the HV pin, but does not restart the converters. To provide safe restart protection, the

capacitor is recharged using the HV pin and the device restarts (see Figure 1).

If OVP of the PFC circuit (V_VOSENSE> V_{OVP(VOSENSE))}occurs, the PFC controller stops

switching until the VOSENSE pin voltage drops to less than V_OVP(VOSENSE). If a mains

undervoltage is detected V_VINSENSE< V_{stop(VINSENSE)}, the PFC controller stops switching

until V_VINSENSE> V_{start(VINSENSE)}again.

When the voltage on the V_CCpin drops below the undervoltage lockout level, both

controllers stop switching and re-enter the safe restart mode. In the safe restart mode, the

driver outputs are disabled and the V_CCpin voltage is recharged using the HV pin.

TEA1752T

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 November 2012

7 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

I

HV

V

startup

V

th(UVLO)

trip

V

CC

V

start(VINSENSE)

en(PFCCOMP)

VINSENSE

V

PFCCOMP

LATCH

V

en(LATCH)

PROTECTION

soft start

PFCSENSE

PFCDRIVER

soft start

FBSENSE

FBDRIVER

FBCTRL

V

to(FBCTRL)

start(fb)

V

VOSENSE

V

O

charging VCC

capacitor

starting

converters

normal

operation

protection

restart

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Fig 4. Start-up sequence, normal operation and restart sequence

7.1.2 Supply management

All internal reference voltages are derived from a temperature compensated and trimmed

on-chip band gap circuit. Internal reference currents are derived from a temperature

compensated and trimmed on-chip current reference circuit.

7.1.3 Latch input

The LATCH pin is a general-purpose input pin, which is used to switch off both converters.

The pin sources a current I_O(LATCH)of 80 A. Switching is stopped as soon as the voltage

on the latch pin drops below 1.25 V.

TEA1752T

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Product data sheet

Rev. 2 — 16 November 2012

8 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

At initial start-up, switching is stopped until the capacitor on the LATCH pin is charged

above 1.35 V. No internal filtering is done on this pin. An internal Zener clamp of 2.9 V

protects this pin from excessive voltages.

7.1.4 Fast latch reset

In a typical application, the mains is interrupted briefly to reset the latched protection. The

PFC bus capacitor, C_bus, does not have to discharge for this latched protection to reset.

When the VINSENSE voltage drops below 750 mV and is then raised to 870 mV, the

latched protection is reset.

The latched protection is also reset by removing both the voltage on the V_CCand HV pins.

7.1.5 Overtemperature protection

An accurate internal temperature protection is provided in the circuit. When the junction

temperature exceeds the thermal shut-down temperature, the IC stops switching. While

OTP is active, the capacitor C_VCCis not recharged from the HV mains. If the V_CCsupply

voltage is not sufficient, the OTP circuit is supplied from the HV pin.

OTP is a latched protection. It is reset by removing the voltage on the V_CCand HV pins or

by the fast latch reset function (see Section 7.1.4).

7.2 Power factor correction circuit

The power factor correction circuit operates in quasi-resonant or Discontinuous

Conduction Mode (DCM) with valley switching. The next primary stroke is only started

when the previous secondary stroke has ended and the voltage across the PFC MOSFET

has reached a minimum value. V_PFCAUXis used to detect transformer demagnetization

and the minimum voltage across the external PFC MOSFET switch.

7.2.1 t_oncontrol

The power factor correction circuit is operated in t_oncontrol. The resulting mains harmonic

reduction is well within the class-D requirements.

7.2.2 Valley switching and demagnetization (PFCAUX pin)

The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry

connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the

voltage across the PFC MOSFET. To reduce switching losses and electromagnetic

Interference (EMI), the next stroke is started if the voltage across the PFC MOSFET is at

its minimum (valley switching).

If a demagnetization signal is not detected on the PFCAUX pin, the controller generates a

Zero Current Signal (ZCS). This ZCS occurs 50 s after the last PFCGATE signal.

If a valley signal is not detected on the PFCAUX pin, the controller generates a valley

signal 4 s after demagnetization is detected.

To protect the internal circuitry during lightning events, for example, add a 5 k series

resistor to PFCAUX. To prevent incorrect switching due to external disturbance, place the

resistor close to the IC on the printed-circuit board.

TEA1752T

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 November 2012

9 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

7.2.3 Frequency limitation

To optimize the transformer and minimize switching losses, the switching frequency is

limited to f_sw(PFC)max. If the frequency for quasi-resonant operation is above the f_sw(PFC)max

limit, the system switches over to DCM. The PFC MOSFET is only switched on at a

minimum voltage across the switch (valley switching).

7.2.4 Mains voltage compensation (VINSENSE pin)

The equation for the transfer function of a power factor corrector contains the square of

the mains input voltage. In a typical application this results in a low bandwidth for low

mains input voltages and a high bandwidth for high mains input voltages.

To compensate for the mains input voltage influence, the TEA1752T contains a correction

circuit. The average input voltage is measured using the VINSENSE pin and the

information is fed to an internal compensation circuit. Using this compensation, it is

possible to keep the regulation loop bandwidth constant over the mains input range. This

feature yields a fast transient response on load steps, while still complying with class-D

MHR requirements.

In a typical application, a resistor and two capacitors on the PFCCOMP pin set the

bandwidth of the regulation loop.

7.2.5 Soft start-up (PFCSENSE pin)

To prevent audible transformer noise at start-up or during hiccup, the soft-start function

slowly increases the transformer peak current. This increase is achieved by inserting R_SS1

and C_SS1between the PFCSENSE pin and current sense resistor R_SENSE1. An internal

current source charges the capacitor to:

V_PFCSENSE= I_{startsoftPFC} R_SS1

(1)

The voltage is limited to V_{start(soft)PFC}

.

The start level and the time constant of the increasing primary current level are adjusted

externally by changing the values of R_SS1and C_SS1

.

(2)

soft–start = 3  R_SS1 C_SS1

The charging current I_{start(soft)PFC}flows as long as V_PFCSENSEis less than 0.5 V. If

V

_PFCSENSEexceeds 0.5 V, the soft-start current source starts limiting current I_{start(soft)PFC}.

When the PFC starts switching, the I_{start(soft)PFC}current source is switched off (see

Figure 5).

Resistor R_SS1and capacitor C_SS1are also used to prevent audible noise, when the PFC is

switched off by performing a soft stop.

TEA1752T

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 November 2012

10 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

ꢁ

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ꢄ

ꢛꢃꢜꢛꢃ/

ꢀꢀꢀꢁꢂꢂꢅꢉꢄꢉ

Fig 5. Soft start-up of PFC

7.2.6 Low-power mode

When the output power of the flyback converter (see Section 7.3) is low, the flyback

converter switches over to frequency reduction mode. When the maximum switching

frequency of the flyback drops below 48 kHz, the power factor correction circuit is

switched off to maintain high efficiency. Connect a capacitor to the PFCTIMER pin to delay

switching off (see Section 7.2.7).

During low-power mode operation, the PFCCOMP pin is clamped to a minimum voltage of

3.5 V and a maximum voltage of 3.9 V. The lower clamp voltage limits the maximum

power that is delivered when the PFC is switched on again. The upper clamp voltage

ensures that the PFC returns to its normal regulation point in a limited time when returning

from low-power mode.

When the flyback converter frequency exceeds 86 kHz, the power factor correction circuit

restores normal operation.

7.2.7 PFC off delay (PFCTIMER pin)

When the flyback converter maximum frequency drops below 48 kHz, the PFC is

switched off. The IC then outputs a 10 A current to the PFCTIMER pin. When the voltage

on the PFCTIMER pin reaches 3.6 V, the PFC is switched off by performing a soft-stop.

When the flyback converter frequency exceeds 86 kHz, a switch discharges the

PFCTIMER pin capacitor. When the voltage on the PFCTIMER pin drops below 1.27 V,

the PFC is switched on (see Figure 6).

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/ꢇꢅ3'

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ꢘꢊꢋꢌꢅꢏꢔꢚꢅꢅꢅꢅꢅ

9

$ꢏ:ꢅꢍꢏ:ꢑꢎ

/-,>ꢅꢕ

/ꢉ ꢊꢋꢌꢀꢁꢂꢃꢄ

ꢀꢀꢀꢁꢂꢂꢃꢇꢂꢉ

Fig 6. PFC start/stop via PPFCTIMER pin

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Product data sheet

Rev. 2 — 16 November 2012

11 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

7.2.8 Dual-boost PFC

The mains input voltage modulates the PFC output voltage. The mains input voltage is

measured using the VINSENSE pin. If the voltage on the VINSENSE pin drops below

2.2 V, the current is sourced from the VOSENSE pin. To ensure stable switch-over, a

200 mV transition region is inserted around the 2.2 V (see Figure 7).

At low VINSENSE input voltages, the output current is 15 A. This output current, in

combination with the resistors on the VOSENSE pin, sets the lower PFC output voltage

level at low mains voltages. At high mains input voltages, the current switches to zero.

The PFC output voltage is then at its maximum. As this current is zero in this situation, it

does not affect the accuracy of the PFC output voltage.

To ensure proper switch-off, the VOSENSE current switches to its maximum value of

15 A when V_VOSENSEdrops below 2.1 V.

,-,ꢅꢕ

ꢕ

ꢕꢁꢜꢛꢃꢜꢛꢃ

</ꢆꢅ3'

ꢁ

ꢁꢘꢕꢖꢛꢃꢜꢛꢃꢚ

ꢀꢀꢀꢁꢂꢂꢃꢃꢇꢇ

Fig 7. Voltage to current transfer function for dual boost PFC

7.2.9 Overcurrent protection (PFCSENSE pin)

The maximum peak current is limited cycle-by-cycle by sensing the voltage across an

external sense resistor, R_SENSE1, on the source of the external MOSFET. The voltage is

measured using the PFCSENSE pin.

7.2.10 Mains undervoltage lockout/brownout protection (VINSENSE pin)

To prevent the PFC from operating at very low mains input voltages, the voltage on the

VINSENSE pin is continuously sensed. When the voltage on this pin drops below the

V

_{stop(VINSENSE)}level, switching of the PFC is stopped.

The voltage on the VINSENSE pin is clamped to a minimum value, V_{start(VINSENSE)}



V_pu(VINSENSE). This voltage clamping provides for a fast restart when the mains input

voltage is restored after a mains dropout.

7.2.11 Overvoltage protection (VOSENSE pin)

To prevent output overvoltage during load steps and mains transients, an overvoltage

protection circuit is built in.

When the voltage on the VOSENSE pin exceeds the V_OVP(VOSENSE)level, switching of the

power factor correction circuit is stopped. Switching of the PFC recommences when the

VOSENSE pin voltage drops below the V_OVP(VOSENSE)level again.

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Product data sheet

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12 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

When the resistor between the VOSENSE pin and ground is open, the overvoltage

protection is also triggered.

7.2.12 PFC open-loop protection (VOSENSE pin)

The power factor correction circuit does not start switching until the voltage on the

VOSENSE pin is greater than the V_{th(ol)(VOSENSE)}level. This feature protects the circuit

from open-loop and VOSENSE short-circuit.

7.2.13 Driver (PFCDRIVER pin)

The driver circuit to the gate of the power MOSFET has a current sourcing capability of

500 mA and a current sink capability of 1.2 A. These capabilities permit fast turn-on and

turn-off of of the power MOSFET for efficient operation.

7.3 Flyback controller

The TEA1752T includes a controller for a flyback converter. The flyback converter

operates in quasi-resonant or DCM with valley switching. The auxiliary winding of the

flyback transformer provides demagnetization detection and powers the IC after start-up.

7.3.1 Multimode operation

The TEA1752T flyback controller operates in several modes (see Figure 8).

flyback

switching

frequency

125 kHz

frequency

reduction

86 kHz

PFC off

PFC on

48 kHz

discontinuous

with valley

switching

I

pmin

quasi-resonant

adjust

output power

014aaa745

Fig 8. Multimode operation flyback

At high output power the converter switches to quasi-resonant mode. The next converter

stroke starts after demagnetization of the transformer and detection of the valley. In

quasi-resonant mode switching losses are minimized. This minimization is achieved by

the converter only switching on when the voltage across the external MOSFET is at its

minimum (see Section 7.3.2).

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Product data sheet

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TEA1752T

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HV start-up flyback controller with integrated PFC controller

To prevent high frequency operation at low loads, the maximum switching frequency is

limited to 125 kHz. When the frequency limit is reached, the quasi-resonant operation

changes to DCM with valley skipping. The frequency limit reduces the MOSFET switch-on

losses and conducted EMI.

A Voltage Controlled Oscillator (VCO) controls the frequency at very low power and

standby levels. The minimum frequency is reduced to zero. During frequency reduction

mode, the primary peak current is kept at an adjustable minimum level to maintain a high

efficiency. As the primary peak current is low in frequency reduction operation, no audible

noise is noticeable at switching frequencies in the audible range. Valley switching is also

active in this mode.

In frequency reduction mode, the PFC controller is switched off. The flyback maximum

frequency changes linearly with the control voltage on the FBCTRL pin (see Figure 9).

Hysteresis has been added for stable on and off switching of the PFC. At no-load

operation, the switching frequency is reduced to (almost) zero.

The input voltage of the flyback converter and the capacitance on the drain node of the

flyback power switch affect the frequency reduction slope. By choosing the proper

compensation, the frequency reduction slope for high input voltages are chosen as the

same as for low input voltages. This compensation yields an input voltage independent

PFC switch-on and switch-off power level (see the application information in Section 11).

PFC off

PFC on

f

sw(fb)max

frequency

reduction

switching frequency

discontinuous

with valley

switching

quasi resonant

1.5 V

V

FBCTRL

014aaa159

Fig 9. Frequency control of flyback

7.3.2 Valley switching (HV pin)

A new cycle starts when the external MOSFET is switched on. V_FBSENSEand V_FBCTRL

determine the on-time. The MOSFET is then switched off and the secondary stroke starts.

After the secondary stroke, the drain voltage shows an oscillation with a frequency of

approximately:

1

f =

(3)

--------------------------------------------------

2    L_p C_d

TEA1752T

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Product data sheet

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TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

where L_pis the primary self-inductance of the flyback transformer and C_dis the

capacitance on the drain node.

When the internal oscillator voltage is high and the secondary stroke ended, the circuit

waits for the lowest drain voltage before starting a new primary stroke.

Figure 10 shows the drain voltage, valley signal, secondary stroke signal and the internal

oscillator signal.

Valley switching allows high frequency operation as capacitive switching losses are

reduced (see Equation 4). High frequency operation makes small and cost-effective

magnetic components possible.

1

2

--

P =  C  V  f

(4)

d

primary

stroke

secondary

stroke

secondary

ringing

drain

valley

secondary

stroke

(2)

(1)

oscillator

014aaa027

(1) Start of new cycle at lowest drain voltage.

(2) Start of new cycle in a classical Pulse Width Modulation (PWM) system without valley detection.

Fig 10. Signals for valley switching

7.3.3 Current mode control (FBSENSE pin)

Current mode control is used for the flyback converter because of its good line regulation.

The FBSENSE pin senses the primary current across an external resistor and compares it

with an internal control voltage. The internal control voltage is proportional to the FBCTRL

pin voltage (see Figure 11).

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Product data sheet

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TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

The FBSENSE pin outputs a current of 3 A. This current runs through the resistors from

the FBSENSE pin to the sense resistor and creates an offset voltage. The minimum peak

current of the flyback is adjusted using this offset voltage. Adjusting the minimum peak

current level changes the frequency reduction slope (see Figure 8).

V

sense(fb)max

0.65 V

FBSENSE

offset voltage

PFC off PFC on

flyback

frequency

reduction

SENSE resistor

peak voltage

flyback

discontinuous

or QR

FBSENSE

peak voltage

flyback

cycle skip

mode

0.325 V

1.5 V 2.0 V

V

FBCTRL

014aaa747

Fig 11. Peak current control of flyback part

7.3.4 Demagnetization (FBAUX pin)

The system is always in QR or DCM mode. The internal oscillator does not start a new

primary stroke until the previous secondary stroke has ended.

Demagnetization features a cycle-by-cycle output short-circuit protection by immediately

lowering the frequency (longer off-time), thus reducing the power level.

Demagnetization recognition is suppressed during the first t_{sup(xfmr_ring)}time of 2 s. This

suppression is necessary at low output voltages and at start-up. It can also be required in

applications where the transformer has a large leakage inductance.

If the FBAUX pin is open-circuit or not connected, a fault condition is assumed and the

converter immediately stops. Operation restarts as soon as the fault condition is removed.

7.3.5 Flyback control/time-out (FBCTRL pin)

The FBCTRL pin is connected to an internal voltage source of 3.5 V using an internal

resistor of 3 k. When the voltage on this pin exceeds 2.5 V, the connection is disabled

and the pin is biased with a small current. If the voltage on this pin exceeds 4.5 V, a fault is

assumed, switching is stopped and a restart is made.

If a capacitor and a resistor are connected in series to this pin, a time-out function is

created to protect against an open control loop. See Figure 12 and Figure 13. The

time-out function is disabled by connecting a resistor (100 k) to ground on the FBCTRL

pin.

If the pin is short-circuited to ground, switching of the flyback controller is prevented.

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Product data sheet

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TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

Under normal operating conditions, the converter regulates the output voltage. The

voltage on the FBCTRL pin then varies between 1.3 V for the minimum output power and

2 V for the maximum output power.

2.5 V

3.5 V

30 μA

4.5 V

3 kΩ

FBCTRL

time-out

014aaa049

Fig 12. Time-out protection circuit

4.5 V

2.5 V

V

FBCTRL

output

voltage

intended output

voltage not

reached within

time-out time.

restart

intended output voltage

reached within time-out

time.

014aaa050

Fig 13. Time-out protection (signals), safe restart

7.3.6 Soft-start-up (FBSENSE pin)

To prevent audible transformer noise during start-up, the soft-start function slowly

increases the transformer peak current. This increase is achieved by inserting a resistor

and a capacitor between the FBSENSE and the current sense resistor.

An internal current source charges the capacitor to:

V = I_{startsoftfb} R_SS2

(5)

with a maximum of approximately 0.63 V.

The start level and the time constant of the increasing primary current level are adjusted

externally by changing the values of R_SS2and C_SS2

.

soft–start = 3  R_SS2 C_SS2

(6)

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Product data sheet

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TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

The soft-start current I_{start(soft)fb}switches on as soon as V_CCreaches V_startup. When

_FBSENSEhas reached 0.63 V, the flyback converter starts switching.

V

The charging current I_{start(soft)(FB)}flows as long as V_FBSENSEis less than approximately

0.63 V. If V_FBSENSEexceeds 0.63 V, the soft-start current source starts limiting the current.

After the flyback converter has started, the soft-start current source is switched off.

ꢛ,

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ꢖꢌꢊ

ꢏꢒꢍꢅ$ꢑ!ꢑ$

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ꢄ

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ꢀꢀꢀꢁꢂꢂꢅꢉꢉꢇ

Fig 14. Soft start-up of flyback.

7.3.7 Maximum on-time

The flyback controller limits the on-time of the external MOSFET to 40 s. When the

on-time is longer than 40 s, the IC stops switching and enters the safe restart mode.

7.3.8 Overvoltage protection (FBAUX pin)

An output overvoltage protection is implemented in the GreenChip III series. In the

TEA1752T, the auxiliary voltage is sensed using the current flowing into the FBAUX pin

during the secondary stroke. The auxiliary winding voltage is a well-defined replica of the

output voltage. An internal filter averages voltage spikes.

An internal up-down counter prevents false OVP detection which can occur during ESD or

lightning events. The internal counter counts up by one when the output voltage exceeds

the OVP trip level within one switching cycle. The internal counter counts down by two

when the output voltage has not exceeded the OVP trip level within one switching cycle.

When the counter has reached eight, the IC assumes a true OVP, sets the latched

protection and switches off both converters.

The converter only restarts after the OVP latch is reset. In a typical application, the

internal latch is reset when the VINSENSE voltage drops below 750 mV and is then raised

to 870 mV.

The latched protection is also reset by removing both the voltage on the VCC and HV

pins.

The demagnetization resistor, R_FBAUXsets the output voltage V_o(OVP)at which the OVP

function trips:

N_s

----------

V_oOVP

=

I_{ovpFBAUX} R_FBAUX+ V_{clampFBAUX}

(7)

N_aux

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Product data sheet

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18 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

where N_sis the number of secondary turns and N_auxis the number of auxiliary turns of the

transformer. Current I_ovp(FBAUX)is internally trimmed.

Accurate OVP detection is made possible by adjusting the value of R_FBAUXto the turns

ratio of the transformer.

7.3.9 Overcurrent protection (FBSENSE pin)

The primary peak current in the transformer is measured accurately cycle-by-cycle using

the external sense resistor R_sense2. V_fbctrlsets the level to which the OCP circuit limits

V_FBSENSE(see Section 7.3.3). The OCP detection is suppressed during the leading-edge

blanking period, t_leb, to prevent false triggering due to switch-on spikes.

t

leb

OCP level

V

FBSENSE

t

014aaa022

Fig 15. OCP leading edge blanking

7.3.10 Overpower protection

During the primary stroke of the flyback converter, the input voltage is measured by

sensing the current drawn from the FBAUX pin.

The current information is used to limit the maximum peak current of the flyback converter,

measured from the FBSENSE pin. The internal compensation is such that a maximum

output power, which is almost independent of the input voltage, is realized.

The OPP curve is given in Figure 16.

V

FBSENSE

(V)

0.65

0.46

−360

−100

0

I

(μA)

FBAUX

014aaa749

Fig 16. Overpower protection curve

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Product data sheet

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TEA1752T

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HV start-up flyback controller with integrated PFC controller

7.3.11 Driver (FBDRIVER pin)

The driver circuit to the power MOSFET gate has a current sourcing capability of 500 mA

and a current sink capability of 1.2 A. These capabilities permit fast turn-on and turn-off of

the power MOSFET, thus ensuring efficient operation.

8. Limiting values

Table 3.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Voltages

V_CC

Parameter

Conditions

Min

Max

Unit

supply voltage

0.4

+38

+5

V

V_LATCH

V_FBCTRL

voltage on the LATCH pin

voltage on the FBCTRL pin

current limited

+5

V_PFCCOMPvoltage on pin PFCCOMP

+5

V_VINSENSEvoltage on the VINSENSE

0.4

+5

V

V_VOSENSEvoltage on the VOSENSE

V_PFCAUX

voltage on the PFCAUX pin

25

+25

+5

V

V_FBSENSEvoltage on the FBSENSE pin current limited

0.4

V_PFCSENSEvoltage on the PFCSENSE

current limited

+5

V_PFCTIMERvoltage on the PFCTIMER

0.4

+5.5

V

V_HV

voltage on the HV pin

+650

Currents

I_FBCTRL

I_FBAUX

current on the FBCTRL pin

current on the FBAUX pin

3

1

0

mA

+1

+10

I_PFCSENSEcurrent on the PFCSENSE

I_FBSENSE

current on the FBSENSE pin

1

+10

+2

mA

A

I_FBDRIVERcurrent on the FBDRIVER

duty cycle < 10 %

0.8

I_PFCDRIVERcurrent on the PFCDRIVER duty cycle < 10 %

0.8

+2

8

A

I_HV

current on the HV pin

-

mA

General

P_tot

total power dissipation

storage temperature

junction temperature

T_amb< 75 C

-

0.6

W

T_stg

55

40

+150

C

T_j

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Product data sheet

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TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

Table 3.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

ESD

Parameter

Conditions

Min

Max

Unit

V_ESD

electrostatic discharge

voltage

class 1

human body

model

[1]

[2]

pins 1 to 13

pin 16 (HV)

-

2000

1500

200

V

machine model

charged device

model

500

[1] Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

[2] Equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10  resistor.

9. Thermal characteristics

Table 4.

Symbol

R_th(j-a)

Thermal characteristics

Parameter

Conditions

Typ

Unit

thermal resistance from

junction to ambient

in free air; JEDEC test board

124

K/W

R_th(j-c)

thermal resistance from

junction to case

in free air; JEDEC test board

37

K/W

10. Characteristics

Table 5.

Characteristics

T_amb= 25 C; V_CC= 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Start-up current source (HV pin)

I_HV

supply current drawn from

the HV pin

V_HV> 80 V

V_CC< V_trip

;

-

1

-

mA

V_th(UVLO)< V_CC< V_startup

V_trip< V_CC< V_th(UVLO)

with auxiliary supply

-

5.4

20

-

mA

A

V

8

40

-

V_BR

breakdown voltage

650

Supply voltage management (V_CCpin)

V_trip

trip voltage

0.55

21

0.65

22

0.75

23

V

V_startup

V_th(UVLO)

start-up voltage

undervoltage lockout threshold

voltage

14

15

16

V_start(hys)

V_hys

hysteresis of start voltage

hysteresis voltage

during start-up phase

-

300

7

-

mV

V

V_startup V_th(UVLO)

6.3

1.2

7.7

0.8

I_ch(low)

low charging current

V_HV> 80 V; V_CC< V_tripor

V_th(UVLO)< V_CC< V_startup

1.0

mA

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TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

Table 5.

Characteristics …continued

T_amb= 25 C; V_CC= 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol

I_ch(high)

Parameter

Conditions

Min

4.6

2.25

Typ

5.4

3

Max

6.3

3.75

Unit

mA

high charging current

operating supply current

V_HV> 80 V; V_trip< V_CC< V_th(UVLO)

I_CC(oper)

no-load on FBDRIVER and

PFCDRIVER pins

Input Voltage Sensing PFC (VINSENSE pin)

V_{stop(VINSENSE)}

V_{start(VINSENSE)}

V_pu(VINSENSE)

I_pu(VINSENSE)

stop voltage on the VINSENSE

0.86

1.11

-

0.89

1.15

100

47

-

0.92

1.19

-

V

start voltage on the VINSENSE

V

pull-up voltage difference on

the VINSENSE pin

active after V_{stop(VINSENSE)}is

detected

mV

A

V

pull-up current on the

VINSENSE pin

active after V_{stop(VINSENSE)}is

detected

55

4

40

-

V_{mvc(VINSENSE)max}maximum mains voltage

compensation voltage on the

VINSENSE pin

V_flr

fast latch reset voltage

active after V_th(UVLO)is detected

-

0.75

0.12

-

V

V_flr(hys)

hysteresis of fast latch reset

voltage

I_I(VINSENSE)

V_bst(dual)

input current on the VINSENSE V_VINSENSE> V_{stop(VINSENSE)}after

5

33

100

nA

V_{start(VINSENSE)}is detected

current switch-over point

switch-over region

dual boost voltage

-

2.2

-

V

200

mV

Loop compensation PFC (PFCCOMP pin)

g_m

transconductance

V_VOSENSEto I_O(PFCCOMP)

V_VOSENSE= 2 V

60

33

45

-

80

100

45

33

-

A/V

A

V

I_O(PFCCOMP)

output current on the

PFCCOMP pin

39

V_VOSENSE= 3.3 V

39

3.5

V_en(PFCCOMP)

enable voltage on pin

PFCCOMP

[1]

V_{clamp(PFCCOMP)}

clamp voltage on the

PFCCOMP pin

Low-power mode; PFC off; lower

clamp voltage.

-

3.5

-

V

Upper clamp voltage

-

3.9

3.5

-

V

V_{ton(PFCCOMP)zero}zero on-time voltage on the

PFCCOMP pin

3.4

3.6

V_{ton(PFCCOMP)max}maximum on-time voltage on

the PFCCOMP pin

1.20

1.25

1.30

V

Pulse width modulator PFC

t_on(PFC)

PFC on-time

V_VINSENSE= 3.3 V;

V_PFCCOMP= V_{ton(PFCCOMP)max}

3.6

30

4.5

40

5

s

V_VINSENSE= 0.9 V;

53

V_PFCCOMP= V_{ton(PFCCOMP)max}

Output voltage sensing PFC (VOSENSE pin)

V_{th(ol)(VOSENSE)}

open-loop threshold voltage on

the VOSENSE pin

-

1.15

-

V

TEA1752T

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Product data sheet

Rev. 2 — 16 November 2012

22 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

Table 5.

Characteristics …continued

T_amb= 25 C; V_CC= 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_reg(VOSENSE)

regulation voltage on the

VOSENSE pin

for I_O(PFCCOMP)= 0

2.475 2.500 2.525

V

V_ovp(VOSENSE)

I_bst(dual)

overvoltage protection voltage

on the VOSENSE pin

2.60

2.63

15

30

2.67

V

dual boost current

V_VINSENSE< V_bst(dual)or

V_VOSENSE< 2.1 V

-

A

nA

V_VINSENSE> V_bst(dual)

Over current protection PFC (PFCSENSE pin)

V_{sense(PFC)max}

maximum PFC sense voltage V/t = 50 mV/s

V/t = 200 mV/s

0.49

0.51

250

0.52

0.54

310

0.55

0.57

370

V

t_leb(PFC)

PFC leading edge blanking

time

ns

I_{prot(PFCSENSE)}

protection current on the

PFCSENSE pin

50

-

5

nA

Soft-start PFC (PFCSENSE pin)

I_{start(soft)PFC}

V_{start(soft)PFC}

V_{stop(soft)PFC}

Oscillator PFC

f_sw(PFC)max

PFC soft-start current

75

60

45

A

V

PFC soft-start voltage

PFC soft-stop voltage

enabling voltage

disabling voltage

0.46

0.42

0.50

0.45

0.54

0.48

V

maximum PFC switching

frequency

-

250

1.1

-

kHz

t_off(PFC)min

minimum PFC off-time

.

0.8

1.4

s

Valley switching PFC (PFCAUX pin)

(V/t)_vrec(PFC)

PFC valley recognition voltage

-

1.7

V/s

change with time

[2]

[3]

t_vrec(PFC)

PFC valley recognition time

V_PFCAUX= 1 V peak-to-peak

-

300

50

6

ns

s

demagnetization to V/t = 0

-

t_to(vrec)PFC

PFC valley recognition time-out

time

3

4

Demagnetization management PFC (PFCAUX pin)

V_{th(comp)PFCAUX}

t_to(demag)PFC

I_prot(PFCAUX)

comparator threshold voltage

on the PFCAUX pin

150 100 50

mV

s

PFC demagnetization time-out

time

40

50

-

60

protection current on the

PFCAUX pin

V_PFCAUX= 50 mV

75

5

nA

PFC off delay (PFCTIMER pin)

I_{source(PFCTIMER)}

I_{sink(PFCTIMER)}

V_{start(PFCTIMER)}

source current on the

PFCTIMER pin

-

10



-

A

mA

V

sink current on the PFCTIMER V_PFCTIMER= 5 V

0.95

1.27

start voltage on the PFCTIMER

TEA1752T

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Product data sheet

Rev. 2 — 16 November 2012

23 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

Table 5.

Characteristics …continued

T_amb= 25 C; V_CC= 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_{stop(PFCTIMER)}

stop voltage on the PFCTIMER

-

3.6

-

V

Driver (PFCDRIVER pin)

I_{src(PFCDRIVER)}source current on the

V_PFCDRIVER= 2 V

-

0.5

-

A

PFCDRIVER pin

I_{sink(PFCDRIVER)}

sink current on the

PFCDRIVER pin

V_PFCDRIVER= 2 V

V_PFCDRIVER= 10 V

-

0.7

-

A

V

-

1.2

-

V_{O(PFCDRIVER)max}maximum output voltage on the

PFCDRIVER pin

9.5

10.8

12

OverVoltage Protection flyback (FBAUX pin)

I_ovp(FBAUX)

overvoltage protection current

on the FBAUX pin

279

6

300

8

321

12

A

N_cy(ovp)

number of overvoltage

protection cycles

Demagnetization management flyback (FBAUX pin)

V_{th(comp)FBAUX}

comparator threshold voltage

on the FBAUX pin

60

80

-

110

mV

nA

I_prot(FBAUX)

protection current on the

FBAUX pin

V_FBAUX= 50 mV

75

5

V_clamp(FBAUX)

clamp voltage on the FBAUX

I_FBAUX= 100 A

I_FBAUX= 300 A

0.85 0.7

0.55

1.09

2.5

V

0.79

1.5

0.94

2

V

t_{sup(xfmr_ring)}

transformer ringing

suppression time

s

Pulse width modulator flyback

t_on(fb)min

minimum flyback on-time

-

t_leb

40

-

ns

t_on(fb)max

maximum flyback on-time

32

48

s

Oscillator flyback

f_sw(fb)max

maximum flyback switching

frequency

100

125

1.5

150

kHz

V

V_{start(VCO)FBCTRL}

f_{sw(fb)swon(PFC)}

f_{sw(fb)swoff(PFC)}

V_VCO(FBCTRL)

VCO start voltage on the

FBCTRL pin

1.3

1.7

PFC switch-on flyback

switching frequency

-

86

-

kHz

V

PFC switch-off flyback

switching frequency

48

VCO voltage difference on the

FBCTRL pin

0.12

Peak current control flyback (FBCTRL pin)

V_FBCTRL

voltage on the FBCTRL pin

for maximum flyback peak current

enable voltage

1.85

2

2.15

V

V_to(FBCTRL)

time-out voltage on the

FBCTRL pin

-

2.5

4.5

3

-

V

trip voltage

4.2

-

4.8

-

V

R_int(FBCTRL)

internal resistance on the

FBCTRL pin

k

TEA1752T

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Product data sheet

Rev. 2 — 16 November 2012

24 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

Table 5.

Characteristics …continued

T_amb= 25 C; V_CC= 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

1.4

0.6

36

Typ

Max

Unit

I_O(FBCTRL)

output current on the FBCTRL V_FBCTRL= 0 V

1.19 0.93 mA

V_FBCTRL= 2 V

0.5

30

0.4

24

mA

I_to(FBCTRL)

time-out current on the

FBCTRL pin

V_FBCTRL= 2.6 V

V_FBCTRL= 4.1 V

A

34.5 28.5 22.5 A

Valley switching flyback (HV pin)

(V/t)_vrec(fb)

flyback valley recognition

voltage change with time

75

-

+75

-

V/s

[4]

t_d(vrec-swon)

valley recognition to switch on

delay time

-

150

ns

Soft-start flyback (FBSENSE pin)

I_{start(soft)fb}flyback soft-start current

V_{start(soft)fb}flyback soft-start voltage

Overcurrent protection flyback (FBSENSE pin)

75

60

45

A

enable voltage

0.55

0.63

0.70

V

V_sense(fb)max

maximum flyback sense

voltage

V/t = 50 mV/s

V/t = 200 mV/s

0.61

0.64

0.65

0.68

0.69

0.72

V

V_sense(fb)min

t_leb(fb)

minimum flyback sense voltage V/t = 50 mV/s

0.305 0.325 0.345

V

flyback leading edge blanking

time

255

305

355

ns

I_adj(FBSENSE)

adjust current on the

FBSENSE pin

3.2

3

2.8

A

Overpower protection flyback (FBSENSE pin)

V_sense(fb)max

maximum flyback sense

voltage

V/t = 50 mV/s

I_FBAUX= 80 A

I_FBAUX= 120 A

I_FBAUX= 240 A

I_FBAUX= 360 A

0.61

0.57

0.47

0.41

0.65

0.62

0.52

0.46

0.69

0.67

0.57

0.51

V

Driver (FBDRIVER pin)

I_{src(FBDRIVER)}source current on the

FBDRIVER pin

V_FBDRIVER= 2 V

-

0.5

-

A

I_{sink(FBDRIVER)}

sink current on the FBDRIVER V_FBDRIVER= 2 V

-

0.7

-

A

V

V_FBDRIVER= 10 V

-

1.2

-

V_{O(FBDRIVER)(max)}maximum output voltage on the

FBDRIVER pin

9.5

10.8

12

LATCH input (LATCH pin)

V_prot(LATCH)

I_O(LATCH)

V_en(LATCH)

V_hys(LATCH)

protection voltage on the

LATCH pin

1.23

85

1.30

80

1.25

80

1.35

100

1.27

75

1.40

140

V

output current on the LATCH

V_prot(LATCH)< V_LATCH< V_oc(LATCH)

at start-up

A

V

enable voltage on the LATCH

hysteresis voltage on the

LATCH pin

V_en(LATCH) V_prot(LATCH)

mV

TEA1752T

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Product data sheet

Rev. 2 — 16 November 2012

25 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

Table 5.

Characteristics …continued

T_amb= 25 C; V_CC= 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_oc(LATCH)

open-circuit voltage on the

LATCH pin

2.65

2.9

3.15

V

Temperature protection

T_pl(IC)

IC protection level temperature

130

-

140

10

150

-

C

T_pl(IC)hys

hysteresis of IC protection level

temperature

[1] For a typical application with a compensation network on pin PFCCOMP, like the example in Figure 3.

[2] Minimum required voltage change time for valley recognition on pin PFCAUX.

[3] Minimum time required between demagnetization detection and V/t = 0 on pin PFCAUX.

[4] Guaranteed by design.

TEA1752T

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Product data sheet

Rev. 2 — 16 November 2012

26 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

11. Application information

A power supply with the TEA1752T consists of a power factor correction circuit and a

flyback converter (see Figure 17).

Capacitor C_VCCbuffers the IC supply voltage. The IC is powered using the high voltage

rectified mains during start-up and the auxiliary winding of the flyback converter during

operation. Sense resistors R_SENSE1and R_SENSE2convert the current through the

MOSFETs S1 and S2 into a voltage at the PFCSENSE and FBSENSE pins. The values of

R

_SENSE1and R_SENSE2define the maximum primary peak current in MOSFETs S1 and S2.

In the example given, the LATCH pin is connected to a Negative Temperature Coefficient

(NTC) resistor. The protection is activated when the resistance drops below a value

calculated as follows:

V_{protLATCH}

I_OLATCH

= 15.6 k

(8)

-------------------------------

A capacitor C_TIMEOUTis connected to the FBCTRL pin. R_LOOPis added so that the

time-out capacitor does not interfere with the normal regulation loop.

R

_S1and R_S2are added to prevent the soft-start capacitors from being charged during

normal operation due to negative voltage spikes across the sense resistors.

Resistor R_AUX1is added to protect the IC from damage during lightning events.

RS3 and RCOMP are added to compensate for input voltage variations. The (stray)

capacitance on the drain node of MOSFET S3 affects the frequency reduction slope and

therefore the PFC switch-on and switch-off levels. Choosing the proper values for RS3

and RCOMP results in an input voltage independent PFC switch-on and switch-off power

level.

TEA1752T

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Product data sheet

Rev. 2 — 16 November 2012

27 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

ꢌ

ꢐꢑꢒꢐꢑꢁ

ꢌ

ꢍꢎꢏꢀ

ꢌ

ꢐꢀ

ꢌ

ꢃꢓꢔꢕ

ꢀꢁ ꢀꢀ

ꢇ

ꢅ

ꢄ

ꢀꢅ ꢀꢆ

ꢀꢉ

ꢌ

ꢐꢁ

ꢌ

ꢐꢆ

ꢌ

ꢐꢑꢒꢐꢑꢀ

ꢂꢃ

ꢊ

ꢀ

ꢋ

ꢈ

ꢆ

ꢁ

ꢃ

ꢗꢃꢃ

ꢃ

ꢖꢂꢔꢑꢓꢎꢖ

ꢀꢀꢀꢁꢂꢂꢃꢃꢂꢈ

Fig 17. Typical application diagram for the TEA1752T IC

TEA1752T

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Product data sheet

Rev. 2 — 16 November 2012

28 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

12. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.39

0.014 0.0075 0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig 18. Package outline SOT109-1 (SO16)

TEA1752T

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Product data sheet

Rev. 2 — 16 November 2012

29 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

13. Revision history

Table 6.

Revision history

Document ID

TEA1752T v.2

Modifications:

Release date

Data sheet status

Change notice

Supersedes

20121116

Product data sheet

-

TEA1752T v.1

• Multiple text changes

• Multiple graphic updates

• Updates to several characteristics

TEA1752T v.1

20090210

Objective data sheet

-

TEA1752T

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Product data sheet

Rev. 2 — 16 November 2012

30 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

14. Legal information

14.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

14.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

14.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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Product data sheet

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31 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

GreenChip — is a trademark of NXP B.V.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

TEA1752T

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 November 2012

32 of 33

TEA1752T

NXP Semiconductors

HV start-up flyback controller with integrated PFC controller

16. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.3.10

7.3.11

Overpower protection. . . . . . . . . . . . . . . . . . . 19

Driver (FBDRIVER pin) . . . . . . . . . . . . . . . . . 20

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

Distinctive features . . . . . . . . . . . . . . . . . . . . . . 2

Green features . . . . . . . . . . . . . . . . . . . . . . . . . 2

PFC green features . . . . . . . . . . . . . . . . . . . . . 2

Flyback green features. . . . . . . . . . . . . . . . . . . 2

Protection features . . . . . . . . . . . . . . . . . . . . . . 2

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 20

Thermal characteristics . . . . . . . . . . . . . . . . . 21

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21

Application information . . . . . . . . . . . . . . . . . 27

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . 30

2.1

2.2

2.3

2.4

2.5

9

10

11

12

13

3

4

5

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

14

Legal information . . . . . . . . . . . . . . . . . . . . . . 31

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 32

14.1

14.2

14.3

14.4

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

7.1

Functional description . . . . . . . . . . . . . . . . . . . 6

General control. . . . . . . . . . . . . . . . . . . . . . . . . 6

Start-up and UnderVoltage LockOut (UVLO) . . 6

Supply management. . . . . . . . . . . . . . . . . . . . . 8

Latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Fast latch reset. . . . . . . . . . . . . . . . . . . . . . . . . 9

Overtemperature protection . . . . . . . . . . . . . . . 9

Power factor correction circuit . . . . . . . . . . . . . 9

t_oncontrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Valley switching and demagnetization

15

16

Contact information . . . . . . . . . . . . . . . . . . . . 32

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.2

7.2.1

7.2.2

(PFCAUX pin). . . . . . . . . . . . . . . . . . . . . . . . . . 9

Frequency limitation . . . . . . . . . . . . . . . . . . . . 10

Mains voltage compensation

7.2.3

7.2.4

(VINSENSE pin) . . . . . . . . . . . . . . . . . . . . . . . 10

Soft start-up (PFCSENSE pin) . . . . . . . . . . . . 10

Low-power mode . . . . . . . . . . . . . . . . . . . . . . 11

PFC off delay (PFCTIMER pin) . . . . . . . . . . . 11

Dual-boost PFC . . . . . . . . . . . . . . . . . . . . . . . 12

Overcurrent protection (PFCSENSE pin) . . . . 12

Mains undervoltage lockout/brownout

7.2.5

7.2.6

7.2.7

7.2.8

7.2.9

7.2.10

protection (VINSENSE pin) . . . . . . . . . . . . . . 12

Overvoltage protection (VOSENSE pin). . . . . 12

PFC open-loop protection (VOSENSE pin) . . 13

Driver (PFCDRIVER pin) . . . . . . . . . . . . . . . . 13

Flyback controller . . . . . . . . . . . . . . . . . . . . . . 13

Multimode operation. . . . . . . . . . . . . . . . . . . . 13

Valley switching (HV pin) . . . . . . . . . . . . . . . . 14

Current mode control (FBSENSE pin) . . . . . . 15

Demagnetization (FBAUX pin) . . . . . . . . . . . . 16

Flyback control/time-out (FBCTRL pin) . . . . . 16

Soft-start-up (FBSENSE pin) . . . . . . . . . . . . . 17

Maximum on-time. . . . . . . . . . . . . . . . . . . . . . 18

Overvoltage protection (FBAUX pin) . . . . . . . 18

Overcurrent protection (FBSENSE pin) . . . . . 19

7.2.11

7.2.12

7.2.13

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

7.3.7

7.3.8

7.3.9

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 November 2012

Document identifier: TEA1752T


型号：	TEA1752T/1791/DB/9
厂家：	NXP
描述：	SMPS combo IC for dual boost PFC and flyback control, safe restart protection, SOT109-1 Package, No Marking, Boards 功率因数校正光电二极管
文件：	总33页 (文件大小：318K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TEA1752T/1791/DB/9 [NXP]

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