TEA1752T/1791/DB12 [NXP]
SMPS combo IC for dual boost PFC and flyback control, safe restart protection, SOT109-1 Package, No Marking, Boards;
| 型号： | TEA1752T/1791/DB12 |
| 厂家： | 
NXP |
| 描述： | SMPS combo IC for dual boost PFC and flyback control, safe restart protection, SOT109-1 Package, No Marking, Boards 功率因数校正 光电二极管 |
| 文件： | 总34页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
Rev. 02 — 24 June 2010
Product data sheet
1. General description
The GreenChip III is the third generation of green Switched Mode Power Supply (SMPS)
controller ICs. The TEA1752T and TEA1752LT combine a controller for Power Factor
Correction (PFC) and a flyback controller. The high level of integration facilitates the
design of a cost-effective power supply using a minimum number of external components.
The special built-in green functions provide high efficiency at all power levels. This applies
to quasi-resonant operation at high power levels, quasi-resonant operation with valley
skipping and reduced frequency operation at lower power levels. At low power levels, the
PFC switches off to maintain high efficiency.
During low power conditions, the flyback controller switches to frequency reduction mode
and limits the peak current to an adjustable minimum value. This will ensure high
efficiency at low power and good standby power performance while minimizing audible
noise from the transformer.
The TEA1752(L)T is a MultiChip Module (MCM), containing two chips. The proprietary
high voltage BCD800 process which enables direct start-up from the rectified universal
mains voltage in an effective and green way and a low voltage Silicon-On Insulator (SOI)
which provides accurate, high speed protection functions and control.
The TEA1752(L)T enables highly efficient and reliable supplies with power requirements
of up to 250 W to be designed easily and with a minimum number of external
components.
2. Features and benefits
2.1 Distinctive features
Integrated PFC and flyback controller
Universal mains supply operation (70 V (AC) to 276 V (AC))
Dual boost PFC with accurate maximum output voltage (NXP Semiconductors
patented, US patent number: US7575280)
High level of integration, resulting in a very low external component count and a
cost-effective design
Adjustable PFC switch-off delay
2.2 Green features
On-chip start-up current source
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
2.3 PFC green features
Valley/zero voltage switching for minimum switching losses
(NXP Semiconductors patented, US patent number: US6256210)
Frequency limitation to reduce switching losses
PFC is switched off when a low load is detected at the flyback output
2.4 Flyback green features
Valley switching for minimum switching losses
(NXP Semiconductors patented, US patent number: US6256210)
Frequency reduction with fixed minimum peak current at low power operation to
maintain high-efficiency at low output power levels
2.5 Protection features
Safe restart mode for system fault conditions
Continuous mode protection by means of demagnetization detection for both
converters (NXP Semiconductors patented, patent number: US5032967)
UnderVoltage Protection (UVP) (foldback during overload)
Accurate OverVoltage Protection (OVP) for PFC
Accurate, adjustable OverVoltage Protection (OVP) for flyback converter
(NXP Semiconductors patented, patent number: US6542386)
Mains voltage independent OverPower Protection (OPP)
(NXP Semiconductors patented, patent number: US6542386)
Open control loop protection for both converters. The open-loop protection on the
flyback converter is latched on the TEA1752LT and safe restart on the TEA1752T
IC overtemperature protection
Low and adjustable OverCurrent Protection (OCP) trip level for both converters
General purpose input for latched protection, e.g. to be used for system
OverTemperature Protection (OTP)
3. Applications
All applications requiring efficient and cost-effective power supply solutions to 250 W.
Notebook adapters in particular can benefit from the high level of integration
TEA1752T_LT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
2 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
SO16
Description
Version
TEA1752T
plastic small outline package; 16 leads; body width 3.9 mm
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
SOT109-1
TEA1752LT
SO16
TEA1752T_LT
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
3 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
5. Block diagram
PFCDRIVER
12
FBDRIVER
13
PFC driver
PFC gate
flyback driver
flyback gate
80 μA
1.12 V
3.5 V
driver
driver
5
LATCH
external
protection
low Vin
1.25 V
VINSENSE
PFCCOMP
7
6
protection
boost
R
R
S
PFC
protection
MAXIMUM
latch
reset
protection
enable PFC
Q
Q
2.5 V
3.5 V
frequency
reduction
S
enable flyback
30 μA
clamp
low
power
1.25 V
PFC
OSCILLATOR
FLYBACK
OSCILLATOR
3.7 V
time-out
3
FBCTRL
2.50 V
boost
VOSENSE
9
t
on(max)
3.5 V
V
good
CC
start flyback
frequency reduction
15 μA
V
o
PFC clamp
SMPS
CONTROL
start flyback
start stop PFC
3.5 V
low Vin
low power delay
external protection
PFC clamp
MINIMUM
OPP
V
o
OVP
PFC
protection
OCP
time-out
S (TEA1752LT only)
external protection
clamp
V
start flyback
short
S
S
S
R
o
LATCHED
PROTECTION
V
o
OTP
OVP flyback
latch reset
flyback driver
BLANK
low power
delay
10
FBSENSE
OCP
time-out
ton max
S (TEA1752T only)
S SAFE RESTART
R PROTECTION
protection
60 μA 3 μA
enable flyback
start flyback
PFC driver
BLANK
500 mV
PFCSENSE 11
V
UVLO
V
short
START
SOFT
o
enable PFC
protection
external protection
60 μA
V
good
CC
charge
VALLEY
SOFT START
SOFT STOP
start stop PFC
CHARGE
CONTROL
V
startup
V
OPP
OVP
th(UVLO)
OPP
TIMER 4 μs
DETECT
VALLEY
DETECT
OVP
flyback
COUNTER
PFCAUX
8
OTP
internal supply
ZERO
CURRENT
SIGNAL
4
FBAUX
PFC gate
flyback
gate
charge
ZERO CURRENT
SIGNAL
V
V
startup
TIMER 50 μs
−100 mV
low power
th(UVLO)
TEMPERATURE
OTP
low power
delay
80 mV
DELAY
14
2
16
HV
1
014aaa742
PFCTIMER
V
GND
CC
Remark:
TEA1752LT time-out is latched.
TEA1752T time-out is safe restart.
Fig 1. Block diagram
TEA1752T_LT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
4 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
6. Pinning information
6.1 Pinning
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
HV
CC
GND
FBCTRL
FBAUX
HVS
PFCTIMER
FBDRIVER
PFCDRIVER
PFCSENSE
FBSENSE
VOSENSE
TEA1752(L)T
LATCH
PFCCOMP
VINSENSE
PFCAUX
014aaa741
Fig 2. Pin configuration: TEA1752(L)T (SOT109-1)
6.2 Pin description
Table 2.
Pin description
Symbol
VCC
Pin
1
Description
supply voltage
ground
GND
2
FBCTRL
FBAUX
3
control input for flyback
4
input from auxiliary winding for demagnetization timing and
overvoltage protection for flyback
LATCH
5
6
7
8
general purpose protection input
frequency compensation pin for PFC
sense input for mains voltage
PFCCOMP
VINSENSE
PFCAUX
input from auxiliary winding for demagnetization timing for PFC
and valley sensing of the PFC part
VOSENSE
FBSENSE
PFCSENSE
PFCDRIVER
FBDRIVER
PFCTIMER
HVS
9
sense input for PFC output voltage
10
11
12
13
14
15
16
programmable current sense input for flyback
programmable current sense input for PFC
gate driver output for PFC
gate driver output for flyback
delay timer pin for PFC on/off control
high voltage safety spacer, not connected
high voltage start-up and valley sensing of flyback part
HV
TEA1752T_LT
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
5 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
7. Functional description
7.1 General control
The TEA1752(L)T contains controllers for a power factor correction circuit and for a
flyback circuit. A typical configuration is shown in Figure 3.
D1
S1
C
bus
D2
C
R
SS1
SS1
T2
C
OUT
R
R
SENSE1
R
AUX1
S1
S2
PFCDRIVER PFCSENSE
12 11
8
VOSENSE HV FBTIMER
9
16 13
PFCAUX
FBSENSE
10
R
S2
PFCCOMP
R
6
SS2
compensation
C
SS2
VINSENSE
FBCTRL
TEA1752(L)T
R
R
AUX2
SENSE2
7
FBAUX
4
V
CC
1
5
LATCH
3
2
14
PFCTIMER
GND
C
VCC
R
LOOP
Θ
C
TIMEOUT
014aaa750
Fig 3. Typical configuration
7.1.1 Start-up and UnderVoltage LockOut (UVLO)
Initially the capacitor on the VCC pin is charged from the high voltage mains via the HV pin.
If VCC is lower than Vtrip, the charge current is low. This protects the IC if the VCC pin is
shorted to ground. The charge current above Vtrip is increased until VCC reaches Vth(UVLO)
to achieve a short start-up time. If VCC is between Vth(UVLO) and Vstartup, the charge current
is low again, ensuring a low duty cycle during fault conditions.
The control logic activates the internal circuitry and switches off the HV charge current
when the voltage on pin VCC passes the Vstartup level. The LATCH pin current source is
then activated and the soft start capacitors on pins PFCSENSE and FBSENSE are
charged and the clamp circuit on pin PFCCOMP is activated. When the LATCH pin
voltage exceeds Ven(LATCH), the PFCCOMP pin voltage exceeds Ven(PFCCOMP) and the soft
start capacitor on pin PFCSENSE pin is charged, the PFC circuit is activated. The flyback
TEA1752T_LT
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
6 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
converter is also activated (providing the soft start capacitor on the FBSENSE pin is
charged). The flyback converter output voltage is then regulated to its nominal value. The
IC supply is taken over by the auxiliary winding of the flyback converter. See Figure 4.
If during start-up the LATCH pin does not reach the Ven(LATCH) level before VCC reaches
V
th(UVLO), the LATCH pin output is deactivated and the charge current is switched on
again.
When the flyback converter is started, the voltage on pin FBCTRL is monitored. If the
flyback converter output voltage does not reach its intended regulation level in a
predefined time, the voltage on pin FBCTRL reaches the Vto(FBCTRL) level and an error is
assumed. The TEA1752T then initiates a safe restart, while in the TEA1752LT the
protection is latched.
When one of the protection functions is activated, both converters stop switching and the
V
CC voltage drops to Vth(UVLO). A latched protection recharges the capacitor CVCC via the
HV pin, but does not restart the converters. For a safe restart protection, the capacitor is
recharged via the HV pin and the device restarts. See Figure 1.
In the event of an overvoltage protection of the PFC circuit where
V
VOSENSE > Vovp(VOSENSE), the PFC controller stops switching until the VOSENSE pin
voltage drops back below Vovp(VOSENSE). If a mains undervoltage is detected where
V
V
VINSENSE < Vstop(VINSENSE), the PFC controller stops switching until
VINSENSE > Vstart(VINSENSE)
.
When the voltage on pin VCC drops below the undervoltage lockout level, both controllers
stop switching and reenter the safe restart mode. In this mode the driver outputs are
disabled and the VCC pin voltage is recharged via the HV pin.
TEA1752T_LT
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
7 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
I
HV
V
startup
V
V
th(UVLO)
trip
V
CC
V
start(VINSENSE)
en(PFCCOMP)
VINSENSE
V
PFCCOMP
LATCH
V
en(LATCH)
PROTECTION
soft start
PFCSENSE
PFCDRIVER
soft start
FBSENSE
FBDRIVER
FBCTRL
V
to(FBCTRL)
V
start(fb)
VOSENSE
V
O
charging VCC
capacitor
starting
normal
protection
restart
014aaa744
converters
operation
Fig 4. Start-up sequence, normal operation and restart sequence
7.1.2 Supply management
All internal control voltages are derived from a temperature compensated and trimmed
on-chip band gap circuit. Internal reference currents are derived from a temperature
compensated and trimmed on-chip current reference circuit.
7.1.3 Latch input
Pin LATCH is a general purpose input pin, which can be used to switch off both
converters. The pin sources a current IO(LATCH) (80 μA typical). Switching off both
converters is stopped as soon as the voltage on this pin drops below 1.25 V.
TEA1752T_LT
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
8 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
At initial start-up the switching is inhibited until the capacitor on the LATCH pin is charged
above 1.35 V (typical). No internal filtering is carried out on this pin. An internal zener
clamp of 2.9 V (typical) protects this pin from excessive voltages.
7.1.4 Fast latch reset
In a typical application the mains supply can be interrupted briefly to reset the latched
protection. The PFC bus capacitor, Cbus, does not need to discharge for this latched
protection to reset.
Typically the PFC bus capacitor, Cbus, must discharge for the VCC to drop to this reset
level. When the latched protection is set, the VINSENSE clamping circuit is disabled. See
Section 7.2.10. When the VINSENSE voltage drops below 0.75 V (typical) then increases
to 0.87 V (typical), the latched protection is reset.
The latched protection is also reset by removing the voltage on pins VCC and HV.
7.1.5 OverTemperature Protection (OTP)
Integrated overtemperature protection ensures the IC stops switching if the junction
temperature exceeds the thermal temperature shutdown limit.
Capacitor CVCC will not recharge from the HV mains while OTP is active. The OTP circuit
is supplied from the HV pin if the VCC supply voltage is insufficient.
OTP is a latched protection that can be reset either by removing the voltage on pins VCC
and HV or by the fast latch reset function. See Section 7.1.4.
7.2 Power Factor Correction circuit (PFC)
The power factor correction circuit operates in quasi-resonant or discontinuous
conduction mode with valley switching. The next primary stroke only starts when the
previous secondary stroke has ended and the voltage across the PFC MOSFET has
reached a minimum value. The voltage on the PFCAUX pin is used to detect transformer
demagnetization and the minimum voltage across the external PFC MOSFET switch.
7.2.1 ton control
The power factor correction circuit is operated in ton control. The resulting mains harmonic
reduction of a typical application is well within the class-D requirements.
7.2.2 Valley switching and demagnetization (PFCAUX pin)
The PFC MOSFET is switched on after the transformer has been demagnetized. Internal
circuitry connected to the PFCAUX pin detects the end of the secondary stroke. It also
detects the voltage across the PFC MOSFET. The next stroke is started when the voltage
across the PFC MOSFET is at its minimum in order to reduce switching losses and
ElectroMagnetic Interference (EMI) (valley switching).
If no demagnetization signal is detected on the PFCAUX pin, the controller generates a
Zero Current Signal (ZCS), 50 μs (typical), after the last PFCGATE signal.
If no valley signal is detected on the PFCAUX pin, the controller generates a valley signal,
4 μs (typical), after demagnetization was detected.
TEA1752T_LT
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
9 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
It is advisable to add a 5 kΩ series resistor to this pin to provide surge protection for the
internal circuitry against events such as lightning surge. To prevent incorrect switching
due to external disturbance, this resistor should be placed as close as possible to the IC
on the printed-circuit board.
7.2.3 Frequency limitation
To optimize the transformer and minimize switching losses, the switching frequency is
limited to fsw(PFC)max. If the frequency for quasi-resonant operation is above the fsw(PFC)max
limit, the system switches over to discontinuous conduction mode. The PFC MOSFET is
then only switched on at a minimum voltage across the switch (valley switching).
7.2.4 Mains voltage compensation (VINSENSE pin)
The mathematical equation for the transfer function of a power factor corrector contains
the square of the mains input voltage. In a typical application this results in a low
bandwidth for low mains input voltages, while at high mains input voltages the Mains
Harmonic Reduction (MHR) requirements may be hard to meet.
The TEA1752(L)T incorporates a correction circuit to compensate for the mains input
voltage influence. The average input voltage is measured via the VINSENSE pin and this
information is fed to an internal compensation circuit. With this compensation it is possible
to keep the regulation loop bandwidth constant over the full mains input range, yielding a
fast transient response on load steps, while still complying with class-D MHR
requirements.
In a typical application, the regulation loop bandwidth is set by a resistor and two
capacitors on the PFCCOMP pin.
7.2.5 Soft start-up (pin PFCSENSE)
To prevent audible transformer noise at start-up or during hiccup, the transformer peak
current is increased slowly by the soft start function. This can be achieved by inserting
R
SS1 and CSS1 between pin PFCSENSE and the current sense resistor, RSENSE1
An internal current source charges the capacitor to VPFCSENSE = Istart(soft)PFC × RSS1. The
voltage is limited to Vstart(soft)PFC
.
.
The start level and time constant of the increasing primary current level can be adjusted
externally by changing the values of RSS1 and CSS1
.
τsoftstart = 3 × R
× C
SS1
SS1
The charging current Istart(soft)PFC flows if the voltage on pin PFCSENSE is lower than
0.5 V (typical). If the voltage on pin PFCSENSE exceeds 0.5 V, the soft start current
source limits current Istart(soft)PFC. When the PFC starts switching, the Istart(soft)PFC current
source is switched off (see Figure 5).
Resistor RSS1 and capacitor CSS1 are also used to prevent audible noise, when the PFC is
switched off by performing a soft stop.
TEA1752T_LT
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
10 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
I
≤ 60 μA
S1
start(soft)PFC
SOFT START
SOFT STOP
CONTROL
R
C
SS1
SS1
11
OCP
PFCSENSE
0.5 V
R
SENSE1
014aaa756
Fig 5. Soft start-up of PFC
7.2.6 Low power mode
When the output power of the flyback converter (see Section 7.3) is low, the flyback
converter switches to frequency reduction mode. When the internal switching frequency
limit of the flyback drops below 48 kHz (typical), the power factor correction circuit is
switched off to maintain high efficiency. The switch-off can be delayed by connecting a
capacitor to the PFCTIMER pin (see Section 7.2.7).
During low power mode operation the PFCCOMP pin is clamped to a minimum voltage of
3.5 V (typical) and a maximum voltage of 3.7 V (typical). The lower clamp voltage limits
the maximum power delivered when the PFC is switched on again. The upper clamp
voltage ensures the PFC can return to its normal regulation point in a limited amount of
time when returning from low power mode.
The power factor correction circuit restores normal operation when the internal switching
frequency limit of the flyback converter rises above 86 kHz (typical).
7.2.7 PFC off delay (pin PFCTIMER)
When the internal switching frequency limit of the flyback controller drops below
48 kHz (typical), the PFC is switched off. To prevent the PFC from switching off due to a
fast changing load at the flyback output, the PFC switch-off can be delayed by connecting
a capacitor to the PFCTIMER pin.
When the flyback controller detects a low power, it enters frequency reduction mode and
the IC outputs a 10 μA (typical) current to the PFCTIMER pin. When the voltage on the
PFCTIMER pin reaches 3.6 V (typical), the PFC is switched off by performing a soft stop.
When the flyback controller part leaves the frequency reduction mode, a switch
discharges the PFCTIMER pin capacitor. When the voltage on the PCTIMER pin drops
below 1.27 V (typical), the PFC is switched on (see Figure 6).
TEA1752T_LT
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
11 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
3.6 V
10 μA
R
low power delay
Q
low power
(PFC on)
S
1.27 V
14 PFCTIMER
014aaa740
Fig 6. PFC start/stop via PFCTIMER pin
7.2.8 Dual boost PFC
The PFC output voltage depends on the mains input voltage. The mains input voltage is
measured via the VINSENSE pin. Current is sourced from the VOSENSE pin if the
voltage on the VINSENSE pin drops below 2.2 V (typical). To ensure a stable switch-over,
a 200 mV transition region is inserted around the 2.2 V, see Figure 7.
For low VINSENSE input voltages, the output current is 15 μA (typical). This output
current, in combination with the resistors on the VOSENSE pin, sets a lower PFC output
voltage level at low mains voltages. At high mains input voltages the current is switched to
zero. The PFC output voltage will then be at its maximum. As this current is zero in this
situation, it does not effect the accuracy of the PFC output voltage.
For proper switch-off behavior, the VOSENSE current is switched to its maximum value,
(15 μA (typical)), as soon as the voltage on pin VOSENSE drops below 2.1 V (typical).
2.2 V
V
VINSENSE
−15 μA
I
I(VOSENSE)
014aaa097
Fig 7. Voltage to current transfer function for dual boost PFC
7.2.9 Overcurrent protection (PFCSENSE pin)
The maximum peak current is limited cycle-by-cycle by sensing the voltage across an
external sense resistor, RSENSE1, on the source of the external MOSFET. The voltage is
measured via the PFCSENSE pin.
7.2.10 Mains undervoltage lockout/brownout protection (VINSENSE pin)
To prevent the PFC from operating at very low mains input voltages, the voltage on the
VINSENSE pin is continuously monitored. When the voltage on this pin drops below the
V
stop(VINSENSE) level, PFC switching is stopped.
TEA1752T_LT
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
12 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
The voltage on pin VINSENSE is clamped to a minimum value,
start(VINSENSE) + ΔVpu(VINSENSE), for a fast restart when mains input voltage is restored
V
after a mains dropout.
7.2.11 Overvoltage protection (VOSENSE pin)
An overvoltage protection circuit is incorporated to prevent output overvoltage during load
steps and mains transients.
When voltage on the VOSENSE pin exceeds the Vovp(VOSENSE) level, switching of the
power factor correction circuit is inhibited. Switching of the PFC recommences when the
VOSENSE pin voltage drops back below the Vovp(VOSENSE) level.
When the resistor between pin VOSENSE and ground is open, the overvoltage protection
is also triggered.
7.2.12 PFC open-loop protection (VOSENSE pin)
The power factor correction circuit will not start switching until the voltage on the
VOSENSE pin is above the Vth(ol)(VOSENSE) level. This protects the circuit from open-loop
and VOSENSE short circuit situations.
7.2.13 Driver (pin PFCDRIVER)
The driver circuit to the gate of the power MOSFET has a current sourcing capability of
typically −500 mA and a current sink capability of typically 1.2 A. This enables fast turn-on
and turn-off of the power MOSFET for efficient operation.
7.3 Flyback controller
The TEA1752(L)T includes a controller for a flyback converter. The flyback converter
operates in quasi-resonant or discontinuous conduction mode with valley switching. The
auxiliary winding of the flyback transformer provides demagnetization detection and
powers the IC after start-up.
7.3.1 Multimode operation
The TEA1752(L)T flyback controller can operate in several modes (see Figure 8).
TEA1752T_LT
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
13 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
flyback
switching
frequency
125 kHz
frequency
reduction
86 kHz
48 kHz
PFC off
PFC on
discontinuous
with valley
switching
I
pmin
quasi-resonant
adjust
output power
014aaa745
Fig 8. Multimode operation flyback
At high output power the converter switches to quasi-resonant mode. The next converter
stroke is started after demagnetization of the transformer current. In quasi-resonant mode
switching losses are minimized as the converter only switches on when the voltage across
the external MOSFET is at its minimum (valley switching, see Section 7.3.2).
To prevent high frequency operation at lower loads, the quasi-resonant operation changes
to discontinuous mode operation with valley skipping, in which the EMI switching
frequency is limited to fsw(fb)max (125 kHz typical). Again, the external MOSFET is only
switched on when the voltage across the MOSFET is at its minimum.
At very low power and standby levels the frequency is reduced by a Voltage Controlled
Oscillator (VCO). The minimum frequency can be reduced to zero. During frequency
reduction mode the primary peak current is kept constant at a minimum adjustable level to
control the PFC on-power and off-power levels. Ipmin in frequency reduction mode will
generally be greater than Ipmax / 4, so a high efficiency at low loads is guaranteed. As the
primary peak current is low in frequency reduction operation, no audible noise is
noticeable at switching frequencies in the audible range. Valley switching is also active in
this mode.
In frequency reduction mode the PFC controller is switched off and the flyback maximum
frequency changes linearly with the control voltage on the FBCTRL pin (see Figure 9 ).
For stable on and off switching of the PFC, hysteresis has been added. At no load
operation the switching frequency can be reduced to (almost) zero.
TEA1752T_LT
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14 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
f
sw(fb)max
flyback
switching
frequency
PFC off
PFC on
discontinuous
with valley
switching
frequency
reduction
quasi-resonant
1.5 V
V
014aaa746
FBCTRL
Fig 9. Frequency control of flyback part
7.3.2 Valley switching (HV pin)
Figure 10 shows that a new cycle starts when the external MOSFET is activated. After the
on-time (determined by the FBSENSE voltage and the FBCTRL voltage), the MOSFET is
switched off and the secondary stroke starts. After the secondary stroke, the drain voltage
1
---------------------------------------------------
shows an oscillation with a frequency of approximately
where Lp is
(2 × π × (L × C ))
p
d
the primary self-inductance of the flyback transformer and Cd is the capacitance on the
drain node.
When the internal oscillator voltage is high again and the secondary stroke has ended, the
circuit waits for the lowest drain voltage before starting a new primary stroke. Figure 10
shows the drain voltage, valley signal, secondary stroke signal and the internal oscillator
signal.
Valley switching allows high frequency operation as capacitive switching losses are
reduced (see Equation 1). High frequency operation makes small and cost-effective
magnetics possible.
1
2
2
⎛
⎝
⎞
--
P = × C × V × f
(1)
d
⎠
TEA1752T_LT
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TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
primary
stroke
secondary
stroke
secondary
ringing
drain
valley
secondary
stroke
(2)
(1)
oscillator
014aaa027
(1) Start of new cycle at lowest drain voltage.
(2) Start of new cycle in a classical Pulse Width Modulation (PWM) system without valley detection.
Fig 10. Signals for valley switching
7.3.3 Current mode control (FBSENSE pin)
Current mode control is used for the flyback converter for its good line regulation.
The primary current is sensed by the FBSENSE pin across external resistor RSENSE2
(see Figure 3) and compared with an internal control voltage. The internal control voltage
is proportional to the FBCTRL pin voltage (see Figure 11).
The FBSENSE pin outputs a current of 3 μA (typical). This current runs through resistors
R
S2 and RSS2 from the FBSENSE pin to the sense resistor, RSENSE2 and creates an offset
voltage (See Figure 3). With this offset voltage, the minimum peak current of the flyback
can be adjusted. Adjusting the minimum peak current level, will change the frequency
reduction slope (See Figure 8).
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TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
V
sense(fb)max
0.65 V
FBSENSE
offset voltage
PFC off PFC on
SENSE resistor
peak voltage
flyback
frequency
reduction
flyback
discontinuous
or QR
FBSENSE
peak voltage
flyback
cycle skip
mode
0.325 V
1.5 V 2.0 V
V
FBCTRL
014aaa747
Fig 11. Peak current control of flyback part
7.3.4 Demagnetization (FBAUX pin)
The system is always in quasi-resonant or discontinuous conduction mode. The internal
oscillator does not start a new primary stroke until the previous secondary stroke has
ended.
Demagnetization features a cycle-by-cycle output short circuit protection by immediately
lowering the frequency (longer off-time), thus reducing the power level.
Demagnetization recognition is suppressed during the first tsup(xfmr_ring) time (2 μs typical).
This suppression may be necessary at low output voltages and at start-up and in
applications where the transformer has a large leakage inductance.
If pin FBAUX is open circuit or not connected, a fault condition is assumed and the
converter stops operating immediately. Operation restarts as soon as the fault condition is
removed.
7.3.5 Flyback control/time-out (FBCTRL pin)
The pin FBCTRL is connected to an internal voltage source of 3.5 V via an internal
resistor (typical resistance is 3 kΩ). As soon as the voltage on this pin rises above
2.5 V (typical), this connection is disabled. Above 2.5 V the pin is biased with a small
current. When the voltage on this pin rises above 4.5 V (typical), a fault is assumed and
switching is inhibited. In the TEA1752T a restart will then be made, while in the
TEA1752LT the protection will be latched.
When a small capacitor is connected to this pin, a time-out function can be created to
protect against an open control loop situation. (see Figure 12 and Figure 13) The time-out
function can be disabled by connecting a resistor (100 kΩ) to ground on the FBCTRL pin.
If the pin is shorted to ground, switching of the flyback controller is inhibited.
In normal operating conditions, when the converter is regulating the output voltage, the
voltage on the FBCTRL pin is between 1.4 V (typical) and 2.0 V (typical) from minimum to
maximum output power.
TEA1752T_LT
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TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
2.5 V
3.5 V
30 μA
4.5 V
3 kΩ
FBCTRL
time-out
014aaa049
Fig 12. Time-out protection circuit
4.5 V
2.5 V
V
FBCTRL
output
voltage
intended output
voltage not
reached within
time-out time.
restart
intended output voltage
reached within time-out
time.
014aaa050
Fig 13. Time-out protection (signals), safe restart in the TEA1752T
4.5 V
2.5 V
V
FBCTRL
output
voltage
intended output
voltage not
latched
reached within
time−out time.
014aaa298
Fig 14. Time-out protection (signals), latched in the TEA1752LT
7.3.6 Soft start-up (pin FBSENSE)
To prevent audible transformer noise during start-up, the transformer peak current is
slowly increased by the soft start function. This can be achieved by inserting a resistor
(RSS2) and a capacitor (CSS2) between pin 10 (FBSENSE) and the current sense resistor.
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NXP Semiconductors
GreenChip III SMPS control IC
An internal current source charges the capacitor to V = Istart(soft)fb × RSS2, with a maximum
of approximately 0.63 V.
The start level and the time constant of the increasing primary current level can be
externally adjusted by changing the values of RSS2 and CSS2
.
τsoftstart = 3 × R × C
SS2
SS2
The soft start current Istart(soft)fb is switched on when VCC reaches Vstartup. When the
voltage on pin FBSENSE has reached 0.63 V the flyback converter starts switching.
The charging current Istart(soft)PFC flows if voltage on pin FBSENSE is below approximately
0.63 V. If the voltage on pin FBSENSE exceeds 0.63 V, the soft start current source limits
the current. Once the flyback converter has started, the soft start current source is
switched off.
I
≤ 60 μA
S2
start(soft)fb
3μA
SOFT START
CONTROL
R
C
SS2
SS2
10
FBSENSE
OCP
ocp level
R
SENSE2
014aaa748
Fig 15. Soft start-up of flyback
7.3.7 Maximum on-time
The flyback controller limits the ‘on-time’ of the external MOSFET to 40 μs (typical). When
the ‘on-time’ is longer than 40 μs, the IC stops switching and enters the safe restart mode.
7.3.8 Overvoltage protection (FBAUX pin)
An output overvoltage protection is implemented in the GreenChip III series. This
operates for the TEA1752(L)T by sensing the auxiliary voltage via the current flowing into
pin FBAUX during the secondary stroke. The auxiliary winding voltage is a well defined
replica of the output voltage. Voltage spikes are averaged by an internal filter.
If the output voltage exceeds the OVP trip level, an internal counter starts counting
subsequent OVP events. The counter has been added to prevent incorrect OVP detection
which might occur during ESD or lightning events. If the output voltage exceeds the OVP
trip level a few times and then not again in a subsequent cycle, the internal counter counts
down at twice the speed it uses when counting up. However, when typically eight cycles of
subsequent OVP events are detected, the IC assumes a true OVP and the OVP circuit
switches the power MOSFET off. As the protection is latched, the converter only restarts
after the internal latch is reset. In a typical application the mains should be interrupted to
reset the internal latch.
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NXP Semiconductors
GreenChip III SMPS control IC
The output voltage Vo(OVP) at which the OVP function trips, can be set by the
demagnetization resistor, RFBAUX
:
N
s
-----------
V
=
(I
× R
+ V
)
clamp(FBAUX)
o(OVP)
ovp(FBAUX)
FBAUX
N
aux
where Ns is the number of secondary turns and Naux is the number of auxiliary turns of the
transformer. The current Iovp(FBAUX) is internally trimmed.
The value of RFBAUX can be adjusted to the turns ratio of the transformer, making an
accurate OVP detection possible.
7.3.9 Overcurrent protection (FBSENSE pin)
The primary peak current in the transformer is accurately measured cycle-by-cycle using
external sense resistor RSENSE2. The OCP circuit limits the voltage on pin FBSENSE to an
internal level (see Section 7.3.3). The OCP detection is suppressed during the leading
edge blanking period, tleb, to prevent false triggering caused by switch-on spikes.
t
leb
OCP level
V
FBSENSE
t
014aaa022
Fig 16. OCP leading edge blanking
7.3.10 Overpower protection
During the primary stroke of the flyback converter its input voltage is measured by sensing
the current that is drawn from pin FBAUX.
This information is used to adjust the peak drain current of the flyback converter
measured via pin FBSENSE. The internal compensation is such that an almost input
voltage independent maximum output power can be realized.
The OPP curve is given in Figure 17.
TEA1752T_LT
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TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
V
FBSENSE
(V)
0.65
0.46
−360
−100
0
I
(μA)
FBAUX
014aaa749
Fig 17. Overpower protection curve
7.3.11 Driver (pin FBDRIVER)
The driver circuit to the gate of the external power MOSFET has a current sourcing
capability of typically −500 mA and a current sink capability of typically 1.2 A. This enables
fast turn-on and turn-off of the power MOSFET for efficient operation.
8. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Voltages
VCC
Parameter
Conditions
Min
Max
Unit
supply voltage
−0.4
−0.4
−0.4
−0.4
−0.4
−0.4
−25
+38
+5
V
V
V
V
V
V
V
V
V
V
V
VLATCH
VFBCTRL
voltage on pin LATCH
voltage on pin FBCTRL
current limited
+5
VPFCCOMP voltage on pin PFCCOMP
VVINSENSE voltage on pin VINSENSE
VVOSENSE voltage on pin VOSENSE
+5
+5
+5
VPFCAUX
voltage on pin PFCAUX
+25
+5
VFBSENSE voltage on pin FBSENSE
VPFCSENSE voltage on pin PFCSENSE
VPFCTIMER voltage on pin PFCTIMER
current limited
current limited
−0.4
−0.4
−0.4
−0.4
+5
+5
VHV
voltage on pin HV
+650
Currents
IFBCTRL
IFBAUX
current on pin FBCTRL
current on pin FBAUX
−3
0
mA
mA
mA
mA
A
−1
+1
+10
+10
+2
IPFCSENSE current on pin PFCSENSE
IFBSENSE current on pin FBSENSE
IFBDRIVER current on pin FBDRIVER
−1
−1
duty cycle < 10 %
−0.8
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NXP Semiconductors
GreenChip III SMPS control IC
Table 3.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
−0.8
-
Max
+2
8
Unit
A
IPFCDRIVER current on pin PFCDRIVER duty cycle < 10 %
IHV
current on pin HV
mA
General
Ptot
total power dissipation
storage temperature
junction temperature
Tamb < 75 °C
-
0.6
W
Tstg
−55
−40
+150
+150
°C
°C
Tj
ESD
VESD
electrostatic discharge
voltage
class 1
human body
model
[1]
[1]
[2]
pins 1 to 13
pin 16 (HV)
-
-
-
-
2000
1500
200
V
V
V
V
machine model
charged device
model
500
[1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
[2] Equivalent to discharging a 200 pF capacitor through a 0.75 μH coil and a 10 Ω resistor.
9. Thermal characteristics
Table 4.
Thermal characteristics
Parameter
thermal resistance from in free air; JEDEC test
junction to ambient board
thermal resistance from in free air; JEDEC test
junction to case board
Symbol
Conditions
Typ
Unit
Rth(j-a)
124
K/W
Rth(j-c)
37
K/W
10. Characteristics
Table 5.
Characteristics
Tamb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Start-up current source (pin HV)
IHV
current on pin HV
VHV > 80 V
VCC < Vtrip
;
-
1.0
-
mA
Vth(UVLO) < VCC < Vstartup
V
trip < VCC < Vth(UVLO)
-
5.4
20
-
-
mA
μA
V
with auxiliary supply
8
40
-
VBR
breakdown voltage
650
Supply voltage management (pin VCC
)
Vtrip
trip voltage
0.55
0.65
0.75
V
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NXP Semiconductors
GreenChip III SMPS control IC
Table 5.
Characteristics …continued
Tamb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Vstartup
Parameter
Conditions
Min
21
Typ
22
Max
23
Unit
V
start-up voltage
Vth(UVLO)
undervoltage lockout threshold
voltage
14
15
16
V
Vstart(hys)
Vhys
hysteresis of start voltage
hysteresis voltage
during start-up phase
-
300
7
-
mV
V
Vstartup − Vth(UVLO)
6.3
−1.2
7.7
−0.8
Ich(low)
low charging current
VHV > 80 V; VCC < Vtrip or
Vth(UVLO) < VCC < Vstartup
−1.0
mA
Ich(high)
high charging current
VHV > 80 V; Vtrip < VCC < Vth(UVLO)
−4.6
−5.4
−6.3
mA
mA
ICC(oper)
operating supply current
no load on pins FBDRIVER and
PFCDRIVER
2.25
3
3.75
Input voltage sensing PFC (pin VINSENSE)
Vstop(VINSENSE)
Vstart(VINSENSE)
ΔVpu(VINSENSE)
stop voltage on pin VINSENSE
start voltage on pin VINSENSE
0.86
1.11
-
0.89
1.15
−100
0.92
1.19
-
V
V
pull-up voltage difference on
pin VINSENSE
active after Vstop(VINSENSE) is
detected
mV
Ipu(VINSENSE)
pull-up current on pin
VINSENSE
active after Vstop(VINSENSE) is
detected
−55
−47
−40
μA
Vmvc(VINSENSE)max maximum mains voltage
compensation voltage on pin
VINSENSE
4.0
-
-
V
Vflr
fast latch reset voltage
active after Vth(UVLO) is detected
-
-
0.75
0.12
-
-
V
V
Vflr(hys)
hysteresis of fast latch reset
voltage
II(VINSENSE)
Vbst(dual)
input current on pin VINSENSE VVINSENSE > Vstop(VINSENSE) after
Vstart(VINSENSE) is detected
5
33
100
nA
dual boost voltage
current switch-over point
switch-over region
-
-
2.2
-
-
V
200
mV
Loop compensation PFC (pin PFCCOMP)
gm
transconductance
VVOSENSE to IO(PFCCOMP)
VVOSENSE = 2.0 V
60
33
−45
-
80
100
45
−33
-
μA/V
μA
μA
V
IO(PFCCOMP)
output current on pin
PFCCOMP
39
VVOSENSE = 3.3 V
−39
3.5
Ven(PFCCOMP)
enable voltage on pin
PFCCOMP
[1]
[1]
Vclamp(PFCCOMP)
clamp voltage on pin
PFCCOMP
low power mode; PFC off; lower
clamp voltage
-
3.5
-
V
upper clamp voltage
-
3.7
3.5
-
V
V
Vton(PFCCOMP)zero zero on-time voltage on pin
PFCCOMP
3.4
3.6
Vton(PFCCOMP)max maximum on-time voltage on
pin PFCCOMP
1.20
1.25
1.30
V
TEA1752T_LT
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GreenChip III SMPS control IC
Table 5. Characteristics …continued
Tamb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Pulse width modulator PFC
ton(PFC) PFC on-time
Parameter
Conditions
Min
Typ
Max Unit
VVINSENSE = 3.3 V;
VPFCCOMP = Vton(PFCCOMP)max
3.6
30
4.5
40
5.0
53
μs
μs
VVINSENSE = 0.9 V;
VPFCCOMP = Vton(PFCCOMP)max
Output voltage sensing PFC (pin VOSENSE)
Vth(ol)(VOSENSE)
Vreg(VOSENSE)
Vovp(VOSENSE)
Ibst(dual)
open-loop threshold voltage on
pin VOSENSE
-
1.15
-
V
regulation voltage on pin
VOSENSE
for IO(PFCCOMP) = 0
2.475 2.500 2.525
2.60 2.63 2.67
V
overvoltage protection voltage
on pin VOSENSE
V
dual boost current
VVINSENSE < Vbst(dual) or
VVOSENSE < 2.1 V
-
-
−15
−30
-
-
μA
nA
VVINSENSE > Vbst(dual)
Overcurrent protection PFC (pin PFCSENSE)
Vsense(PFC)max
maximum PFC sense voltage ΔV/Δt = 50 mV/μs
ΔV/Δt = 200 mV/μs
0.49 0.52 0.55
0.51 0.54 0.57
V
V
tleb(PFC)
PFC leading edge blanking
time
250
310
370
ns
Iprot(PFCSENSE)
protection current on pin
PFCSENSE
−50
-
−5
nA
Soft start PFC (pin PFCSENSE)
Istart(soft)PFC
Vstart(soft)PFC
Vstop(soft)PFC
Rstart(soft)PFC
Oscillator PFC
fsw(PFC)max
PFC soft start current
−75
−60
−45
μA
V
PFC soft start voltage
PFC soft stop voltage
PFC soft start resistance
enabling voltage
disabling voltage
0.46 0.50 0.54
0.42 0.45 0.48
V
12
-
-
kΩ
maximum PFC switching
frequency
-
250
1.1
-
kHz
toff(PFC)min
minimum PFC off-time
0.8
1.4
μs
Valley switching PFC (pin PFCAUX)
(ΔV/Δt)vrec(PFC)
PFC valley recognition voltage
change with time
-
-
1.7
V/μs
[2]
[3]
tvrec(PFC)
PFC valley recognition time
VPFCAUX = 1 V peak-to-peak
-
-
300
50
6
ns
ns
μs
demagnetization to ΔV/Δt = 0
-
-
tto(vrec)PFC
PFC valley recognition time-out
time
3
4
Demagnetization management PFC (pin PFCAUX)
Vth(comp)PFCAUX
comparator threshold voltage
on pin PFCAUX
−150 −100 −50
40 50 60
mV
tto(demag)PFC
PFC demagnetization time-out
time
μs
TEA1752T_LT
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NXP Semiconductors
GreenChip III SMPS control IC
Table 5.
Characteristics …continued
Tamb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Iprot(PFCAUX)
protection current on pin
PFCAUX
VPFCAUX = 50 mV
−75
-
−5
nA
PFC off delay (pin PFCTIMER)
Isource(PFCTIMER)
source current on pin
-
−10
-
μA
PFCTIMER
Isink(PFCTIMER)
Vstart(PFCTIMER)
Vstop(PFCTIMER)
sink current on pin PFCTIMER
start voltage on pin PFCTIMER
stop voltage on pin PFCTIMER
-
-
-
0.9
-
-
-
mA
V
1.27
3.6
V
Driver (pin PFCDRIVER)
Isrc(PFCDRIVER) source current on pin
VPFCDRIVER = 2 V
-
−0.5
-
A
PFCDRIVER
Isink(PFCDRIVER)
sink current on pin
PFCDRIVER
VPFCDRIVER = 2 V
VPFCDRIVER = 10 V
-
-
-
0.7
1.2
11
-
A
A
V
-
VO(PFCDRIVER)max maximum output voltage on pin
PFCDRIVER
12
Overvoltage protection flyback (pin FBAUX)
Iovp(FBAUX)
overvoltage protection current
on pin FBAUX
279
6
300
8
321
12
μA
Ncy(ovp)
number of overvoltage
protection cycles
Demagnetization management flyback (pin FBAUX)
Vth(comp)FBAUX
comparator threshold voltage
on pin FBAUX
60
80
-
110
mV
nA
Iprot(FBAUX)
protection current on pin
FBAUX
VFBAUX = 50 mV
−75
−5
Vclamp(FBAUX)
clamp voltage on pin FBAUX
IFBAUX = −100 μA
IFBAUX = 300 μA
−0.85 −0.7
−0.55
1.09
2.5
V
0.79
1.5
0.94
2
V
tsup(xfmr_ring)
transformer ringing
suppression time
μs
Pulse width modulator flyback
ton(fb)min
minimum flyback on-time
-
tleb
40
-
ns
ton(fb)max
maximum flyback on-time
32
48
μs
Oscillator flyback
fsw(fb)max
maximum flyback switching
frequency
100
125
1.5
86
150
kHz
V
Vstart(VCO)FBCTRL
fsw(fb)swon(PFC)
fsw(fb)swoff(PFC)
ΔVVCO(FBCTRL)
VCO start voltage on pin
FBCTRL
1.3
1.7
PFC switch-on flyback
switching frequency
-
-
-
-
-
-
kHz
kHz
V
PFC switch-off flyback
switching frequency
48
VCO voltage difference on pin
FBCTRL
−0.2
TEA1752T_LT
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Product data sheet
Rev. 02 — 24 June 2010
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TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
Table 5.
Characteristics …continued
Tamb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Peak current control flyback (pin FBCTRL)
VFBCTRL
voltage on pin FBCTRL
for maximum flyback peak current
enable voltage
1.85
2.0
2.5
4.5
3
2.15
V
Vto(FBCTRL)
time-out voltage on pin
FBCTRL
-
-
V
trip voltage
4.2
-
4.8
-
V
Rint(FBCTRL)
IO(FBCTRL)
internal resistance on pin
FBCTRL
kΩ
output current on pin FBCTRL VFBCTRL = 0 V
VFBCTRL = 2 V
−1.4
−0.6
−36
−1.19 −0.93 mA
−0.5
−30
−0.4
−24
mA
Ito(FBCTRL)
time-out current on pin
FBCTRL
VFBCTRL = 2.6 V
VFBCTRL = 4.1 V
μA
−34.5 −28.5 −22.5 μA
Valley switching flyback (pin HV)
(ΔV/Δt)vrec(fb)
flyback valley recognition
voltage change with time
−75
-
+75
-
V/μs
[4]
td(vrec-swon)
valley recognition to switch-on
delay time
-
150
ns
Soft start flyback (pin FBSENSE)
Istart(soft)fb
Vstart(soft)fb
Rstart(soft)fb
flyback soft start current
−75
0.55
16
−60
0.63
-
−45
0.70
-
μA
V
flyback soft start voltage
enable voltage
flyback soft start resistance
kΩ
Overcurrent protection flyback (pin FBSENSE)
Vsense(fb)max
maximum flyback sense
voltage
ΔV/Δt = 50 mV/μs
ΔV/Δt = 200 mV/μs
0.61
0.64
0.65
0.68
0.69
0.72
V
V
Vsense(fb)min
tleb(fb)
minimum flyback sense voltage ΔV/Δt = 50 mV/μs
0.305 0.325 0.345
V
flyback leading edge blanking
time
255
305
355
ns
Iadj(FBSENSE)
adjust current on pin
FBSENSE
peak current
−3.2
−3.0
−2.8
μA
Overpower protection flyback (pin FBSENSE)
Vsense(fb)max
maximum flyback sense
voltage
ΔV/Δt = 50 mV/μs
IFBAUX = 80 μA
IFBAUX = 120 μA
IFBAUX = 240 μA
IFBAUX = 360 μA
0.61
0.57
0.47
0.41
0.65
0.62
0.52
0.46
0.69
0.67
0.57
0.51
V
V
V
V
Driver (pin FBDRIVER)
Isrc(FBDRIVER) source current on pin
FBDRIVER
VFBDRIVER = 2 V
-
−0.5
-
A
Isink(FBDRIVER)
sink current on pin FBDRIVER VFBDRIVER = 2 V
VFBDRIVER = 10 V
-
-
-
0.7
1.2
11
-
A
A
V
-
VO(FBDRIVER)(max) maximum output voltage on pin
FBDRIVER
12
TEA1752T_LT
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Product data sheet
Rev. 02 — 24 June 2010
26 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
Table 5.
Characteristics …continued
Tamb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LATCH input (pin LATCH)
Vprot(LATCH)
protection voltage on pin
1.23
1.25
1.27
V
LATCH
IO(LATCH)
output current on pin LATCH
enable voltage on pin LATCH
Vprot(LATCH) < VLATCH < Voc(LATCH)
at start-up
−85
1.30
80
−80
1.35
100
−75
1.40
140
μA
V
Ven(LATCH)
Vhys(LATCH)
hysteresis voltage on pin
LATCH
Ven(LATCH) − Vprot(LATCH)
mV
Voc(LATCH)
open-circuit voltage on pin
LATCH
2.65
2.9
3.15
V
Temperature protection
Tpl(IC)
IC protection level temperature
130
-
140
10
150
-
°C
°C
Tpl(IC)hys
hysteresis of IC protection level
temperature
[1] For a typical application with a compensation network on pin PFCCOMP (see Figure 3).
[2] Minimum required voltage change time for valley recognition on pin PFCAUX.
[3] Minimum time required between demagnetization detection and ΔV/Δt = 0 on pin PFCAUX.
[4] Guaranteed by design.
TEA1752T_LT
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Product data sheet
Rev. 02 — 24 June 2010
27 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
11. Application information
A power supply with the TEA1752(L)T consists of a power factor correction circuit
followed by a flyback converter (See Figure 18).
Capacitor CVCC buffers the IC supply voltage, which is powered via the high voltage
rectified mains supply during start-up and via the auxiliary winding of the flyback converter
during operation. Sense resistors RSENSE1 and RSENSE2 convert the current through
MOSFETs S1 and S2 into a voltage on pins PFCSENSE and FBSENSE. The values of
R
SENSE1 and RSENSE2 define the maximum primary peak current on MOSFETs S1 and S2.
In the example shown in Figure 18, the LATCH pin is connected to a Negative
Temperature Coefficient (NTC) resistor. When the resistance drops below
Vprot(LATCH)
IO(LATCH)
= 15.6 kΩ (typical) , the protection is activated. A capacitor CTIMEOUT is
-------------------------------
connected to the FBCTRL pin. Time-out protection is activated typically after 10 ms for a
120 nF capacitor. RLOOP is added so the time-out capacitor does not interfere with the
normal regulation loop.
R
S1 and RS2 prevent the soft start capacitors from being charged during normal operation
due to negative voltage spikes across the sense resistors.
Resistor RAUX1 protects the IC from damage during events such as lightning strikes.
TEA1752T_LT
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
28 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
D1
S1
C
bus
D2
C
R
SS1
SS1
T2
C
OUT
R
R
SENSE1
R
AUX1
S1
S2
PFCDRIVER PFCSENSE
12 11
8
VOSENSE HV FBTIMER
16 13
9
PFCAUX
FBSENSE
10
R
S2
PFCCOMP
compensation
R
6
SS2
C
SS2
VINSENSE
TEA1752(L)T
R
R
AUX2
SENSE2
7
FBAUX
4
V
CC
1
5
FBCTRL
LATCH
3
2
14
PFCTIMER
GND
C
VCC
R
LOOP
Θ
C
TIMEOUT
014aaa750
Fig 18. Typical application diagram TEA1752(L)T
TEA1752T_LT
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Product data sheet
Rev. 02 — 24 June 2010
29 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 19. Package outline SOT109-1 (SO16)
TEA1752T_LT
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Product data sheet
Rev. 02 — 24 June 2010
30 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
13. Revision history
Table 6.
Revision history
Document ID
TEA1752T_LT v.2
Modifications
Release date
Data sheet status
Change notice
Supersedes
20100624
Product data sheet
-
TEA1752T_LT_1
• Template upgraded to Rev 2.12.0 including revised legal information.
• Text and drawings updated throughout entire data sheet.
• Figure 1 updated.
• Vstop(soft)PFC added in Table 5.
• Minimum junction temperature changed in Table 3.
TEA1752T_LT_1
20090213
Objective data sheet
-
-
TEA1752T_LT
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Product data sheet
Rev. 02 — 24 June 2010
31 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
14.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
14.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
TEA1752T_LT
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Product data sheet
Rev. 02 — 24 June 2010
32 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
GreenChip — is a trademark of NXP B.V.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TEA1752T_LT
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 24 June 2010
33 of 34
TEA1752T; TEA1752LT
NXP Semiconductors
GreenChip III SMPS control IC
16. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
7.3.10
7.3.11
Overpower protection. . . . . . . . . . . . . . . . . . . 20
Driver (pin FBDRIVER) . . . . . . . . . . . . . . . . . 21
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Distinctive features . . . . . . . . . . . . . . . . . . . . . . 1
Green features . . . . . . . . . . . . . . . . . . . . . . . . . 1
PFC green features . . . . . . . . . . . . . . . . . . . . . 2
Flyback green features. . . . . . . . . . . . . . . . . . . 2
Protection features . . . . . . . . . . . . . . . . . . . . . . 2
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 21
Thermal characteristics . . . . . . . . . . . . . . . . . 22
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22
Application information . . . . . . . . . . . . . . . . . 28
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . 31
2.1
2.2
2.3
2.4
2.5
9
10
11
12
13
3
4
5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
14
Legal information . . . . . . . . . . . . . . . . . . . . . . 32
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 32
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 33
14.1
14.2
14.3
14.4
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
7.1
Functional description . . . . . . . . . . . . . . . . . . . 6
General control. . . . . . . . . . . . . . . . . . . . . . . . . 6
Start-up and UnderVoltage LockOut (UVLO) . . 6
Supply management. . . . . . . . . . . . . . . . . . . . . 8
Latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Fast latch reset. . . . . . . . . . . . . . . . . . . . . . . . . 9
OverTemperature Protection (OTP) . . . . . . . . . 9
Power Factor Correction circuit (PFC) . . . . . . . 9
ton control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Valley switching and demagnetization
15
16
Contact information . . . . . . . . . . . . . . . . . . . . 33
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.2.1
7.2.2
(PFCAUX pin). . . . . . . . . . . . . . . . . . . . . . . . . . 9
Frequency limitation . . . . . . . . . . . . . . . . . . . . 10
Mains voltage compensation
7.2.3
7.2.4
(VINSENSE pin) . . . . . . . . . . . . . . . . . . . . . . . 10
Soft start-up (pin PFCSENSE) . . . . . . . . . . . . 10
Low power mode . . . . . . . . . . . . . . . . . . . . . . 11
PFC off delay (pin PFCTIMER) . . . . . . . . . . . 11
Dual boost PFC . . . . . . . . . . . . . . . . . . . . . . . 12
Overcurrent protection (PFCSENSE pin) . . . . 12
Mains undervoltage lockout/brownout
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
protection (VINSENSE pin) . . . . . . . . . . . . . . 12
Overvoltage protection (VOSENSE pin). . . . . 13
PFC open-loop protection (VOSENSE pin) . . 13
Driver (pin PFCDRIVER) . . . . . . . . . . . . . . . . 13
Flyback controller . . . . . . . . . . . . . . . . . . . . . . 13
Multimode operation. . . . . . . . . . . . . . . . . . . . 13
Valley switching (HV pin) . . . . . . . . . . . . . . . . 15
Current mode control (FBSENSE pin) . . . . . . 16
Demagnetization (FBAUX pin) . . . . . . . . . . . . 17
Flyback control/time-out (FBCTRL pin) . . . . . 17
Soft start-up (pin FBSENSE) . . . . . . . . . . . . . 18
Maximum on-time. . . . . . . . . . . . . . . . . . . . . . 19
Overvoltage protection (FBAUX pin) . . . . . . . 19
Overcurrent protection (FBSENSE pin) . . . . . 20
7.2.11
7.2.12
7.2.13
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 June 2010
Document identifier: TEA1752T_LT
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