PL611S-26-XXXTC [PLL]
1.8V-3.3V PicoPLLTM Programmable Clock; 1.8V - 3.3V PicoPLLTM可编程时钟
| 型号： | PL611S-26-XXXTC |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | 1.8V-3.3V PicoPLLTM Programmable Clock |
| 文件： | 总8页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
(Preliminary)PL611s-26
1.8V-3.3V PicoPLLTM Programmable Clock
FEATURES
DESCRIPTION
The PL611s-26 is a general purpose frequency
synthesizer and a member of PhaseLink’s PicoPLLTM
product family. Designed to fit in a small 6-pin DFN
or 6-pin SOT package for high performance
• Advanced One Time Programmable (OTP) PLL design
• Programmable PLL or direct oscillation operation
• Very low Jitter and Phase Noise (30-70ps Pk-Pk
typical)
applications, the PL611s-26 offers very low phase
noise, jitter, and power consumption, while offering
up to 2 clock outputs.. The Frequency Switching
(FSEL) capability of PL611s-26 allows for
programming two sets of frequencies, while the
power down feature of PL611s-26, when activated,
allows the IC to consume less than 10µA of power.
PL611s-26’s programming flexibility allows
• Output Frequency up to
o133MHz @ 1.8V operation
o166MHz @ 2.5V operation
o200MHz @ 3.3V operation
• Reference Input Frequency: 1MHz to 200MHz
• Accepts >0.1V reference signal input voltage
• Low current consumption, <10µA when PDB is
activated
• One programmable I/O pin can be configured as
Output Enable (OE),Power Down (PDB) input or an
additional clock output (CLK1).
generating any output using Reference input signal.
• Frequency Switching (FSEL) capability
• Single 1.8V, 2.5V, or 3.3V ± 10% power supply
• Operating temperature range from -40°C to 85°C
• Available in 6-pin SOT23 and DFN GREEN/RoHS
compliant packaging
BLOCK DIAGRAM
FREF
R-Counter
(8-bit)
FIN
Phase
Detector
Charge
Pump
Loop
Filter
M-Counter
(11-bit)
FVCO = FREF * (2 * M/R)
VCO
P-Counter
(5-bit)
CLK0
FSEL
FOUT = FVCO / (2 * P)
Programming
Logic
Programmable Function
OE, PDB,
CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 1
(Preliminary)PL611s-26
1.8V-3.3V PicoPLLTM Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Programmable
Input/Output
Output Drive Strength
Output Frequency
F
OUT = FREF * M / (R * P)
Where M = 11 bit
R = 8 bit
Three optional drive strengths to
choose from:
One output pin can be configured
as:
P = 5 bit
• Low: 4mA
• OE - input
CLK0 = FOUT, FREF or FREF / (2*P)
CLK1 = FREF, FREF/2, CLK0 or CLK0/2
• Std: 8mA (default)
• High: 16mA
• PDB - input
• CLK1 – output
PACKAGE PIN CONFIGURATION AND DESCRIPTION
OE, PDB, CLK1
CLK0
VDD
1
2
3
6
5
4
FIN
OE,PDB,CLK1
GND
FSEL
VDD
CLK0
1
2
3
6
5
4
GND
FIN
FSEL
DFN-6L
(2.0mmx1.3mmx0.6mm)
SOT23-6L
(3.0mmx3.0mmx1.35mm)
PIN DESCRIPTION
Pin Assignment
DFN Pin# SOT Pin #
Name
Type
Description
This programmable I/O pin can be configured as an Output Enable (OE)
input, Power Down input (PDB) or CLK1 Clock output. This pin has an
internal 60KΩ pull up resistor (OE and PDB functions only).
OE,
PDB,
CLK1
2
1
I/O
Pin State
OE
PDB
0
Disable CLK
Normal mode
Power Down Mode
Normal mode
1 (default)
GND
FIN
3
1
2
3
P
I
GND connection
Reference input pin
Frequency Switching Input pin. This pin has an internal 60KΩ pull up
resistor.
FSEL
State
FSEL
6
4
I
0
Frequency 2
Frequency 1
1 (default)
VDD
5
4
5
6
P
VDD connection
Programmable Clock Output
CLK0
O
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 2
(Preliminary)PL611s-26
1.8V-3.3V PicoPLLTM Programmable Clock
FUNCTIONAL DESCRIPTION
PL611s-26 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-26 accepts a reference clock input of 1MHz to 200MHz and is
capable of producing two outputs up to 200MHz. This flexible design allows the PL611s-26 to deliver any PLL
generated frequency, FREF (Ref Clk) frequency or FREF /(2*P) to CLK0 and/or CLK1. Some of the design features
of the PL611s-26 are mentioned below:
PLL Programming
Frequency Select (FSEL)
The PLL in the PL611s-26 is fully programmable.
The PLL is equipped with an 8-bit input frequency
divider (R-Counter), and an 11-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 5-bit post VCO divider (P-
Counter). The output frequency is determined by
the following formula [FOUT = FREF * M / (R * P) ].
The Frequency Select (FSEL) feature allows the
PL611s-26 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60kΩ pull
up resistor giving a default condition of logic “1”.
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60kΩ pull up
resistor giving a default condition of logic “1”.
Clock Output (CLK0)
CLK0 is the main clock output. The PL611s-26 can
also be programmed to provide a second clock
output, CLK1, on the programmable I/O pin (see
OE/PDB/CLK1 pin description below). The output of
CLK0 can be configured as the PLL output
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to
put the PL611s-26 into “Sleep Mode”. When
(FVCO/(2*P)), FREF (Ref Clk Frequency) output, or
F
REF/(2*P) output. The output drive level can be
activated (logic ‘0’), PDB ‘Disables the PLL, the
oscillator circuitry, counters, and all other active
circuitry. In Power Down mode the IC consumes
<10µA of power. The PDB pin incorporates a 60kΩ
pull up resistor giving a default condition of logic “1”.
programmed to Low Drive (4mA), Standard Drive
(8mA) or High Drive (16mA). The maximum output
frequency is determined by the power supply voltage
as shown below:
Clock Output (CLK1)
The CLK1 feature allows the PL611s-26 to have an
additional clock output. This output can be
programmed to one of the following:
F
F
REF - Reference (Ref Clk ) Frequency
REF / 2
CLK0
CLK0 / 2
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 3
(Preliminary)PL611s-26
1.8V-3.3V PicoPLLTM Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
VDD
7
V
V
-
-
-
0.5
0.5
0.5
Input Voltage Range
V
VDD
VDD
+
+
0.5
0.5
I
Output Voltage Range
V
V
O
Soldering Temperature (Green package)
Data Retention @ 85°C
260
°C
Year
°C
°C
10
Storage Temperature
-65
-40
150
85
T
S
Ambient Operating Temperature*
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX. UNITS
@ VDD =3.3V
@ VDD =2.5V
@ VDD =1.8V
200
Input (FIN) Frequency
1
MHz
Vpp
166
133
VDD
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Internally AC coupled (High Frequency)
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
0.9
0.1
VDD
Vpp
@ VDD =3.3V
200
166
133
2
MHz
MHz
MHz
ms
ns
Output Frequency
@ VDD =2.5V
@ VDD =1.8V
Settling Time
At power-up (after VDD increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
10
Output Enable Time
PDB Function; Ta=25º C, 15pF Load
15pF Load, 10/90% VDD, High Drive, 3.3V
15pF Load, 90/10% VDD, High Drive, 3.3V
VDD /2
2
ms
ns
Output Rise Time
Output Fall Time
Duty Cycle
1.2
1.2
50
1.7
1.7
55
ns
45
%
Period Jitter,Pk-to-Pk*
(measured from 10,000 samples) GND.
With capacitive decoupling between VDD and
70
ps
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 4
(Preliminary)PL611s-26
1.8V-3.3V PicoPLLTM Programmable Clock
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
5.5
MAX.
UNITS
mA
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic with
Loaded CMOS Outputs
Stand By Current, with Loaded
Outputs
@ VDD =3.3V, 27MHz,
load=15pF
@ VDD =2.5V, 27MHz,
load=15pF
@ VDD =1.8V, 27MHz,
load=15pF
IDD
IDD
IDD
IDD
3.8
mA
1.8*
mA
When PDB=0
<10
µA
Operating Voltage
VDD
VOL
VOH
IOSD
1.62
3.63
0.4
V
V
Output Low Voltage
Output High Voltage
Output Current, Low Drive
IOL = +4mA Standard Drive
IOH = -4mA Standard Drive
VOL = 0.4V, VOH = 2.4V
VDD – 0.4
V
4
8
mA
Output Current, Standard Drive
Output Current, High Drive
IOSD
IOHD
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
mA
mA
16
* Note: Please contact PhaseLink, if super low-power is required.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 5
(Preliminary)PL611s-26
1.8V-3.3V PicoPLLTM Programmable Clock
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
- Keep all the PCB traces to the PL611s-26 as short
as possible, as well as keeping all other traces as
far away from it as possible.
- Place a 0.01µF~0.1µF decoupling capacitor
between VDD and GND, on the component side of
the PCB, close to the VDD pin. It is not
recommended to place this component on the
backside of the PCB. Going through vias will reduce
the signal integrity, causing additional jitter and
phase noise.
- It is highly recommended to keep the VDD and
GND traces as short as possible.
- When connecting long traces (> 1 inch) to a CMOS
output, it is important to design the traces as a
transmission line or ‘stripline’, to avoid reflections or
ringing. In this case, the CMOS output needs to be
matched to the trace impedance. Usually ‘striplines’
are designed for 50Ω impedance and CMOS outputs
usually have lower than 50 Ω impedance so
matching can be achieved by adding a resistor in
series with the CMOS output pin to the ‘stripline’
trace.
- Please contact PhaseLink for additional information
on how to design outputs driving long traces or for
the Gerber files for the PL611s-26 eval board
shown.
DFN-6L Evaluation Board
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 6
(Preliminary)PL611s-26
1.8V-3.3V PicoPLLTM Programmable Clock
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOT23-6L
Dimension in MM
Symbol
Min.
1.05
0.05
1.00
0.30
0.08
2.80
1.50
2.60
0.35
Max.
1.35
0.15
1.20
0.50
0.20
3.00
1.70
3.0
E
H
A
A1
A2
b
D
c
D
E
A2
A
H
L
A1
C
0.55
b
e
L
e
0.95 BSC
DFN-6L
D1
Dimension in MM
e
Symbol
D
b
Min.
0.50
0.00
0.152
0.15
Max.
0.60
0.05
0.152
0.25
Pin 6 ID
Chamfer
A
A1
A3
b
E
E1
e
0.40BSC
D
1.25
1.95
0.75
0.95
0.20
1.35
2.05
0.85
1.05
0.30
L
E
Pin1 Dot
D1
E1
L
A1
A
A3
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 7
(Preliminary)PL611s-26
1.8V-3.3V PicoPLLTM Programmable Clock
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
PL611s-26-XXX X X X
PART NUMBER
3 DIGIT ID Code *
(will be assigned at
programming time)
NONE= TUBE
R=TAPE and REEL
PACKAGE TYPE
G=DFN-6L
T=SOT23-6L
TEMPERATURE
C=COMMERCIAL
I = INDUSTRIAL
Part/Order Number
Marking†
Package Option
PL611s-26-XXXGC-R
PL611s-26-XXXTC-R
XXX
6-Pin DFN (Tape and Reel)
6-Pin SOT23 (Tape and Reel)
26XXX
† Note: ‘XXX’ designates marking identifier that, at times, could be independent of the part number. Please consult your
PhaseLink sales for marking information.
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 8
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