PLL500-27BSCLR [PLL]
Low Power CMOS Output VCXO Family (17MHz to 130MHz); 低功耗CMOS输出VCXO系列（ 17MHz至为130MHz ）
| 型号： | PLL500-27BSCLR |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | Low Power CMOS Output VCXO Family (17MHz to 130MHz) |
| 文件： | 总5页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL500-17B/27B/37B
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
FEATURES
PIN CONFIGURATION
•
VCXO output for the 17MHz to 130MHz range
XIN
OE^
VIN
XOUT
DS^
1
2
3
4
8
7
6
5
-
-
-
PLL500-17B: 17MHz to 36MHz
PLL500-27B: 27MHz to 65MHz
PLL500-37B: 65MHz to 130MHz
VDD*
CLK
•
•
•
Low phase noise (-142 dBc @ 10kHz offset).
CMOS output with OE tri-state control.
Selectable output drive (Standard or High drive).
GND
^: Denotes internal Pull-up
-
-
Standard: 8mA drive capability at TTL level.
High: 24mA drive capability at TTL level.
•
•
•
•
•
•
Fundamental crystal input.
DIE PAD LAYOUT
32 mil
(812,986)
Integrated high linearity variable capacitors.
+/- 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5 to 3.3V operation.
8
XOUT
1
2
XIN
DRIVSEL^
7
Available in 8-Pin SOIC or DIE.
OE^
DESCRIPTION
VDD
CLK
6
5
The PLL500-17B/27B/37B are a low cost, high per-
formance, low phase noise, and high linearity VCXO
family for the 17 to 130MHz range, providing less
than -130dBc at 10kHz offset. The very low jitter (2.5
ps RMS period jitter) makes these chips ideal for
applications requiring voltage controlled frequency
sources. The IC’s are designed to accept fundamen-
tal resonant mode crystals.
VCON
GND
3
4
DIE ID:PLL500-17B: C500A0505-05P
PLL500-27B: C500A0505-05Q
PLL500-37B: C500A0505-05R
(0,0)
Y
X
Note: ^ denotes internal pull up
FREQUENCY RANGE
DIE SPECIFICATIONS
PART #
MULTIPLIER
No PLL
FREQUENCY
17 – 36 MHz
27 – 65 MHz
65 – 130 MHz
Name
Value
PLL500-17B
PLL500-27B
PLL500-37B
Size
39 x 32 mil
GND
No PLL
Reverse side
No PLL
Pad dimensions
Thickness
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
XIN
XTAL
OSC
XOUT
VARICAP
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/21/05 Page 1
PLL500-17B/27B/37B
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
PIN AND PAD DESCRIPTION
Die Pad Position
Name
Pin#
Type
Description
X (µm)
Y (µm)
XIN
OE
1
2
94.183
768.599
I
I
Crystal input pin.
Output Enable input pin. Disables the output when low. Internal
pull-up enables output by default if pin is not connected low.
94.157
605.029
VCON
GND
CLK
3
4
5
6
94.183
94.193
331.756
140.379
203.866
455.726
I
Frequency control voltage input pin.
Ground pin.
P
O
P
715.472
715.307
Output clock pin.
VDD
VDD power supply pin.
Output drive select pin. High drive if set to ‘0’. Low drive if set
to ‘1’. Internal pull-up.
Crystal output pin. Ref clock input.
DRIVSEL
XOUT
7
8
715.472
476.906
626.716
888.881
I
I
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
VDD+0.5
VDD+0.5
150
V
Input Voltage, dc
-0.5
-0.5
-65
V
Output Voltage, dc
VO
TS
TA
TJ
V
Storage Temperature
°C
°C
°C
°C
kV
Ambient Operating Temperature*
Junction Temperature
-40
85
125
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
260
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
PLL500-17B
MIN.
TYP.
MAX.
UNITS
17
27
65
36
65
Input Crystal Frequency
MHz
PLL500-27B
PLL500-47B
130
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Measured @ 1.4V
0.8
2.5
50
Output Clock Rise/Fall Time
ns
Output Clock Duty Cycle
Short Circuit Current
45
55
%
mA
±50
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/21/05 Page 2
PLL500-17B/27B/37B
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
3. Voltage Control Crystal Oscillator
PARAMETERS
SYMBOL
CONDITIONS
From power valid
MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
TVCXOSTB
10
ms
FXIN = 12 – 25MHz;
XTAL C0/C1 < 250
0V ≤ VCON ≤ 3.3V
VCXO Tuning Range
300
100
ppm
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
ppm
ppm/V
%
VCON=1.65V, ±1.65V
±150
5
Frequency change with
VDD varied +/- 10%
Power Supply Rejection
PWSRR
-1
+1
ppm
VCON pin input impedance
VCON modulation BW
2000
45
kΩ
kHz
0V ≤ VCON ≤ 3.3V, -3dB
Note: Preliminary Specifications still to be characterized. Parameters denoted with an asterisk (*) represent nominal characterization data and are not
production tested to any specific limits.
4. Jitter and Phase Noise Specifications
PARAMETERS
RMS Period Jitter
(1 sigma – 10,000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
CONDITIONS
MIN.
TYP.
MAX.
UNITS
With capacitive decoupling
between VDD and GND.
2.5
ps
@100Hz offset
@1kHz offset
@10kHz offset
@100kHz offset
@1MHz offset
-100
-125
-142
-150
-150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise relative to carrier
Phase Noise relative to carrier
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/21/05 Page 3
PLL500-17B/27B/37B
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
5. DC Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
FXIN = 27MHz, 15pF output load
FXIN = 35MHz, 15pF output load
FXIN = 78MHz, 15pF output load
PLL500-17B
2.8
4.2
7.2
4
6
Supply Current, Dynamic,
with Loaded Outputs
IDD
mA
9
30
20
pF
pF
PLL500-27B
PLL500-37B Std drive up to
100MHz
Allowable output load
capacitance
CL
(Output)
15
pF
PLL500-37B High drive
10
pF
V
Operating Voltage
Output High Voltage
Output Low Voltage
VDD
VOH
VOL
2.25
2.4
3.63
IOH = -8mA
IOL = 8mA
V
0.4
V
Output High Voltage at
CMOS level
IOH = -4mA
VDD – 0.4
V
Standard drive at TTL level
High drive at TTL level
8
9.5
27
Output drive current
mA
24
Short Circuit Current
VCXO Control Voltage
mA
V
±50
VCON
0
VDD
6. Crystal Specifications
PARAMETERS
SYMBOL
MIN.
TYP.
MAX.
UNITS
Crystal Loading Rating (VCON = 1.65V)
Maximum Sustainable Drive Level
Operating Drive Level
Max C0 for PLL500-17B
Max C0 for PLL500-27B
Max C0 for PLL500-37B
C0/C1
8.5
pF
CL
(xtal)
200
µW
µW
50
5
pF
3.5
2.5
250
30
-
ESR
RS
Ω
Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally.
This however may reduce the pull range.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/21/05 Page 4
PLL500-17B/27B/37B
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
PACKAGE INFORMATION
SOIC 8L(Dimensions in mm)
Dimension in MM
Symbol
Min.
1.35
0.10
1.25
0.33
0.19
4.80
3.80
5.80
0.40
Max.
1.75
0.25
1.50
0.53
0.27
5.00
4.00
6.20
0.89
A
A1
A2
B
E
H
D
C
D
E
A2
A
H
A1
C
L
L
b
e
1.27 BSC
e
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL500-X7B X X X X
NONE= TUBE
PART NUMBER
R=TAPE AND REEL
NONE=NORMAL PACKAGE
L=GREEN PACKAGE
PACKAGE TYPE
S=SSOP
TEMPERATURE
C=COMMERCIAL
I=INDUSTRIAL
Order Number
PLL500-X7BDC
PLL500-X7BSC
PLL500-X7BSC-R
PLL500-X7BSCL
PLL500-X7BSCL-R
Marking
Package Option
Die (Waffle Pack)
8-Pin SOIC (Tube)
8-Pin SOIC (Tape and Reel)
8-Pin SOIC (Tube), GREEN
8-Pin SOIC (Tape and Reel) , GREEN
P500-X7BDC
P500-X7BSC
P500-X7BSC
P500-X7BSCL
P500-X7BSCL
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/21/05 Page 5
相关型号：
©2020 ICPDF网 联系我们和版权申明