PLL620-3XOIL [PLL]
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output); PECL和LVDS低相位噪声XO （ 32.5至为130MHz输出）
| 型号： | PLL620-3XOIL |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) |
| 文件： | 总6页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL620-38/39
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)
FEATURES
PIN CONFIGURATION
•
•
•
•
•
•
65MHz to 130MHz Crystal input.
Output range: 32.5MHz – 130MHz (no PLL).
Low Injection Power for crystal, 50uW.
PECL (PLL620-38) or LVDS output (PLL620-39).
Supports 2.5V or 3.3V-Power Supply.
Available in 16-Pin TSSOP.
V D D
XIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D N C
D N C
XOU T
D N C
G N D
CLK C
V D D
DESCRIPTION
S2^
OE _CT RL
D N C
CLK T
G N D B U F
G N D
The PLL620-38/-39 is a family of XO IC’s specifically
designed to work with high frequency fundamental or
3rd OT crystals from 65MHz to 130MHz, with
selectable PECL or LVDS outputs. They achieve
very low current into the crystal resulting in better
overall stability. Their very low jitter makes them
ideal for the most demanding timing requirements.
G N D
Note: ^ designates internal pull-up resistor.
BLOCK DIAGRAM
OUTPUT ENABLE LOGICAL LEVELS
OE
Q
Part #
OE
0
(Default)
State
Output enabled
PLL620-38
Q
Oscillator
1
Tri-state
Tri-state
Amplifier
XIN
0
1
PLL620-39
S2
Output enabled
(Default)
XOUT
PLL620-38/-39
OE input: Logical states defined by PECL levels for PLL620-38
Logical states defined by CMOS levels for PLL620-39
OUTPUT FREQUENCY SELECTOR
S2
Output
0
Input/2
Input
1(Default)*
*Internally set to ‘Default’ through 60KΩ pull-up resistor
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/15/05 Page 1
PLL620-38/-39
PECL and LVDS Low Phase Noise XO (for 32.5-130MHz Output)
PIN DESCRIPTIONS
Name
Number
Type
Description
XIN
XOUT
2
3
I
I
Crystal input. See Crystal Specifications on page 2.
Crystal output. See Crystal Specifications on page 2.
When pulled low the output is equal to the input divided by 2. Internal
pull up.
S2
5
I
OE_CTRL
GND
6
8, 14
I
Output enable. See Output Enable Logic table on page 1.
P
O
O
-
Ground.
CLKT
CLKC
DNC
11
True output PECL (PLL620-38) or LVDS (PLL620-39).
Complementary output PECL (PLL620-38) or LVDS (PLL620-39).
Do Not connect.
13
4,7,10,15,16
1, 12
VDD
P
Power supply.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
VDD+0.5
VDD+0.5
150
V
Input Voltage, dc
-0.5
-0.5
-65
V
Output Voltage, dc
VO
TS
TA
TJ
V
Storage Temperature
°C
°C
°C
°C
kV
Ambient Operating Temperature*
Junction Temperature
-40
85
125
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
260
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Loading Rating
CL (xtal)
C0
8.5
2.6
65MHz to 130MHz
(VDD=3.3V)
pF
Inter-electrode capacitance
Crystal Resonator Frequency
FXIN
Fund.
65
130
MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/15/05 Page 2
PLL620-38/-39
PECL and LVDS Low Phase Noise XO (for 32.5-130MHz Output)
3. General Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current (Loaded
Outputs)
Operating Voltage
IDD
PECL/LVDS
100/80
3.63
mA
V
VDD
2.97
@ 1.25V (LVDS)
@ VDD – 1.3V (PECL)
45
45
50
50
±50
55
55
Output Clock Duty Cycle
Short Circuit Current
%
mA
4. Jitter Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Period jitter RMS
77.76MHz
77.76MHz
2.5
18.5
0.5
ps
ps
ps
Period jitter peak-to-peak
Integrated jitter RMS
Integrated 12kHz to 20MHz at 77.76MHz
5. Phase Noise Specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz
@1kHz @10kHz @100kHz UNITS
Phase Noise relative
to carrier
77.76MHz
-75
-95
-125
-145
-155
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/15/05 Page 3
PLL620-38/-39
PECL and LVDS Low Phase Noise XO (for 32.5-130MHz Output)
6. LVDS Electrical Characteristics
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
∆VOD
VOH
247
-50
355
454
50
mV
mV
V
1.4
1.1
1.2
3
1.6
RL = 100 Ω
(see figure)
VOL
0.9
1.125
0
V
VOS
1.375
25
V
Offset Magnitude Change
mV
∆VOS
Vout = VDD or GND
VDD = 0V
Power-off Leakage
IOXD
IOSD
uA
±1
±10
Output Short Circuit Current
-5.7
-8
mA
7. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
RL = 100 Ω
CL = 10 pF
(see figure)
Differential Clock Rise Time
Differential Clock Fall Time
tr
tf
0.2
0.2
0.7
0.7
1.0
1.0
ns
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50
50
Ω
Ω
VOD
VOS
VDIFF
RL = 100Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
80%
80%
VDIFF
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/15/05 Page 4
PLL620-38/-39
PECL and LVDS Low Phase Noise XO (for 32.5-130MHz Output)
8. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Output High Voltage
Output Low Voltage
VOH
VOL
VDD – 1.025
V
V
RL = 50 Ω to (VDD – 2V)
(see figure)
VDD – 1.620
9. PECL Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Clock Rise Time
Clock Fall Time
tr
tf
@20/80% - PECL
@80/20% - PECL
0.6
0.5
1.5
1.5
ns
ns
PECL Levels Test Circuit
PECL Output Skew
OUT
VDD
OUT
50
50
Ω
Ω
2.0V
50%
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/15/05 Page 5
PLL620-38/-39
PECL and LVDS Low Phase Noise XO (for 32.5-130MHz Output)
PACKAGE INFORMATION
16 PIN TSSOP ( mm )
Symbol
Min.
-
Max.
1.20
0.15
0.30
0.20
5.10
4.50
E
H
A
A1
B
C
D
E
0.05
0.19
0.09
4.90
4.30
D
A
H
L
e
6.40 BSC
A1
0.45
0.75
C
0.65 BSC
L
B
e
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL620-3X X X X R
N ON E = T U B E
PA RT N U M B E R
R=T A PE A N D RE E L
F A M ILY
D E SIG N A T OR
N ON E =N ORM A L PA CK A G E
L=G RE E N PA CK A G E
PA CK A G E T Y PE
O= T SSOP
T E M PE RA T U RE
C=COM M E RCIA L
I=IN D U ST RIA L
Part / Order Number
Marking
Package Option
PLL620-3XOC
P620-3XDC
P620-3XSC
P620-3XSCL
P620-3XSCL
TSSOP - Tube
TSSOP (Tape and Reel)
TSSOP – Tube (GREEN)
PLL620-3XOC-R
PLL620-3XOCL
PLL620-3XOCL-R
TSSOP (Tape and Reel) (GREEN)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/15/05 Page 6
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