TB502-3X-520-XX [PLL]
Test Board for chip evaluation and Layout recommendations; 测试主板芯片评估和布局建议
| 型号： | TB502-3X-520-XX |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | Test Board for chip evaluation and Layout recommendations |
| 文件： | 总2页 (文件大小：43K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TB502-3x-520-xx
Test Board for chip evaluation and Layout recommendations
A generic test board for the PLL502-3x and PLL520-0x/-1x/-2x/-3x/-4x/-7x
In order to provide an example of recommended layout for PLL502-3x and PLL520-xx products, PhaseLink provides a
generic test board for these parts. Test boards are available for both TSSOP and SOIC 16 pin components.
In addition, the test board is designed to simplify the testing of the PLL502-3x and PLL520-xx parts. It includes selection
jumpers allowing the user to easily configure the selector pins (connecting them to GND or leaving them unconnected) as
necessary. Depending on the parts under evaluation, these selector pins allow the user to enable or disable the phase
locked loop, or even select a multiplier value (see the datasheet of each part for details).
General Layout recommendations
While this test board achieves satisfactory decoupling results, best results are achieved when the chip or die are laid out
into the final PCB, following the recommendations indicated in the data sheet.
+3.3V
C?
R?
R?
C1
C3
C2
4.7 uf
0.1uf
0.1uf
26
26
0.01 uf
CLKC
-10 db out
R?
35
Evaluation Chip
U?
R1
50
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDA
XIN
XOUT
S3
S2
OE
VCON
GNDA
S0
S1
GND
CLKC
VDD
CLKT
GND
GND
Vin - PECL
Y1
R2
50
CRYSTAL
502-38
CLKT
C?
Vcontrol
R3
R?
R?
0 or 10 ohms
C4
0.1uf
26
26
0.01 uf
-10 db out
R?
35
S0
S1
S2
S3
JP1
JP2
JP3
JP4
1
2
1
2
1
2
1
2
Jumper Selections
NOTE:
1.
2.
For PECL and PECL outputs: 50W resistors (R1 and R2) should be installed.
For CMOS output: 50W resistors (R1 and R2) should be removed.
In particular, it is essential to include decoupling (by-pass) capacitors as close to the chip as possible in order to minimize
noise sensitivity from the power-supply and thus achieve best phase noise and jitter performance. The generic test board
provides positions for by-pass capacitors (C1, C2, C3) in order to decouple VDD and GND. An additional by-pass capacitor
(C4) is provisioned in order to optimize the signal path coming in from Vcontrol.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 2/20/02 Page 1
TB502-3x-520-xx
Test Board for chip evaluation and Layout recommendations
1. Selection Jumpers
Four selection jumpers (JP1 to JP4) are present, allowing to easily connect pins 16, 15, 4 and 5 to GND, respectively
(jumper on), or likewise to leave them unconnected (jumper off). For simplicity, the board is marked S0 to S3 to identify the
jumpers. The correct connection of pins 4, 5 and 15, 16 is indicated on the datasheets.
2. PECL and LVDS output
In order to simplify the testing of LVDS and PECL outputs, the board already includes two 50W resistors (R1 and R2) in
series between the OUT and OUTB pins. When using PECL, a biasing of voltage of VDD – 2V must be connected at the
middle point between R1 and R2.
In addition, the test board provides access to the output clock via probes or coaxial transmission lines.
In case probes are used, care must be taken to use very low capacitance probes in order to not deteriorate the output
waveform at high frequency. It is recommended to use probes of loading values of 0.7pF or below.
In case transmission lines are used, the test board includes a -10dB attenuation segment before a matched 50W micro-
stripline. It is recommended to connect the coaxial transmission lines to SMA connectors soldered at the end of the micro-
striplines. Transmission lines will provide better phasenoise performance than simple probes.
3. CMOS output
If the parts under evaluation are CMOS outputs, the 50W resistors required for PECL and LVDS should be removed.
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 2/20/02 Page 2
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