PM29F004T-70PC中文资料_数据手册_规格书

PRELIMINARY

PMC

Pm29F004

4 Megabit (512K X 8) 5.0 Volt-only CMOS Flash Memory

FEATURES

• Data# Polling and Toggle Bit Features

• Single Power Supply Operation

- 5.0 V ± 10% Read/Program/Erase

• Low Power Consumption

- Typical 15 mA active read current

- Typical 40 mA program/erase current

- Typical 0.1 µA CMOS standby current

• High Performance Read

- 70/90 ns access time

• Memory Blocks Architecture

- One 16 Kbytes top or bottom Boot Block with

software lockout

- Two 8 Kbytes Parameter Blocks

- One 96 Kbytes Main Block

• High Product Endurance

- Guarantee 10,000 program/erase cycles

- Typical 50,000 program/erase cycles

- Minimum 10 years data retention

- Three 128 Kbytes Main Blocks

• Industrial Standard Pin-out and Packaging

- 32-pin Plastic DIP

- 32-pin PLCC

• Automatic Block Erase and Byte Program

- Typical 12 µs/byte programming

- Typical 50 ms block or chip erase

• Manufactured on 0.30 µm process

• Hardware Data Protection

GENERAL DESCRIPTION

The Pm29F004 is a 4 Megabit, 5 Volt-only Flash Memory organized as 524,288 bytes of 8 bits each. This

device is designed to use a 5.0 Volt power supply to perform in-system programming, 12.0 Volt V_PPpower supply

for program and erase operation is not required. The device can be programmed in standard EPROM program-

mers as well.

The 4 Megabit memory array is divided into seven blocks of one 16 Kbytes, two 8 Kbytes, one 96 Kbytes,

and three 128 Kbytes for BIOS and parameters storage. The seven blocks allow users to flexibly make chip erase

or block erase operation. The block erase feature allows a particular block to be erased and reprogrammed

without affecting the data in other blocks. After the device performed chip erase or block erase operation, it can

be reprogrammed on a byte-by-byte basis.

The device has a standard microprocessor interface as well as JEDEC single-power-supply Flash compatible

pin-out and command set. The program operation of Pm29F004 is executed by issuing the program command

code into command register. The internal control logic automatically handles the programming voltage ramp-up

and timing. The erase operation of Pm29F004 is executed by issuing the chip erase or block erase command

code into command register. The internal control logic automatically handles the erase voltage ramp-up and

timing. The preprogramming on the array which has not been programmed is not required before the erase

operation. The device also features Data# Polling and Toggle Bit function, the end of program or erase operation

can be detected by Data# Polling of I/O7 or Toggle Bit of I/O6.

The device has an optional 16 Kbytes top or bottom boot block with a software lockout feature for data

security. The boot block can be used to store user secure code. When the lockout feature is enabled, the boot

block is permanently protected from being reprogrammed.

The Pm29F004 is manufactured on PMC’s advanced 0.30 µm, P-FLASH™, nonvolatile memory process.

The device is packaged in a 32-pin DIP and PLCC with access time of 70 and 90 ns.

Programmable Microelectronics Corp.

Issue Date: November, 2000 Rev:1. 0

1

Pm29F004 Preliminary

PMC

CONNECTION DIAGRAMS

1

2

3

32

31

A18

A16

V

CC

W E #

A17

A14

4

3

2

1

32

31

30

29

28

27

26

25

24

23

22

A15

A7

5

6

29

28

A14

A13

4

5

6

A12

A7

A6

A5

A13

A8

7

27

26

25

A8

A9

A5

A4

A3

7

8

A9

A4

A3

8

A11

9

A11

9

OE#

A10

CE#

I/O7

I/O6

I/O5

I/O4

10

11

A2

A1

A0

10

24

23

22

21

A2

OE#

A10

11

12

A1

A0

12

13

14

15

21

20

19

I/O0

CE#

I/O7

I/O1

I/O2

13

I/O0

18

17

18

20

16

17

19

15

14

16

G N D

I/O3

32-Pin PDIP

32-Pin PLCC

LOGIC SYMBOL

19

A0-A18

8

I/O0-I/O7

CE#

OE#

W E #

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

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Pm29F004 Preliminary

PMC

PRODUCT ORDERING INFORMATION

Pm29F004

T

-70 P C

Temperature Range

C = Commercial (0°C to +70°C)

Package Type

P = 32-pin Plastic DIP (32P)

J = 32-pin Plastic J-Leaded Chip Carrier (32J)

Speed Option

Boot Block Location

T = Top Boot Block

B = Bottom Boot Block

PMC Device Number

Boot

Location

Temperature

Package

t

ACC

Part Number

Pm29F004T-70JC

Range

(ns)

32J

32P

32J

32P

32J

32P

32J

32P

Top

Pm29F004T-70PC

Pm29F004B-70JC

Pm29F004B-70PC

Pm29F004T-90JC

Pm29F004T-90PC

Pm29F004B-90JC

Pm29F004B-90PC

Commercial

(0°C to +70°C)

70

90

Bottom

Top

Commercial

(0°C to +70°C)

Bottom

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

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Pm29F004 Preliminary

PMC

PIN DESCRIPTIONS

SYMBOL

TYPE

DESCRIPTION

Address Inputs: For memory addresses and command register.

Addresses are internally latched during a write cycle.

A0 - A18

INPUT

Chip Enable: CE# low activates the device's internal circuitries

for device operation. CE# high deselects the device and

switches into standby mode to reduce the power consumption.

Please refer to DC characteristics table.

CE#

Write Enable: Activate the device for write operation. WE# is

active low.

WE#

OE#

INPUT

Output Enable: Control the device's data buffers during a read

cycle. OE# is active low.

Data Inputs/Outputs: Inputs array data during program operation,

when CE# and WE# are active. Data is internally latched during

the write and program cycles. When CE# and OE# are active,

the output sends array data, manufacturer code or device code.

The data pins float to tri-state when the chip is deselected or the

outputs are disabled.

INPUT/

OUTPUT

I/O0 - I/O7

V_CC

Device Power Supply

Ground

GND

NC

No Connection

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

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Pm29F004 Preliminary

PMC

BLOCK DIAGRAM

ERASE/PROGRAM

VOLTAGE

I/O0-I/O7

GENERATOR

I/O BUFFERS

HIGH VOLTAGE

SWITCH

W E #

COMMAND

REGISTER

DATA

LATCH

SENSE

AMP

CE,OE LOGIC

CE#

OE#

Y-GATING

Y-DECODER

X-DECODER

MEMORY

ARRAY

A0-A18

BOOT BLOCK LOCKOUT DETECTION

DEVICE OPERATION

The state of the Boot Block lockout can be de-

tected by software product identification entry. After

entry, selects Boot Block address with A0 = “0” and A1

= “1” and then read I/O0. A data of “0” means the lock-

out feature is disabled and the Boot Block can be erased

or programmed. A data of “1” means the lockout fea-

ture is enabled and the Boot Block is protected. Prod-

uct identification exit must be executed before the de-

vice returns to read mode.

READ OPERATION

The access of Pm29F004 is similar as that of

EPROM. To obtain data at the outputs, three control

functions must be satisfied:

• CE# is the chip enable and should be pulled low

( V_IL).

• OE# is the output enable and should be pulled

low ( V_IL).

• WE# is the write enable and should remains high

( V_IH).

PRODUCT IDENTIFICATION

The product identification mode can be used to identify

the device and the manufacturer by hardware or soft-

ware operation. The hardware operation mode is acti-

vated by applying a 12.0 Volt on A9 pin, typically used

by an external programmer to select the right program-

ming algorithm for the device. For detail, please see

Bus Operation Modes in Table 3. The software opera-

tion mode is activated by three-bus-cycle command.

Please see Software Command Definition in Table 4.

BOOT BLOCK LOCKOUT

The device has a software lockout feature to pre-

vent the data in the boot block from being erased or

reprogrammed. The boot block can be located at the

top or bottom of the address location. The block size is

16 Kbytes. Once the lockout feature is enable, the boot

block can not be erased or reprogrammed. Data in the

main memory block can still be updated through the

regular programming method. The boot block lockout

feature can be turned on by issuing a six-bus-cycle com-

mand sequence. Please refer to Table 4 and Chart 4.

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

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Pm29F004 Preliminary

PMC

DEVICE OPERATION (CONTINUED)

BYTE PROGRAMMING

I/O7 DATA# POLLING

The programming is a four-bus-cycle operation

and the data is programmed into the device (to a logical

“0”) on a byte-by-byte basis. Please see Software Com-

mand Definition in Table 4. A program operation is ac-

tivated by writing the three-byte command sequence

followed by one byte of data into the device. The ad-

dress are latched on the falling edge of WE# or CE#

whichever occurs later, and the data is latched on the

rising edge of WE# or CE#, whichever occurs first. The

internal control logic automatically handles the internal

programming voltages and timing.

The Pm29F004 provides Data# Polling feature to

indicate the process or the completion of a program or

erase cycle. During a program cycle, an attempt to read

the device will result in the complement of the last loaded

data on I/O7. Once the program cycle is completed,

the true data of the last loaded data is valid on all out-

puts. During a block or chip erase operation, an attempt

to read the device will result a “0” on I/O7. After the

erase cycle is completed, an attempt to read the device

will result a “1” on I/O7.

A data “0” can not be programmed back to a “1”.

Only erase operation can convert “0”s to “1”s. The Data#

Polling of I/O7 or Toggle Bit of I/O6 can be used to de-

tect when the programming operation is completed.

I/O6 TOGGLE BIT

The Pm29F004 also provides Toggle Bit feature

as a method to detect the process or the end of a pro-

gram or erase cycle. During a program or erase opera-

tion, an attempt to read data from the device will result

in I/O6 toggling between “1” and “0”. When the program

or erase operation is complete, I/O6 will stop toggling

and valid data will be read. Toggle bit may be accessed

at any time during a program or erase cycle.

CHIP ERASE

The entire memory array can be erased through

a chip erase operation. Pre-programs the device is not

required prior to chip erase operation. Chip erase starts

after a six-bus-cycle chip erase command sequence.

All commands will be ignored once the chip erase

operation has started. The device will return back to

read mode after the completion of chip erase. When

the boot block lockout feature is enabled, the boot block

will not be erased during a chip erase operation. Only

the parameter blocks and the main blocks will be erased.

HARDWARE DATA PROTECTION

Hardware data protection protects the device from

unintentional erase or program operation. It is performed

in the following ways: (a) V_CCsense: if V_CCis below 3.8

V (typical), the program function is inhibited. (b) Write

inhibit: holding any of the signal OE# low, CE# high or

WE# high inhibits a write cycle. (c) Noise filter: pulses

of less than 20 ns (typical) on the WE# or CE# inputs

will not initiate a write cycle.

BLOCK ERASE

The memory array is organized into seven blocks:

one 16 Kbytes boot block, two 8 Kbytes parameter

blocks, one 96 Kbytes and three 128 Kbytes main

blocks. A block erase operation allows to erase any

individual block. Pre-programs the block is not required

prior to block erase operation. If the boot block lockout

feature is enable, the block erase command attempts

to erase the boot block will be ignored. The block erase

command is similar to chip erase command except for

the last bus cycle command where the block addresses

are used to select the block for erasure and the input

data to the I/Os is 30h. Each block erase operation

erases one block. Block erase and chip erase are both

internally controlled and timed.

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

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Pm29F004 Preliminary

PMC

MEMORY BLOCKS AND ADDRESSES

Table 1. Top Boot Block Address Table (Pm29F004T)

Block

Main Block 4

Block Size

Address Range

00000h-1FFFFh

20000h-3FFFFh

40000h-5FFFFh

60000h-77FFFh

78000h-79FFFh

7A000h-7BFFFh

7C000h-7FFFFh

128 Kbytes

96 Kbytes

8 Kbytes

Main Block 3

Main Block 2

Main Block 1

Parameter Block 2

Parameter Block 1

Boot Block

8 Kbytes

16 Kbytes

Table 2. Bottom Boot Block Address Table ( Pm29F004B)

Block

Boot Block

Block Size

16 Kbytes

8 Kbytes

Address Range

00000h-03FFFh

04000h-05FFFh

06000h-07FFFh

08000h-1FFFFh

20000h-3FFFFh

40000h-5FFFFh

60000h-7FFFFh

Parameter Block 1

Parameter Block 2

Main Block 1

8 Kbytes

96 Kbytes

128 Kbytes

Main Block 2

Main Block 3

Main Block 4

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

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Pm29F004 Preliminary

PMC

OPERATING MODES

Table 3. Bus Operation Modes

Mode

Read

CE#

V_IL

V_IH

X

OE#

V_IL

V_IH

X

WE#

V_IH

V_IL

X

ADDRESS

I/O

D_OUT

X ⁽¹⁾

X

Write

D_IN

Standby

X

High Z

Output Disable

V_IH

X

(2)

A2 - A18 = X, A9 = V_H

A1 = V_IL, A0 = V_IL

,

Manufacturer Code ⁽³⁾

Product Identification

Hardware

V_IL

V_IH

(2)

A2 - A18 = X, A9 = V_H

A1 = V_IL, A0 = V_IH

,

Device Code ⁽³⁾

Notes:

1. X can be V_IL, V_IHor addresses.

2. V_H= 12.0 V ± 0.5 V.

3. Manufacturer Code: 9Dh;

Device Code: 1Eh (top boot), 2Eh (bottom boot)

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

8

Pm29F004 Preliminary

PMC

COMMAND DEFINITION

Table 4. Software Command Definition

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cylce

6th Bus

Cycle

Command

Sequence

Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read

1

6

Addr D_OUT

Chip Erase

Block Erase

555h AAh

2AAh 55h 555h 80h

555h AAh

2AAh 55h 555h 10h

2AAh 55h BA ⁽¹⁾30h

Byte

Program

4

6

555h AAh

2AAh 55h 555h A0h

2AAh 55h 555h 80h

Addr D_IN

Boot Block

Lockout ^(2,3)

555h AAh

2AAh 55h 555h 40h

BA ⁽⁴⁾00h ⁽⁵⁾

BA ⁽⁴⁾01h ⁽⁵⁾

Boot Block

Lockout

3

555h AAh

2AAh 55h 555h 90h

Detection ⁽³⁾

Product

Manufacturer ID

3

1

555h AAh

XXXh F0h

2AAh 55h 555h 90h

2AAh 55h 555h F0h

X00h 9Dh

X01h 1Eh

X01h 2Eh

Product Device

ID (Top Boot)

Product Device

ID (Bottom Boot)

Product ID

Exit ⁽⁶⁾

Product ID

Exit ⁽⁶⁾

Notes:

1. BA = Block address of the block to be erased.

2. When the boot block lockout feature is enabled, the boot block will not be erased when a chip erase

command or a block erase command for boot block erasure is issued. Once the boot block is not

protected, the boot block will be erased when a chip erase command or a block erase command for

boot block erasure is issued.

3. After completion of the boot block lockout enable or detection command, the Product ID Exit com-

mand must be issued to return to standard read mode.

4. BA = Block address of the boot block;

For top boot block location, A0 = “0”, A1 = “1”, and A14-A18 = “1” where A2-A13 = Don’t Care;

For bottom boot block location, A0 = “0”, A1 = “1”, and A14-A18 = “0” where A2-A13 = Don’t Care.

5. I/O0 = “1” means boot block lockout is enabled, I/O0 = “0” means boot block lockout is disabled.

6. Either one of the Product ID Exit command can be used.

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

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Pm29F004 Preliminary

PMC

DEVICE OPERATIONS FLOWCHARTS

AUTOMATIC PROGRAMMING

Start

Load Data AAh

to

Address 555H

Load Data 55h

to

Address 2AAh

Load Data A0h

to

Address 555h

Address

Increment

Load Program

Data to

Program Address

I/O7 = Data?

or

I/O6 Stop Toggle?

No

Yes

Last Address?

Yes

No

Programming

Completed

Chart 1. Automatic Programming Flowchart

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

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Pm29F004 Preliminary

PMC

DEVICE OPERATIONS FLOWCHARTS (CONTINUED)

AUTOMATIC ERASE

Start

Write Chip

or Block

Erase Command

Data = FFh?

or

I/O6 Stop Toggle?

No

Yes

Erasure

Completed

BLOCK ERASE COMMAND

CHIP ERASE COMMAND

Load Data AAh

to

Load Data AAh

to

Address 555h

Load Data 55h

to

Load Data 55h

to

Address 2AAh

Load Data 80h

to

Load Data 80h

to

Address 555h

Load Data AAh

to

Address 555h

Load Data AAh

to

Address 555h

Notes:

1. Please see Software Command

Definition in Table 1 and Table

2 for block addresses.

Load Data 55h

to

Address 2AAh

Load Data 55h

to

Address 2AAh

2. Only erase one block per each

block erase cycle.

3. When the boot block lockout

feature has been enabled, the

boot block will not be erased.

Load Data 10h

to

Address 555h

Load Data 30h

to

Block Address

(3)

(1,2,3)

Chart 2. Automatic Erase Flowchart

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

11

Pm29F004 Preliminary

PMC

DEVICE OPERATIONS FLOWCHARTS (CONTINUED)

SOFTWARE PRODUCT IDENTIFICATION EXIT

SOFTWARE PRODUCT IDENTIFICATION ENTRY

Load Data AAh

to

Load Data AAh

to

Address 555h

Load Data 55h

Load Data F0h

Load Data 55h

to

Address 2AAh

to

Address 2AAh

Address XXXh

or

Load Data F0h

Exit Product

Load Data 90h

to

Address 555h

to

Identification

(3)

Address 555h

Mode

Enter Product

Identification

Mode

Exit Product

Identification

Mode

(1,2)

(3)

Notes:

1. Manufacturer Code is read when A0-A18 = XX00h, where X = Don’t Care;

Device Code is read when A0-A18 = XX01h.

2. Manufacturer Code = 9Dh;

Device Code = 1Eh (top boot device);

Device Code = 2Eh (bottom boot device).

3. The device returns to standard read operation.

Chart 3. Software Product Identification Entry/Exit Flowchart

12

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

Pm29F004 Preliminary

PMC

DEVICE OPERATIONS FLOWCHARTS (CONTINUED)

BOOT BLOCK LOCKOUT ENABLE ^(1,2)

Load Data AAh

to

Address 555h

Load Data 55h

to

Address 2AAh

Notes:

Load Data 80h

1. Please call manufacturer for the command code to

disable the boot block lockout.

2. After excuting the boot block lockout command, the

Product ID Exit command must be issued to return

to standard read mode.

to

Address 555h

Load Data AAh

to

Address 555h

Load Data 55h

to

Address 2AAh

Load Data 40h

to

Address 555h

Pause 500 ms

Boot Block

Lockout Enabled

Chart 4. Boot Block Lockout Enable Flowchart

13

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

Pm29F004 Preliminary

PMC

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

Temperature Under Bias

-65^OC to +125^OC

Storage Temperature

-65^OC to +125^OC

-0.5 V to +6.25 V

-0.5 V to +13.0 V

-0.5 V to V_CC+ 0.6 V

-0.5 V to +6.25 V

Input Voltage with Respect to Ground on All Pins except A9 pin ⁽²⁾

Input Voltage with Respect to Ground on A9 pin ⁽³⁾

All Output Voltage with Respect to Ground

(2)

V_CC

Notes:

1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only. The functional operation of the device

or any other conditions under those indicated in the operational sections of this specifica-

tion is not implied. Exposure to absolute maximum rating condition for extended periods

may affected device reliability.

2. Maximum DC voltage on input or I/O pins are +6.25 V. During voltage transitioning period,

input or I/O pins may overshoot to V_CC+ 2.0 V for a period of time up to 20 ns. Minimum

DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period, input or I/O

pins may undershoot GND to -2.0 V for a period of time up to 20 ns.

3. Maximum DC voltage on A9 pin is +13.0 V. During voltage transitioning period, A9 pin

may overshoot to +14.0 V for a period of time up to 20 ns. Minimum DC voltage on A9 pin

is -0.5 V. During voltage transitioning period, A9 pin may undershoot GND to -2.0 V for a

period of time up to 20 ns.

DC AND AC OPERATING RANGE

Part Number

Pm29F004

0^oC to 70^oC

4.5 V - 5.5 V

Operating Temperature

Vcc Power Supply

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

14

Pm29F004 Preliminary

PMC

DC CHARACTERISTICS

Symbol

I_LI

Parameter

Condition

Min

Typ

Max

Units

Input Load Current

V_IN= 0 V to V_CC, V_CC= V_{CC max}

1

µA

I_LO

Output Leakage Current

V_I/O= 0 V to V_CC, V_CC= V_{CC max}

1

µA

mA

V

I_SB1

I_SB2

I_CC1

I_CC2

V_IL

V_CCStandby Current CMOS CE#, OE# = V_CC± 0.5 V

0.1

0.2

15

5

3

V_CCStandby Current TTL

V_CCActive Read Current

V_CCProgram/Erase Current

Input Low Voltage

CE# = V_IHto V_CC

f = 5 MHz; I_OUT= 0 mA

30

(1)

40

60

-0.5

2.0

0.8

V_IH

V_OL

V_OH

Input High Voltage

V_CC+ 0.5

0.45

V

Output Low Voltage

I_OL= 12 mA, V_CC= V_{CC min}

V

Output High Voltage

I_OH= −2.5 mA, V_CC= V_{CC min}

2.4

V

Note: 1. Characterized but not 100% tested.

AC CHARACTERISTICS

READ OPERATIONS CHARACTERISTICS

Pm29F004-70

Pm29F004-90

Symbol

Parameter

Units

Min

Max

Min

Max

t_RC

t_ACC

t_CE

t_OE

t_DF

Read Cycle Time

70

90

ns

Address to Output Delay

CE# to Output Delay

70

35

25

90

40

30

OE# to Output Delay

CE# or OE# to Output High Z

0

Output Hold from OE#, CE# or

Address, whichever occured first

t_OH

ns

µs

t_VCS

V_CCSet-up Time

50

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

15

Pm29F004 Preliminary

PMC

AC CHARACTERISTICS (CONTINUED)

READ OPERATIONS AC WAVEFORMS

t_RC

ADDRESS

ADDRESS VALID

t_ACC

t_CE

CE#

OE#

t_OE

t_DF

W E #

t_OH

HIGH

Z

OUTPUT

VALID

OUTPUT

t_VCS

V_CC

OUTPUT TEST LOAD

INPUT TEST WAVEFORMS

AND MEASUREMENT LEVEL

5.0 V

1.8 K

3.0 V

AC

OUTPUT PIN

Input

1.5 V

Measurement

Level

0.0 V

1.3 K

100 pF

PIN CAPACITANCE ( f = 1 MHz, T = 25°C )

Typ

4

Max

6

Units

Conditions

C_IN

pF

V_IN= 0 V

C_OUT

8

12

V_OUT= 0 V

Note: These parameters are characterized and are not 100% tested.

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

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Pm29F004 Preliminary

PMC

AC CHARACTERISTICS (CONTINUED)

WRITE (PROGRAM/ERASE) OPERATIONS CHARACTERISTICS

Pm29F004-70

Pm29F004-90

Units

Symbol

Parameter

Write Cycle Time

Min

70

0

Max

Min

90

0

Max

t_WC

t_AS

ns

µs

ms

µs

Address Set-up Time

Address Hold Time

CE# Set-up Time

t_AH

t_CS

t_CH

t_WS

t_WH

t_DS

t_DH

t_WP

t_WPH

t_BP

45

0

50

0

CE# Hold Time

0

WE# Set-up Time

WE# Hold Time

0

Data Set-up Time

30

0

45

0

Data Hold Time

Write Pulse Width

Write Pulse Width High

Byte Programming Time

Chip or Block Erase Cycle Time

V_CCSet-up Time

35

20

45

20

50

t_EC

t_VCS

100

50

PROGRAM OPERATIONS AC WAVEFORMS - WE# CONTROLLED

Program Cycle

OE#

t_CH

t_VCS

CE#

t_CS

t_BP

t_WPH

t_{W P}

WE#

t_AH

555

t_{W C}

t_AS

A0 - A17

2AA

555

t_DH

ADDRESS

t_DS

INPUT

DATA

VALID

DATA

DATA IN

V_CC

AA

55

A0

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

17

Pm29F004 Preliminary

PMC

AC CHARACTERISTICS (CONTINUED)

PROGRAM OPERATIONS AC WAVEFORMS - CE# CONTROLLED

Program Cycle

OE#

t_{W H}

t_VCS

W E #

t_{W S}

t_BP

t_WPH

t_{W P}

CE#

A0 - A17

DATA IN

V_CC

t_AH

555

t_{W C}

t_AS

2AA

555

t_DH

ADDRESS

t_DS

INPUT

DATA

VALID

DATA

AA

55

A0

CHIP ERASE OPERATIONS AC WAVEFORMS

OE#

t_VCS

CE#

t_{W P}

t_WPH

W E #

t_AS

t_AH

t_DH

555

t_{W C}

2AA

555

2AA

555

10

AO - A17

t_EC

t_DS

AA

55

80

AA

55

DATA IN

V_CC

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

18

Pm29F004 Preliminary

PMC

AC CHARACTERISTICS (CONTINUED)

BLOCK ERASE OPERATIONS AC WAVEFORMS

OE#

t_VCS

CE#

t_{W P}

t_WPH

W E #

t_AS

t_AH

555

t_{W C}

t_DH

BLOCK

ADDRESS

2AA

555

2AA

55

AO - A17

t_EC

t_DS

AA

55

80

AA

30

DATA IN

V_CC

PROGRAM/ERASE PERFORMANCE

Parameter

Unit

Min

Typ

50

Max

100

50

Remarks

From writing erase command

to erase completion

Block Erase Time

ms

µs

From writing erase command

to erase completion

Chip Erase Time

50

Excludes the time of four-cycle

program command execution

Byte Programming Time

Program/Erase Endurance

12

Cycles

10,000

50,000

Note: These parameters are characterized and are not 100% tested.

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

19

Pm29F004 Preliminary

PMC

AC CHARACTERISTICS (CONTINUED)

TOGGLE BIT AC WAVEFORMS

W E #

t_OEH

CE#

OE#

t_DF

t_OE

t_OH

STOP

TOGGLING

VALID

DATA

TOGGLE

I/O6

Note: Toggling either CE#, OE# or both OE# and CE# will operate Toggle Bit.

DATA# POLLING AC WAVEFORMS

W E #

CE#

t_CH

t_CE

t_OEH

OE#

I/O7

t_OE

t_DF

I/O7#

VALID DATA

t_OH

Note: Toggling either CE#, OE# or both OE# and CE# will operate Data# Polling.

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

20

Pm29F004 Preliminary

PMC

PACKAGE TYPE INFORMATION

32P

32-Pin Plastic DIP Dimensions in Inches (Millimeters)

1.640(41.7)

1.680(42.7)

.600(15.24)

.625(15.88)

32

17

16

.008(0.20)

.013(0.33)

.537(13.64)

.557(14.05)

.625(15.88)

.665(16.89)

Pin 1 I.D.

0°

10°

.005(.127)

MIN

.040(1.02)

.065(1.65)

.146(3.71)

.162(4.11)

SEATING PLANE

.090(2.29)

.110(2.79)

.014(.36)

.022(.56)

.120(3.05)

.160(4.07)

.015(.38) MIN

32J

32-Pin Plastic Leaded Chip Carrier Dimensions in Inches (Millimeters)

.485(12.32)

.495(12.51)

.447(11.35)

.453(11.51)

.009

.015

025(.635)X30°

.585(14.86)

.595(15.11)

.123(3.12)

.140(3.56)

Pin 1 I.D.

.076(1.93)

.095(2.41)

.547(13.89)

.553(14.05)

SEATING

PLANE

.400

REF.

.510(12.95)

.530(13.46)

.013(.33)

.021(.53)

.050 REF.

.026(.66)

.032(.81)

TOP VIEW

SIDE VIEW

Issue Date: November, 2000 Rev: 1.0

Programmable Microelectronics Corp.

21

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