LYT4212 [POWERINT]
LYTSwitch High Power LED Driver IC Family;
| 型号： | LYT4212 |
| 厂家： | 
Power Integrations |
| 描述： | LYTSwitch High Power LED Driver IC Family |
| 文件： | 总20页 (文件大小：2714K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LYT4211-4218/4311-4318
™
LYTSwitch High Power LED Driver IC Family
Single-Stage Accurate Primary-Side Constant Current (CC) Controller with
PFC for Low-Line Applications, TRIAC Dimming and Non-Dimming Options
Product Highlights
•ꢀ Better than ±±5 CC regulation
•ꢀ TRIAC dimmable to less than ±5 output
•ꢀ Fast start-up
•ꢀ <2±0 ms at full brightness
•ꢀ <1s at 105 brightness
•ꢀ High power factor >0.9
•ꢀ Easily meets EN61000-3-2
•ꢀ Less than 105 THD in optimized designs
CONTROL
•ꢀ Up to 925 efficient
•ꢀ 132 kHz switching frequency for small magnetics
High Performance, Combined Driver, Controller, Switch
The LYTSwitch family enables off-line LED drivers with high
power factor which easily meet international requirements for THD
Figure 1. Typical Schematic.
and harmonics. Output current is tightly regulated with better
than ±±5 CC tolerance1. Efficiency of up to 925 is easily
achieved in typical applications.
Optimized for Different Applications and Power Levels
Part Number
LYT4211-LYT4218
LYT4311-LYT4318
Input Voltage Range
8±-132 VAC
TRIAC Dimmable
Supports a Wide Selection of TRIAC Dimmers
The LYTSwitch family provides excellent turn-on characteristics
for leading-edge and trailing-edge TRIAC dimming applications.
This results in drivers with a wide dimming range and fast
start-up, even when turning-on from a low conduction angle.
Large dimming ratio and low “pop-on” current.
No
8±-132 VAC
Yes
Output Power Table1,2
Product6
Minimum Output Power3 Maximum Output Power4
Low Solution Cost and Long Lifetime
LYTSwitch ICs are highly integrated and employ a primary-side
control technique that eliminates the optoisolator and reduces
component count. This allows the use of low-cost single-sided
printed circuit boards. Combining PFC and CC functions into a
single-stage also helps reduce cost and increase efficiency. The
132 kHz switching frequency permits the use of small, low-cost
magnetics.
LYT4x11E/L5
2.± W
2.± W
3.8 W
4.± W
±.± W
6.8 W
8.0 W
18 W
12 W
1± W
18 W
22 W
2± W
3± W
±0 W
78 W
LYT4x12E/L
LYT4x13E/L
LYT4x14E/L
LYT4x15E/L
LYT4x16E/L
LYT4x17E/L
LYT4x18E/L
LED drivers using the LYTSwitch family do not use primary-side
aluminum electrolytic bulk capacitors. This means greatly
extended driver lifetime, especially in bulb and other high
temperature applications.
Table 1. Output Power Table.
Notes:
1. Performance for typical design. See Applications section.
2. Continuous power in an open-frame design with adequate heat sinking; device
local ambient of 70 °C. Power level calculated assuming a typical LED string
voltage and efficiency >805.
3. Minimum output power requires CBP = 47 µF.
4. Maximum output power requires CBP = 4.7 µF.
±. LYT4311 CBP = 47 µF, LYT4211 CBP = 4.7 µF.
6. Package: eSIP-7C, eSIP-7F (see Figure 2).
eSIP-7C (E Package)
Figure 2. Package Options.
eSIP-7F (L Package)
www.powerint.com
February 2013
LYT4211-4218/4311-4318
Topology
Isolated Flyback
Buck
Tapped Buck
Buck-Boost
Isolation
Efficiency
885
Cost
High
Low
Middle
Low
THD
Best
Good
Best
Best
Output Voltage
Any
Yes
No
No
No
925
895
905
Limited
Any
High-Voltage
Table 2.
Performance of Different Topologies in a Typical Non-Dimmable 10 W Low-Line Design.
Typical Circuit Schematic
Key Features
Flyback
Benefits
•ꢀ Provides isolated output
•ꢀ Supports widest range of output voltages
•ꢀ Very good THD performance
Limitations
•ꢀ Flyback transformer
•ꢀ Overall efficiency reduced by parasitic capacitance
and inductance in the transformer
CONTROL
•ꢀ Larger PCB area to meet isolation requirements
•ꢀ Requires additional components (primary clamp and bias)
•ꢀ Higher RMS switch and winding currents increases losses
and lowers efficiency
Figure 3a. Typical Isolated Flyback Schematic.
Buck
Benefits
•ꢀ Highest efficiency
•ꢀ Lowest component count – small size
•ꢀ Simple low-cost power inductor
•ꢀ Low drain source voltage stress
•ꢀ Best EMI/lowest component count for filter
Limitations
•ꢀ Single input line voltage range
•ꢀ Output voltage <0.6 × VIN(AC) × 1.41
•ꢀ Output voltage for low THD designs
•ꢀ Non-isolated
AC
IN
LYTSwitch
BP
D
S
V
CONTROL
R
FB
PI-6841-081512
Figure 3b. Typical Buck Schematic.
Tapped Buck
Benefits
•ꢀ Ideal for low output voltage designs (<20 V)
•ꢀ High efficiency
•ꢀ Low component count
•ꢀ Simple low-cost tapped inductor
Limitations
•ꢀ Designs best suited for single input line voltage
•ꢀ Requires additional components (primary clamp)
•ꢀ Non-isolated
LYTSwitch
AC
IN
D
V
CONTROL
BP
S
R
FB
PI-6842-081512
Figure 3c. Typical Tapped Buck Schematic.
Buck-Boost
Benefits
•ꢀ Ideal for non-isolated high output voltage designs
•ꢀ High efficiency
•ꢀ Low component count
•ꢀ Simple common low-cost power inductor can be used
•ꢀ Lowest THD
Limitations
•ꢀ Maximum VOUT is limited by MOSFET breakdown voltage
•ꢀ Single input line voltage range
•ꢀ Non-isolated
AC
IN
LYTSwitch
BP
D
V
CONTROL
S
R
FB
PI-6859-081512
Figure 3d. Typical Buck-Boost Schematic.
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LYT4211-4218/4311-4318
DRAIN (D)
5.9 V
REGULATOR
BYPASS (BP)
BYPASS
CAPACITOR
SELECT
SOFT-START
TIMER
HYSTERETIC
THERMAL
SHUTDOWN
+
-
FAULT
PRESENT
ILIM
MI
5.9 V
5.0 V
AUTO-RESTART
COUNTER
BYPASS PIN
UNDERVOLTAGE
Gate
Driver
1 V
VOLTAGE
MONITOR (V)
SenseFet
LEB
STOP
LOGIC
JITTER
CLOCK
Comparator
OSCILLATOR
-
+
FBOFF
3-VT
DCMAX
OCP
OV
LINE
SENSE
+
-
CURRENT LIMIT
COMPARATOR
ILIM
IV
FEEDBACK (FB)
PFC/CC
CONTROL
VSENSE
VBG
MI
IFB
FBOFF
FEEDBACK
SENSE
DCMAX
IS
REFERENCE
BLOCK
REFERENCE (R)
VBG
6.4 V
PI-6843-071112
SOURCE (S)
Figure 4. Functional Block Diagram.
Pin Functional Description
DRAIN (D) Pin:
VOLTAGE MONITOR (V) Pin:
This pin is the power FET drain connection. It also provides
internal operating current for both start-up and steady-state
operation.
This pin interfaces with an external input line peak detector,
consisting of a rectifier, filter capacitor and resistors. The
applied current is used to control stop logic for overvoltage (OV),
provide feed-forward to control the output current and the
remote ON/OFF function.
SOURCE (S) Pin:
This pin is the power FET source connection. It is also the
ground reference for the BYPASS, FEEDBACK, REFERENCE
and VOLTAGE MONITOR pins.
Exposed Pad
(Backside) Internally
Connected to
BYPASS (BP) Pin:
SOURCE Pin
E Package (eSIP-7C)
This is the connection point for an external bypass capacitor for
the internally generated ±.9 V supply. This pin also provides
output power selection through choice of the BYPASS pin
capacitor value.
L Package (eSIP-7F)
(Top View)
7 D
5 S
4 BP
3 FB
2 V
FEEDBACK (FB) Pin:
1 R
The FEEDBACK pin is used for output voltage feedback. The
current into the FEEDBACK pin is directly proportional to the
output voltage. The FEEDBACK pin also includes circuitry to
protect against open load and overload output conditions.
3
FB
5
S
1
R
Exposed Pad
(backside) Internally
Connected to
SOURCE Pin (see
eSIP-7C Package
Drawing)
2
4
7
D
Lead Bend Outward
from Drawing
(Refer to eSIP-7F Package
Outline Drawing)
V BP
PI-5432-082411
REFERENCE (R) Pin:
This pin is connected to an external precision resistor and is
used to configure for dimming (LYT4311-4318) and non-TRIAC
dimming (LYT4211-4218) modes of operation.
Figure 5. Pin Configuration.
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Rev. B 02/13
LYT4211-4218/4311-4318
Functional Description
A LYTSwitch device monolithically combines a controller and
high-voltage power FET into one package. The controller
provides both high power factor and constant current output in
a single-stage. The LYTSwitch controller consists of an
oscillator, feedback (sense and logic) circuit, ±.9 V regulator,
hysteretic over-temperature protection, frequency jittering,
cycle-by-cycle current limit, auto-restart, inductance correction,
power factor and constant current control.
non-dimming or PWM dimming applications with LYT4211-4218,
the external resistor should be a 24.9 kW ±15. For phase angle
AC dimming with LYT4311-4318, the external resistor should be
a 49.9 kW ±15. One percent resistors are recommended as
the resistor tolerance directly affects the output tolerance.
Other resistor values should not be used.
BYPASS Pin Capacitor Power Gain Selection
LYTSwitch devices have the capability to tailor the internal gain
to either full or a reduced output power setting. This allows
selection of a larger device to minimize dissipation for both
thermal and efficiency reasons. The power gain is selected with
the value of the BYPASS pin capacitor. The full power setting is
selected with a 4.7 µF capacitor and the reduced power setting
(for higher efficiency) is selected with a 47 µF capacitor. The
BYPASS pin capacitor sets both the internal power gain as well
as the over-current protection (OCP) threshold. Unlike the
larger devices, the LYT4x11 power gain is not programmable.
Use a 47 µF capacitor for the LYT4x11.
FEEDBACK Pin Current Control Characteristics
The figure shown below illustrates the operating boundaries of
the FEEDBACK pin current. Above IFB(SKIP) switching is disabled
and below IFB(AR) the device enters into auto-restart.
IFB(SKIP)
Skip-Cycle
Switching Frequency
CC Control
Region
IFB
The switching frequency is 132 kHz during normal operation.
To further reduce the EMI level, the switching frequency is
jittered (frequency modulated) by approximately 2.6 kHz.
During start-up the frequency is 66 kHz to reduce start-up time
when the AC input is phase angle dimmed. Jitter is disabled in
deep dimming.
IFB(DCMAXR)
Soft-Start
Soft-Start and
CC Fold-Back
Region
The controller includes a soft-start timing feature which inhibits
the auto-restart protection feature for the soft-start period (tSOFT
to distinguish start-up into a fault (short-circuit) from a large
output capacitor. At start-up the LYTSwitch clamps the
maximum duty cycle to reduce the output power. The total
)
soft-start period is tSOFT
.
Remote ON/OFF and EcoSmart™
IFB(AR)
Auto-Restart
The VOLTAGE MONITOR pin has a 1 V threshold comparator
connected at its input. This voltage threshold is used for
remote ON/OFF control. When a signal is received at the
VOLTAGE MONITOR pin to disable the output (VOLTAGE
MONITOR pin tied to ground through an optocoupler photo-
transistor) the LYTSwitch will complete its current switching
cycle before the internal power FET is forced off.
DC10
Maximum Duty Cycle
DCMAX
PI-5433-060410
Figure 6. FEEDBACK Pin Current Characteristic.
The FEEDBACK pin current is also used to clamp the maximum
duty cycle to limit the available output power for overload and
open-loop conditions. This duty cycle reduction characteristic
also promotes a monotonic output current start-up characteristic
and helps preventing over-shoot.
The remote ON/OFF feature can also be used as an eco-mode
or power switch to turn off the LYTSwitch and keep it in a very
low power consumption state for indefinite long periods. When
the LYTSwitch is remotely turned on after entering this mode, it
will initiate a normal start-up sequence with soft-start the next
time the BYPASS pin reaches ±.9 V. In the worst case, the
delay from remote on to start-up can be equal to the full
discharge/charge cycle time of the BYPASS pin. This reduced
consumption remote off mode can eliminate expensive and
unreliable in-line mechanical switches.
REFERENCE Pin
The REFERENCE pin is tied to ground (SOURCE) via an external
resistor. The value selected sets the internal references,
determining the operating mode for dimming (LYT4311-4318)
and non-dimming (LYT4211-4218) operation and the line
overvoltage thresholds of the VOLTAGE MONITOR pin. For
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LYT4211-4218/4311-4318
completed. Special consideration must be made to appropriately
size the output capacitor to ensure that after the soft-start
period (tSOFT) the FEEDBACK pin current is above the IFB(AR)
threshold to ensure successful power-supply start-up.
After the soft-start time period, auto-restart is activated only
D
S
V
CONTROL
when the FEEDBACK pin current falls below IFB(AR)
.
BP
Over-Current Protection
R
FB
The current limit circuit senses the current in the power FET.
When this current exceeds the internal threshold (ILIMIT), the power
FET is turned off for the remainder of that cycle. A leading edge
blanking circuit inhibits the current limit comparator for a short
time (tLEB) after the power FET is turned on. This leading edge
blanking time has been set so that current spikes caused by
capacitance and rectifier reverse recovery will not cause
premature termination of the power FET conduction.
PI-5435-052510
Figure 7. Remote ON/OFF VOLTAGE MONITOR Pin Control.
Line Overvoltage Protection
5.9 V Regulator/Shunt Voltage Clamp
This device includes overvoltage detection to limit the maximum
operating voltage detected through the VOLTAGE MONITOR pin.
An external peak detector consisting of a diode and capacitor is
required to provide input line peak voltage to the VOLTAGE
MONITOR pin through a resistor.
The internal ±.9 V regulator charges the bypass capacitor
connected to the BYPASS pin to ±.9 V by drawing a current
from the voltage on the DRAIN pin whenever the power FET is
off. The BYPASS pin is the internal supply voltage node. When
the power FET is on, the device operates from the energy stored
in the bypass capacitor. Extremely low power consumption of the
internal circuitry allows LYTSwitch to operate continuously from
current it takes from the DRAIN pin. A bypass capacitor value
of 47 or 4.7 µF is sufficient for both high frequency decoupling
and energy storage. In addition, there is a 6.4 V shunt regulator
clamping the BYPASS pin at 6.4 V when current is provided to
the BYPASS pin through an external resistor. This facilitates
powering of LYTSwitch externally through a bias winding to
increase operating efficiency. It is recommended that the
BYPASS pin is supplied current from the bias winding for
normal operation.
The resistor sets line overvoltage (OV) shutdown threshold which,
once exceeded, forces the LYTSwitch to stop switching. Once
the line voltage returns to normal, the device resumes normal
operation. A small amount of hysteresis is provided on the OV
threshold to prevent noise-generated toggling. When the power
FET is off, the rectified DC high voltage surge capability is
increased to the voltage rating of the power FET (670 V), due to the
absence of the reflected voltage and leakage spikes on the drain.
Hysteretic Thermal Shutdown
The thermal shutdown circuitry senses the controller die
temperature. The threshold is set at 142 °C typical with a 7± °C
hysteresis. When the die temperature rises above this threshold
(142 °C) the power FET is disabled and remains disabled until
the die temperature falls by 7± °C, at which point the power FET
is re-enabled.
Auto-Restart
In the event of an open-loop fault (open FEEDBACK pin resistor
or broken path to feedback winding), output short-circuits or an
overload condition the controller enters into the auto-restart
mode. The controller annunciates both short-circuit and
open-loop conditions once the FEEDBACK pin current falls
below the IFB(AR) threshold after the soft-start period. To minimize
the power dissipation under this fault condition the shutdown/
auto-restart circuit turns the power supply on (same as the
soft-start period) and off at an auto-restart duty cycle of
typically DCAR for as long as the fault condition persists. If the
fault is removed during the auto-restart off-time, the power
supply will remain in auto-restart until the full off-time count is
Safe Operating Area (SOA) Protection
The device also features a safe operating area (SOA) protection
mode which disables FET switching for 40 cycles in the event
the peak switch current reaches the ILIMIT threshold and the switch
on-time is less than tON(SOA). This protection mode protects the
device under short-circuited LED conditions and at start-up during
the soft-start period when auto-restart protection is inhibited.
The SOA protection mode remains active in normal operation.
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Rev. B 02/13
LYT4211-4218/4311-4318
Application Example
25 W TRIAC Dimmable High Power Factor LED Driver
Design Example (DER-350)
peak drain voltage of U1 below the 72± V rating of the internal
power FET. Bridge rectifier BR1 rectifies the AC line voltage.
EMI filtering is provided by L1-L3, C1, C4, R2, R24 and R2±
together with the safety rated Y class capacitor (CY1) that bridges
the safety isolation barrier between primary and secondary.
Resistor R2, R24 and R2± act to damp any resonances formed
between L1, L2, L3, C1 and the AC line impedance. A small
bulk capacitor (C4) is required to provide a low impedance
source for the primary switching current. The maximum value
of C2 and C4 is limited in order to maintain a power factor of
greater than 0.9.
The circuit schematic in Figure 8 shows a TRIAC dimmable high
power factor LED driver based on LYT4317E from the LYTSwitch
family of devices. The design is configurable for non-dimmable
only applications by simple component value changes. It was
optimized to drive an LED string at a voltage of 36 V with a
constant current of 0.7 A ideal for Lumens PAR lamp retro-fit
applications. The design operates over an input voltage range
of 90 VAC to 132 VAC.
LYTSwitch Primary
The key goals of this design were compatibility with standard
leading edge TRIAC AC dimmers, very wide dimming range
(1000:1, 700 mA:0.7 mA), high efficiency (>8±5) and high power
factor (>0.9). The design is fully protected from faults such as
no-load (open load), overvoltage and output short-circuit or
overload conditions and over temperature.
To provide peak line voltage information to U1 the incoming
rectified AC peak charges C6 via D2. This is then fed into the
VOLTAGE MONITOR pin of U1 as a current via R10. This
sensed current is also used by the device to set the line input
overvoltage protection threshold. Resistor R9 provides a
discharge path for C6 with a time constant much longer than
that of the rectified AC to prevent generation of line frequency
ripple.
Circuit Description
The LYTSwitch device (U1- LYT4317E) integrates the power FET,
controller and start-up functions into a single package reducing
the component count versus typical implementations. Configured
as part of an isolated continuous conduction mode flyback
converter, U1 provides high power factor via its internal control
algorithm together with the small input capacitance of the
design. Continuous conduction mode operation results in
reduced primary peak and RMS current. This both reduces
EMI noise, allowing simpler, smaller EMI filtering components
and improves efficiency. Output current regulation is maintained
without the need for secondary-side sensing which eliminates
current sense resistors and improves efficiency.
The VOLTAGE MONITOR pin current and the FEEDBACK pin
current are used internally to control the average output LED
current. For TRIAC phase-dimming applications a 49.9 kW
resistor (R14) is used on the REFERENCE pin and 2 MW (R10)
on the VOLTAGE MONITOR pin to provide a linear relationship
between input voltage and the output current and maximizing
the dimming range.
Diode D3, R1± and C7 clamp the drain voltage to a safe level
due to the effects of leakage inductance. Diode D4 is
necessary to prevent reverse current from flowing through U1
for the period of the rectified AC input voltage that the voltage
across C4 falls to below the reflected output voltage (VOR).
Input Stage
Fuse F1 provides protection from component failures while RV1
provides a clamp during differential line surges, keeping the
C13
100 pF
200 V
R26
30 Ω
C11
C12
63 V
D9
D2
DFLU1400
36 V,
R23
20 kΩ
330 µF 330 µF
DFLU1400-7
700 mA
63 V
12
1
FL1
R24
D7
47 kΩ
R9
510 kΩ
1/8 W
C7
2.2 nF
630 V
BYW29-200
R15
200 kΩ
1/8 W
BR1
MB6S
600 V
FL2
10
D6
RTN
BAV21
R20
39 Ω
1/8 W
C9
C5
100 nF
50 V
D3
US1J
56 µF
50 V
11
R10
C1
220 nF
250 V
R1
510
1/2 W
T1
RM8
2 MΩ
R19
20 kΩ
1%
1/8 W
D4
C2
C4
C6
R6
US1D
100 nF
250 V
100 nF 2.2 µF
360 kΩ
250 V 250 V
L3
5 mH
D5
R2
R25
47 kΩ
1/8 W
L1
1 mH
L2
1 mH
BAV16
47 kΩ
D8
1/8 W
R17
3 kΩ
1/10 W
R18
165 kΩ
1%
BAV21
D
S
V
1/16 W
CONTROL
LYTSwitch
U1
LYT4317E
BP
RV1
140 VAC
F1
5 A
Q1
Q2
MMBT3904
R
FB
R14
C15
100 nF
50 V
X0202MA2BL2
90 - 132
VAC
C3
470 nF
50 V
L
N
49.9 kΩ
1%
1/16 W
R27
R22
1 kΩ
1/10 W
C14
10 nF
50 V
R8
100 Ω
1 W
10 Ω
C8
47 µF
16 V
1/10 W
CY1
470 pF
250 VAC
PI-6875-101812
Figure 8. DER-350 Schematic of an Isolated, TRIAC Dimmable, High Power Factor, 90-132 VAC, 25 W / 36 V / 700 mA LED Driver.
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LYT4211-4218/4311-4318
Diode D6, C±, C9, R19 and R20 create the primary bias supply
from an auxiliary winding on the transformer. Capacitor C8
provides local decoupling for the BYPASS pin of U1 which is the
supply pin for the internal controller. During start-up C8 is
charged to ~6 V from an internal high-voltage current source
tied to the device DRAIN pin. This allows the part to start
switching at which point the operating supply current is provided
from the bias supply via R17. Capacitor C8 also selects the
output power mode (47 µF for reduced power was selected to
reduce dissipation in U1 and increase efficiency for this design).
TRIAC Phase Dimming Control Compatibility
The requirement to provide output dimming with low-cost,
TRIAC-based, leading edge phase dimmers introduces a
number of trade-offs in the design.
Due to the much lower power consumed by LED based lighting
the current drawn by the overall lamp is below the holding
current of the TRIAC within the dimmer. This can cause
undesirable behaviors such as limited dimming range and/or
flickering as the TRIAC fires inconsistently. The relatively large
impedance the LED lamp presents to the line allows significant
ringing to occur due to the inrush current charging the input
capacitance when the TRIAC turns on. This too can cause
similar undesirable behavior as the ringing may cause the
TRIAC current to fall to zero and turn off.
Feedback
The bias winding voltage is proportional to the output voltage
(set by the turns ratio between the bias and secondary
windings). This allows the output voltage to be monitored
without secondary-side feedback components. Resistor R18
converts the bias voltage into a current which is fed into the
FEEDBACK pin of U1. The internal engine within U1 combines
the FEEDBACK pin current, the VOLTAGE MONITOR pin current
and drain current information to provide a constant output
current over a 1.±:1 output voltage variation (LED string voltage
variation of ±2±5) at a fixed line input voltage.
To overcome these issues simple two circuits, the SCR active
damper and R-C passive bleeder, are incorporated. The
drawback of these circuits is increased dissipation and
therefore reduced efficiency of the supply. For non-dimming
applications these components can simply be omitted.
The SCR active damper consists of components R6, C3, and
Q1 in conjunction with R8. This circuit limits the inrush current
that flows to charge C4 when the TRIAC turns on by placing R8
in series for the first ~1 ms of the TRIAC conduction. After
approximately 1 ms, Q1 turns on and bypasses R8. This keeps
the power dissipation on R8 low and allows a larger value
during current limiting. Resistor R6 and C3 provide the delay
on Q1 turn on after the TRIAC conducts. Diode D9 blocks the
charge in capacitor C4 from flowing back after the TRIAC turns
on which helps in dimming compatibility especially with high
power dimmers.
To limit the output voltage at no-load an output overvoltage
protection circuit is set by D8, C1±, R22, VR4, R27, C14 and Q2.
Should the output load be disconnected then the bias voltage
will increase until VR4 conducts, turning on Q2 and reducing
the current into the FEEDBACK pin. When this current drops
below 10 µA the part enters auto-restart and switching is
disabled for 300 ms allowing time for the output and bias
voltages to fall.
Output Rectification
The transformer secondary winding is rectified by D7 and
filtered by C11 and C12. An ultrafast TO-220 diode was
selected for efficiency and the combined value of C11 and C12
were selected to give peak-to-peak LED ripple current equal to
305 of the mean value. For designs where lower ripple is
desirable the output capacitance value can be increased.
The passive bleeder circuit is comprised of R1 and C1. This
helps keep the input current above the TRIAC holding current
while the input current corresponding to the effective driver
resistance increases during each AC half-cycle.
A small pre-load is provided by R23 which discharges residual
charge in output capacitors when turned off.
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Rev. B 02/13
LYT4211-4218/4311-4318
Modified DER-350 25 W High Power Factor LED Driver
for Non-Dimmable and Enhanced Line Regulation
•ꢀ For maximum output power column
•ꢀ Reflected output voltage (VOR) of 6± V
•ꢀ FEEDBACK pin current of 16± µA
•ꢀ BYPASS pin capacitor value of 4.7 µF (LYT4x11 = 4.7 µF)
The circuit schematic in Figure 9 shows a high power factor
LED driver based on a LYT4317 from the LYTSwitch family of
devices. It was optimized to drive an LED string at a voltage of
36 V with a constant current of 0.7 A, ideal for high lumen PAR
lamp retro-fit applications. The design operates over the
low-line input voltage range of 90 VAC to 132 VAC and is
non-dimming application. A non-dimming application has
tighter output current variation with changes in the line voltage
than a dimming application. It’s key to note that, although not
specified for dimming, no circuit damage will result if the end
user does operate the design with a phase controlled dimmer.
Note that input line voltages above 8± VAC do not change the
power delivery capability of LYTSwitch devices.
Device Selection
Select the device size by comparing the required output power
to the values in Table 1. For thermally challenging designs, e.g.,
incandescent lamp replacement, where either the ambient
temperature local to the LYTSwitch device is high and/or there
is minimal space for heat sinking use the minimum output
power column. This is selected by using a 47 µF BYPASS pin
capacitor and results in a lower device current limit and therefore
lower conduction losses. For open frame design or designs
where space is available for heat sinking then refer to the
maximum output power column. This is selected by using a
4.7 µF BYPASS pin capacitor for all but the LYT4x11 which has
only one power setting. In all cases in order to obtain the best
output current tolerance maintain the device temperature below
100 °C
Modification for Non-Dimmable Configuration
The design is configurable for non-dimmable application by
simply removing the component for SCR active damper (R6,
R8, C3, and Q1), blocking diode D9 and R-C bleeder (R1, C1)
changes and replacing the reference resistor R14 with 24.9 kW.
(See Figure 9)
Key Application Considerations
Power Table
Maximum Input Capacitance
The data sheet power table (Table 1) represents the minimum
and maximum practical continuous output power based on the
following conditions:
To achieve high power factor, the capacitance used in both the
EMI filter and for decoupling the rectified AC (bulk capacitor)
must be limited in value. The maximum value is a function of
the output power of the design and reduces as the output
power reduces. For the majority of designs limit the total
capacitance to less than 200 nF with a bulk capacitor value of
100 nF. Film capacitors are recommended compared to
ceramic types as they minimize audible noise with operating
with leading edge phase dimmers. Start with a value of 10 nF
for the capacitance in the EMI filter and increase in value until
there is sufficient EMI margin.
•ꢀ Efficiency of 805
•ꢀ Device local ambient of 70 °C
•ꢀ Sufficient heat sinking to keep the device temperature below
100 °C
•ꢀ For minimum output power column
•ꢀ Reflected output voltage (VOR) of 120 V
•ꢀ FEEDBACK pin current of 13± µA
•ꢀ BYPASS pin capacitor value of 47 µF
C13
100 pF
200 V
R26
30 Ω
R24
C11
C12
63 V
47 kΩ
D2
DFLU1400
36 V,
R23
20 kΩ
330 µF 330 µF
1/8 W
700 mA
63 V
12
1
FL1
D7
R9
510 kΩ
1/8 W
BYW29-200
C7
2.2 nF
630 V
R15
200 kΩ
BR1
MB6S
600 V
FL2
10
D6
RTN
BAV21
R20
39 Ω
1/8 W
C9
C5
100 nF
50 V
D3
US1J
56 µF
50 V
11
R10
T1
RM8
2 MΩ
R19
20 kΩ
1%
1/8 W
D4
C2
100 nF
250 V
C4
C6
US1D
R2
47 kΩ
1/8 W
R25
47 kΩ
1/8 W
100 nF 2.2 µF
L1
1 mH
L2
1 mH
250 V 250 V
L3
5 mH
D5
BAV16
D8
R17
3 kΩ
1/10 W
R18
165 kΩ
1%
BAV21
D
S
V
1/16 W
CONTROL
LYTSwitch
U1
LYT4317E
RV1
BP
140 VAC
F1
5 A
Q2
MMBT3904
R
FB
R14
C15
100 nF
50 V
90 - 132
VAC
L
N
24.9 kΩ
1%
1/16 W
R27
R22
1 kΩ
1/10 W
C14
10 nF
50 V
10 Ω
C8
47 µF
16 V
1/10 W
CY1
470 pF
250 VAC
PI-6875a-101512
Figure 9. Modified Schematic of RD-350 for Non-Dimmable, Isolated, High Power Factor, 90-132 VAC, 25 W / 36 V LED Driver.
8
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LYT4211-4218/4311-4318
REFERENCE Pin Resistance Value Selection
Operation with Phase Controlled Dimmers
The LYTSwitch family contains phase dimming devices,
LYT4311-4318, and non-dimming devices, LYT4211-4218. The
non-dimmable devices use a 24.9 kW ±15 REFERENCE pin
resistor for best output current tolerance (over AC input voltage
changes). The dimmable devices (i.e. LYT4311-4318) use 49.9
kW ±15 to achieve the widest dimming range.
Dimmer switches control incandescent lamp brightness by not
conducting (blanking) for a portion of the AC voltage sine wave.
This reduces the RMS voltage applied to the lamp thus reducing
the brightness. This is called natural dimming and the LYTSwitch
LYT4311-4318 devices when configured for dimming utilize
natural dimming by reducing the LED current as the RMS line
voltage decreases. By this nature, line regulation performance is
purposely decreased to increase the dimming range and more
closely mimic the operation of an incandescent lamp. Using a
49.9 kW REFERENCE pin resistance selects natural dimming
mode operation.
VOLTAGE MONITOR Pin Resistance Network Selection
For widest AC phase angle dimming range with LYT4311-4318,
use a 2 MW (1.7 MW for 100 VAC (Japan)) resistor connected to
the line voltage peak detector circuit. Make sure that the
resistor’s voltage rating is sufficient for the peak line voltage. If
necessary use multiple series connected resistors.
Leading Edge Phase Controlled Dimmers
The requirement to provide flicker-free output dimming with low-
cost, TRIAC-based, leading edge phase dimmers introduces a
number of trade-offs in the design.
Primary Clamp and Output Reflected Voltage VOR
A primary clamp is necessary to limit the peak drain to source
voltage. A Zener clamp requires the fewest components and
board space and gives the highest efficiency. RCD clamps are
also acceptable however the peak drain voltage should be
carefully verified during start-up and output short-circuits as the
clamping voltage varies with significantly with the peak drain
current.
Due to the much lower power consumed by LED based lighting
the current drawn by the overall lamp is below the holding
current of the TRIAC within the dimmer. This causes
undesirable behaviors such as limited dimming range and/or
flickering. The relatively large impedance the LED lamp presents
to the line allows significant ringing to occur due to the inrush
current charging the input capacitance when the TRIAC turns
on. This too can cause similar undesirable behavior as the
ringing may cause the TRIAC current to fall to zero and turn off.
For the highest efficiency, the clamping voltage should be
selected to be at least 1.± times the output reflected voltage,
VOR, as this keeps the leakage spike conduction time short.
This will ensure efficient operation of the clamp circuit and will
also keep the maximum drain voltage below the rated
breakdown voltage of the FET. An RCD (or RCDZ) clamp
provides tighter clamp voltage tolerance than a Zener clamp.
The RCD clamp is more cost effective than the Zener clamp but
requires more careful design to ensure that the maximum drain
voltage does not exceed the power FET breakdown voltage.
These VOR limits are based on the BVDSS rating of the internal
FET, a VOR of 60 V to 100 V is typical for most designs, giving
the best PFC and regulation performance.
To overcome these issues two circuits, the active damper and
passive bleeder, are incorporated. The drawback of these
circuits is increased dissipation and therefore reduced efficiency
of the supply so for non-dimming applications these components
can simply be omitted.
Figure 10a shows the line voltage and current at the input of a
leading edge TRIAC dimmer with Figure 10b showing the
resultant rectified bus voltage. In this example, the TRIAC
conducts at 90 degrees.
Series Drain Diode
PI-5983-060810
An ultrafast or Schottky diode in series with the drain is
necessary to prevent reverse current flowing through the
device. The voltage rating must exceed the output reflected
voltage, VOR. The current rating should exceed two times the
average primary current and have a peak rating equal to the
maximum drain current of the selected LYTSwitch device.
350
250
150
50
0.35
0.25
0.15
0.05
-0.05
-0.15
-0.25
Voltage
Current
0.5
50
100
150
200
250
300
350
400
-50
Line Voltage Peak Detector Circuit
LYTSwitch devices use the peak line voltage to regulate the
power delivery to the output. A capacitor value of 1 µF to 4.7 µF
is recommended to minimize line ripple and give the highest
power factor (>0.9), smaller values are acceptable but result in
lower PF and higher line current distortion.
-150
-250
-350
-0.35
Conduction Angle (°)
Figure 10a. Ideal Input Voltage and Current Waveform for a Leading Edge
TRIAC Dimmer at 90°.
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Rev. B 02/13
LYT4211-4218/4311-4318
PI-5984-060810
PI-5986-060810
350
0.35
0.3
350
250
150
50
0.35
0.25
0.15
0.05
-0.05
-0.15
-0.25
Voltage
Voltage
Current
300
Current
250
200
150
100
50
0.25
0.2
0
50
100
150
200
250
300
350
0.15
0.1
-50
-150
-250
0.05
0
0
-350
-0.35
50
100
0
150
200
250
300
350
400
Conduction Angle (°)
Conduction Angle (°)
Figure 10b. Resultant Waveforms Following Rectification of TRIAC Dimmer Output.
Figure 12. Ideal Dimmer Output Voltage and Current Waveforms for a Trailing
Edge Dimmer at 90° Conduction Angle.
Figure 11 shows undesired rectified bus voltage and current
with the TRIAC turning off prematurely and restarting.
Start by adding a bleeder circuit. Add a 0.44 µF capacitor and
±10 W 1 W resistor (components in series) across the rectified
bus (C1 and R1 in Figure 8). If the results in satisfactory operation
reduce the capacitor value to the smallest that result in acceptable
performance to reduce losses and increase efficiency.
If the TRIAC is turning off before the end of the half-cycle
erratically or alternate half AC cycles have different conduction
angles then flicker will be observed in the LED light due to
variations in the output current. This can be solved by including
a bleeder and damper circuit.
If the bleeder circuit does not maintain conduction in the TRIAC,
then add an active damper as shown in Figure 12. This consists
of components R6, C3, and Q1 in conjunction with R8. This
circuit limits the inrush current that flows to charge C4 when the
TRIAC turns on by placing R8 in series for the first 1 ms of the
TRIAC conduction. After approximately 1 ms, Q1 turns on and
shorts R8. This keeps the power dissipation on R8 low and
allows a larger value to be used during current limiting.
Increasing the delay before Q1 turns on by increasing the value
of resistor R6 will improve dimmer compatibility but cause more
power to be dissipated across R8. Monitor the AC line current
and voltage at the input of the power supply as you make the
adjustments. Increase the delay until the TRIAC operates
properly but keep the delay as short as possible for efficiency.
Dimmers will behave differently based on manufacturer and
power rating, for example a 300 W dimmer requires less
dampening and requires less power loss in the bleeder than a
600 W or 1000 W dimmer due to different drive circuits and
TRIAC holding current specifications. Multiple lamps in parallel
driven from the same dimmer can introduce more ringing due to
the increased capacitance of parallel units. Therefore, when
testing dimmer operation verify on a number of models,
different line voltages and with both a single driver and multiple
drivers in parallel.
PI-5985-060810
350
300
250
200
150
100
50
0.35
0.3
Voltage
Current
As a general rule the greater the power dissipated in the bleeder
and damper circuits, the more types of dimmers will work with
the driver.
0.25
0.2
Trailing Edge Phase Controlled Dimmers
0.15
0.1
Figure 11 shows the line voltage and current at the input of the
power supply with a trailing edge dimmer. In this example, the
dimmer conducts at 90 degrees. Many of these dimmers use
back-to-back connected power FETs rather than a TRIAC to
control the load. This eliminates the holding current issue of
TRIACs and since the conduction begins at the zero crossing,
high current surges and line ringing are minimized. Typically these
types of dimmers do not require damping and bleeder circuits.
0.05
0
0
50
100
0
150
200
250
300
350
400
Conduction Angle (°)
Figure 11. Example of Phase Angle Dimmer Showing Erratic Firing.
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LYT4211-4218/4311-4318
Audible Noise Considerations for Use with
Leading Edge Dimmers
lifetime. For every 10 °C rise in temperature, component life is
reduced by a factor of 2. Therefore it is important to properly
heat sink and to verify the operating temperatures of all devices.
Noise created when dimming is typically created by the input
capacitors, EMI filter inductors and the transformer. The input
capacitors and inductors experience high di/dt and dv/dt every
AC half-cycle as the TRIAC fires and an inrush current flows to
charge the input capacitance. Noise can be minimized by
selecting film vs. ceramic capacitors, minimizing the capacitor
value and selecting inductors that are physically short and wide.
Layout Considerations
Primary-Side Connections
Use a single point (Kelvin) connection at the negative terminal of
the input filter capacitor for the SOURCE pin and bias returns.
This improves surge capabilities by returning surge currents
from the bias winding directly to the input filter capacitor. The
BYPASS pin capacitor should be located as close to the
BYPASS pin and connected as close to the SOURCE pin as
possible. The SOURCE pin trace should not be shared with the
main power FET switching currents. All FEEDBACK pin
components that connect to the SOURCE pin should follow the
same rules as the BYPASS pin capacitor. It is critical that the
main power FET switching currents return to the bulk capacitor
with the shortest path as possible. Long high current paths
create excessive conducted and radiated noise.
The transformer may also create noise which can be minimized
by avoiding cores with long narrow legs (high mechanical
resonant frequency). For example, RM cores produce less
audible noise than EE cores for the same flux density. Reducing
the core flux density will also reduce the noise. Reducing the
maximum flux density (BM) to 1±00 Gauss usually eliminates
any audible noise but must be balanced with the increased core
size needed for a given output power.
Thermal and Lifetime Considerations
Lighting applications present thermal challenges to the driver.
In many cases the LED load dissipation determines the working
ambient temperature experienced by the drive so thermal
evaluation should be performed with the driver inside the final
enclosure. Temperature has a direct impact on driver and LED
Secondary-Side Connections
The output rectifier and output filter capacitor should be as
close as possible. The transformer’s output return pin should
have a short trace to the return side of the output filter capacitor.
BYPASS Pin
Capacitor
LYT4317EG
Output
Diode
Clamp Transformer
Input EMI Filter
Bullk
Capacitor
Output
Capacitor
REFERENCE Pin
Resistor
FEEDBACK Pin
Resistor
Output
Capacitors
VOLTAGE MONITOR Pin
Resistor
PI-6904-101612
Figure 13. DER-350 25 W Layout Example, Top Silk / Bottom Layer.
11
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Rev. B 02/13
LYT4211-4218/4311-4318
Quick Design Checklist
Maximum Drain Voltage
Verify that the peak VDS does not exceed 670 V under all
operating conditions including start-up and fault conditions.
Maximum Drain Current
Measure the peak drain current under all operation conditions
including start-up and fault conditions. Look for signs of
transformer saturation (usually occurs at highest operating
ambient temperatures). Verify that the peak current is less than
the stated Absolute Maximum Rating in the data sheet.
Thermal Check
At maximum output power, both minimum and maximum line
voltage and ambient temperature; verify that temperature
specifications are not exceeded for the LYTSwitch, transformer,
output diodes, output capacitors and drain clamp components.
12
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LYT4211-4218/4311-4318
Absolute Maximum Ratings(1,4)
Lead Temperature(3) ........................................................260 °C
Storage Temperature …………………................... -6± to 1±0 °C
Operating Junction Temperature(2)........................ -40 to 1±0 °C
DRAIN Pin Peak Current(±): LYT4x11 .................................1.37 A
LYT4x12 ................................ 2.08 A
LYT4x13 .................................2.72 A
LYT4x14 ................................ 4.08 A
LYT4x1± ................................ ±.44 A
Notes:
1. All voltages referenced to SOURCE, TA = 6± °C.
2. Normally limited by internal circuitry.
3. 1/16 in. from case for ± seconds.
LYT4x16 ................................ 6.88 A
LYT4x17 ................................. 7.73 A
LYT4x18 ................................ 9.00 A
4. Absolute Maximum Ratings specified may be applied, one
at a time without causing permanent damage to the
product. Exposure to Absolute Maximum Ratings for
extended periods of time may affect product reliability.
±. Peak DRAIN current is allowed while the DRAIN voltage is
simultaneously less than 400 V. See also Figure 13.
DRAIN Pin Voltage ………………………................ -0.3 to 670 V
BYPASS Pin Voltage ................................................. -0.3 to 9 V
BYPASS Pin Current ………………………..................... 100 mA
VOLTAGE MONITOR Pin Voltage............................... -0.3 to 9 V
FEEDBACK Pin Voltage …….................................... -0.3 to 9 V
REFERENCE Pin Voltage .......................................... -0.3 to 9 V
Thermal Resistance
Thermal Resistance: E or L Package
Notes:
(qJA) ....................................................10± °C/W(1) 1. Free standing with no heat sink.
(qJC).................................................... 2 °C/W(2) 2. Measured at back surface tab.
Conditions
SOURCE = 0 V; TJ = -20 °C to 12± °C
(Unless Otherwise Specified)
Parameter
Symbol
Min
Typ
Max
Units
Control Functions
Average
TJ = 6± °C
124
132
±.4
140
Switching Frequency
fOSC
kHz
kHz
Peak-Peak Jitter
Frequency Jitter
Modulation Rate
TJ = 6± °C
See Note B
fM
2.6
LYT4x11
-4.1
-7.3
-3.4
-6.1
-2.7
-4.9
-7.0
-8.3
-0.43
-1.7
-3.1
-4.2±
LYT4x12
VBP = 0 V,
ICH1
TJ = 6± °C
LYT4x13-4x17
-12
-9.±
LYT4x18
LYT4x11
-13.3
-0.81
-3.1
-10.8
-0.62
-2.4
BYPASS Pin
Charge Current
mA
LYT4x12
VBP = ± V,
ICH2
TJ = 6± °C
LYT4x13-4x17
-±.6
-4.3±
-±.±
LYT4x18
See Note A, B
-6.7±
Charging Current
Temperature Drift
0.7
5/°C
BYPASS Pin Voltage
VBP
0 °C < TJ < 100 °C
0 °C < TJ < 100 °C
±.7±
±.9±
0.8±
6.1±
6.6
V
V
BYPASS Pin
Voltage Hysteresis
VBP(H)
BYPASS Pin
Shunt Voltage
IBP = 4 mA
0 °C < TJ < 100 °C
VBP(SHUNT)
tSOFT
6.1
±±
6.4
76
V
TJ = 6± °C
VBP = ±.9 V
Soft-Start Time
ms
13
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Rev. B 02/13
LYT4211-4218/4311-4318
Conditions
SOURCE = 0 V; TJ = -20 °C to 12± °C
Parameter
Symbol
Min
Typ
Max
Units
(Unless Otherwise Specified)
Control Functions (cont.)
0 °C < TJ < 100 °C
FET Not Switching
ICD2
ICD1
0.±
1
0.8
2.±
1.2
4
Drain Supply Current
mA
0 °C < TJ < 100 °C
FET Switching at fOSC
VOLTAGE MONITOR Pin
TJ = 6± °C
R = 24.9 kW
RRR = 49.9 kW
Threshold
Hysteresis
11±
123
6
131
Line Overvoltage
Threshold
IOV
µA
VOLTAGE MONITOR
Pin Voltage
0 °C < TJ < 100 °C
VV
2.7±
16±
0.±
3.0
3.2±
20±
V
µA
V
IV < IOV
VOLTAGE MONITOR Pin
Short-Circuit Current
VV = ± V
TJ = 6± °C
IV(SC)
18±
Remote ON/OFF
Threshold
VV(REM)
TJ = 6± °C
FEEDBACK Pin
FEEDBACK Pin Current
at Onset of Maximum
Duty Cycle
IFB(DCMAXR)
0 °C < TJ < 100 °C
0 °C < TJ < 100 °C
90
µA
FEEDBACK Pin Current
Skip Cycle Threshold
IFB(SKIP)
DCMAX
VFB
220
90
µA
5
V
IFB(DCMAXR) < IFB < IFB(SKIP)
0 °C < TJ < 100 °C
Maximum Duty Cycle
FEEDBACK Pin Voltage
99.9
2.±6
480
IFB = 1±0 µA
0 °C < TJ < 100 °C
2.1
2.3
FEEDBACK Pin
Short-Circuit Current
VFB = ± V
TJ = 6± °C
IFB(SC)
320
17
400
µA
DC10
DC40
DC60
IFB = IFB(AR), TJ = 6± °C, See Note B
IFB = 40 µA, TJ = 6± °C
Duty Cycle Reduction
34
±±
5
IFB = 60 µA, TJ = 6± °C
Auto-Restart
TJ = 6± °C
VBP = ±.9 V
Auto-Restart ON-Time
tAR
±±
76
2±
ms
5
TJ = 6± °C
See Note B
Auto-Restart
Duty Cycle
DCAR
tON(SOA)
IFB(AR)
SOA Minimum Switch
ON-Time
TJ = 6± °C
See Note B
1.7±
10
µs
µA
FEEDBACK Pin Current
During Auto-Restart
0 °C < TJ < 100 °C
6.±
14
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LYT4211-4218/4311-4318
Conditions
SOURCE = 0 V; TJ = -20 °C to 12± °C
Parameter
Symbol
Min
Typ
Max
Units
(Unless Otherwise Specified)
REFERENCE Pin
REFERENCE Pin
Voltage
VR
IR
1.223
48.69
1.24±
49.94
1.273
±1.19
V
RR = 24.9 kW
0 °C < TJ < 100 °C
REFERENCE Pin
Current
µA
Current Limit/Circuit Protection
di/dt = 174 mA/µs
di/dt = 174 mA/µs
di/dt = 22± mA/µs
di/dt = 320 mA/µs
di/dt = 3±0 mA/µs
di/dt = 426 mA/µs
di/dt = 133 mA/µs
di/dt = 19± mA/µs
di/dt = 192 mA/µs
di/dt = 240 mA/µs
di/dt = 33± mA/µs
di/dt = 380 mA/µs
di/dt = 483 mA/µs
di/dt = 930 mA/µs
LYT4x12
LYT4x13
LYT4x14
LYT4x1±
LYT4x16
LYT4x17
LYT4x11
LYT4x12
LYT4x13
LYT4x14
LYT4x1±
LYT4x16
LYT4x17
LYT4x18
1.00
1.24
1.46
1.76
2.43
3.26
0.74
0.81
1.00
1.19
1.17
1.44
1.70
2.04
2.83
3.79
0.86
0.9±
1.16
1.38
1.66
2.0±
2.73
±.70
Full Power
Current Limit
(CBP = 4.7 µF)
ILIMIT(F)
A
T = 6± °C
J
Reduced Power
Current Limit
(CBP = 47 µF)
ILIMIT(R)
A
T = 6± °C
1.43
1.76
2.3±
4.90
J
Minimum ON-Time
Pulse
tLEB + tIL(D)
tLEB
TJ = 6± °C
300
1±0
±00
700
±00
ns
ns
ns
°C
°C
Leading Edge
Blanking Time
TJ = 6± °C
See Note B
TJ = 6± °C
See Note B
Current Limit Delay
tIL(D)
1±0
142
7±
Thermal Shutdown
Temperature
See Note B
See Note B
13±
1±0
Thermal Shutdown
Hysteresis
BYPASS Pin Power-Up
Reset Threshold
Voltage
VBP(RESET)
0 °C < TJ < 100 °C
2.2±
3.30
4.2±
V
15
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Rev. B 02/13
LYT4211-4218/4311-4318
Conditions
SOURCE = 0 V; TJ = -20 °C to 12± °C
Parameter
Symbol
Min
Typ
Max
Units
(Unless Otherwise Specified)
Output
TJ = 6± °C
LYT4x11
11.±
13.±
6.9
8.4
±.3
6.3
3.4
3.9
2.±
3.0
1.9
2.3
1.7
2.0
1.3
1.6
13.2
1±.±
8.0
9.7
6.0
7.3
3.9
4.±
2.9
3.4
2.2
2.7
2.0
2.4
1.±
1.8
ID = 100 mA
TJ = 100 °C
TJ = 6± °C
LYT4x12
ID = 100 mA
TJ = 100 °C
TJ = 6± °C
LYT4x13
ID = 1±0 mA
TJ = 100 °C
TJ = 6± °C
LYT4x14
ID = 1±0 mA
TJ = 100 °C
ON-State Resistance
RDS(ON)
W
TJ = 6± °C
LYT4x1±
ID = 200 mA
TJ = 100 °C
TJ = 6± °C
LYT4x16
ID = 2±0 mA
TJ = 100 °C
TJ = 6± °C
LYT4x17
ID = 3±0 mA
TJ = 100 °C
TJ = 6± °C
LYT4x18
ID = 600 mA
TJ = 100 °C
VBP = 6.4 V
VDS = ±60 V
TJ = 100 °C
OFF-State Drain
Leakage Current
IDSS
±0
µA
VBP = 6.4 V
TJ = 6± °C
Breakdown Voltage
BVDSS
670
36
V
V
Minimum Drain
Supply Voltage
TJ < 100 °C
Rise Time
Fall Time
tR
tF
100
±0
ns
ns
Measured in a Typical Flyback
See Note B
NOTES:
A. For specifications with negative values, a negative temperature coefficient corresponds to an increase in magnitude with increasing
temperature and a positive temperature coefficient corresponds to a decrease in magnitude with increasing temperature.
B. Guaranteed by characterization. Not tested in production.
16
Rev. B 02/13
www.powerint.com
LYT4211-4218/4311-4318
Typical Performance Characteristics
10000
300
200
100
Scaling Factors:
Scaling Factors:
LYT4x11 0.18
LYT4x12 0.28
LYT4x13 0.38
LYT4x14 0.56
LYT4x15 0.75
LYT4x16 1.00
LYT4x17 1.16
LYT4x18 1.55
LYT4x11 0.18
LYT4x12 0.28
LYT4x13 0.38
LYT4x14 0.56
LYT4x15 0.75
LYT4x16 1.00
LYT4x17 1.16
LYT4x18 1.55
1000
100
0
0
0
100 200 300 400 500 600
0
100 200 300 400 500 600 700
DRAIN Pin Voltage (V)
DRAIN Voltage (V)
Figure 14. Drain Capacitance vs. Drain Pin Voltage.
Figure 15. Power vs. Drain Voltage.
5
4
3
1.2
1
0.8
0.6
0.4
0.2
Scaling Factors:
LYT4x11 0.18
LYT4x12 0.28
LYT4x13 0.38
LYT4x14 0.56
LYT4x15 0.75
LYT4x16 1.00
LYT4x17 1.16
LYT4x18 1.55
2
1
LYT4x28 TCASE = 25 °C
LYT4x28 TCASE = 100 °C
0
0
0
2
4
6
8
10 12 14 16 18 20
0
100 200 300 400 500 600 700 800
DRAIN Voltage (V)
DRAIN Voltage (V)
Figure 16. Drain Current vs. Drain Voltage.
Figure 17. Maximum Allowable Drain Current vs. Drain Voltage.
17
www.powerint.com
Rev. B 02/13
LYT4211-4218/4311-4318
eSIP-7C (E Package)
C
2
0.403 (10.24)
0.397 (10.08)
0.264 (6.70)
Ref.
0.081 (2.06)
0.077 (1.96)
A
B
Detail A
2
0.290 (7.37)
Ref.
0.325 (8.25)
0.320 (8.13)
0.198 (5.04) Ref.
0.519 (13.18)
Ref.
0.207 (5.26)
0.187 (4.75)
Pin #1
I.D.
0.016 (0.41)
Ref.
0.140 (3.56)
0.120 (3.05)
3
4
0.047 (1.19)
0.118 (3.00)
SIDE VIEW
0.070 (1.78) Ref.
0.033 (0.84)
0.028 (0.71)
0.010 M 0.25 M C A B
6×
0.100 (2.54)
0.050 (1.27)
0.016 (0.41)
0.011 (0.28)
3
6×
0.020 M 0.51 M C
FRONT VIEW
BACK VIEW
0.100 (2.54)
10° Ref.
All Around
0.050 (1.27)
0.050 (1.27)
0.020 (0.50)
0.060 (1.52)
Ref.
0.021 (0.53)
0.019 (0.48)
PIN 1
0.048 (1.22)
0.046 (1.17)
0.019 (0.48) Ref.
0.155 (3.93)
0.059 (1.50)
0.378 (9.60)
Ref.
0.023 (0.58)
0.027 (0.70)
PIN 7
END VIEW
0.059 (1.50)
Notes:
DETAIL A
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.100 (2.54)
0.100 (2.54)
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but including
any mismatch between the top and bottom of the plastic
body. Maximum mold protrusion is 0.007 [0.18] per side.
MOUNTING HOLE PATTERN
(not to scale)
3. Dimensions noted are inclusive of plating thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches (mm).
PI-4917-061510
18
Rev. B 02/13
www.powerint.com
LYT4211-4218/4311-4318
eSIP-7F (L Package)
C
2
0.403 (10.24)
0.397 (10.08)
0.081 (2.06)
0.077 (1.96)
A
0.264 (6.70) Ref.
0.198 (5.04) Ref.
B
Detail A
0.325 (8.25)
0.320 (8.13)
0.290 (7.37)
2
Ref.
3
0.490 (12.45) Ref.
0.016 (0.41)
0.011 (0.28)
6×
0.020 M 0.51 M C
0.173 (4.40)
0.163 (4.15)
1
7
7
1
0.084 (2.14)
0.047 (1.19) Ref.
Pin 1 I.D.
0.089 (2.26)
0.079 (2.01)
0.070 (1.78) Ref.
3
4
0.100 (2.54)
0.050 (1.27)
0.033 (0.84)
0.028 (0.71)
0.129 (3.28)
0.122 (3.08)
6×
0.010 M 0.25 M C A B
BOTTOM VIEW
Exposed pad hidden
SIDE VIEW
TOP VIEW
Exposed pad up
Notes:
1. Dimensioning and tolerancing per ASME
Y14.5M-1994.
1
7
0.021 (0.53)
0.019 (0.48)
0.020 (0.50)
0.023 (0.58)
0.060 (1.52) Ref.
2. Dimensions noted are determined at the
outermost extremes of the plastic body
exclusive of mold flash, tie bar burrs, gate
burrs, and interlead flash, but including
any mismatch between the top and bottom
of the plastic body. Maximum mold
protrusion is 0.007 [0.18] per side.
3. Dimensions noted are inclusive of plating
thickness.
0.019 (0.48) Ref.
0.378 (9.60)
Ref.
0.048 (1.22)
0.046 (1.17)
0.027 (0.70)
END VIEW
DETAIL A (Not drawn to scale)
4. Does not include inter-lead flash or
protrusions.
5. Controlling dimensions in inches (mm).
PI-5204-061510
Part Ordering Information
• LYTSwitch Product Family
• 4 Series Number
• PFC/Dimming
2
3
PFC No Dimming
PFC Dimming
• Voltage Range
1
Low-Line
• Device Size
• Package Identifier
E
L
eSIP-7C
eSIP-7F
LYT
4 2 1 3 E
19
www.powerint.com
Rev. B 02/13
Revision
Notes
Date
11/12
A
B
B
Initial Release.
Corrected Min and Typ parameter table values on pages 13 and 14.
Updated parameters ICH1, ICH2, ICD1, DCAR, ILIMIT(F), ILIMIT(R), on pages 13, 14 and 1±.
02/13
02/20/13
For the latest updates, visit our website: www.powerint.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered
by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A
complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under
certain patent rights as set forth at http://www.powerint.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)
whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant
injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, LYTSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS,
HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc.
Other trademarks are property of their respective companies. ©2013, Power Integrations, Inc.
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World Headquarters
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Taiwan
±24± Hellyer Avenue
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Germany
Phone: +49-89±-±27-39110
Fax: +49-89±-±27-39200
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Fax: +886-2-26±9-4±±0
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