TOP222YNTL_技术文档

This product is not recommended for new designs.

TOP221-227

TOPSwitch-II Family

Three-Terminal Off-Line PWM Switch

Product Highlights

AC

IN

• Lowest cost, lowest component count switcher solution

• Cost competitive with linears above 5 W

• Very low AC/DC losses – up to 90% efﬁciency

• Built-in Auto-restart and Current limiting

• Latching Thermal shutdown for system level protection

• Implements Flyback, Forward, Boost or Buck topology

• Works with primary or opto feedback

• Stable in discontinuous or continuous conduction mode

• Source connected tab for low EMI

D

S

CONTROL

C

TOPSwitch

• Circuit simplicity and Design Tools reduce time to market

Description

PI-1951-091996

The second generation TOPSwitch™-II family is more cost

effective and provides several enhancements over the ﬁrst

generation TOPSwitch family. The TOPSwitch-II family

extends the power range from 100W to 150W for 100/115/

230 VAC input and from 50W to 90W for 85-265 VAC univer-

sal input. This brings TOPSwitch technology advantages

to many new applications, i.e. TV, Monitor, Audio ampliﬁers,

etc. Many signiﬁcant circuit enhancements that reduce the

sensitivity to board layout and line transients now make the

design even easier. The standard 8L PDIP package option

Figure 1. Typical Flyback Application.

reduces cost in lower power, high efﬁciency applications.

The internal lead frame of this package uses six of its pins to

transfer heat from the chip directly to the board, eliminating

the cost of a heat sink. TOPSwitch incorporates all functions

necessary for a switched mode control system into a three

terminal monolithic IC: power MOSFET, PWM controller, high

voltage start up circuit, loop compensation and fault protec-

tion circuitry.

Output Power Table

TO-220 (Y) Package¹

8L PDIP (P) or 8L SMD (G) Package²

Wide Range Input

85 to 265 VAC

Single Voltage Input³

100/115/230 VAC 15ꢀ

Wide Range Input

85 to 265 VAC

PART

ORDER

NUMBER

PART

ORDER

NUMBER

100/115/230 VAC 15ꢀ

4,6

5,6

P_MAX

12 W

25 W

7 W

TOP221YN

TOP222YN

TOP223YN

TOP224YN

TOP225YN

TOP226YN

TOP227YN

9 W

6 W

TOP221PN or TOP221GN

TOP222PN or TOP222GN

15 W

30 W

45 W

60 W

75 W

90 W

15 W

25 W

30 W

10 W

15 W

20 W

TOP223PN or TOP223GN

TOP224PN or TOP224GN

50 W

75 W

100 W

125 W

150 W

Notes: 1. Package outline: TO-220/3 2. Package Outline: DIP-8 or SMD-8 3. 100/115 VAC with doubler input 4. Assumes appro-

priate heat sinking to keep the maximum TOPSwitch junction temperature below 100 °C. 5. Soldered to 1 sq. in. (6.45 cm²), 2 oz.

copper clad (610 gm/m²) 6. P_MAXis the maximum practical continuous power output level for conditions shown. The continuous

power capability in a given application depends on thermal environment, transformer design, efﬁciency required, minimum spec-

iﬁed input voltage, input storage capacitance, etc. 7. Refer to key application considerations section when using TOPSwitch-II in

an existing TOPSwitch design.

www.power.com

August 2016

This Product is Covered by Patents and/or Pending Patent Applications.

TOP221-227

ꢐ

ꢋ

ꢛ

1

ꢋOꢅTꢈOꢌ

ꢃꢈꢇꢎꢅ

ꢎꢅTꢉꢈꢅꢇꢌ

ꢀꢂPPꢌꢑ

ꢙ

ꢋ

ꢀꢁꢂTꢃOꢄꢅꢆ

ꢇꢂTO-ꢈꢉꢀTꢇꢈT

ꢀꢁꢂꢅT ꢈꢉꢏꢂꢌꢇTOꢈꢆ

ꢉꢈꢈOꢈ ꢇꢊPꢌꢎꢗꢎꢉꢈ

ꢖ

-

∏ ꢚ

-

ꢒꢓ7 ꢐ

ꢔꢓ7 ꢐ

ꢒꢓ7 ꢐ

ꢖ

-

ꢐ

ꢎ

ꢌꢎꢊꢎT

ꢎ

ꢗꢘ

Tꢁꢉꢈꢊꢇꢌ

ꢀꢁꢂTꢃOꢄꢅ

ꢆ

R

ꢇ

POꢄꢉꢈ-ꢂP

ꢈꢉꢀꢉT

ꢇ

ꢋOꢅTꢈOꢌꢌꢉꢃ

Tꢂꢈꢅ-Oꢅ

ꢏꢇTꢉ

ꢃꢈꢎꢐꢉꢈ

OꢀꢋꢎꢌꢌꢇTOꢈ

ꢃ

ꢊꢇꢕ

ꢋꢌOꢋꢍ

ꢀꢇꢄ

ꢆ

ꢇ

-

ꢌꢉꢇꢃꢎꢅꢏ

ꢉꢃꢏꢉ

ꢖ

R

ꢘꢌꢇꢅꢍꢎꢅꢏ

Pꢄꢊ

ꢋOꢊPꢇꢈꢇTOꢈ

ꢊꢎꢅꢎꢊꢂꢊ

Oꢅ-Tꢎꢊꢉ

ꢃꢉꢌꢇꢑ

ꢈ

ꢉ

ꢀOꢂꢈꢋꢉ

ꢀꢁꢂ1ꢃꢄꢅꢂ0ꢃ16ꢃ6

Figure 2. Functional Block Diagram.

Pin Functional Description

DRAIN Pin:

Tꢋꢕ ꢆꢖꢗꢏꢘꢖꢋꢙꢙꢚ

ꢀꢛꢖꢖꢏꢌꢗꢏꢜ ꢗꢛ ꢇOꢈꢂꢀꢉ Pꢝꢖ

Output MOSFET drain connection. Provides internal bias

current during start-up operation via an internal switched

high-voltage current source. Internal current sense point.

ꢄꢂꢅꢆꢁ

ꢇOꢈꢂꢀꢉ

CONTROL Pin:

ꢀOꢁTꢂOꢃ

Error ampliﬁer and feedback current input pin for duty cycle

control. Internal shunt regulator connection to provide inter-

nal bias current during normal operation. It is also used as

the connection point for the supply bypass and auto-restart/

compensation capacitor.

ꢊ Pꢋꢌꢍꢋꢎꢏ ꢐTO-22ꢑꢒꢓꢔ

ꢇ

ꢇ ꢐꢞꢟ ꢂTꢁꢔ

1

2

ꢠ

7

SOURCE Pin:

ꢇ ꢐꢞꢟ ꢂTꢁꢔ

ꢄ

YN package – Output MOSFET source connection for high

voltage power return. Primary side circuit

common and reference point.

2

ꢤ

ꢥ

ꢣ

ꢇ

ꢀ

PN and GN package – Primary-side control circuit common

and reference point.

P Pꢋꢌꢍꢋꢎꢏ ꢐꢄꢆP-ꢠꢔ

ꢡ Pꢋꢌꢍꢋꢎꢏ ꢐꢇꢢꢄ-ꢠꢔ

ꢀꢁꢂꢃ08ꢄꢂ0ꢄ0ꢄ01

SOURCE (HV RTN) Pin: (P and G package only)

Output MOSFET source connection for high voltage power

return.

Figure 3. Pin Conﬁguration.

2

Rev. G 08/16

www.power.com

TOP221-227

ꢔꢋꢕꢖꢌ ꢗ Pꢘꢁ ꢙꢚꢛꢜ

ꢓꢑꢒ

TOPSwitch-II Family Functional Description

TOPSwitch is a self biased and protected linear control cur-

rent-to-duty cycle converter with an open drain output. High

efﬁciency is achieved through the use of CMOS and integra-

tion of the maximum number of functions possible. CMOS

process signiﬁcantly reduces bias currents as compared to

bipolar or discrete solutions. Integration eliminates external

power resistors used for current sensing and/or supplying

initial start-up bias current.

ꢂꢆꢇꢕ-ꢞꢌꢟꢇꢚꢞꢇ

ꢄ

ꢝ

ꢀ

ꢁꢂꢃ

During normal operation, the duty cycle of the internal output

MOSFET decreases linearly with increasing CONTROL pin

current as shown in Figure 4. To implement all the required

control, bias, and protection functions, the DRAIN and CON-

TROL pins each perform several functions as described

below. Refer to Figure 2 for a block diagram and to Figure 6

for timing and voltage waveforms of the TOPSwitch inte-

grated circuit.

ꢀ

ꢁꢄꢅ

ꢄ

2ꢑꢒ

ꢉꢀ1

ꢄ

ꢍꢐꢂꢏ

ꢉ

ꢀꢁꢂꢃ0ꢄ0ꢂ0ꢅ01ꢆꢇ

Figure 4. Relationship of Duty Cycle to CONTROL Pin Current.

5.7 V

4.7 V

V

C

0

V

IN

DRAIN

0

5.7 V

4.7 V

V

C

0

V

IN

DRAIN

0

C is the total external capacitance

T

connected to the CONTROL pin

Figure 5. Start-up Waveforms for (a) Normal Operation and (b) Auto-restart.

3

Rev. G 08/16

www.power.com

TOP221-227

Oscillator

TOPSwitch-II Family Functional Description (cont.)

The internal oscillator linearly charges and discharges the

internal capacitance between two voltage levels to create a

sawtooth waveform for the pulse width modulator. The oscil-

lator sets the pulse width modulator/current limit latch at the

beginning of each cycle. The nominal frequency of 100 kHz

was chosen to minimize EMI and maximize efﬁciency in

power supply applications. Trimming of the current reference

improves the frequency accuracy.

Control Voltage Supply

CONTROL pin voltage V_Cis the supply or bias voltage for the

controller and driver circuitry. An external bypass capacitor

closely connected between the CONTROL and SOURCE

pins is required to supply the gate drive current. The total

amount of capacitance connected to this pin (C_T) also sets

the auto-restart timing as well as control loop compensation.

V_Cis regulated in either of two modes of operation. Hyster-

etic regulation is used for initial start-up and overload opera-

tion. Shunt regulation is used to separate the duty cycle

error signal from the control circuit supply current. During

start-up, CONTROL pin current is supplied from a high-volt-

age switched current source connected internally between

the DRAIN and CONTROL pins. The current source pro-

vides sufﬁcient current to supply the control circuitry as well

as charge the total external capacitance (C_T).

Pulse Width Modulator

The pulse width modulator implements a voltage-mode

control loop by driving the output MOSFET with a duty cycle

inversely proportional to the current into the CONTROL pin

which generates a voltage error signal across R_E. The error

signal across R_Eis ﬁltered by an RC network with a typical

corner frequency of 7 kHz to reduce the effect of switching

noise. The ﬁltered error signal is compared with the internal

oscillator sawtooth waveform to generate the duty cycle

waveform. As the control current increases, the duty cycle

decreases. A clock signal from the oscillator sets a latch

which turns on the output MOSFET. The pulse width modu-

lator resets the latch, turning off the output MOSFET. The

maximum duty cycle is set by the symmetry of the internal

oscillator. The modulator has a minimum ON-time to keep

the current consumption of the TOPSwitch independent

of the error signal. Note that a minimum current must be

driven into the CONTROL pin before the duty cycle begins to

change.

The ﬁrst time V_Creaches the upper threshold, the high-

voltage current source is turned off and the PWM modulator

and output transistor are activated, as shown in Figure 5(a).

During normal operation (when the output voltage is regulat-

ed) feedback control current supplies the V_Csupply current.

The shunt regulator keeps V_Cat typically 5.7 V by shunting

CONTROL pin feedback current exceeding the required DC

supply current through the PWM error signal sense resistor

R_E. The low dynamic impedance of this pin (Z_C) sets the

gain of the error ampliﬁer when used in a primary feedback

conﬁguration. The dynamic impedance of the CONTROL

pin together with the external resistance and capacitance

determines the control loop compensation of the power

system.

Gate Driver

The gate driver is designed to turn the output MOSFET on at

a controlled rate to minimize common-mode EMI. The gate

drive current is trimmed for improved accuracy.

If the CONTROL pin total external capacitance (C_T) should

discharge to the lower threshold, the output MOSFET is

turned off and the control circuit is placed in a low-current

standby mode. The high-voltage current source turns on

and charges the external capacitance again. Charging

current is shown with a negative polarity and discharging

current is shown with a positive polarity in Figure 6. The

hysteretic auto-restart comparator keeps V_Cwithin a window

of typically 4.7 to 5.7 V by turning the high-voltage current

source on and off as shown in Figure 5(b). The auto-restart

circuit has a divide-by-8 counter which prevents the output

MOSFET from turning on again until eight discharge-charge

cycles have elapsed. The counter effectively limits

Error Ampliﬁer

The shunt regulator can also perform the function of an er-

ror ampliﬁer in primary feedback applications. The shunt

regulator voltage is accurately derived from the temperature

compensated bandgap reference. The gain of the error

ampliﬁer is set by the CONTROL pin dynamic impedance.

The CONTROL pin clamps external circuit signals to the V_C

voltage level. The CONTROL pin current in excess of the

supply current is separated by the shunt regulator and ﬂows

through R_Eas a voltage error signal.

Cycle-By-Cycle Current Limit

TOPSwitch power dissipation by reducing the auto-restart

duty cycle to typically 5%. Auto-restart continues to cycle

until output voltage regulation is again achieved.

The cycle by cycle peak drain current limit circuit uses the

output MOSFET ON-resistance as a sense resistor. A current

limit comparator compares the output MOSFET ON-state

drain-source voltage, V_DS(ON)with a threshold voltage. High

drain current causes V_DS(ON)to exceed the threshold voltage

and turns the output MOSFET off until the start of the next

clock cycle. The current limit comparator threshold voltage

is temperature compensated to minimize variation of the

effective peak current limit due to temperature related

Bandgap Reference

All critical TOPSwitch internal voltages are derived from a

temperature-compensated bandgap reference. This refer-

ence is also used to generate a temperature-compensated

current source which is trimmed to accurately set the oscilla-

tor frequency and MOSFET gate drive current.

changes in output MOSFET R_DS(ON)

.

4

Rev. G 08/16

www.power.com

TOP221-227

V

IN

V

IN

0

DRAIN

V

OUT

0

I

OUT

• • •

V

C

C(reset)

0

• • •

I

C

Figure 6. Typical Waveforms for (1) Normal Operation, (2) Auto-restart, and (3) Power Down Reset.

The leading edge blanking circuit inhibits the current limit

comparator for a short time after the output MOSFET is

turned on. The leading edge blanking time has been set so

that current spikes caused by primary-side capacitances

and secondary-side rectiﬁer reverse recovery time will not

cause premature termination of the switching pulse.

Overtemperature Protection

Temperature protection is provided by a precision analog

circuit that turns the output MOSFET off when the junction

temperature exceeds the thermal shutdown temperature

(typically 135 °C). Activating the power-up reset circuit by

removing and restoring input power or momentarily pulling

the CONTROL pin below the power-up reset threshold resets

the latch and allows TOPSwitch to resume normal power

supply operation. V_Cis regulated in hysteretic mode and a

4.7 V to 5.7 V (typical) sawtooth waveform is present on the

CONTROL pin when the power supply is latched off.

The current limit can be lower for a short period after the

leading edge blanking time as shown in Figure 12. This is

due to dynamic characteristics of the MOSFET. To avoid trig-

gering the current limit in normal operation, the drain current

waveform should stay within the envelope shown.

High-Voltage Bias Current Source

This current source biases TOPSwitch from the DRAIN pin

and charges the CONTROL pin external capacitance (C_T)

during start-up or hysteretic operation. Hysteretic opera-

tion occurs during auto-restart and overtemperature latched

shutdown. The current source is switched on and off with an

effective duty cycle of approximately 35%. This duty cycle

is determined by the ratio of CONTROL pin charge (I_C) and

discharge currents (I_CD1and I_CD2). This current source is

turned off during normal operation when the output MOSFET

is switching.

Shutdown/Auto-restart

To minimize TOPSwitch power dissipation, the shutdown/

auto-restart circuit turns the power supply on and off at an

auto-restart duty cycle of typically 5% if an out of regulation

condition persists. Loss of regulation interrupts the external

current into the CONTROL pin. V_Cregulation changes from

shunt mode to the hysteretic auto-restart mode described

above. When the fault condition is removed, the power sup-

ply output becomes regulated, V_Cregulation returns to shunt

mode, and normal operation of the power supply resumes.

5

Rev. G 08/16

www.power.com

TOP221-227

ꢑ1

ꢆ.ꢆ µꢒ

ꢉꢃ

ꢊꢋꢄꢅ01

ꢑꢒ ꢓ

ꢄTꢏ

ꢌꢃ

ꢌꢆ

ꢑ

ꢆꢆ0 µꢋ

100 µꢋ

Rꢆ

ꢅꢇ ꢈΩ

ꢌ1

ꢃ.ꢃ ꢍꢋ

1 ꢈꢎ

ꢎR1

10 ꢎ

ꢉ1

ꢊꢋꢅ00ꢄ

Rꢃ

100 Ω

ꢉꢆ

1ꢓꢅ1ꢅ8

R1

10 Ω

ꢀꢁꢂꢃ-ꢄꢅꢆꢇꢃ

ꢈꢉ ꢊꢆꢋꢌꢍ

ꢏ1

ꢑ

TOPꢎꢔꢁꢍꢕꢖ-ꢊꢊ

ꢊ1

ꢌꢅ

100 µꢋ

16 ꢎ

ꢈ

ꢏꢐꢀꢃꢃ1ꢀ

ꢉOꢏTꢄOꢐ

ꢉ

ꢊꢃ

ꢀꢌ81ꢇꢔ

12 ꢓ ꢏꢗꢆ-ꢊꢘꢗꢙꢅꢍꢃꢂ

ꢌꢄ

ꢅꢇ µꢋ

10 ꢎ

ꢎ

-

ꢀꢁꢂꢃ11ꢄꢂ0ꢅ0ꢅ01

Figure 7. Schematic Diagram of a 4 W TOPSwitch-II Standby Power Supply using an 8 lead PDIP.

Application Examples

the full universal AC input range. The TOP221 is packaged in

an 8 pin power DIP package.

Following are just two of the many possible TOPSwitch

implementations. Refer to the Data Book and Design Guide

for additional examples.

The output voltage (5 V) is directly sensed by the Zener

diode (VR1) and the optocoupler (U2). The output voltage is

determined by the sum of the Zener voltage and the volt-

age drop across the LED of the optocoupler (the voltage

drop across R1 is negligible). The output transistor of the

optocoupler drives the CONTROL pin of the TOP221. C5

bypasses the CONTROL pin and provides control loop com-

pensation and sets the auto-restart frequency.

4 W Standby Supply using 8 Lead PDIP

Figure 7 shows a 4 W standby supply. This supply is used

in appliances where certain standby functions (e.g. real time

clock, remote control port) must be kept active even while

the main power supply is turned off.

The 5 V secondary is used to supply the standby function

and the 12 V non-isolated output is used to supply power

for the PWM controller of the main power supply and other

primary side functions.

The transformer’s leakage inductance voltage spikes are

snubbed by R3 and C1 through diode D1. The bias winding

is rectiﬁed and ﬁltered by D3 and C4 providing a non-isolat-

ed 12 V output which is also used to bias the collector of the

optocoupler’s output transistor. The isolated 5 V output wind-

ing is rectiﬁed by D2 and ﬁltered by C2, L1 and C3.

For this application the input rectiﬁers and input ﬁlter are

sized for the main supply and are not shown. The input DC

rail may vary from 100 V to 380 V DC which corresponds to

6

Rev. G 08/16

www.power.com

TOP221-227

ꢗ1

ꢅ.ꢅ µꢙ

ꢇꢃ

ꢈꢉRꢊꢃ0

ꢌ12 ꢍ

ꢅTꢁ

ꢌꢃ

ꢅꢅ0 µꢍ

ꢅꢎ ꢏ

ꢌꢅ

ꢃꢃ0 µꢍ

ꢅꢎ ꢏ

ꢏR1

ꢀ6ꢓꢔꢃ00

ꢇ1

ꢑꢒꢏꢃ6ꢌ

ꢑR1

ꢊ00 ꢏ

ꢗꢃ

ꢃꢃ ꢘꢙ

ꢇꢅ

1ꢋꢊ1ꢊ8

R1

ꢌ1

100 Ω

ꢊꢆ µꢍ

ꢌꢊ

0.1 µꢍ

ꢊ00 ꢏ

TOPꢃꢆꢇꢈꢉꢊ-ꢋꢋ

ꢌ6

Rꢃ

ꢉ1

ꢂ

ꢃ

0.1 µꢍ

ꢐ1

ꢃꢃ0 Ω

ꢐꢚꢀꢃꢃꢊꢀ

ꢄ

ꢄOꢁTꢅOꢀ

ꢃꢎ0 ꢏꢕꢌ

ꢉꢃ

ꢀꢌ81ꢆꢕ

Rꢅ

6.8 Ω

ꢍ1

ꢅ.1ꢎ ꢕ

ꢏRꢃ

1ꢋꢎꢃꢊ1ꢑ

11 ꢏ

ꢌꢆ

1 ꢛꢍ

ꢃꢎ0 ꢏꢕꢌ

ꢒ1

ꢖ1

ꢌꢎ

ꢊꢆ µꢍ

ꢀ

ꢁ

ꢀꢁꢂꢃ01ꢄꢂ0ꢅꢅ1ꢄꢆ

Figure 8. Schematic Diagram of a 20 W Universal Input TOPSwitch-II Power Supply using an 8 lead PDIP.

20 W Universal Supply using 8 Lead PDIP

VR1 clamp leading-edge voltage spikes caused by trans-

former leakage inductance. The power secondary winding

is rectiﬁed and ﬁltered by D2, C2, L1, and C3 to create the

12 V output voltage. R2 and VR2 provide a slight pre-load

on the 12 V output to improve load regulation at light loads.

The bias winding is rectiﬁed and ﬁltered by D3 and C4 to

create a TOPSwitch bias voltage. L2 and Y1-safety capaci-

tor C7 attenuate common mode emission currents caused

by high-voltage switching waveforms on the DRAIN side of

the primary winding and the primary to secondary capaci-

tance. Leakage inductance of L2 with C1 and C6 attenu-

ates differential-mode emission currents caused by the

fundamental and harmonics of the trapezoidal or triangular

primary current waveform. C5 ﬁlters internal MOSFET gate

drive charge current spikes on the CONTROL pin, deter-

mines the auto-restart frequency, and together with R1 and

R3, compensates the control loop.

Figure 8 shows a 12 V, 20 W secondary regulated ﬂyback

power supply using the TOP224P in an eight lead PDIP

package and operating from universal 85 to 265 VAC input

voltage. This example demonstrates the advantage of the

higher power 8 pin leadframe used with the TOPSwitch-II

family. This low cost package transfers heat directly to the

board through six source pins, eliminating the heatsink and

the associated cost. Efﬁciency is typically 80% at low line

input. Output voltage is directly sensed by optocoupler U2

and Zener diode VR2. The output voltage is determined by

the Zener diode (VR2) voltage and the voltage drops across

the optocoupler (U2) LED and resistor R1. Other output

voltages are possible by adjusting the transformer turns ratio

and value of Zener diode VR2.

AC power is rectiﬁed and ﬁltered by BR1 and C1 to create

the high voltage DC bus applied to the primary winding of

T1. The other side of the transformer primary is driven by

the integrated TOPSwitch-II high-voltage MOSFET. D1 and

7

Rev. G 08/16

www.power.com

TOP221-227

Key Application Considerations

General Guidelines

• Short interruptions of AC power may cause TOPSwitch

to enter the 8-count auto-restart cycle before starting

again. This is because the input energy storage capaci-

tors are not completely discharged and the CONTROL

pin capacitance has not discharged below the internal

power-up reset voltage.

• Keep the SOURCE pin length very short. Use a Kelvin

connection to the SOURCE pin for the CONTROL pin by-

pass capacitor. Use single point grounding techniques

at the SOURCE pin as shown in Figure 9.

• In some cases, minimum loading may be necessary to

keep a lightly loaded or unloaded output voltage within

the desired range due to the minimum ON-time.

• Minimize peak voltage and ringing on the DRAIN volt-

age at turn-off. Use a Zener or TVS Zener diode to

clamp the drain voltage below the breakdown voltage

rating of TOPSwitch under all conditions, including start-

up and overload. The maximum recommended clamp

Zener voltage for the TOP2XX series is 200 V and the

corresponding maximum reﬂected output voltage on the

primary is 135 V. Please see Step 4: AN-16 in the 1996-

97 Data Book and Design Guide or on our Web site.

Replacing TOPSwitch with TOPSwitch-II

There is no external latching shutdown function in

TOPSwitch-II. Otherwise, the functionality of the TOPSwitch-II

devices is same as that of the TOPSwitch family. However,

before considering TOPSwitch-II as a 'drop in' replace-

ment in an existing TOPSwitch design, the design should

be veriﬁed as described below.

• The transformer should be designed such that the rate

of change of drain current due to transformer saturation

is within the absolute maximum speciﬁcation (∆I_Din

100 ns before turn off as shown in Figure 13). As a

guideline, for most common transformer cores, this can

be achieved by maintaining the Peak Flux Density (at

maximum I_LIMITcurrent) below 4200 Gauss (420 mT).

The transformer spreadsheets Rev. 2.1 (or later) for con-

tinuous and Rev.1.0 (or later) for discontinuous conduc-

tion mode provide the necessary information.

The new TOPSwitch-II family offers more power capability

than the original TOPSwitch family for the same MOSFET

_DS(ON). Therefore, the original TOPSwitch design must

be reviewed to make sure that the selected TOPSwitch-II

replacement device and other primary components are not

over stressed under abnormal conditions.

R

The following veriﬁcation steps are recommended:

• Do not plug TOPSwitch into a “hot” IC socket dur-

ing test. External CONTROL pin capacitance may be

charged to excessive voltage and cause TOPSwitch

damage.

• Check the transformer design to make sure that it

meets the ∆I_Dspeciﬁcation as outlined in the General

Guidelines section above.

• While performing TOPSwitch device tests, do not

exceed maximum CONTROL pin voltage of 9 V or maxi-

mum CONTROL pin current of 100 mA.

• Thermal: Higher power capability of the TOPSwitch-II

would in many instances allow use of a smaller MOS-

FET device (higher R_DS(ON)) for reduced cost. This may

affect TOPSwitch power dissipation and power supply

efﬁciency. Therefore thermal performance of the power

supply must be veriﬁed with the selected TOPSwitch-II

device.

• Under some conditions, externally provided bias or

supply current driven into the CONTROL pin can hold

the TOPSwitch in one of the 8 auto-restart cycles in-

deﬁnitely and prevent starting. To avoid this problem when

doing bench evaluations, it is recommended that the V_C

power supply be turned on before the DRAIN voltage is

applied. TOPSwitch can also be reset by shorting the

CONTROL pin to the SOURCE pin momentarily.

• Clamp Voltage: Reﬂected and Clamp voltages should

be veriﬁed not to exceed recommended maximums

for the TOP2XX Series: 135 V Reﬂected/200 V Clamp.

Please see Step 4: AN-16 in the Data Book and Design

Guide and readme.txt ﬁle attached to the transformer

design spreadsheets.

• CONTROL pin currents during auto-restart operation

are much lower at low input voltages (< 36 V) which in-

creases the auto-restart cycle time (see the I_Cvs. DRAIN

Voltage Characteristic curve).

• Agency Approval: Migrating to TOPSwitch-II may

require agency re-approval.

8

Rev. G 08/16

www.power.com

TOP221-227

TO-220 PACKAGE

S

D

C

TOP VIEW

DIP-8/SMD-8 PACKAGE

SOURCE

CONTROL

DRAIN

TOP VIEW

Figure 9. Recommended TOPSwitch Layout.

Design Tools

All data sheets, application literature and up-to-date versions

of the Transformer Design Spreadsheets can be downloaded

from our Web site at www.power.com. A diskette of the

Transformer Design Spreadsheets may also be obtained by

sending in the completed form provided at the end of this

data sheet.

The following tools available from Power Integrations greatly

simplify TOPSwitch based power supply design.

• Data Book and Design Guide includes extensive

application information

• Excel Spreadsheets for Transformer Design - Use of

this tool is strongly recommended for all TOPSwitch

designs.

• Reference design boards – Production viable designs

that are assembled and tested.

9

Rev. G 08/16

www.power.com

TOP221-227

ABSOLUTE MAXIMUM RATINGS^(1,5)

Notes:

DRAIN Voltage .................................................. -0.3 to 700 V

1. All voltages referenced to SOURCE, T_A= 25 °C.

2. Related to transformer saturation – see Figure 13.

3. Normally limited by internal circuitry.

DRAIN Current Increase (∆I_D) in 100 ns except during

blanking time ................................................. 0.1 x I_LIMIT(MAX)

(2)

CONTROL Voltage............................................ - 0.3 V to 9 V

CONTROL Current.................................................... 100 mA

Storage Temperature ........................................-65 to 150 °C

Operating Junction Temperature⁽³⁾...................-40 to 150 °C

Lead Temperature⁽⁴⁾...................................................260 °C

4. 1/16" from case for 5 seconds.

5. The Absolute Maximum Ratings speciﬁed may be applied,

one at a time without causing permanent damage to the

product. Exposure to Absolute Maximum Ratings for ex-

tended periods of time may affect product reliability.

THERMAL RESISTANCE

Thermal Resistance: Y Package

Notes:

(θ_JA)⁽¹⁾............................................. 70 °C/W 1. Free standing with no heat sink.

(θ_JC)⁽²⁾............................................... 2 °C/W 2. Measured at tab closest to plastic interface or SOURCE pin.

P/G Package:

3. Soldered to 0.36 sq. inch (232 mm²), 2 oz. (610 gm/m²) copper clad.

(θ_JA) ............................45 °C/W⁽³⁾; 35 °C/W⁽⁴⁾4. Soldered to 1 sq. inch (645 mm²), 2 oz. (610 gm/m²) copper clad.

(θ_JC)⁽²⁾............................................. 11 °C/W

Conditions

(Unless Otherwise Speciﬁed)

Parameter

Symbol

Min

Typ

Max

Units

See Figure 14

SOURCE = 0 V; T_J= -40 to 125 °C

CONTROL FUNCTIONS

f_OSC

Output Frequency

I_C= 4 mA, T_J= 25 °C

I_C= I_CD1+ 0.4 mA, See Figure 10

I_C= 10 mA, See Figure 10

90

64

100

67

110

70

kHz

%

D_MAX

Maximum Duty Cycle

Minimum Duty Cycle

D_MIN

0.7

-21

1.7

-16

2.7

-11

%

PWM

Gain

I_C= 4 mA, T_J= 25 °C

%/mA

See Figure 4

PWM Gain

Temperature Drift

-0.05

2.0

See Note A

%/mA/°C

External Bias Current

Dynamic Impedance

I_B

0.8

10

3.3

22

mA

See Figure 4

I_C= 4 mA, T_J= 25 °C

15

Ω

Z_C

See Figure 11

Dynamic Impedance

Temperature Drift

0.18

%/°C

SHUTDOWN/AUTO-RESTART

V_C= 0 V

V_C= 5 V

-2.4

-2

-1.9

-1.5

-1.2

-0.8

CONTROL Pin

I_C

T_J= 25 °C

mA

Charging Current

Temperature Drift

See Note A

S1 open

0.4

V_C(AR)

%/°C

10

Rev. G 08/16

www.power.com

TOP221-227

Conditions

(Unless Otherwise Speciﬁed)

See Figure 14

Parameter

Symbol

Min

Typ

Max

Units

SOURCE = 0 V; T_J= -40 to 125 °C

SHUTDOWN/AUTO-RESTART (cont.)

Auto-restart

Threshold Voltage

S1 open

5.7

4.7

1.0

V

UV Lockout

Threshold Voltage

4.4

0.6

5.0

Auto-restart

Hysteresis Voltage

V

TOP221-222

TOP223-227

2

5

9

8

Auto-restart

Duty Cycle

S1 open

%

Hz

Auto-restart

Frequency

S1 open

1.2

CIRCUIT PROTECTION

di/dt = 40 mA/µs,

T_J= 25 °C

TOP221YN

TOP221PN or GN

TOP222YN

0.23

0.45

0.25

0.50

0.28

0.55

di/dt = 80 mA/µs,

T_J= 25 °C

di/dt = 160 mA/µs,

T_J= 25 °C

TOP222PN or GN

TOP223YN

0.90

1.35

1.80

2.25

2.70

1.00

1.50

2.00

2.50

3.00

1.10

1.65

2.20

2.75

3.30

TOP223PN or GN

TOP224YN

Self-protection

I_LIMIT

di/dt = 240 mA/µs,

T_J= 25 °C

A

Current Limit

TOP224PN or GN

di/dt = 320 mA/µs,

T_J= 25 °C

TOP225YN

TOP226YN

di/dt = 400 mA/µs,

T_J= 25 °C

di/dt = 480 mA/µs,

TOP227YN

T_J= 25 °C

0.75 x

I_LIMIT(MIN)

≤ 85 VAC

(Rectiﬁed Line Input)

See Figure 12

I_INIT

A

T_J= 25 °C

Initial Current Limit

0.6 x

I_LIMIT(MIN)

265 VAC

(Rectiﬁed Line Input)

Leading Edge

t_LEB

I_C= 4 mA,

T_J= 25 °C

ns

180

Blanking Time

11

Rev. G 08/16

www.power.com

TOP221-227

Conditions

(Unless Otherwise Speciﬁed)

See Figure 14

Parameter

Symbol

Min

Typ

Max

Units

SOURCE = 0 V; T_J= -40 to 125 °C

CIRCUIT PROTECTION (cont.)

Current Limit

t_ILD

I_C= 4 mA

ns

°C

V

100

135

3.3

Delay

Thermal Shutdown

Temperature

I_C= 4 mA

S2 open

125

2.0

Power-up Reset

V_C(RESET)

4.3

Threshold Voltage

OUTPUT

31.2

36.0

TOP221

T_J= 25 °C

I_D= 25 mA

T_J= 100 °C

51.4

15.6

25.7

60.0

18.0

30.0

TOP222

I_D= 50 mA

TOP223

T_J= 25 °C

T_J= 100 °C

T_J= 25 °C

T_J= 100 °C

7.8

12.9

5.2

9.0

15.0

6.0

I_D= 100 mA

TOP224

T_J= 25 °C

Ω

ON-State

R_DS(ON)

Resistance

I_D= 150 mA

T_J= 100 °C

8.6

10.0

TOP225

I_D= 200 mA

TOP226

T_J= 25 °C

T_J= 100 °C

T_J= 25 °C

3.9

6.4

3.1

5.2

2.6

4.3

4.5

7.5

3.6

6.0

3.0

5.0

I_D= 250 mA

TOP227

T_J= 100 °C

T_J= 25 °C

T_J= 100 °C

I_D= 300 mA

See Note B

V_DS= 560 V, T_A= 125 °C

OFF-State

Current

250

µA

I_DSS

See Note B

I_D= 100 µA, T_A= 25 °C

Breakdown

Voltage

700

V

BV_DSS

Rise

Time

100

50

ns

t_R

Measured in a Typical Flyback

Converter Application.

Fall

Time

t_F

12

Rev. G 08/16

www.power.com

TOP221-227

Conditions

(Unless Otherwise Speciﬁed)

See Figure 14

Parameter

Symbol

Min

Typ Max

Units

SOURCE = 0 V; T_J= -40 to 125 °C

OUTPUT (cont.)

V

See Note C

I_C= 4 mA

36

DRAIN Supply Voltage

Shunt Regulator

Voltage

V_C(SHUNT)

5.5

5.7

50

6.0

Shunt Regulator

Temperature Drift

ppm/°C

Output

TOP221-224

TOP225-227

0.6

0.7

1.2

1.4

1.6

1.8

I_CD1

CONTROL Supply/

Discharge Current

MOSFET Enabled

mA

I_CD2

0.5

0.8

1.1

Output MOSFET Disabled

NOTES:

A. For speciﬁcations with negative values, a negative temperature coefﬁcient corresponds to an increase in

magnitude with increasing temperature, and a positive temperature coefﬁcient corresponds to a decrease in

magnitude with increasing temperature.

B. The breakdown voltage and leakage current measurements can be accomplished as shown in Figure 15 by

using the following sequence:

i. The curve tracer should initially be set at 0 V. The base output should be adjusted through a voltage

sequence of 0 V, 6.5 V, 4.3 V, and 6.5 V, as shown. The base current from the curve tracer should not

exceed 100 mA. This CONTROL pin sequence interrupts the Auto-restart sequence and locks the

TOPSwitch internal MOSFET in th OFF-state.

ii. The breakdown and the leakage measurements can now be taken with the curve tracer. The maximum

voltage from the curve tracer must be limited to 700 V under all conditions.

C. It is possible to start up and operate TOPSwitch at DRAIN voltages well below 36 V. However, the CONTROL

pin charging current is reduced, which affects start-up time, auto-restart frequency, and auto-restart duty cycle.

Refer to the characteristic graph on CONTROL pin charge current (I_C) vs. DRAIN voltage for low voltage opera-

tion characteristics.

13

Rev. G 08/16

www.power.com

TOP221-227

120

100

80

60

ꢀ0

20

0

t

ꢄ

t

ꢅ

HV

90%

t

ꢀRAIN

ꢁꢂLTAꢃE

1

2

D =

1

Dynamic

ꢃ

10%

Impedance Slope

0 V

PI-2039-033001

0

2

ꢀ

6

8

10

Figure 10. TOPSwitch Duty Cycle Measurement.

CONTROL Pin Voltage (V)

Figure 11. TOPSwitch CONTROL Pin I-V Characteristic.

t

(ꢅlanking Time)

LEꢅ

1.3

1.2

1.1

1.0

0.ꢀ

0.8

0.ꢃ

0.6

0.ꢂ

0.ꢁ

0.3

0.2

0.1

100 ꢇꢈ

ꢉ_ꢊꢋꢌ

∆ꢁ_ꢆ

I_INIT(MIN)@ 85 VAC

I_INIT(MIN)@ 265 VAC

DRAIN

CURRENT

I_LIMIT(MAꢄ)@ 25 ˚C

I_LIMIT(MIN)@ 25 ˚C

0 ꢍ

0

1

2

3

ꢁ

ꢂ

6

ꢃ

8

ꢀꢁꢂꢃ0ꢄ1ꢂ0ꢅ0ꢅ01

Time (µs)

Figure 13. Example of ∆I_Don Drain Current Waveform with

Figure 12. Self-protection Current Limit Envelope.

Saturated Transformer.

14

Rev. G 08/16

www.power.com

TOP221-227

ꢄꢆ0 Ω

ꢇ ꢉ

ꢊꢋ

ꢄ

ꢂ

ꢅOꢀTꢆOꢇ

ꢄꢆ0 Ω

ꢅ

TOPꢂꢈꢉꢊꢋꢌ

ꢊ1

ꢄ0 ꢈ

0.1 µꢅ

ꢄꢆ µꢅ

0ꢂꢇ0 ꢈ

ꢀOTꢁꢂꢃ 1. ꢌꢍꢎꢏ ꢐeꢏꢐ ꢑꢎꢒꢑꢓꢎꢐ ꢎꢏ ꢔꢕꢐ ꢖꢗꢗꢘꢎꢑꢖꢙꢘe ꢚꢕꢒ ꢑꢓꢒꢒeꢔꢐ ꢘꢎꢛꢎꢐ ꢕꢒ ꢕꢓꢐꢗꢓꢐ ꢑꢍꢖꢒꢖꢑꢐeꢒꢎꢏꢐꢎꢑ ꢛeꢖꢏꢓꢒeꢛeꢔꢐꢏ.

ꢋ. ꢅꢕꢒ ꢀ ꢗꢖꢑꢜꢖꢝeꢞ ꢏꢍꢕꢒꢐ ꢖꢘꢘ ꢊꢟꢠRꢡꢢ ꢖꢔꢣ ꢊꢟꢠRꢡꢢ ꢤꢥꢈ Rꢌꢦꢧ ꢗꢎꢔꢏ ꢐꢕꢝeꢐꢍeꢒ.

ꢀꢁꢂ1ꢃ6ꢄꢂ1106ꢃ6

Figure 14. TOPSwitch General Test Circuit.

ꢆꢇꢈve

ꢉꢈꢊꢋeꢈ

ꢆ

ꢠ

ꢟ

ꢃ

ꢄ

ꢅOꢀTꢆOꢇ

ꢅ

TOPꢄꢈꢉꢊꢋꢌ

6.ꢡ ꢢ

ꢅ.ꢣ ꢢ

ꢀOTꢁꢂ ꢉꢌꢍꢎ ꢆꢏꢐꢉRꢏꢑ ꢒꢍꢓ ꢎeꢔꢇeꢓꢋe ꢍꢓꢕeꢈꢈꢇꢒꢕꢎ ꢕꢌe ꢖꢇꢕꢗꢂꢈeꢎꢕꢊꢈꢕ ꢎeꢔꢇeꢓꢋe ꢊꢓꢘ

ꢙꢗꢋꢚꢎ ꢕꢌe ꢉꢏꢀꢛꢜꢍꢕꢋꢌ ꢍꢓꢕeꢈꢓꢊꢙ ꢝꢏꢛꢞꢟꢉ ꢍꢓ ꢕꢌe ꢏꢞꢞꢂꢛꢕꢊꢕe.

ꢀꢁꢂꢃ10ꢄꢂ0ꢅ0ꢅ01

Figure 15. Breakdown Voltage and Leakage Current Measurement Test Circuit.

15

Rev. G 08/16

www.power.com

TOP221-227

BENCH TEST PRECAUTIONS FOR EVALUATION OF ELECTRICAL CHARACTERISTICS

The following precautions should be followed when testing

TOPSwitch by itself outside of a power supply. The sche-

matic shown in Figure 14 is suggested for laboratory testing

of TOPSwitch.

in this Auto-restart mode, there is only a 12.5% chance that

the control pin oscillation will be in the correct state (DRAIN

active state) so that the continuous DRAIN voltage waveform

may be observed. It is recommended that the V_Cpower sup-

ply be turned on ﬁrst and the DRAIN power supply second

if continuous drain voltage waveforms are to be observed.

The 12.5% chance of being in the correct state is due to the

8:1 counter. Temporarily shorting the CONTROL pin to the

SOURCE pin will reset TOPSwitch, which then will come up

in the correct state.

When the DRAIN supply is turned on, the part will be in the

Auto-restart mode. The CONTROL pin voltage will be oscil-

lating at a low frequency from 4.7 to 5.7 V and the DRAIN is

turned on every eighth cycle of the CONTROL pin oscilla-

tion. If the CONTROL pin power supply is turned on while

Typical Performance Characteristics

FREQUENCY vs. TEMPERATURE

BREAKDOWN vs. TEMPERATURE

Junction Temperature (°C)

CURRENT LIMIT vs. TEMPERATURE

ꢃ ꢖꢗꢘ ꢀꢁꢂꢃꢄ ꢅOꢏTꢂꢙꢚ

ꢎ

ꢀ

ꢂ

ꢄ ꢅ ꢂ

ꢃ

1.6

1.ꢀ

0.8

0.ꢁ

0

ꢀ0

ꢁ0

60

80

100

Junction Temperature (°C)

ꢀꢁꢂꢃꢄ ꢅꢆꢇꢈꢉꢊꢋ ꢌꢅꢍ

16

Rev. G 08/16

www.power.com

TOP221-227

Typical Performance Characteristics (cont.)

OUTPUT CHARACTERISTICS

C

OSS

vs. DRAIN VOLTAGE

°

DRAIN Voltage (V)

DRAIN CAPACITANCE POWER

DRAIN Voltage (V)

17

Rev. G 08/16

www.power.com

TOP221-227

Plastic TO-220/3

J

mm

DIM

inches

B

K

P

11.68-12.19

10.16-10.54

5.99-6.60

6.10 - REF.

13.21-14.22

.71-.97

A

B

C

D

E

F

.460-.480

.400-.415

.236-.260

.240 - REF.

.520-.560

.028-.038

.045-.055

.090-.110

.165-.185

.045-.055

.095-.115

.015-.020

.705-.715

.146-.156

.103-.113

Notes:

C

1. Package dimensions conform

to JEDEC specification TO-220

AB for standard flange

mounted, peripheral lead

package; .100 inch lead

spacing (Plastic) 3 leads (issue

J, March 1987).

O

A

N

2. Controlling dimensions are

inches.

1.14-1.40

2.29-2.79

4.19-4.70

1.14-1.40

2.41-2.92

.38-.51

G

H

J

3. Pin numbers start with Pin 1,

and continue from left to right

when viewed from the top.

4. Dimensions shown do not

include mold flash or other

protrusions. Mold flash or

protrusions shall not exceed

.006 (.15 mm) on any side.

5. Position of terminals to be

measured at a position .25

(6.35 mm) from the body.

6. All terminals are solder plated.

7. Bent lead should be 12 mil

max.

L

D

K

L

E

M

N

O

P

17.91-18.16

3.71-3.96

2.62-2.87

F

M

H

G

Y03A

PI-1848-050602

PDIP-8 (P Package)

D S .004 (.10)

DIM

Inches

mm

8

5

-E-

A

B

C

G

H

J1

J2

K

L

M

N

P

Q

0.356-0.387

0.240-0.260

0.125-0.145

0.015-0.040

0.118-0.140

0.057-0.068

0.014-0.022

0.008-0.015

0.100 BSC

0.030 (MIN)

0.300-0.320

0.300-0.390

0.300 BSC

9.05-9.83

6.10-6.60

3.18-3.68

0.38-1.02

3.00-3.56

1.45-1.73

0.36-0.56

0.20-0.38

2.54 BSC

0.76 (MIN)

7.62-8.13

7.62-9.91

7.62 BSC

B

1

4

A

-D-

-F-

M

J1

N

Notes:

1. Package dimensions conform to JEDEC

C

speciﬁcation MS-001-AB for standard dual in-line

(DIP) package .300 inch row spacing (PLASTIC)

8 leads (issue B, 7/85).

2. Controlling dimensions are inches.

3. Dimensions shown do not include mold ﬂash

or other protrusions. Mold ﬂash or protrusions

shall not exceed .006 (.15) on any side.

4. D, E and F are reference datums on the molded

body.

H

K

G

Q

J2

P08A

L

P

PI-2076-081716

18

Rev. G 08/16

www.power.com

TOP221-227

SMD-8 (G Package)

D S .004 (.10)

DIM

Inches

mm

8

5

-E-

A

B

C

G

H

J1

J2

J3

J4

K

L

M

P

0.356-0.387

0.240-0.260

0.125-0.145

0.004-0.012

0.036-0.044

0.057-0.068

0.048-0.053

0.032-0.037

0.007-0.011

0.010-0.012

0.100 BSC

0.030 (MIN)

0.372-0.388

0-8°

9.05-9.83

6.10-6.60

3.18-3.68

0.10-0.30

0.91-1.12

1.45-1.73

1.22-1.35

0.81-0.94

0.18-0.28

0.25-0.30

2.54 BSC

0.76 (MIN)

9.45-9.86

0-8°

.420

P

B

.046

.060 .046

.060

.080

Pin 1

1

4

L

.086

.186

.286

α

A

-D-

-F-

Solder Pad Dimensions

M

J1

Notes:

1. Package dimensions conform to JEDEC

speciﬁcation MS-001-AB (issue B, 7/85)

except for lead shape and size.

2. Controlling dimensions are inches.

3. Dimensions shown do not include mold

ﬂash or other protrusions. Mold ﬂash or

protrusions shall not exceed .006 (.15) on

any side.

C

K

.004 (.10)

H

J3

J4

.010 (.25) M A S

α

G

4. D, E and F are reference datums on the

molded body.

G08A

J2

PI-2077-081716

Part Ordering Information

• TOPSwitch Product Family

• II Series Number

• Package Identiﬁer

G

P

Y

Plastic SMD-8

Plastic DIP-8

Plastic TO-220/3

• Lead Finish

N

Lead Free

• Tape & Reel and Other Options

Blank

TL

Standard Conﬁgurations

Tape & Reel, 1000 pcs minimum, G Package only

TOP 222

G N TL

19

Rev. G 08/16

www.power.com

TOP221-227

Revision Notes

Date

C

-

12/97

Updated package references, corrected spelling, storage temperature and 0JC and updated nomenclature in param-

eter table. Added G package references to Self-Protection Current Limit parameter. Corrected font sizes in ﬁgures.

D

07/01

E

F

Updated with new Brand Style.

07/15

10/15

08/16

Updated part numbers with the "N" sufﬁx. Added Y, P and G package drawings.

Updated PDIP-8 (P Package) and SMD-8 (G Package) per PCN-16232.

G

For the latest updates, visit our website: www.power.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations

does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY

HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF

MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information

The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one

or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of

Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set

forth at http://www.power.com/ip.htm.

Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)

whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signiﬁcant injury

or death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the

failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, SENZero, SCALE-iDriver, Qspeed, PeakSwitch, LYTSwitch, LinkZero, LinkSwitch, InnoSwitch, HiperTFS,

HiperPFS, HiperLCS, DPA-Switch, CAPZero, Clampless, EcoSmart, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of

Power Integrations Worldwide Sales Support Locations

World Headquarters

5245 Hellyer Avenue

San Jose, CA 95138, USA.

Main: +1-408-414-9200

Customer Service:

Phone: +1-408-414-9665

Fax: +1-408-414-9765

e-mail: usasales@power.com

Germany

Lindwurmstrasse 114

80337 Munich

Japan

Kosei Dai-3 Bldg.

2-12-11, Shin-Yokohama,

Kohoku-ku

Yokohama-shi Kanagawa

222-0033 Japan

Phone: +81-45-471-1021

Fax: +81-45-471-3717

e-mail: japansales@power.com

Taiwan

5F, No. 318, Nei Hu Rd., Sec. 1

Nei Hu Dist.

Taipei 11493, Taiwan R.O.C.

Phone: +886-2-2659-4570

Fax: +886-2-2659-4550

e-mail: taiwansales@power.com

Germany

Phone: +49-895-527-39110

Fax: +49-895-527-39200

e-mail: eurosales@power.com

India

UK

China (Shanghai)

Rm 1601/1610, Tower 1,

Kerry Everbright City

No. 218 Tianmu Road West,

Shanghai, P.R.C. 200070

Phone: +86-21-6354-6323

Fax: +86-21-6354-6325

e-mail: chinasales@power.com

#1, 14th Main Road

Vasanthanagar

Bangalore-560052 India

Phone: +91-80-4113-8020

Fax: +91-80-4113-8023

e-mail: indiasales@power.com

Cambridge Semiconductor,

a Power Integrations company

Westbrook Centre, Block 5, 2nd Floor

Korea

RM 602, 6FL

Korea City Air Terminal B/D, 159-6 Milton Road

Samsung-Dong, Kangnam-Gu,

Seoul, 135-728, Korea

Phone: +82-2-2016-6610

Fax: +82-2-2016-6630

Cambridge CB4 1YG

Phone: +44 (0) 1223-446483

e-mail: eurosales@power.com

Italy

Via Milanese 20, 3rd. Fl.

20099 Sesto San Giovanni

(MI) Italy

e-mail: koreasales@power.com

China (Shenzhen)

17/F, Hivac Building, No. 2,

Keji Nan 8th Road, Nanshan

Singapore

51 Newton Road

Phone: +39-024-550-8701

District, Shenzhen, China, 518057 Fax: +39-028-928-6009

#19-01/05 Goldhill Plaza

Singapore, 308900

Phone: +65-6358-2160

Fax: +65-6358-2015

e-mail: singaporesales@power.com

Phone: +86-755-8672-8689

Fax: +86-755-8672-8690

e-mail: eurosales@power.com

e-mail: chinasales@power.com

20

Rev. G 08/16

www.power.com


型号：	TOP222YNTL
厂家：	Power Integrations
描述：	Three-Terminal Off-Line PWM Switch
文件：	总20页 (文件大小：1537K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TOP222YNTL [POWERINT]

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