3291-00 [PSEMI]
1200 MHz / 550 MHz Dual Fractional-N FlexiPower? PLL for Frequency Synthesis; 1200兆赫/ 550 MHz双通道小数N分FlexiPower ？锁相环频率合成
| 型号： | 3291-00 |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | 1200 MHz / 550 MHz Dual Fractional-N FlexiPower? PLL for Frequency Synthesis |
| 文件： | 总15页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specification
PE3291
1200 MHz / 550 MHz Dual
Fractional-N FlexiPower™ PLL
for Frequency Synthesis
Product Description
TM
The PE3291 is a dual fractional-N FlexiPower phase-lock loop
(PLL) IC designed for frequency synthesis. Each PLL includes
Features
TM
a FlexiPower prescaler, phase detector, charge pump and on-
• Ultra-Low Power via FlexiPower
board fractional spur compensation.
variable supply voltages
The FlexiPowerprescalers are supplied power on dedicated
pins and can operate at a substantial power savings at
voltages as low as 0.8 volts, while allowing a 3 volt charge
pump supply. For 3 volt only systems, on-chip voltage
regulation may be used to generate the prescaler power
supplies.
• Modulo-32 fractional-N main counters
• On-board fractional spur compensation:
No tuning required, stable over
temperature
• Improved phase noise compared to
integer-N architectures
Figure 1 illustrates the implementation of the FlexiPower
technology. The prescaler power supply may be provided
externally or internally regulated down from VDD. In a typical
950 MHz application the total current consumed by the PLL is
2.1 mA. Operation at reduced current levels provides
significant battery life extension. The PE3291 allows the
system designer to minimize power consumption by controlling
the voltage on the prescaler. For additional operating speeds
and current consumptions refer to Figures 5 and 6.
Applications
• CDMA handsets
• CDMA base stations
• Analog Cordless phones
• One and two way pagers
PE3291 provides fractional-N division with power-of-two
denominator values up to 32. This allows comparison
frequencies up to 32 times the channel spacing, providing a
lower phase noise floor than integer PLLs. The 32/33 RF
prescaler (PLL1) operates up to 1200 MHz and the 16/17 IF
prescaler (PLL2) operates up to 550 MHz.
Figure 1: FlexiPower technology enables
the prescaler to operate at voltages down to
0.8 volts. This significantly reduces the total
power.
To Loop Filter
3 Volts
0.8 3 Volts
Regulator
The PE3291 Phase Locked-Loop is manufactured on
Peregrine’s UltraCMOS™ process, a patented variation of
silicon-on-insulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy and
integration of conventional CMOS.
Phase Comparator
and
Charge pump
Ref.
Input
Prescaler
Low
Speed Counters
PE3291
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15
PE3291
Product Specification
Figure 2. Pin Configurations (Top View)
Figure 3. Package Type
20-lead TSSOP
N/C
VDD
1
2
3
4
5
6
7
8
9
20 VDD
19 VDD
18 CP2
17 GND
16 fin2
CP1
GND
fin1
Dec1
15 Dec2
VDD
1
fr
14 VDD2
13 LE
GND
12 Data
11 Clock
foLD 10
Table 1. Pin Descriptions
Pin No.
Pin Name
Type
Description
1
2
N / C
No connect.
Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed
as close as possible to this pin and be connected directly to the ground plane.
VDD
(Note 1)
Output
Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external
VCO.
3
CP1
4
5
GND
fin1
Ground.
Input
Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.2 GHz.
Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and
be connected directly to the ground plane.
6
Dec1
7
8
9
VDD1
fr
PLL1 prescaler power supply (FlexiPower 1).
Reference frequency input.
Ground.
Input
GND
Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and
data out of the shift register. CMOS output (see Table 11, foLD Programming Truth Table).
10
foLD
Output
CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift
register.
11
12
13
14
15
Clock
Data
LE
Input
Input
Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits.
Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded
into one of the four appropriate latches (as assigned by the control bits).
Input
VDD2
Dec2
Output
Output
Input
PLL2 prescaler power supply (FlexiPower 2).
Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and
be connected directly to the ground plane.
16
17
Fin2
Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550 MHz.
Ground.
GND
Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external
VCO.
18
CP2
Output
19
20
VDD
VDD
(Note 1)
(Note 1)
Same as pin 2.
Same as pin 2.
Note 1: VDD pins 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions
Page 2 of 15
PE3291
Product Specification
PE3291 Description
FlexiPower Operation
The PE3291 is intended for such applications as
the local oscillator for the RF and first IF of dual-
conversion transceivers. The RF PLL (PLL1)
includes a 32/33 prescaler with a 1200 MHz
maximum frequency of operation, where the IF
PLL (PLL2) incorporates a 16/17 prescaler with a
550 MHz maximum frequency of operation. Using
an advanced fractional-N phase-locked loop
technique, the PE3291 can generate a stable,
very low phase-noise signal. The dual fractional
architecture allows fine resolution in both PLLs,
with no degradation in phase noise performance.
Each FlexiPower PLL prescaler can be supplied
its own dedicated supply voltage as low as 0.8
volts for substantial power savings. The maximum
frequency of operation scales with the FlexiPower
supply voltage. If voltages less than VDD are not
available, the FlexiPower supplies can be
internally generated, but the power savings will
not be as great as when using external
FlexiPower supplies.
Spurious Response
A critical parameter for synthesizer designs is
spurious output. Spurs occur at the integer
multiples of the step size away from center tone.
An important feature of fractional synthesizers is
their ability to reduce these spurious sidebands.
The PE3291 has a built-in method for reducing
these spurs, with no external components or
tuning required. In addition, this circuitry works
over the full commercial temperature range.
Data is transferred into the PE3291 via a three-
wire interface (Data, Clock, LE). Supply voltage
can range from 2.7 to 3.3 volts for VDD and from
0.8 to 3.3 volts for the FlexiPower supply. PE3291
features very low power consumption and is
available in a 20-lead TSSOP (JEDEC MO-153-
AC) package.
Figure 4. PE3291 Block Diagram
32/33
Prescaler
19-bit Fractional-N
Main Divider
Fractional Spur
Compensation
fin1
Ref.
Amp.
9-bit Reference
Divider
Phase
Charge
Pump
CP1
foLD
CP2
fr
Detector
Clock
Data
LE
21-bit Serial Control
Interface
Multiplexer
9-bit Reference
Divider
Phase
Detector
Charge
Pump
Fractional Spur
Compensation
16/17
Prescaler
18-bit Fractional-N
Main Divider
fin2
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 15
PE3291
Product Specification
Table 2. Absolute Maximum Ratings
Table 3. Operating Ratings
Symbol
Parameter/Conditions Min Max Units
Symbol
Parameter/Conditions Min Max Units
VDD
VI
Supply voltage
-0.3
-0.3
4.0
V
V
VDD
Supply voltage
2.7
3.3
V
Voltage on any input
VDD
+ 0.3
TA
Operating ambient
-40
85
°C
II
DC into any input
DC into any output
-10
-10
-65
+10
+10
150
mA
mA
°C
Table 4. ESD Ratings
IO
Tstg
Storage temperature
range
Symbol
Parameter/Conditions
Level Units
VESD
ESD voltage human body model
1000
V
Absolute Maximum Ratings are those values listed in
the above table. Exceeding these values may cause
permanent device damage. Functional operation
should be restricted to the limits in the DC and AC
Characteristics table. Exposure to absolute maximum
ratings for extended periods may affect device
reliability.
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IDD
3 V supply current when VDD1
and VDD2 are internally
regulated down from VDD
(10 MHz Ref. Freq.)
P2, P1 = 01 RF
RF PLL1 low speed
1.4
2.0
2.1
2.7
3.1
mA
mA
mA
mA
mA
(note 1)
P2, P1 = 1X
C10, C20 = 01
P2, P1 = 01
C10, C20 = 00
P2, P1 = 10
C10, C20 = 00
P2, P1 = 11
C10, C20 = 00
P2, P1 = 00
RF PLL1 high speed
IF PLL2 off
RF PLL1 low speed
IF PLL2 low speed
RF PLL1 high speed
IF PLL2 low speed
RF PLL1 high speed
IF PLL2 high speed
2 PLL’s enabled
IDD
3 V supply current when VDD1
and VDD2 are externally
supplied (note 1)
1.0
0.7
mA
mA
1 PLL enabled
IDD1
PLL1 FlexiPower Prescaler
supply current (see fig. 5)
P2, P1 = 00
PLL1 enabled
PLL2 enabled
VDD1 = 1/0 volt
VDD1 = 1.8 volts
VDD1 = 2.7 volts
0.5
1.5
4.0
mA
mA
mA
IDD2
PLL2 FlexiPower Prescaler
supply current (see fig. 5)
P2, P1 = 00
VDD2 = 1.0 volt
VDD2 = 1.8 volts
VDD2 = 2.7 volts
0.4
1.2
2.0
5
mA
mA
mA
mA
Istby
Total standby current
50
Digital inputs: Clock, Data, LE
VIH
VIL
IIH
High level input voltage
VDD = 2.7 to 3.3 volts
VDD = 2.7 to 3.3 volts
VIH = VDD = 3.3 volts
0.7 x VDD
V
V
Low level input voltage
High level input current
Low level input current
0.3 x VDD
-1
-1
+1
+1
mA
IIL
VIL = 0, VDD = 3.3 volts
mA
Note 1: The total current consumed by the device is IDD when internal regulation is employed and IDD + IDD1 + IDD2 when VDD1 and VDD2 are
externally supplied. When VDD1 and VDD2 are internally generated, pins 7 and 14 should be left floating.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions
Page 4 of 15
PE3291
Product Specification
Table 5. DC Characteristics (continued): VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Reference Divider input: fr
IIHR
IILR
Digital output: foLD
Input current
VIH = VDD = 3.6 volts
+25
mA
mA
Input current
VIL = 0, VDD = 3.6 volts
-25
VOLD
VOHD
Output voltage LOW
Output voltage HIGH
Iout = 1 mA
Iout = -1 mA
V
V
VDD-0.4
Charge Pump outputs: CP1, CP2
ICP - Source
-70
70
mA
mA
nA
Drive current
ICP - Sink
VCP = VDD / 2
ICPL
ICP – Source
vs.
Leakage current
0.5 V < VCP < VDD-0.5 volt
-5
5
Sink vs. Source mismatch
VCP = VDD / 2, TA = 25° C
VCP = VDD / 2
10
%
ICP vs. TA
Output current vs. temperature
10
10
%
%
ICP vs. VCP
Output current magnitude variation vs.
voltage
0.5 V < VCP < VDD – 0.5
volt, TA = 25° C
Figure 5. Prescaler Current vs. FlexiPower Voltage (VDD1 and VDD2 externally supplied)
4.00
PLL1
PLL2
3.00
2.00
1.00
0.00
0.8
1.2 1.6
2
2.4 2.8 3.
FlexiPower voltage (VDD1, VDD2
)
Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
Control Interface and Latches (see figure 8)
fClk
tClockH
tClockL
tDSU
Serial data clock frequency
10
MHz
ns
Serial clock HIGH time
50
50
50
10
50
50
50
Serial clock LOW time
ns
Data set-up time to Clock rising edge
Data hold time after Clock rising edge
LE pulse width
ns
tDHLD
tLEW
ns
ns
tCLE
Clock falling edge to LE rising edge
LE falling edge to Clock rising edge
Data Out delay after Clock falling edge (foLD pin)
ns
tLEC
ns
tData Out
CL = 50 pf
90
ns
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Page 5 of 15
PE3291
Product Specification
Table 6. AC Characteristics (continued): VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
Main Divider (Including Prescaler)
fin1
Operating frequency (see figure 6)
P2, P1 = 00
VDD1 = 1.0 volts
VDD1 = 1.8 volts
VDD1 = 2.7 volts
300
300
300
450
900
MHz
MHz
MHz
1200
P2, P1 = 01
V
DD1 = internally generated (low speed)
300
300
800
MHz
MHz
P2, P1 = 1X = (10 or 11)
VDD1 = internally generated (high speed)
1100
fin2
Operating frequency (see figure 6)
P2, P1 = 00
V
V
V
DD1 = 1.0 volts
45
45
45
300
550
550
MHz
MHz
MHz
DD1 = 1.8 volts
DD1 = 2.7 volts
P2, P1 = 01 or 10
DD2 = internally generated (low speed)
V
45
300
MHz
P2, P1 = 11
VDD1 = internally generated (high speed)
45
550
MHz
Pfin1
Input level range
External AC coupling
External AC coupling
-10
-10
5
5
dBm
dBm
MHz
Pfin2
Input level range
fc
Comparison frequency
10
Reference Divider
fr
Operating frequency
Input sensitivity
50
MHz
VP-P
Vfr
External AC coupling (note 1)
0.5
Note 1: CMOS logic levels may be used if DC coupled
Figure 6. PLL Maximum Frequency vs. FlexiPower Voltage
1400
PLL1
1200
1000
800
600
PLL2
400
200
2.4
FlexiPower voltage (VDD1 ,VDD2
0.8 1.2 1.6
2
2.8 3.2
)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions
Page 6 of 15
PE3291
Product Specification
Functional Description
the reference frequency fr by the following
equation:
The Functional Block Diagram in Figure 7 shows a
21-bit serial control register, a multiplexed output,
and PLL sections PLL1 and PLL2. Each PLL
contains a fractional-N main counter chain, a
reference counter, a phase detector, and an
internal charge pump with on-chip fractional spur
compensation. Each fractional-N main counter
chain includes an internal dual modulus prescaler,
supporting counters, and a fractional accumulator.
fin1 = [(32 x M1) + A1 + (F1/32)] x (fr/R1)
(1) Note that A1 must be less than M1. Also, fin1
must be greater than or equal to 1024 x (fr/R1) to
obtain contiguous channels.
The PLL2 (IF) VCO frequency fin2 is related to the
reference frequency fr by the following equation:
Serial input data is clocked on the rising edge of
Clock, MSB first. The last two bits are the address
bits that determine the register address. Data is
transferred into the counters as shown in Table 8,
PE3291 Register Set. If the foLD pin is configured
as data out, then the contents of shift register bit
S20 are clocked on the falling edge of Clock onto
the foLD pin. This feature allows the PE3291 and
compatible devices to be connected in a daisy-
chain configuration.
fin2 = [(16 x M2) + A2 + (F2/32)] x (fr/R2)
(2) Note that A2 must be less than M2. Also, fin2
must be greater than or equal to 256 x (fr/R2) to
obtain contiguous channels.
F1 sets PLL1 fractionality. If F1 is an even number,
the PE3291 automatically reduces the fraction.
For example, if F1 = 12, then the fraction 12/32 is
automatically reduced to 3/8. In this way,
fractional denominators of 2, 4, 8, 16 and 32 are
available. F2 sets the fractionality for PLL2 in the
same manner.
The PLL1 (RF) VCO frequency fin1 is related to
Figure 7. Functional Block Diagram
A1
5
A1 Counter
0<A1<31
Prescaler
Control Logic
P1
P2
M1
9
F1
5
32/33
M
1 Counter
F
1 Counter
Fractional Spur
Compensation
fin1
Prescaler
3<M1<511
0<F1<31
Ref.
9-bit Reference
Divider
Phase
Charge
Pump
CP1
foLD
CP2
fr
Amp.
Detector
R1
9
C11
C12
C22
C22
Clock
Data
LE
21-bit Serial Control
Interface
Multiplexer
C22
C22
R2
9
C21
C22
9-bit Reference
Divider
Phase
Detector
Charge
Pump
16/17
M2 Counter
3<M2<511
F2 Counter
0<F2<31
Fractional Spur
Compensation
fin2
Prescaler
M2
9
F2
5
P1
P2
A2 Counter
0<A2<15
Prescaler
Control Logic
A2
4
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Page 7 of 15
PE3291
Product Specification
Table 7. Register Set
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Test
0
PLL2 Synthesizer control
C23 C22 C21
PLL2 Reference counter R2 divide ratio
R 26 R 25 R 24 R 23 R 22
Address
0 0
Reserved
C24
C20
R28
R 27
R 21
R 20
PLL2 Swallow counter A2
divide ratio
PLL2 Fractional counter F2
numerator value
PLL2 Main counter M2 divide ratio
M26 M25 M24 M23 M22
Address
Res.
M28
M27
M21
M20
C10
A14
A23
A22
A21
A20
F24
F23
F22
F21
F20
0
1
FlexiPower voltage
regulation
PLL1 Synthesizer control
C13 C12 C11
PLL1 Reference counter R1 divide ratio
R16 R15 R14 R13 R12
Address
Res.
P2
P1
C14
R18
R17
R11
R10
1
0
Res.
PLL1 Swallow counter A1
divide ratio
PLL1 Fractional counter F1
numerator value
PLL1 Main counter M1 divide ratio
M16 M15 M14 M13 M12
Address
M18
M17
M11
M10
A13
A12
A11
A10
F14
F13
F12
F11
F10
1
1
MSB (first in)
(last in) LSB
Figure 8. Serial Interface Mode Timing Diagram
Data
tDSU
tDHLD
tClockL
tClockH
Clock
LE
tCLE
tLEW
tLEC
tData Out
Data Out
(foLD pin)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions
Page 8 of 15
PE3291
Product Specification
Programmable Divide Values
(R1, R2, F1, F2, A1, A2, M1, M2)
Table 8. PE3291 Counter Programming Example
Divide Value
MSB
LSB Address
Data is clocked into the 21-bit shift register, MSB
first. When LE is asserted HIGH, data is latched
into the registers addressed by the last two bits
shifted into the 21-bit register, according to Table
7. For example, to program the PLL1 (RF)
swallow counter, A1, the last two bits shifted into
the register (S0, S1) would be (1,1). The 5-bit A1
counter would then be programmed according to
Table 8. For normal operation, S16 of address
(0,0) (the Test bit) must be programmed to 0 even
if PLL2 (IF) is not used.
S11
A14
0
S10
A13
0
S9
A12
0
S8
A11
0
S7
A10
0
S1
1
S0
1
0
1
1
1
0
0
0
0
1
1
1
2
0
0
0
1
0
1
1
-
-
-
-
-
-
1
1
31
1
1
1
1
1
1
1
Program Modes
Several modes of operation can be programmed with bits C10 - C14 and C20 - C24, including the phase detector
polarity, charge pump high impedance, output of the foLD pin and power-down modes. The PE3291 modes of
operation are shown on Table 9. The truth table for the foLD output is shown in Table 10.
Table 9. PE3291 Program Modes
S15
S14
S13
S12
S11
S1
S0
C24
C23
C22
C21 (Note 2)
C20 (Note 1)
0 = PLL2 on
0
0
See Table 10
See Table 10
0 = PLL2 CP normal
0 = PLL2 Phase Detector inverted
1 = PLL2 CP High Z
C12
1 = PLL2 Phase Detector normal
C11 (Note 2)
1 = PLL2 off
C10 (Note 1)
C14
C13
1
0
See Table 10
See Table 10
0 = PLL1 CP normal
1 = PLL1 CP High Z
0 = PLL1 Phase Detector inverted
1 = PLL1 Phase Detector normal
0 = PLL1 on
1 = PLL1 off
Note 1: The PLL1 power-down mode disables all of PLL1’s components except the R1 counter and the reference frequency input buffer, with
CP1 (pin 3) and fin1 (pin 5) becoming high impedance. The power down of PLL2 has similar results with CP2 (pin 18) and fin2 (pin 16)
becoming high impedance. Power down of both PLL1 and PLL2 further disables counters R1 and R2, the reference frequency input, and
the foLD output, causing fr (pin 8) and foLD (pin 10) to become high impedance. The Serial Control Interface remains active at all times.
Note 2: The C11 and C21 bits should be set according to the voltage versus frequency slope of the VCO as shown in Figure 9. This relationship
presumes the use of a passive loop filter. If an inverting active loop filter is used the relationship is also inverted.
Figure 9. VCO Characteristics
(1) Positive slope VCO
•
•
•
•
When VCO1 (RF) slope is positive like (1), C11 should be set HIGH.
When VCO1 (RF) slope is negative like (2), C11 should be set LOW.
When VCO2 (IF) slope is positive like (1), C21 should be set HIGH.
When VCO2 (IF) slope is negative like (2), C21 should be set LOW.
VCO
Output
Frequency
(2) Negative slope VCO
VCO Input voltage
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Page 9 of 15
PE3291
Product Specification
Table 10. foLD Programming Truth Table
X = don’t care condition
foLD
C14
C13
C24
C23
Output State
(PLL1F0)
(PLL1LD)
(PLL2F0)
(PLL2LD)
Disabled1
0
0
0
0
1
0
1
0
1
1
1
1
0
1
0
1
X
X
X
X
0
0
1
1
0
0
0
0
0
1
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
PLL 1 Lock detect2 (LD1)
PLL2 Lock detect2 (LD2)
PLL1 / PLL2 Lock detect2
PLL1 Reference divider output (fc1)
PLL2 Reference divider output (fc2)
PLL1 Programmable divider output (fp1)
PLL2 Programmable divider output (fp2)
Serial data out
Reserved
Reserved
Counter reset3
Note: 1. When the foLD is disabled the output is a CMOS LOW.
2. Lock detect indicates when the VCO frequency is in “lock”. When PLL1 is in lock and PLL1 lock detect is selected, the foLD pin will be HIGH
with narrow pulses LOW. When PLL2 is in lock and PLL2 lock detect is selected, the foLD pin will be HIGH with narrow pulses LOW. When
PLL1 / PLL2 lock detect is selected the foLD pin will be HIGH with narrow pulses LOW only when both PLL1 and PLL2 are in lock.
3. The counter reset state when activated resets all counters. Upon removal of the reset, counters M, A, and F resume counting in close
alignment with the R counter (the maximum error is one prescaler cycle). The reset bits can be activated to allow smooth acquisition upon
powering up.
Programming the FlexiPower voltage
The PE3291 can be programmed to internally regulate down from the VDD
voltage to supply the FlexiPower voltage, as shown in Table 11. This is
implemented by programming P2, P1 (S18 & S16 - address 1,0). When
programmed with 0,0 external voltage supplies must be provided to the
part at pins VDD1 and VDD2. When using internal regulation, the FlexiPower
supply pins should be left grounded.
Table 11. FlexiPower Voltage Regulation Programming
FlexiPower 1 voltage
(RF PLL1)
FlexiPower 2 voltage
(IF PLL2)
P2 P1
0
0
1
1
0
1
0
1
No regulation (FlexiPower externally provided)
Low power
High speed
High speed
Low power
Low power
High speed
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions
Page 10 of 15
PE3291
Product Specification
Phase Comparator Characteristics
PLL1 has the timing relationships shown below for fc1, fp1, LD1, UP1, and DOWN1. When C11 = HIGH, UP1
directs the internal PLL1 charge pump to source current and DOWN1 directs the PLL1 internal charge pump
to sink current. If C11 = LOW, UP1 and DOWN1 are interchanged.
PLL2 has the timing relationships shown below for fc2, fp2, LD2, UP2, and DOWN2. When C21 = HIGH, UP2
directs the internal PLL2 charge pump to source current and DOWN2 directs the PLL2 internal charge pump
to sink current. If C21 = LOW, UP2 and DOWN2 are interchanged.
Figure 10. Phase Comparator Timing Diagram
fc1 (2)
(Note 1)
fp1 (2)
(Note 1)
LD1 (2)
(Note 1)
UP1 (2)
DOWN1 (2)
fc leads fp
fc = fp
fc lags fp
fc lags fp
fc lags fp
Note 1: fc1(2), fp1(2), and LD1(2) are accessible via the foLD pin per programming in Table 11.
Document No. 70-0009-04 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 15
PE3291
Product Specification
Loop Filter
Digital Control Lines
Second/Third Order Loops
Control Line Noise
Choosing the optimum loop filter for a design
encompasses many trade offs. The rule of thumb
for choosing the loop filter bandwidth is 10 percent
of the step size. A second order loop (C1 C2 R2
and C4 C5 R5 in Figure 11 omitting C3 R3 C6 and
R6) will provide the least amount of components
and the fastest lock times. If lock time is an issue,
one might try opening up the loop filter, although if
it is too wide, instability will dominate and worsen
lock time. If lock time is not an issue, a narrower
second order filter will minimize residual FM
without requiring additional components.
We have noticed frequency jitter during
programming when a low impedance, such as a
capacitor to ground, is placed next to any control
line pin (clock, data, and load enable). The use of
a 51 k ohm resistor in series with the control line
will eliminate the problem with no effect to
programming time.
Enable Line Voltage
The PE329x series PLLs use a level sensitive
load enable. Therefore the digital controller must
provide an active low to the part at all times
except when the data is to be loaded into the shift
register. If the PLL controller does not hold the
voltage low, a high impedance resistor to ground
should be added to the enable line to ensure
stable operation.
Third Order loop filters (C1 C2 R2 C3 R3 and C4 C5
R5 C6 R6 in Figure 11) provide a good
compromise between lock time and residual FM.
We have found using a third order loop with 20 dB
of rejection at the step size will halve the Residual
FM as measured with a similar second order loop,
with minimum effect on lock time.
5 Volt Operation:
The PE329x series PLLs are not capable of
accepting control voltages greater than 3.3 volts.
Interface to 5 volt controllers requires the addition
of resistor dividers to comply with the 3.3 volt
maximum operation voltage.
Loop Filter Bandwidth Design Considerations
As part of the spur compensation circuitry, the
PE329x series PLLs contain capacitors to ground
internal to the charge pump. PLL1 contains a 50
pF capacitor and PLL2 contains a 100 pF
capacitor. To ensure accurate loop filter
calculations, it is critical that the calculated value
of the first shunt capacitor (C1 & C4 in Figure 11)
be at least 100 pF for PLL1 and 200 pF for PLL2.
With this requirement satisfied, the remaining loop
components can be calculated.
For a stable loop, it is also important that the loop
bandwidth be less than or equal to one tenth of
the step size.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions
Page 12 of 15
PE3291
Product Specification
Figure 11. Application Example
Note 1: For optimum fractional spur and lock-time performance C2 and C5 should be polyester (or poly
propylene). In addition, the loop filter components must be free from contamination. Contamination
will result in poor spur performance. For accurate loop bandwidth, C1 must be greater than or equal to
100 pF, and C4 must be greater than or equal to 200 pF.
Document No. 70-0009-04 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 13 of 15
PE3291
Product Specification
Figure 12. Package Drawing
20-lead TSSOP (JEDEC MO-153-AC)
12o REF
0.20
R 0.90 MIN
TOP VIEW
0.65BSC
R 0.90 MIN
GAGE
PLANE
20 19
18
17
16 15
14 13 12
11
0o
8o
12o REF
0.25
+.15
0.60
-.10
1.0 REF
3.20
2X
4.40±0.10
Ø1.00±0.10
1.00
- B -
.20
C
B
A
1
2
3
4
5
6
7
8
9
10
1.00
6.40
0.325
SIDE VIEW
S
Y
M
B
O
L
- A -
COMMON DIMENSION(MILLIMETERS)
6.50±0.10
0.90±0.05
0.10±0.05
0.65mm LEAD PITCH
MIN
---
NOM
---
---
0.90
0.60
---
---
---
0.22
---
---
MAX
1.10
0.15
0.95
0.75
---
1.10 MAX
A
A1
A2
L
R
R1
b
b1
c
c1
01
L1
aaa
bbb
ccc
ddd
e
02
03
- C -
0.05
0.85
0.50
0.09
0.09
0.19
0.19
0.09
0.09
0°
0.10
C
0.30 MAX
0.10
C B A
FRONT VIEW
---
S
0.30
0.25
0.20
0.16
8°
Y
M
B
O
L
N
O
T
AC
E
MIN
6.40
4.30
NOM
6.50
4.40
6.4 BSC
0.65 BSC
20
MAX
6.60
4.50
---
3,8
4,8
D
1.0 REF
0.10
0.10
0.05
0.20
0.65 BSC
12° REF
12° REF
E1
E
e
N
6
1,2
A
NOTE
ISSUE
Table 12. Ordering Information
Order Code
3291-11
Part Marking
PE3291
Description
Package
Shipping Method
PE3291-20TSSOP-74A
PE3291-20TSSOP-2000C
PE3291-20TSSOP-Eval Kit
20-lead TSSOP
20-lead TSSOP
Evaluation Kit
74 units / Tube
3291-12
PE3291
2000 unit / T&R
1 / Box
3291-00
PE3291EK
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions
Page 14 of 15
PE3291
Product Specification
Sales Offices
The Americas
North Asia Pacific
Peregrine Semiconductor Corporation
Peregrine Semiconductor K.K.
9450 Carroll Park Drive
San Diego, CA 92121
Tel 858-731-9400
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax 858-731-9499
Fax: +81-3-3502-5213
Europe
Peregrine Semiconductor, Korea
#B-2402, Kolon Tripolis, #210
Geumgok-dong, Bundang-gu, Seongnam-si,
Gyeonggi-do, 463-480 S. Korea
Tel: +82-31-728-4300
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: +33-1-47-41-91-73
Fax : +33-1-47-41-91-73
Fax: +82-31-728-4305
South Asia Pacific
Space and Defense Products
Peregrine Semiconductor, China
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Americas:
Tel: 505-881-0438
Fax: 505-881-0443
Fax: +86-21-5836-7652
Europe, Asia Pacific:
180 Rue Jean de Guiramand
13852 Aix-En-Provence cedex 3, France
Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS and HaRP are trademarks of Peregrine
Semiconductor Corp.
Document No. 70-0009-04 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 15 of 15
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