3339-00 [PSEMI]
3.0 GHz Integer-N PLL for Low Phase Noise Applications; 3.0 GHz的整数N分频PLL的低相位噪声应用型号: | 3339-00 |
厂家: | Peregrine Semiconductor |
描述: | 3.0 GHz Integer-N PLL for Low Phase Noise Applications |
文件: | 总12页 (文件大小:143K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRODUCT SPECIFICATION
PE3339
3.0 GHz Integer-N PLL for Low
Phase Noise Applications
Product Description
Peregrine’s PE3339 is a high performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The
superior phase noise performance of the PE3339 makes
it ideal for applications such as wireless local loop
basestations, LMDS systems and other demanding
terrestrial systems.
Features
• 3.0 GHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector with
charge pump
• Serial programmable
• Low power ⎯ 23 mA at 3 V
• Ultra-low phase noise
The PE3339 features a 10/11 dual modulus prescaler,
counters, phase detector and a charge pump as shown
in Figure 1. Counter values are programmable through a
three wire serial interface.
• Available in 20-lead TSSOP
Fabricated in Peregrine’s patented UTSi® (Ultra Thin
Silicon) CMOS technology, the PE3339 offers excellent
RF performance with the economy and integration of
conventional CMOS.
Figure 1. Block Diagram
Fin
Fin
Prescaler
10/11
Main
Counter
13
Primary
20-bit
Latch
Secon-
dary
20-bit
Latch
PD_U
Charge
Pump
Phase
Detector
20
20
20
CP
Sdata
PD_D
6
6
fr
R Counter
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PE3339
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Figure 2. Pin Configuration
1
20
19
18
17
16
15
14
13
12
11
VDD
fr
2
Enh
GND
N/C
CP
3
S_WR
4
Sdata
5
Sclk
VDD
Dout
LD
6
GND
7
FSELS
8
E_WR
Cext
GND
9
VDD
10
Fin
Fin
Table 1. Pin Descriptions
Pin No.
Pin Name
Type
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
1
VDD
(Note 1)
Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 kΩ pull-up
resistor.
2
Enh
Input
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are
transferred to the secondary register on S_WR rising edge.
3
4
5
6
7
S_WR
Sdata
Sclk
Input
Input
Input
Binary serial data input. Input data entered MSB first.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit
enhancement register (E_WR “high”) on the rising edge of Sclk.
GND
Ground.
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal
counters. Internal 70 kΩ pull-down resistor.
FSELS
Input
Input
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement
register on the rising edge of Sclk. Internal 70 kΩ pull-down resistor.
8
E_WR
9
VDD
Fin
(Note 1)
Input
Same as pin 1.
10
Prescaler input from the VCO. Max frequency input is 3.0 GHz.
Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be
connected in series with a 50 Ω resistor to the ground plane.
11
12
13
Fin
Input
GND
Cext
Ground.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to an
external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
Output
Output,
OD
Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance,
otherwise LD is a logic low (“0”).
14
LD
15
16
Dout
VDD
Output
Data out function, Dout, enabled in enhancement mode.
Same as pin 1.
(Note 1)
File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS
Copyright © Peregrine Semiconductor Corp. 2004
Page 2 of 12
PE3339
Advance Information
Pin No.
Pin Name
Type
Output
Output
Description
17
18
19
20
CP
NC
GND
fr
Charge pump current is sourced when fc leads fp and sinked when fc lags fp.
No connection.
Ground.
Input
Reference frequency input.
Note 1: VDD pins 1, 9, and 16 are connected by diodes and must be supplied with the same positive voltage level.
Table 2. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 4.
Symbol
Parameter/Conditions Min Max Units
VDD
VI
Supply voltage
-0.3
-0.3
4.0
V
V
Voltage on any input
VDD
+ 0.3
II
DC into any input
DC into any output
-10
-10
-65
+10
+10
150
mA
mA
°C
IO
Tstg
Storage temperature
range
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
Table 3. Operating Ratings
Symbol
Parameter/Conditions Min Max Units
VDD
TA
Supply voltage
2.85
-40
3.15
85
V
Operating ambient
temperature range
°C
Table 4. ESD Ratings
Symbol
Parameter/Conditions
Level Units
1000
VESD
ESD voltage human body
model (Note 1)
V
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
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PE3339
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Table 5. DC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Operational supply current;
Prescaler enabled
Digital Inputs: S_WR, Sdata, Sclk
Conditions
Min
Typ
Max
Units
IDD
VDD = 2.85 to 3.15 V
23
35
mA
VIH
VIL
IIH
High level input voltage
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
0.7 x VDD
V
V
Low level input voltage
High level input current
Low level input current
0.3 x VDD
+1
µA
µA
IIL
-1
Digital Inputs: Enh (contains a 70 kΩ pull-up resistor)
VIH
VIL
IIH
High level input voltage
Low level input voltage
High level input current
Low level input current
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
0.7 x VDD
V
V
0.3 x VDD
+1
µA
µA
IIL
-100
Digital Inputs: FSELS, E_WR (contains a 70 kΩ pull-down resistor)
VIH
VIL
IIH
High level input voltage
Low level input voltage
High level input current
Low level input current
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
0.7 x VDD
V
V
0.3 x VDD
+100
µA
µA
IIL
-1
Reference Divider input: fr
IIHR High level input current
IILR Low level input current
Counter output: Dout
VIH = VDD = 3.15 V
+100
0.4
µA
µA
VIL = 0, VDD = 3.15 V
-100
VOLD
VOHD
Output voltage LOW
Output voltage HIGH
Iout = 6 mA
Iout = -3 mA
V
V
VDD - 0.4
VDD - 0.4
Lock detect outputs: (Cext, LD)
VOLC
VOHC
VOLLD
Output voltage LOW, Cext
Iout = 0.1 mA
Iout = -0.1 mA
Iout = 1 mA
0.4
0.4
V
V
V
Output voltage HIGH, Cext
Output voltage LOW, LD
Charge Pump output: CP
ICP – Source
ICP – Sink
ICPL
Drive current
VCP = VDD / 2
-2.6
1.4
-1
-2
2
-1.4
2.6
1
mA
mA
µA
%
Drive current
VCP = VDD / 2
Leakage current
1.0 V < VCP < VDD – 1.0 V
ICP – Source
VS. ICP Sink
Sink vs. source mismatch
15
VCP = VDD / 2, TA = 25° C
ICP VS. VCP
Output current magnitude variation vs. voltage
1.0 V < VCP < VDD – 1.0 V TA
15
%
= 25° C
File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS
Copyright © Peregrine Semiconductor Corp. 2004
Page 4 of 12
PE3339
Advance Information
Table 6. AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
Control Interface and Latches (see Figures 3, 4, 5)
fClk
tClkH
tClkL
tDSU
tDHLD
tPW
Serial data clock frequency
(Note 1)
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial clock HIGH time
30
30
10
10
30
30
30
30
30
Serial clock LOW time
Sdata set-up time to Sclk rising edge
Sdata hold time after Sclk rising edge
S_WR pulse width
tCWR
tCE
tWRC
tEC
Sclk rising edge to S_WR rising edge
Sclk falling edge to E_WR transition
S_WR falling edge to Sclk rising edge
E_WR transition to Sclk rising edge
Main Divider (Including Prescaler)
Fin
Operating frequency
Input level range
500
-5
3000
5
MHz
dBm
PFin
External AC coupling
External AC coupling
Main Divider (Prescaler Bypassed)
Fin
Operating frequency
Input level range
50
-5
300
5
MHz
dBm
PFin
Reference Divider
fr
Operating frequency
(Note 3)
100
20
MHz
dBm
Pfr
Reference input power (Note 2)
Single ended input
-2
Phase Detector
fc
Comparison frequency
(Note 3)
MHz
SSB Phase Noise (Fin = 1.3 GHz, fr = 10 MHz, fc = 1.25 MHz, LBW = 70 kHz, VDD = 3.0 V, Temp = -40° C)
100 Hz Offset
1 kHz Offset
-75
-85
dBc/Hz
dBc/Hz
Note 1: fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk
specification.
Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase
noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Note 3: Parameter is guaranteed through characterization only and is not tested.
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Functional Description
The PE3339 consists of a prescaler, counters, a
phase detector, charge pump and control logic .
The dual modulus prescaler divides the VCO
frequency by either 10 or 11, depending on the
value of the modulus select. Counters “R” and “M”
divide the reference and prescaler output,
respectively, by integer values stored in a 20-bit
register. An additional counter (“A”) is used in the
modulus select logic.
The phase-frequency detector generates up and
down frequency control signals which direct the
charge pump operation. The control logic includes a
selectable chip interface. Data is written into the
internal registers via the three wire serial bus.
There are also various operational and test modes
and a lock detect output.
Figure 3. Functional Block Diagram
R Counter
(6-bit)
fr
fc
PD_U
R(5:0)
M(8:0)
A(3:0)
Sdata
Phase
Detector
Control
Logic
Charge
Pump
CP
PD_D
Control
Pins
LD
Cext
Modulus
Select
Fin
Fin
10/11
Prescaler
M Counter
(9-bit)
fp
File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS
Copyright © Peregrine Semiconductor Corp. 2004
Page 6 of 12
PE3339
Advance Information
Main Counter Chain
Note that programming R with “0” will pass the
reference frequency (fr) directly to the phase
detector.
Normal Operating Mode
Setting the Pre_en control bit “low” enables the
÷10/11 prescaler. The main counter chain then
divides the RF input frequency (Fin) by an integer
derived from the values in the “M” and “A” counters.
Register Programming
Serial Interface Mode
In this mode, the output from the main counter
chain (fp) is related to the VCO frequency (Fin) by
the following equation:
While the E_WR input is “low” and the S_WR input
is “low”, serial input data (Sdata input), B0 to B19,
are clocked serially into the primary register on the
rising edge of Sclk, MSB (B0) first. The contents
from the primary register are transferred into the
secondary register on the rising edge of either
S_WR according to the timing diagrams shown in
Figure 4. Data are transferred to the counters as
shown in Table 7 on page 9.
fp = Fin / [10 x (M + 1) + A]
(1)
where A ≤ M + 1, 1 ≤ M ≤ 511
When the loop is locked, Fin is related to the
reference frequency (fr) by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1))
(2)
where A ≤ M + 1, 1 ≤ M ≤ 511
The double buffering provided by the primary and
secondary registers allows for “ping-pong” counter
control using the FSELS input. When FSELS is
“high”, the primary register contents set the counter
inputs. When FSELS is “low”, the secondary
register contents are utilized.
A consequence of the upper limit on A is that Fin
must be greater than or equal to 90 x (fr / (R+1)) to
obtain contiguous channels. The A counter can
accept values as high as 15, but in typical operation
it will cycle from 0 to 9 between increments in M.
While the E_WR input is “high” and the S_WR input
is “low”, serial input data (Sdata input), B0 to B7, are
clocked serially into the enhancement register on
the rising edge of Sclk, MSB (B0) first. The
enhancement register is double buffered to prevent
inadvertent control changes during serial loading,
with buffer capture of the serially entered data
performed on the falling edge of E_WR according to
the timing diagram shown in Figure 4. After the
falling edge of E_WR, the data provide control bits
as shown in Table 8 on page 9 will have their bit
functionality enabled by asserting the Enh input
“low”.
Programming the M counter with the minimum
allowed value of “1” will result in a minimum M
counter divide ratio of “2”.
Prescaler Bypass Mode
Setting the frequency control register bit Pre_en
“high” allows Fin to bypass the ÷10/11 prescaler. In
this mode, the prescaler and A counter are powered
down, and the input VCO frequency is divided by
the M counter directly. The following equation
relates Fin to the reference frequency fr:
Fin = (M + 1) x (fr / (R+1))
(3)
where 1 ≤ M ≤ 511
Reference Counter
The reference counter chain divides the reference
frequency fr down to the phase detector comparison
frequency fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
fc = fr / (R + 1)
(4)
where 0 ≤ R ≤ 63
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PE3339
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Table 7. Primary Register Programming
Interface Mode
Enh
R5
R4
M8
M7 Pre_en M6
B3 B4 B5
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
Serial*
1
B0
B1
B2
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode
Power
down
Counter
load
MSEL
output
fc output
Enh
Reserved
Reserved
fp Output
Reserved
Serial*
0
B0
B1
B2
B3
B4
B5
B6
B7
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
(last in) LSB
Figure 4. Serial Interface Mode Timing Diagram
Sdata
E_WR
tEC
tCE
Sclk
S_WR
tDSU
tDHLD
tClkH
tClkL
tCWR
tPW
tWRC
File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS
Copyright © Peregrine Semiconductor Corp. 2004
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PE3339
Advance Information
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Reserved**
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Reserved**
fp output
Drives the M counter output onto the Dout output.
Power down
Counter load
MSEL output
fc output
Power down of all functions except programming interface.
Immediate and continuous load of counter programming.
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Drives the reference counter output onto the Dout output
Reserved**
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_U, and
PD_D. If the divided VCO leads the divided
reference in phase or frequency (fp leads fc), PD_D
pulses “low”. If the divided reference leads the
divided VCO in phase or frequency (fc leads fp),
PD_U pulses “low”. The width of either pulse is
directly proportional to phase offset between the
two input signals, fp and fc.
current pulses from pin CP are low pass filtered
externally and then connected to the VCO tune
voltage. PD_U pulses result in a current source,
which increases the VCO frequency and PD_D
results in a current sink, which decreases VCO
frequency when using a positive Kv VCO.
A lock detect output, LD is also provided, via the pin
Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kohm resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.
The signals from the phase detector couple directly
to a charge pump. PD_U controls a current source
at pin CP with constant amplitude and pulse
duration approximately the same as PD_U. PD_D
similarly drives a current sink at pin CP. The
Figure 5. Typical PE3339 Loop Filter Application Example
Charge
Pump
R
To VCO
Tune
C2
C1
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PE3339
Advance Information
Figure 6. Package Drawing
20-lead TSSOP (JEDEC MO-153-AC)
TOP VIEW
0.65BSC
20 19
18 17 16 15 14 13 12 11
12o REF
3.20
2X
0.20
R 0.90 MIN
4.40±0.10
Ø1.00±0.10
R 0.90 MIN
GAGE
PLANE
0o
8o
1.00
12o REF
0.25
- B -
+.15
-.10
1.0 REF
0.60
.20 C B A
1
2
3
4
5
6
7
8
9
10
1.00
0.325
- A -
6.50±0.10
0.90±0.05
1.10 MAX
- C -
0.10
C
0.30 MAX
C B A
0.10±0.05
6.40
0.10
FRONT VIEW
SIDE VIEW
File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS
Copyright © Peregrine Semiconductor Corp. 2004
Page 10 of 12
PE3339
Advance Information
Table 10. Ordering Information
Order
Shipping
Method
Part Marking
Code
Description
PE3339-20TSSOP-74A
Package
3339-11
3339-12
3339-00
PE3339
20-lead TSSOP
20-lead TSSOP
20-lead TSSOP
74 units / Tube
2000 units / T&R
1 / Box
PE3339
PE3339-20TSSOP-200C
PE3339EK
PE3339-20TSSOP-EVAL KIT
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Sales Offices
United States
Japan
Peregrine Semiconductor Corp.
9450 Carroll Park Drive
San Diego, CA 92121
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel 1-858-731-9400
Fax 1-858-731-9499
Tel: (+81)-03-3507-5755
Fax: (+81)-03-3507-5601
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches France
Tel (+33)-1-47-41-91-73
Fax (+33)-1-47-41-91-73
For a list of representatives in your area, please refer to our Web site at: http://www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be
reliable. However, Peregrine assumes no liability for the
use of this information. Use shall be entirely at the
user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change
in any manner without notice.
No patent rights or licenses to any circuits described in
this data sheet are implied or granted to any third party.
Preliminary Specification
The data sheet contains preliminary data. Additional
data may be added at a later date. Peregrine reserves
the right to change specifications at any time without
notice in order to supply the best possible product.
Peregrine’s products are not designed or intended for
use in devices or systems intended for surgical implant,
or in other applications intended to support or sustain
life, or in any application in which the failure of the
Peregrine product could create a situation in which
personal injury or death might occur. Peregrine
assumes no liability for damages, including
Product Specification
The data sheet contains final data. In the event
Peregrine decides to change the specifications,
Peregrine will notify customers of the intended changes
by issuing a DCN (Document Change Notice).
consequential or incidental damages, arising out of the
use of its products in such applications.
Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp.,
and UTSi are registered trademarks of Peregrine Semiconductor Corporation.
Copyright © 2004 Peregrine Semiconductor Corp. All rights reserved.
File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS
Copyright © Peregrine Semiconductor Corp. 2004
Page 12 of 12
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