PE3335EK_技术文档

Product Specification

PE3335

3000 MHz UltraCMOS™ Integer-N PLL

for Low Phase Noise Applications

Product Description

Features

Peregrine’s PE3335 is a high performance integer-N PLL

capable of frequency synthesis up to 3000 MHz. The

superior phase noise performance of the PE3335 makes it

ideal for applications such as LMDS / MMDS / WLL

basestations and demanding terrestrial systems.

• 3000 MHz operation

• ÷10/11 dual modulus prescaler

• Internal phase detector with

charge pump

The PE3335 features a 10/11 dual modulus prescaler,

counters, phase comparator and a charge pump as shown

in Figure 1. Counter values are programmable through

either a serial or parallel interface and can also be directly

hard wired.

• Serial, parallel or hardwired

programmable

• Ultra-low phase noise

• Available in 44-lead PLCC and

7x7 mm 48-lead QFN packages

The PE3335 Phase Locked-Loop is optimized for terrestrial

applications. It is manufactured on Peregrine’s

UltraCMOS™ process, a patented variation of silicon-on-

insulator (SOI) technology on a sapphire substrate, offering

the performance of GaAs with the economy and integration

of conventional CMOS.

Figure 1. Block Diagram

F_in

Prescaler

10/11

Main

Counter

f_p

13

D(7:0)

8

Sdata

Primary

20-bit

Latch

Secon-

dary

20-bit

Latch

PD_U

Charge

Pump

Phase

Detector

20

CP

20

16

PD_D

Pre_en

M(6:0)

A(3:0)

R(3:0)

6

f_r

R Counter

f_c

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Page 1 of 15

PE3335

Product Specification

Figure 2. Pin Configurations (Top View)

48 47 46 45 44 43 42 41 40 39 38 37

6

5

4

3

2

1

44 43 42 41 40

D₀, M₀

D₁, M₁

f_c

7

8

39

38

37

36

35

34

33

32

31

30

29

f_c

D0, M0

D1, M1

1

2

3

4

5

6

7

8

9

36

35

V_DD_f_c

NC

D2, M2

34 NC

D₂, M₂

9

NC

33

D3, M3

D₃, M₃

CP

10

11

12

13

14

15

16

17

CP

32

V_DD

C_ext

V_DD

D_out

V_DD_f_p

f_p

GND

V_DD

31

30

29

28

27

26

25

V_DD

C_ext

V_DD

D_out

V_DD_f_p

f_p

V_DD

S_WR, D4, M4

Sdata, D5, M5

Sclk, D6, M6

S_WR, D₄, M₄

Sdata, D₅, M₅

Sclk, D₆, M₆

FSELS, D₇, Pre_en

GND

FSELS, D7, Pre_en 10

GND 11

FSELP, A0

12

GND

18 19 20 21 22 23 24 25 26 27 28

13 14 15 16 17 18 19 20 21 22 23 24

44-lead PLCC

48-lead QFN

Table 1. Pin Descriptions

Pin No.

Name

Interface

Mode

Type

Description

(44-lead

PLCC)

(48-lead

QFN)

Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing

recommended.

1

43

V_DD

ALL

(Note 1)

2

3

4

5

6

44

45

46

47

48

R₀

Direct

ALL

Input

R Counter bit0 (LSB).

R Counter bit1.

R₁

Input

R₂

Input

R Counter bit2.

R₃

Input

R Counter bit3.

GND

D₀

(Note 1)

Input

Ground.

Parallel

Direct

Parallel

Direct

Parallel

Direct

Parallel

Direct

ALL

Parallel data bus bit0 (LSB).

M Counter bit0 (LSB).

Parallel data bus bit1.

M Counter bit1.

7

8

1

2

3

4

M₀

D₁

Input

M₁

D₂

Input

Parallel data bus bit2.

M Counter bit2.

9

M₂

D₃

Input

Parallel data bus bit3.

M Counter bit3.

10

M₃

V_DD

Input

11

12

5

6

(Note 1)

Same as pin 1 (QFN48 pin 43).

ALL

Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions

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PE3335

Product Specification

Table 1. Pin Descriptions (continued)

Pin No.

Name

Interface

Mode

Type

Description

(44-lead

PLCC)

(48-lead

QFN)

Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.

Primary register data are transferred to the secondary register on S_WR or

Hop_WR rising edge.

S_WR

Serial

Input

13

14

7

8

D₄

M₄

Parallel

Direct

Input

Parallel data bus bit4

M Counter bit4

Sdata

D₅

Serial

Input

Binary serial data input. Input data entered MSB first.

Parallel data bus bit5.

Parallel

Direct

M₅

M Counter bit5.

Serial clock input. Sdata is clocked serially into the 20-bit primary register

(E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising

edge of Sclk.

Sclk

Serial

Input

15

16

9

D₆

M₆

Parallel

Direct

Input

Parallel data bus bit6.

M Counter bit6.

Selects contents of primary register (FSELS=1) or secondary register

(FSELS=0) for programming of internal counters while in Serial Interface

Mode.

FSELS

Serial

Input

10

D₇

Parallel

Direct

ALL

Input

Parallel data bus bit7 (MSB).

Pre_en

GND

Prescaler enable, active “low”. When “high”, F_inbypasses the prescaler.

Ground.

17

18

11

12

Selects contents of primary register (FSELP=1) or secondary register

(FSELP=0) for programming of internal counters while in Parallel Interface

Mode.

FSELP

A₀

Parallel

Input

Direct

Serial

Input

A Counter bit0 (LSB).

Enhancement register write enable. While E_WR is “high”, Sdata can be

serially clocked into the enhancement register on the rising edge of Sclk.

E_WR

Enhancement register write. D[7:0] are latched into the enhancement register

on the rising edge of E_WR.

19

13

Parallel

Direct

Input

A₁

A Counter bit1.

M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the

rising edge of M2_WR.

M2_WR

A₂

Parallel

Direct

20

21

14

15

A Counter bit2.

Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface

Mode (Bmode=0, Smode=0).

Serial,

Parallel

Smode

A₃

Direct

ALL

Input

A Counter bit3 (MSB).

16

Bmode

V_DD

Selects direct interface mode (Bmode=1).

Same as pin 1 (MLP48 pin 43).

22

23

Input

17,18

ALL

(Note 1)

M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the

24

25

19

20

M1_WR

A_WR

Parallel

Input

rising edge of M1_WR.

A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the

rising edge of A_WR.

Serial,

Parallel

Hop write. The contents of the primary register are latched into the

secondary register on the rising edge of Hop_WR.

26

27

21

22

Hop_WR

F_in

Input

ALL

Prescaler input from the VCO. 3.0 GHz max frequency.

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PE3335

Product Specification

Table 1. Pin Descriptions (continued)

Pin No.

Name

Interface

Mode

Type

Description

(44-lead

PLCC)

(48-lead

QFN)

Prescaler complementary input. A bypass capacitor should be placed as

close as possible to this pin and be connected in series with a 50 Ω resistor

directly to the ground plane.

23

F_in

28

ALL

Input

29

30

31

32

33

24

25

26

27

28

GND

f_p

ALL

Ground.

Monitor pin for main divider output. Switching activity can be disabled through

enhancement register programming or by floating or grounding V_DDpin 31.

Output

(Note 1)

Output

(Note 1)

V_DD-f_p

Dout

V_DD

V_DDfor f_p. Can be left floating or connected to GND to disable the f_poutput.

Serial,

Parallel

Data Out. The MSEL signal and the raw prescaler output are available on

Dout through enhancement register programming.

ALL

Same as pin 1 (QFN48 pin 43).

Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ

series resistor. Connecting Cext to an external capacitor will low pass filter

the input to the inverting amplifier used for driving LD.

34

29

Cext

Output

35

36

37

38

30

32

V_DD

ALL

(Note 1)

Output

Same as pin 1 (QFN48 pin 43).

CP

Charge pump current is sourced when f_cleads f_pand sinked when f_clags f_p.

No connection.

33, 34

35

NC

V_DD-f_c

(Note 1)

Output

V_DDfor f_ccan be left floating or connected to GND to disable the f_coutput.

Monitor pin for reference divider output. Switching activity can be disabled

through enhancement register programming or by floating or grounding V_DD

pin 38.

39

36

f_c

ALL

40

41

42

31,37

38,39

40

GND

f_r

ALL

Ground.

Input

Reference frequency input.

Lock detect and open drain logical inversion of Cext. When the loop is in lock,

LD is high impedance, otherwise LD is a logic low (“0”).

43

44

41

LD

ALL

Output

Serial,

Parallel

Enhancement mode. When asserted low (“0”), enhancement register bits are

functional.

42

Enh

Input

Note 1: All V_DDpins are connected by diodes and must be supplied with the same positive voltage level.

V_DD-f_pand V_DD-f_care used to power the f_pand f_coutputs and can alternatively be left floating or connected to GND to disable the f_pand f_c

outputs.

Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.

Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions

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PE3335

Product Specification

Table 2. Absolute Maximum Ratings

Table 4. ESD Ratings

Symbol

Parameter/Conditions Min Max Units

Symbol

Parameter/Conditions

Level

Units

V_DD

V_I

Supply voltage

-0.3

4.0

V

V_ESD

ESD voltage (Human Body

1000

V

Voltage on any input

V_DD

+

Note 1: Periodically sampled, not 100% tested. Tested per MIL-

0.3

STD-883, M3015 C2

I_I

DC into any input

-10

-65

+10

150

mA

°C

I_O

DC into any output

Electrostatic Discharge (ESD) Precautions

T_stg

Storage temperature range

When handling this UltraCMOS™ device, observe

the same precautions that you would use with

other ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the specified rating in Table 4.

Table 3. Operating Ratings

Symbol

Parameter/Conditions Min Max Units

V_DD

Supply voltage

2.85

-40

3.15

85

V

Latch-Up Avoidance

T_A

Operating ambient

temperature range

°C

Unlike conventional CMOS devices, UltraCMOS™

devices are immune to latch-up.

Table 5. DC Characteristics: V_DD= 3.0 V, -40° C < T_A< 85° C, unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Units

I_DD

Operational supply current;

Prescaler disabled

V_DD= 2.85 to 3.15 V

10

24

mA

Prescaler enabled

31

Digital Inputs: All except f_r, R₀, F_in, F_in

V_IH

V_IL

I_IH

High level input voltage

Low level input voltage

High level input current

Low level input current

V_DD= 2.85 to 3.15 V

V_IH= V_DD= 3.15 V

0.7 x V_DD

V

0.3 x V_DD

+70

µA

I_IL

V_IL= 0, V_DD= 3.15 V

-1

Reference Divider input: f_r

I_IHRHigh level input current

I_ILRLow level input current

R0 Input (Pull-up Resistor): R₀

I_IHROHigh level input current

I_ILROLow level input current

Counter output D_out

V_IH= V_DD= 3.15 V

+100

+5

µA

V_IL= 0, V_DD= 3.15 V

-100

V_IH= V_DD= 3.15 V

µA

V_IL= 0, V_DD= 3.15 V

-5

V_OLD

V_OHD

Output voltage LOW

Output voltage HIGH

I_out= 6 mA

I_out= -3 mA

0.4

V

V_DD- 0.4

Lock detect outputs: Cext, LD

V_OLC

V_OHC

V_OLLD

Output voltage LOW, Cext

I_out= 100 mA

I_out= -100 mA

I_out= 6 mA

0.4

V

Output voltage HIGH, Cext

Output voltage LOW, LD

Charge Pump output: CP

I_CP- Source Drive current

V_CP= V_DD/ 2

-2.6

1.4

-1

-2

2

-1.4

2.6

mA

µA

%

I_CP– Sink

Drive current

V_CP= V_DD/ 2

I_CPL

Leakage current

1.0 V < V_CP< V_DD– 1.0 V

VCP = V_DD/ 2,

T_A= 25° C

1

I_CP– Source

Sink vs. source mismatch

15

vs. I_CPSink

I_CPvs. V_CP

Output current magnitude variation vs. voltage

V < V_CP< V_DD– 1.0 V

T_A= 25° C

%

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PE3335

Product Specification

Table 6. AC Characteristics: V_DD= 3.0 V, -40° C < T_A< 85° C, unless otherwise specified

Symbol

Parameter

Conditions

Min

Max

Units

Control Interface and Latches (see Figures 3, 4, 5)

f_Clk

Serial data clock frequency

Serial clock HIGH time

Serial clock LOW time

10

MHz

ns

t_ClkH

t_ClkL

t_DSU

30

10

ns

Sdata set-up time after Sclk rising edge, D[7:0] set-up time

to M1_WR, M2_WR, A_WR, E_WR rising edge

ns

t_DHLD

Sdata hold time after Sclk rising edge, D[7:0] hold time to

M1_WR, M2_WR, A_WR, E_WR rising edge

10

ns

t_PW

S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width

30

ns

t_CWR

Sclk rising edge to S_WR rising edge. S_WR, M1_WR,

M2_WR, A_WR falling edge to Hop_WR rising edge

t_CE

Sclk falling edge to E_WR transition

30

ns

t_WRC

S_WR falling edge to Sclk rising edge. Hop_WR falling

edge to S_WR, M1_WR, M2_WR, A_WR rising edge

t_EC

E_WR transition to Sclk rising edge

30

ns

t_MDO

MSEL data out delay after Fin rising edge

C_L= 12 pf

8

Main Divider (Including Prescaler)

F_in

Operating frequency

Input level range

500

-5

3000

5

MHz

dBm

P_Fin

External AC coupling

Main Divider (Prescaler Bypassed)

F_in

Operating frequency

Input level range

50

-5

300

5

MHz

dBm

P_Fin

Reference Divider

f_r

Operating frequency

Reference input power

Input sensitivity

(Note 1)

(Note 2)

-2

100

10

MHz

dBm

V_P-P

P_fr

V_fr

Single ended input

External AC coupling

(Note 3)

0.5

Phase Detector

f_c

Comparison frequency

(Note 1)

20

MHz

Note 1: Parameter is guaranteed through characterization only and is not tested.

Note 2: Running at low frequencies (< 10 MHz sinewave), the device will still be functional but may cause phase noise degradation. Inserting a low-

noise amplifier to square up the edges is recommended at lower input frequencies.

Note 3: CMOS logic levels may be used if DC coupled. For optimum phase noise performance, the reference input falling edge rate should be faster

than 80mV/ns.

Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions

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PE3335

Product Specification

Functional Description

The PE3335 consists of a prescaler, counters, a

phase detector, a charge pump and control logic.

The dual modulus prescaler divides the VCO

frequency by either 10 or 11, depending on the

value of the modulus select. Counters “R” and “M”

divide the reference and prescaler output,

detector generates up and down frequency control

signals. The control logic includes a selectable

chip interface. Data can be written via serial bus,

parallel bus, or hardwired direct to the pins. There

are also various operational and test modes and

lock detect.

respectively, by integer values stored in a 20-bit

register. An additional counter (“A”) is used in

the modulus select logic. The phase-frequency

Figure 3. Functional Block Diagram

R Counter

f_r

f_c

(6-bit)

PD_U

R(5:0)

M(8:0)

A(3:0)

D(7:0)

Sdata

Phase

Control

Logic

Charge

PD_D

CP

Detector

Pump

Control

Pins

LD

Cext

2 kΩ

Modulus

Select

F_in

10/11

M Counter

(9-bit)

f_p

Prescaler

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PE3335

Product Specification

Main Counter Chain

Register Programming

The main counter chain divides the RF input

frequency, F_in, by an integer derived from the user

defined values in the “M” and “A” counters. It is

composed of the 10/11 dual modulus prescaler,

modulus select logic, and 9-bit M counter. Setting

Pre_en “low” enables the 10/11 prescaler. Setting

Pre_en “high” allows F_into bypass the prescaler

and powers down the prescaler.

Parallel Interface Mode

Parallel Interface Mode is selected by setting the

Bmode input “low” and the Smode input “low”.

Parallel input data, D[7:0], are latched in a

parallel fashion into one of three, 8-bit primary

register sections on the rising edge of M1_WR,

M2_WR, or A_WR per the mapping shown in

Table 7 on page 10. The contents of the primary

register are transferred into a secondary register

on the rising edge of Hop_WR according to the

timing diagram shown in Figure 4. Data are

transferred to the counters as shown in Table 7

on page 10.

The output from the main counter chain, f_p, is

related to the VCO frequency, F_in, by the following

equation:

f_p= F_in/ [10 x (M + 1) + A]

(1)

where A ≤ M + 1, 1 ≤ M ≤ 511

The secondary register acts as a buffer to allow

rapid changes to the VCO frequency. This

double buffering for “ping-pong” counter control

is programmed via the FSELP input. When

FSELP is “high”, the primary register contents

set the counter inputs. When FSELP is “low”, the

secondary register contents are utilized.

When the loop is locked, F_inis related to the

reference frequency, f_r, by the following equation:

F_in= [10 x (M + 1) + A] x (f_r/ (R+1))

(2)

where A ≤ M + 1, 1 ≤ M ≤ 511

A consequence of the upper limit on A is that F_in

must be greater than or equal to 90 x (f_r/ (R+1)) to

obtain contiguous channels. Programming the M

Counter with the minimum value of “1” will result in

a minimum M Counter divide ratio of “2”.

Parallel input data, D[7:0], are latched into the

enhancement register on the rising edge of

E_WR according to the timing diagram shown in

Figure 4. This data provides control bits as

shown in Table 8 on page 10 with bit

functionality enabled by asserting the Enh input

“low”.

When the prescaler is bypassed, the equation

becomes:

F_in= (M + 1) x (f_r/ (R+1))

(3)

where 1 ≤ M ≤ 511

Serial Interface Mode

Serial Interface Mode is selected by setting the

Bmode input “low” and the Smode input “high”.

In Direct Interface Mode, main counter inputs M₇

and M₈are internally forced low.

While the E_WR input is “low” and the S_WR

input is “low”, serial input data (Sdata input), B₀

to B₁₉, are clocked serially into the primary

register on the rising edge of Sclk, MSB (B₀)

first. The contents from the primary register are

transferred into the secondary register on the

rising edge of either S_WR or Hop_WR

according to the timing diagram shown in

Figures 4-5. Data are transferred to the counters

as shown in Table 7 on page 10.

Reference Counter

The reference counter chain divides the reference

frequency, f_r, down to the phase detector

comparison frequency, f_c.

The output frequency of the 6-bit R Counter is

related to the reference frequency by the following

equation:

f_c= f_r/ (R + 1)

(4)

The double buffering provided by the primary

and secondary registers allows for “ping-pong”

counter control using the FSELS input. When

FSELS is “high”, the primary register contents

set the counter inputs. When FSELS is “low”, the

secondary register contents are utilized.

where 0 ≤ R ≤ 63

Note that programming R equal to “0” will pass the

reference frequency, f_r, directly to the phase

detector.

In Direct Interface Mode, R Counter inputs R₄and

R₅are internally forced low (“0”).

While the E_WR input is “high” and the S_WR

Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions

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PE3335

Product Specification

Direct Interface Mode

input is “low”, serial input data (Sdata input), B₀to

B₇, are clocked serially into the enhancement

register on the rising edge of Sclk, MSB (B₀) first.

The enhancement register is double buffered to

prevent inadvertent control changes during serial

loading, with buffer capture of the serially entered

data performed on the falling edge of E_WR

according to the timing diagram shown in Figure

5. After the falling edge of E_WR, the data provide

control bits as shown in Table 8 with bit

Direct Interface Mode is selected by setting the

Bmode input “high”.

Counter control bits are set directly at the pins as

shown in Table 7. In Direct Interface Mode, main

counter inputs M₇and M₈, and R Counter inputs

R₄and R₅are internally forced low (“0”).

functionality enabled by asserting the Enh input

“low”.

Table 7. Primary Register Programming

Interface

Mode

Smode

R₅

R₄

M₈

M₇

M₆

M₅

M₄

M₃

M₂

M₁

M₀

R₃

R₂

R₁

R₀

A₃

A₂

A₁

A₀

Enh

Bmode

Pre_en

Parallel

1

0

M2_WR rising edge load

M1_WR rising edge load

A_WR rising edge load

D₃

D₂

D₁

D₀

D₇

B₄

D₆

B₅

D₅

D₄

D₃

D₂

D₁

D₀

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

Serial*

Direct

1

0

1

B₀

0

B₁

0

B₂

0

B₃

0

B₆

B₇

B₈

B₉

B₁₀

M₁

B₁₁

M₀

B₁₂

R₃

B₁₃

R₂

B₁₄

R₁

B₁₅

R₀

B₁₆

A₃

B₁₇

A₂

B₁₈B₁₉

A₁A₀

X

Pre_en M₆

M₅

M₄

M₃

M₂

*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.

MSB (first in)

(last in) LSB

Table 8. Enhancement Register Programming

Interface

Mode

Power

down

Counter

load

MSEL

output

Prescaler

output

Smode

Reserved

f_c, f_pOE

Enh

0

Bmode

E_WR rising edge load

Parallel

Serial*

X

0

1

D₇

B₀

D₆

B₁

D₅

B₂

D₄

B₃

D₃

B₄

D₂

B₅

D₁

B₆

D₀

B₇

0

*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

MSB (first in)

(last in) LSB

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PE3335

Product Specification

Figure 4. Parallel Interface Mode Timing Diagram

t_DSU

t_DHLD

[

]

7 : 0

D

t_PW

t_CWR

t_WRC

M1_WR

M2_WR

A_WR

t_PW

E_WR

Hop_WR

Figure 5. Serial Interface Mode Timing Diagram

Sdata

E_WR

t_EC

t_CE

Sclk

S_WR

t_DSU

t_DHLD

t_ClkH

t_ClkL

t_CWR

t_PW

t_WRC

Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions

Page 10 of 15

PE3335

Product Specification

Enhancement Register

The functions of the enhancement register bits are shown below with all bits active “high”.

Table 9. Enhancement Register Bit Functionality

Bit Function

Description

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Reserved**

Power down

Counter load

Power down of all functions except programming interface.

Immediate and continuous load of counter programming as directed by the Bmode and

Bit 5

Bit 6

Bit 7

MSEL output

Prescaler output

f_p, f_cOE

Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.

Drives the raw internal prescaler output onto the Dout output.

f_p, f_coutputs disabled.

** Program to 0

Phase Detector

The phase detector is triggered by rising edges

from the main Counter (f_p) and the reference

counter (f_c). It has two outputs, PD_U, and PD_D.

If the divided VCO leads the divided reference in

phase or frequency (f_pleads f_c), PD_D pulses

“low”. If the divided reference leads the divided

VCO in phase or frequency (f_cleads f_p), PD_U

pulses “low”. The width of either pulse is directly

proportional to phase offset between the two input

signals, f_pand f_c.

CP. The current pulses from pin CP are low pass

filtered externally and then connected to the VCO

tune voltage. PD_U pulses result in a current

source, which increases the VCO frequency;

PD_D pulses result in a current sink, which

decreases VCO frequency (for a positive Kv

VCO).

A lock detect output, LD is also provided, via the

pin Cext. Cext is the logical “NAND” of PD_U and

PD_D waveforms, which is driven through a series

2 kohm resistor. Connecting Cext to an external

shunt capacitor provides low pass filtering of this

signal. Cext also drives the input of an internal

inverting comparator with an open drain output.

Thus LD is an “AND” function of PD_U and PD_D.

The signals from the phase detector couple

directly to a charge pump. PD_U controls a

current source at pin CP with constant amplitude

and pulse duration approximately the same as

PD_U. PD_D similarly drives a current sink at pin

Document No. 70-0049-02 │ www.psemi.com

Page 11 of 15

PE3335

Product Specification

Handling Requirements

All surface mount products which do not meet

Level 1 moisture sensitivity requirements are

processed through dry bake and pack procedure.

The necessary data is recorded on the caution

label of each shipment. Both packages for the

PE3335 are moisture sensitivity Level 3.

Level 3 Caution Label

Level and Body temperature defined by:

IPC/JEDEC-J-STD-020

The caution label should contain the following

information for Level 3 devices:

1. Calculated shelf life in sealed bag: 12 months

at <40 °C and <90% relative humidity (RH)

For Dry Bake Procedures, see:

IPC/JEDEC-J-STD-033

2. Peak package body temperature is 225 °C.

Operator must observe ESD precautions per

ESD Control Procedure and Parts Handling and

shipping Procedure.

3. After bag is opened, devices that will be

subjected to reflow solder or other high

temperature process must

a) Be mounted within 168 hours of factory

conditions <30 °C/60% RH, or

b) Be stored at <10% RH

4. Devices require bake, before mounting, if:

a) Humidity Indicator Card is > 10% when

read at 23 ± 5 °C

b) 3a or 3b are not met

5. If baking is required, devices may be baked for

48 hours at 125 +5/-0 °C

Note: If device containers cannot be subjected to

high temperature or shorter bake times are

desired, reference IPC/JEDEC-J-STD-033 for

bake procedure.

Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions

Page 12 of 15

PE3335

Product Specification

Figure 6. Package Drawing

48-lead QFN

7.00

- B -

3.50

INDEX AREA

3.50 X 3.50

0.25

C

- A -

0.10

0.08

C

2

SEATING

PLANE

- C -

EXPOSED PAD &

TERMINAL PADS

5.00

5.25

2.50

2.63

13

24

12

25

0.23

0.18

1

48

36

37

EXPOSED PAD

2

DETAIL

A

0.50 TYP

0.23

0.10

C A B

1

1. DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED

BETWEEN 0.25 AND 0.30 FROM TERMINAL TIP.

2. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL

AS THE TERMINALS.

Document No. 70-0049-02 │ www.psemi.com

Page 13 of 15

PE3335

Product Specification

Figure 7. Package Drawing

44-lead PLCC

0.690±0.005

0.653±0.003

0.045 X 45°

0.010 X 45°

1*

4*

0.020 MIN.

R0.025

PIN 1

SURFACE

MOUNT

POINT

0.610 ±0.020

2*

3*

A

DETAIL

BOTTOM VIEW

0.027 (WIDTH OF LEAD SLOT)

*EJECT PIN POSITION

0.070

Ø0.040

DIMENSIONS ARE IN INCHES

TOLERANCES ARE ± 0.004

50X 45°

0.180 MAX.

0.070

0.004

0.010

SEE DETAIL A

Table 10. Ordering Information

Order Code

3335-21

Part Marking

PE3335

Description

Package

Shipping Method

PE3335-44PLCC-27A

44-lead PLCC

48-lead QFN

Evaluation Kit

27 units / Tube

500 units / T&R

52 units / Tube

2000 units / T&R

1 / Box

3335-22

PE3335

PE3335-44PLCC-500C

3335-23

PE3335

PE3335-48QFN 7x7 mm-52A

PE3335-48QFN 7x7 mm-2000C

PE3335-44PLCC-EVAL KIT

3335-24

PE3335

3335-00

PE3335EK

3335-01

PE3335-48QFN 7x7 mm-EK

1 / Box

Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions

Page 14 of 15

PE3335

Product Specification

Sales Offices

The Americas

North Asia Pacific

Peregrine Semiconductor Corporation

Peregrine Semiconductor K.K.

9450 Carroll Park Drive

San Diego, CA 92121

Tel 858-731-9400

5A-5, 5F Imperial Tower

1-1-1 Uchisaiwaicho, Chiyoda-ku

Tokyo 100-0011 Japan

Tel: +81-3-3502-5211

Fax 858-731-9499

Fax: +81-3-3502-5213

Europe

Peregrine Semiconductor, Korea

#B-2402, Kolon Tripolis, #210

Geumgok-dong, Bundang-gu, Seongnam-si,

Gyeonggi-do, 463-480 S. Korea

Tel: +82-31-728-4300

Peregrine Semiconductor Europe

Bâtiment Maine

13-15 rue des Quatre Vents

F- 92380 Garches, France

Tel: +33-1-47-41-91-73

Fax : +33-1-47-41-91-73

Fax: +82-31-728-4305

South Asia Pacific

Space and Defense Products

Peregrine Semiconductor, China

Shanghai, 200040, P.R. China

Tel: +86-21-5836-8276

Americas:

Tel: 505-881-0438

Fax: 505-881-0443

Fax: +86-21-5836-7652

Europe, Asia Pacific:

180 Rue Jean de Guiramand

13852 Aix-En-Provence cedex 3, France

Tel: +33(0) 4 4239 3361

Fax: +33(0) 4 4239 7227

For a list of representatives in your area, please refer to our Web site at: www.psemi.com

Data Sheet Identification

Advance Information

The information in this data sheet is believed to be reliable.

However, Peregrine assumes no liability for the use of this

information. Use shall be entirely at the user’s own risk.

The product is in a formative or design stage. The data

sheet contains design target specifications for product

development. Specifications and features may change in

any manner without notice.

No patent rights or licenses to any circuits described in this

data sheet are implied or granted to any third party.

Preliminary Specification

Peregrine’s products are not designed or intended for use in

devices or systems intended for surgical implant, or in other

applications intended to support or sustain life, or in any

application in which the failure of the Peregrine product could

create a situation in which personal injury or death might occur.

Peregrine assumes no liability for damages, including

consequential or incidental damages, arising out of the use of

its products in such applications.

The data sheet contains preliminary data. Additional data

may be added at a later date. Peregrine reserves the right

to change specifications at any time without notice in order

to supply the best possible product.

Product Specification

The data sheet contains final data. In the event Peregrine

decides to change the specifications, Peregrine will notify

customers of the intended changes by issuing a DCN

(Document Change Notice).

The Peregrine name, logo, and UTSi are registered trademarks

and UltraCMOS and HaRP are trademarks of Peregrine

Semiconductor Corp.

Document No. 70-0049-02 │ www.psemi.com

Page 15 of 15


型号：	PE3335EK
厂家：	Peregrine Semiconductor
描述：	3000 MHz UltraCMOS⑩ Integer-N PLL for Low Phase Noise Applications 3000兆赫UltraCMOS⑩整数N分频PLL的低相位噪声应用
文件：	总15页 (文件大小：235K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PE3335EK [PSEMI]

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