PE4302-01 [PSEMI]
50 Ohm RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHZ; 50欧姆RF数字衰减器6位， 31.5分贝， DC- 4.0 GHZ
| 型号： | PE4302-01 |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | 50 Ohm RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHZ |
| 文件： | 总11页 (文件大小：458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specification
PE4302
50 Ω RF Digital Attenuator
6-bit, 31.5 dB, DC – 4.0 GHz
Product Description
Features
The PE4302 is a high linearity, 6-bit RF Digital Step Attenuator
“DSA” covering a 31.5 dB attenuation range in 0.5 dB steps.
This 50-ohm RF DSA provides both parallel and serial CMOS
control interface operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4302 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4mm QFN
footprint.
• Attenuation: 0.5 dB steps to 31.5 dB
• Flexible parallel and serial programming
interfaces
• Unique power-up state selection
• Positive CMOS control logic
• High attenuation accuracy and linearity
over temperature and frequency
• Very low power consumption
• Single-supply operation
• 50 Ω impedance
The PE4302 is manufactured in Peregrine’s patented Ultra
Thin Silicon (UTSi®) CMOS process, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
• Packaged in a 20 lead 4x4mm QFN
Figure 1. Functional Schematic Diagram
Figure 2. Package Type
4x4mm -20 Lead QFN
Switched Attenuator Array
RF Input
RF Output
6
3
2
Parallel Control
Serial Control
Control Logic Interface
Power-Up Control
Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V
Parameter
Test Conditions
Frequency
Minimum
Typical
Maximum
Units
MHz
dB
Operation Frequency
Insertion Loss2
DC
-
4000
DC - 2.2 GHz
DC ≤ 1.0 GHz
1.0 < 2.2 GHz
1 MHz - 2.2 GHz
1.5
-
1.75
±(0.10 + 3% of atten setting)
±(0.15 + 5% of atten setting)
-
dB
dB
Any Bit or Bit
Combination
Attenuation Accuracy
-
1 dB Compression3
Input IP31,2
30
-
34
52
20
dBm
dBm
Two-tone inputs
+18 dBm
1 MHz - 2.2 GHz
DC - 2.2 GHz
-
Return Loss
15
-
dB
50% control to 0.5 dB
of final value
Switching Speed
-
-
1
µs
Notes: 1. Device Linearity will begin to degrade below 1 Mhz
2. See Max input rating in Table 2 & Figures on Pages 2 to 4 for data across frequency.
3. Note Absolute Maximum in Table 3.
Document No. 70/0056~02D │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE4302
Product Specification
Typical Performance Data (25°C, VDD=3.0 V)
Figure 3. Insertion Loss
Figure 4. Attenuation at Major steps
0
-1
-2
35
30
25
20
15
10
5
31.5dB
-40C
25C
85C
-3
16dB
2dB
-4
-5
-6
1dB
0.5dB
8dB
4dB
0
0
500
1000
1500 2000 2500
RF Frequency (MHz)
3000 3500
4000
0
500
1000
1500 2000 2500
RF Frequency (MHz)
3000 3500
4000
Figure 5. Input Return Loss at Major
Attenuation Steps
Figure 6. Output Return Loss at Major
Attenuation Steps
0
-10
-20
0
-10
-20
16dB
-30
-40
-50
-30
31.5dB
31.5dB
-40
-50
0
500
1000
1500 2000 2500
RF Frequency (MHz)
3000 3500
4000
0
500
1000
1500 2000 2500
RF Frequency (MHz)
3000 3500
4000
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70/0056~02D │ UltraCMOS™ RFIC Solutions
Page 2 of 11
PE4302
Product Specification
Typical Performance Data (25°C, VDD=3.0 V)
Figure 7. Attenuation Error Vs. Frequency
Figure 8. Attenuation Error Vs. Attenuation
Setting
2
0
0.5
0
10Mhz
31.5 (dB)
-2
500Mhz
1000Mhz
-4
-6
-0.5
-1
1500Mhz
2000Mhz
2200Mhz
-8
-10
-1.5
0
500
1000
1500 2000 2500
RF Frequency (MHz)
3000 3500
4000
0
5
10
15
20
25
30
35
40
Attenuation Setting (dB)
Figure 9. Attenuation Error Vs. Attenuation
Setting
Figure 10. Attenuation Error Vs. Attenuation
Setting
0.6
0.4
0.4
0.2
0
10Mhz, -40C
500Mhz, -40C
0.2
0
1000Mhz, -40C
-0.2
-0.4
-0.6
-0.8
-1
1000Mhz, 25C
10Mhz, 25C
1500Mhz, -40C
1000Mhz, 85C
1490Mhz, 25C
1490Mhz, 85C
500Mhz, 25C
-0.2
-0.4
-0.6
10Mhz, 85C
500Mhz, 85C
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Attenuation Setting (dB)
Attenuation Setting (dB)
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE4302
Product Specification
Typical Performance Data (25°C, VDD=3.0 V)
Figure 11. Attenuation Error Vs. Frequency
Figure 12. Input IP3 Vs. Frequency
0.5
60
55
50
45
40
35
2200Mhz, -40C
0
-0.5
-1
2000Mhz, -40C
2200Mhz, 25C
2000Mhz, 25C
2200Mhz, 85C
2000Mhz, 85C
0dB
1dB
2dB
4dB
16dB
30
25
20
.5dB
8dB
31.5dB
-1.5
0
5
10
15
20
25
30
35
40
0
500
1000
1500
2000
2500
3000
Attenuation Setting (dB)
RF Frequency (MHz)
Figure 13. Input 1 dB Compression
40
35
30
25
20
0dB
1dB
2dB
4dB
8dB
16dB
15
10
0.5dB
31.5dB
2500
0
500
1000
1500
2000
3000
RF Frequency (MHz)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70/0056~02D │ UltraCMOS™ RFIC Solutions
Page 4 of 11
PE4302
Product Specification
Figure 14. Pin Configuration (Top View)
Table 3. Absolute Maximum Ratings
Symbol
Parameter/Conditions
Min Max Units
VDD
Power supply voltage
-0.3
-0.3
-65
-40
4.0
V
VDD
+
VI
TST
TOP
PIN
Voltage on any input
V
0.3
Storage temperature range
150
85
°C
1
2
3
4
5
15
14
13
12
11
C16
RF1
C8
Operating temperature
range
°C
RF2
20-lead QFN
4x4mm
Input power (50ꢀ)
ESD voltage (Human Body
Model)
24
dBm
V
Data
Clock
LE
P/S
Exposed Solder Pad
Vss/GND
GND
VESD
500
Table 4. DC Electrical Specifications
Parameter
Min
Typ
Max
Units
V
VDD Power Supply
Voltage
2.7
3.0
3.3
IDD Power Supply
Current
Table 2. Pin Descriptions
100
µA
Pin
No.
Pin
Name
Digital Input High
Digital Input Low
Digital Input Leakage
0.7xVDD
V
V
Description
0.3xVDD
1
1
2
C16
RF1
Attenuation control bit, 16dB (Note 4).
RF port (Note 1).
µA
3
Data
Clock
LE
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
Exposed Solder Pad Connection
4
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
5
6
VDD
7
PUP1
PUP2
VDD
Power-up selection bit, MSB.
Power-up selection bit, LSB.
Power supply pin.
Electrostatic Discharge (ESD) Precautions
8
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
9
10
11
12
GND
GND
Vss/GND
Ground connection.
Ground connection.
Negative supply voltage or GND
connection(Note 3)
13
14
P/S
RF2
C8
Parallel/Serial mode select.
RF port (Note 1).
Latch-Up Avoidance
15
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
16
C4
17
C2
Switching Frequency
18
GND
C1
The PE4302 has a maximum 25kHz switching
rate.
19
Attenuation control bit, 1 dB.
Attenuation control bit, 0.5 dB.
Ground for proper operation
20
C0.5
GND
Paddle
Resistor on Pin 1 & 3
Note 1: Both RF ports must be held at 0 VDC or DC blocked with an
external series capacitor.
A 10 kꢀ resistor on the inputs to Pin 1 & 3 (see
Figure 16) will eliminate package resonance
between the RF input pin and the two digital
inputs. Specified attenuation error versus
frequency performance is dependent upon this
condition.
2: Latch Enable (LE) has an internal 100 kꢀ resistor to VDD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 kꢀ resistor in series, as close to pin as possible
to avoid frequency resonance.
Document No. 70/0056~02D │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
PE4302
Product Specification
Programming Options
Clock, and Latch Enable (LE). The Data and Clock
inputs allow data to be serially entered into the shift
register, a process that is independent of the state of
the LE input.
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the PE4302. The P/S bit provides this
selection, with P/S=LOW selecting the parallel
interface and P/S=HIGH selecting the serial
interface.
The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator. When LE is
brought LOW, data in the shift register is latched.
Parallel Mode Interface
The parallel interface consists of five CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 5.
The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The timing for this operation is defined by
Figure 17 (Serial Interface Timing Diagram) and
Table 8 (Serial Interface AC Characteristics).
The parallel interface timing requirements are
defined by Figure 18 (Parallel Interface Timing
Diagram), Table 9 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
Power-up Control Settings
For latched parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 18) to latch new attenuation state into
device.
The PE4302 always assumes a specifiable
attenuation setting on power-up. This feature exists
for both the Serial and Parallel modes of operation,
and allows a known attenuation state to be
established before an initial serial or parallel control
word is provided.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
When the attenuator powers up in Serial mode (P/
S=1), the six control bits are set to whatever data is
present on the six parallel data inputs (C0.5 to C16).
This allows any one of the 64 attenuation settings to
be specified as the power-up state.
Table 5. Truth Table
When the attenuator powers up in Parallel mode (P/
S=0) with LE=0, the control bits are automatically set
to one of four possible values. These four values
are selected by the two power-up control bits, PUP1
and PUP2, as shown in Table 6 (Power-Up Truth
Table, Parallel Mode).
Attenuation
P/S C16 C8
C4
C2
C1 C0.5
State
Reference Loss
0.5 dB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
1
1 dB
2 dB
Table 6. Parallel PUP Truth Table
4 dB
8 dB
P/S
0
LE
0
PUP2 PUP1
Attenuation State
Reference Loss
8 dB
16 dB
31.5 dB
0
1
0
1
X
0
0
1
1
X
0
0
Note: Not all 64 possible combinations of C0.5-C16 are shown in table
0
0
16 dB
0
0
31 dB
Serial Interface
0
1
Defined by C0.5-C16
The serial interface is a 6-bit serial-in, parallel-out
shift register buffered by a transparent latch. It is
controlled by three CMOS-compatible signals: Data,
Note: Power up with LE=1 provides normal parallel operation with
C0.5-C16, and PUP1 and PUP2 are not active.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70/0056~02D │ UltraCMOS™ RFIC Solutions
Page 6 of 11
PE4302
Product Specification
Figure 15. Evaluation Board Layout
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4302 Digital Step Attenuator.
J9 is used in conjunction with the supplied DC
cable to supply VDD, GND, and –VDD. If use of
the internal negative voltage generator is desired,
then connect –VDD (Black banana plug) to
ground. If an external –VDD is desired, then apply
-3V.
J1 should be connected to the parallel port of a
PC with the supplied ribbon cable. The evaluation
software is written to operate the DSA in serial
mode, so Switch 7 (P/S) on the DIP switch SW1
should be ON with all other switches off. Using the
software, enable or disable each attenuation
setting to the desired combined attenuation. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
To evaluate the Power Up options, first disconnect
the parallel ribbon cable from the evaluation
board. The parallel cable must be removed to
prevent the PC parallel port from biasing the
control pins.
Figure 16. Evaluation Board Schematic
During power up with P/S=1 high and LE=0 or P/
S=0 low and LE=1, the default power-up signal
attenuation is set to the value present on the six
control bits on the six parallel data inputs (C0.5 to
C16). This allows any one of the 64 attenuation
settings to be specified as the power-up state.
C0.5 C1
C2 C4
10k
1
2
3
4
5
15
14
13
12
11
C16
Z=50 Ohm
C8
Z=50 Ohm
C16
C8
J5
J4
1
1
RFin
DATA
CLK
LE
RFout
PS
MLPQ4X4
U1
DATA
PS
SMA
SMA
During power up with P/S=0 high and LE=0, the
control bits are automatically set to one of four
possible values presented through the PUP
interface. These four values are selected by the
two power-up control bits, PUP1 and PUP2, as
shown in the Table 6.
10k
CLK
LE
Vss/GND
GND
PUP1 PUP2
VDD
Resistor on Pin 1 & 3
100 pF
A 10 kꢀ resistor on the inputs to Pin 1 & 3 (Figure
16) will eliminate package resonance between the
RF input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
Note: Resistors on pins 1 and 3 are required to avoid package
resonance and meet error specifications over frequency.
Document No. 70/0056~02D │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
PE4302
Product Specification
Figure 17. Serial Interface Timing Diagram
Table 7. 6-Bit Attenuator Serial Programming
Register Map
LE
Clock
B5
B4
B3
B2
B1
B0
C16
C8
C4
C2
C1
C0.5
Data
MSB
LSB
↑
↑
MSB (first in)
LSB (last in)
tLESUP
tLEPW
tSDSUP
tSDHLD
Figure 18. Parallel Interface Timing Diagram
LE
Parallel Data
C16:C0.5
tLEPW
tPDSUP
tPDHLD
Table 8. Serial Interface AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Table 9. Parallel Interface AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Min
Max
Unit
Symbol
tLEPW
Parameter
Min
10
Max
Unit
ns
Serial data clock fre-
quency (Note 1)
10
MHz
LE minimum pulse width
fClk
Data set-up time before
rising edge of LE
10
ns
Serial clock HIGH time
Serial clock LOW time
30
30
10
ns
ns
ns
tClkH
tClkL
tLESUP
tLEPW
tPDSUP
Data hold time after
falling edge of LE
10
ns
tPDHLD
LE set-up time after last
clock falling edge
LE minimum pulse width
30
10
ns
ns
Serial data set-up time
before clock rising edge
tSDSUP
Serial data hold time
after clock falling edge
10
ns
tSDHLD
Note: fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked at
10 MHz to verify fclk specification.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70/0056~02D │ UltraCMOS™ RFIC Solutions
Page 8 of 11
PE4302
Product Specification
Figure 19. Package Drawing
4.00
2.00
INDEX AREA
2.00 X 2.00
- B -
0.25
C
- A -
0.10
0.08
C
C
SEATING
PLANE
- C -
EXPOSED PAD &
TERMINAL PADS
2.00
1.00
0.435
6
10
5
1
11
0.18
15
20
16
EXPOSED PAD
2
DETAIL A
DETAIL A
0.23
0.10
C A B
1
1. Dimension applies to metallized terminal and is measured
between 0.25 and 0.30 from terminal tip.
2. Coplanarity applies to the exposed heat sink slug as well as
the terminals.
3. Dimensions are in millimeters.
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 11
PE4302
Product Specification
Figure 20. Marking Specifications
4302
YYWW
ZZZZZ
YYWW = Date Code
ZZZZZ = Last five digits of PSC Lot Number
Figure 21. Tape and Reel Drawing
Table 10. Ordering Information
Order Code Part Marking
Description
Package
Shipping Method
75 units / Tube
3000 units / T&R
1 / Box
75 units / Tube
3000 units / T&R
4302-01
4302-02
4302-00
4302-51
4302-52
4302
4302
PE4302-EK
4302
PE4302-20MLP 4x4mm-75A
PE4302-20MLP 4x4mm-3000C
PE4302-20MLP 4x4mm-EK
PE4302G-20MLP 4x4mm-75A
PE4302G-20MLP 4x4mm-3000C
20-lead 4x4mm QFN
20-lead 4x4mm QFN
Evaluation Kit
Green 20-lead 4x4mm QFN
Green 20-lead 4x4mm QFN
4302
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70/0056~02D │ UltraCMOS™ RFIC Solutions
Page 10 of 11
PE4302
Product Specification
Sales Offices
United States
Japan
Peregrine Semiconductor Corp.
9450 Carroll Park Drive
San Diego, CA 92121
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel 1-858-731-9400
Fax 1-858-731-9499
Tel: 011-81-3-3502-5211
Fax: 011-81-3-3502-5213
Europe
China
Peregrine Semiconductor Europe
Bâtiment Maine
Peregrine Semiconductor
28G, Times Square,
No. 500 Zhangyang Road,
Shanghai, 200122, P.R. China
Tel: 011-86-21-5836-8276
Fax: 011-86-21-5836-7652
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: 011- 33-1-47-41-91-73
Fax : 011-33-1-47-41-91-73
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS is a trademark of Peregrine Semiconductor
Corp.
Document No. 70/0056~02D │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 11
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