PE43701MLI [PSEMI]
50 Ω RF Digital Attenuator 7-bit, 31.75 dB, DC-4.0 GHz; 50 Ω RF数字衰减器7位， 31.75分贝， DC- 4.0 GHz的
| 型号： | PE43701MLI |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | 50 Ω RF Digital Attenuator 7-bit, 31.75 dB, DC-4.0 GHz |
| 文件： | 总13页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specification
PE43701
50 Ω RF Digital Attenuator
7-bit, 31.75 dB, DC-4.0 GHz
Product Description
Features
The PE43701 is a HaRP™-enhanced, high linearity, 7-bit RF
Digital Step Attenuator (DSA). This highly versatile DSA
covers a 31.75 dB attenuation range in 0.25 dB steps. The
Peregrine 50Ω RF DSA provides a parallel or serial-
addressable CMOS control interface. It maintains high
attenuation accuracy over frequency and temperature and
exhibits very low insertion loss and low power consumption.
Performance does not change with Vdd due to on-board
regulator. This next generation Peregrine DSA is available in a
5x5 mm 32-lead QFN footprint.
• HaRP™-enhanced UltraCMOS™ device
• Attenuation: 0.25 dB steps to 31.75 dB
• High Linearity: Typical +59 dBm IIP3
• Excellent low-frequency performance
• 3.3 V or 5.0 V Power Supply Voltage
• Fast switch settling time
• Programming Modes:
• Direct Parallel
• Latched Parallel
• Serial-Addressable: Program up to
eight addresses 000 - 111
The PE43701 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
• High-attenuation state @ power-up (PUP)
• CMOS Compatible
Figure 1. Package Type
• No DC blocking capacitors required
• Packaged in a 32-lead 5x5x0.85 mm QFN
32-lead 5x5x0.85 mm QFN Package
Figure 2. Functional Schematic Diagram
Switched Attenuator Array
RF Input
RF Output
7
Parallel Control
Serial In
Control Logic Interface
CLK
LE
A0
A1
A2
P/S
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©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 13
PE43701
Product Specification
Table 1. Electrical Specifications @ +25°C, VDD = 3.3 V or 5.0 V
Parameter
Test Conditions
Frequency
Min
Typical
Max
Units
Frequency Range
Attenuation Range
Insertion Loss
DC – 4
0 – 31.75
1.9
GHz
dB
0.25 dB Step
DC ≤ 4 GHz
2.4
dB
±(0.2+1.5%)
±(0.15+4%)
±(0.25+4.5%)
0 dB - 7.75 dB Attenuation settings
8 dB - 31.75 dB Attenuation settings
0 dB - 31.75 dB Attenuation settings
DC < 3 GHz
DC < 3 GHz
3 GHz ≤ 4 GHz
dB
dB
dB
Attenuation Error
Return Loss
DC - 4 GHz
DC - 4 GHz
20 MHz - 4 GHz
20 MHz - 4 GHz
1MHz
18
44
dB
deg
Relative Phase
P1dB
All States
Input
30
32
dBm
dBm
dBm
mVpp
IIP3
Two tones at +18 dBm, 20 MHz spacing
59
Typical Spurious Value
Video Feed Through
-110
10
Switching Time
RF Trise/Tfall
50% DC CTRL to 10% / 90% RF
10% / 90% RF
650
400
ns
ns
RF settled to within 0.05 dB of final value
RBW = 5 MHz, Averaging ON.
Settling Time
4
25
µs
Performance Plots
Figure 3. 0.25 dB Step Error vs. Frequency*
Figure 4. 0.25dB Attenuation vs. Attenuation
200 MHz
900 MHz
1800 MHz
2200 MHz
3000 MHz
35
0.500
0.400
0.300
0.200
0.100
0.000
900 MHz
1800 MHz
30
2200 MHz
3800 MHz
25
20
15
10
5
0
0.0
4.0
8.0
12.0
16.0
20.0
24.0
28.0
32.0
0
5
10
15
20
25
30
35
Attenuation Setting (dB.)
Attenuation State
*Monotonicity is held so long as Step-Error does not cross zero
Figure 6. 0.25 dB Attenuation Error vs. Frequency
Figure 5. 0.25 dB Major State Bit Error
0.25dB State
4dB State
0.5 dB State
8dB State
1dB State
2dB State
200 MHz
2200 MHZ
900 MHz
3000 MHz
1800 MHz
4000 MHz
16dB State
31.75dB State
1.500
1.000
0.500
0.000
-0.500
-1.000
-1.500
2.00
1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50
-2.00
0.0
4.0
8.0
12.0
16.0
20.0
24.0
28.0
32.0
0.0
1.0
2.0
Frequency (GHz)
3.0
4.0
Attenuation Setting (dB.)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0243-04 │ UltraCMOS™ RFIC Solutions
Page 2 of 13
PE43701
Product Specification
Figure 7. Insertion Loss vs. Temperature
Figure 8. Input Return Loss vs. Attenuation:
T = +25C
0dB
4dB
0.25dB
8dB
0.5dB
16dB
1dB
31.75dB
2dB
-40C
+25C
+85C
0
-0.5
-1
0
-10
-20
-30
-40
-50
-60
-70
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
Frequency (GHz)
0
1
2
3
4
5
6
7
8
9
Frequency (GHz.)
Figure 10. Input Return Loss vs. Temperature:
16dB State
Figure 9. Output Return Loss vs. Attenuation:
T = +25C
0dB
4dB
0.25dB
8dB
0.5dB
16dB
1dB
31.75dB
2dB
-40C
25C
85C
0
-10
-20
-30
-40
-50
-60
0
-5
-10
-15
-20
-25
-30
-35
-40
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
Frequency (GHz.)
Frequency (GHz.)
Figure 12. Relative Phase vs. Frequency
Figure 11. Output Return Loss vs. Temperature:
16dB State
0dB
4dB
0.25dB
8dB
0.5dB
16dB
1dB
31.75dB
2dB
-40C
25C
85C
120
100
80
60
40
20
0
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
Frequency (GHz.)
Frequency (GHz.)
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Page 3 of 13
PE43701
Product Specification
Figure 13. Relative Phase vs. Temperature:
31.75dB State
Figure 14. Attenuation Error vs. Attenuation
Setting: 900 MHz
900 MHz @ T=+25 C
900 MHz @ T= -40C
900 MHz @ T= +85C
900 MHz
1800 MHz
3000 MHz
0.500
0.300
35.00
30.00
25.00
20.00
15.00
10.00
5.00
0.100
-0.100
-0.300
-0.500
0.00
-40
-20
0
20
40
60
80
0.0
4.0
8.0
12.0
16.0
20.0
24.0
28.0
32.0
Attenuation Setting (dB.)
Temperature (Deg. C.)
Figure 16. Attenuation Error vs. Attenuation
Setting: 3000 MHz
Figure 15. Attenuation Error vs. Attenuation
Setting: 1800 MHz
1800 MHz @ T= +25C
1800 MHz @ T= -40C
1800 MHz @ T= +85C
3000 MHz@ T= +25C
3000 MHz @ T= -40C
3000 MHz@ T= +85C
0.500
0.300
0.100
-0.100
-0.300
-0.500
0.500
0.300
0.100
-0.100
-0.300
-0.500
0.0
4.0
8.0
12.0
16.0
20.0
24.0
28.0
32.0
0.0
4.0
8.0
12.0
16.0
20.0
24.0
28.0
32.0
Attenuation Setting (dB.)
Attenuation Setting (dB.)
Figure 17. Input IP3 vs. Frequency
0dB
4dB
0.25dB
8dB
0.5dB
16dB
1dB
31.75dB
2dB
70
65
60
55
50
45
40
35
30
0
500
1000
1500
2000
2500
3000
3500
4000
4500
Frequency (MHz.)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0243-04 │ UltraCMOS™ RFIC Solutions
Page 4 of 13
PE43701
Product Specification
Figure 18. Pin Configuration (Top View)
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating.
32 31 30 29 28 27 26 25
NC
VDD
CLK
LE
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
P/S
A1
Latch-Up Avoidance
A0
A2
Exposed
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
GND
GND
RF1
GND
GND
GND
RF2
GND
Solder pad
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE43701 in
the 5x5 QFN package is MSL1.
9
10 11 12 13 14 15 16
Switching Frequency
The PE43701 has a maximum 25 kHz switching rate.
Switching rate is defined to be the speed at which the
DSA can be toggled across attenuation states.
Table 2. Pin Descriptions
Pin No.
Pin Name
Description
Exposed Solder Pad Connection
1
2
3
4
N/C
VDD
P/S
A0
No Connect
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Power supply pin
Serial/Parallel mode select
Address Bit A0 (LSB)
5, 6, 8-17,
19, 20
GND
Ground
7
18
RF1
RF2
A2
RF1 port
RF2 port
21
Address Bit A2
22
A1
Address Bit A1
23
LE
Latch Enable input
24
CLK
SI
Serial interface clock input
Serial Interface input
Attenuation control bit, 16 dB
Attenuation control bit, 8 dB
Attenuation control bit, 4 dB
Attenuation control bit, 2 dB
Attenuation control bit, 1 dB
Attenuation control bit, 0.5 dB
Attenuation control bit, 0.25 dB
Ground for proper operation
25
26
C16
C8
27
28
C4
29
C2
30
C1
31
C0.5
C0.25
GND
32
Paddle
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Page 5 of 13
PE43701
Product Specification
Table 3. Operating Ranges
Table 4. Absolute Maximum Ratings
Parameter
Min
Typ
3.3
5.0
70
Max
Units
V
Symbol
VDD
Parameter/Conditions
Power supply voltage
Min
-0.3
-0.3
Max
6.0
Units
V
DD Power Supply Voltage
DD Power Supply Voltage
3.0
V
V
V
5.5
350
5.5
V
VI
Voltage on any Digital input
5.8
Input power (50Ω)
1 Hz ≤ 20 MHz
IDD Power Supply Current
Digital Input High
µA
V
PIN
TST
See fig. 19 dBm
20 MHz ≤ 4 GHz
+23
dBm
2.6
Storage temperature range
-65
150
°C
P
IN Input power (50Ω):
1 Hz ≤ 20 MHz
20 MHz ≤ 4 GHz
See fig. 19
dBm
dBm
+23
ESD voltage (HBM)1
ESD voltage (Machine Model)
500
100
V
V
VESD
T
OP Operating temperature
-40
0
25
85
°C
range
Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
Digital Input Low
1
V
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Digital Input Leakage1
15
µA
Note 1. Input leakage current per Control pin
Figure 19. Maximum Power Handling Capability: Z0 = 50 Ω
30.0
25.0
20.0
15.0
10.0
5.0
0.0
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
1.0E+08
1.0E+09
Hz
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0243-04 │ UltraCMOS™ RFIC Solutions
Page 6 of 13
PE43701
Product Specification
Table 5. Control Voltage
Table 8. Address Word Truth Table
State
Bias Condition
Address Word
Address
Setting
A7
(MSB)
0 to +1.0 Vdc at 2 µA (typ)
Low
A6
A5
A4
A3
A2
A1
A0
+2.6 to +5 Vdc at 10 µA (typ)
High
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
L
000
001
010
011
100
101
110
111
L
H
H
L
Table 6. Latch and Clock Specifications
L
H
L
H
H
H
H
Shift Clock
Latch Enable
Function
L
H
L
0
↑
Shift Register Clocked
H
H
Contents of shift register
transferred to attenuator core
↑
X
H
Table 7. Parallel Truth Table
Table 9. Attenuation Word Truth Table
Attenuation Word
Parallel Control Setting
Attenuation
Setting
RF1-RF2
Attenuation
Setting
RF1-RF2
D0
(LSB)
D6
D7
D5
D4
D3
D2
D1
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
L
H
L
L
L
L
L
H
L
L
H
L
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
L
H
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
L
H
Reference I.L.
0.25 dB
0.5 dB
1 dB
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
L
H
L
L
L
L
L
H
L
L
H
L
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
L
H
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
L
H
Reference I.L.
0.25 dB
0.5 dB
1 dB
2 dB
2 dB
4 dB
4 dB
8 dB
8 dB
16 dB
16 dB
31.75 dB
31.75 dB
Table 10. Serial-Addressable Register Map
Bits can either be set to logic high or logic low
MSB (last in)
LSB (first in)
Q15
Q14
A6
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
D4
Q3
D3
Q2
D2
Q1
Q0
A7
A5
A4
A3
A2
A1
A0
D7
D6
D5
D1
D0
Address Word
Attenuation Word
Attenuation Word is derived directly from the attenuation value. For example, to program the 18.25 dB state
at address 3:
Address word: XXXXX011
Attenuation Word: Multiply by 4 and convert to binary → 4 * 18.25 dB → 73 → X1001001
Serial Input: XXXXX011X1001001
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Page 7 of 13
PE43701
Product Specification
Programming Options
The serial-addressable interface is controlled
Parallel/Serial Selection
using three CMOS-compatible signals: Serial-In
(SI), Clock (CLK), and Latch Enable (LE). The SI
and CLK inputs allow data to be serially entered
into the shift register. Serial data is clocked in
LSB first, beginning with the attenuation word.
Either a parallel or serial interface can be used to
control the PE43701. The P/S bit provides this
selection, with P/S=LOW selecting the parallel
interface and P/S=HIGH selecting the serial
interface.
The shift register must be loaded while LE is held
LOW to prevent the attenuator value from
Parallel Mode Interface
The parallel interface consists of seven CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 7.
changing as data is entered. The LE input should
then be toggled HIGH and brought LOW again,
latching the new data into the DSA. Address word
and attenuation word truth tables are listed in
Table 8 & Table 9, respectively. A programming
example of the serial-addressable register is
illustrated in Table 10. The serial-addressable
timing diagram is illustrated in Fig. 20.
The parallel interface timing requirements are
defined by Fig. 21 (Parallel Interface Timing
Diagram), Table 12 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
For latched-parallel programming the Latch
Enable (LE) should be held LOW while changing
attenuation state control values, then pulse LE
HIGH to LOW (per Fig. 21) to latch new
attenuation state into device.
Power-up Control Settings
The PE43701 will always initialize to the maximum
attenuation setting (31.75 dB) on power-up for
both the serial-addressable and latched-parallel
modes of operation and will remain in this setting
until the user latches in the next programming
word. In direct-parallel mode, the DSA can be
preset to any state within the 31.75 dB range by
pre-setting the parallel control pins prior to power-
up. In this mode, there is a 400-µs delay between
the time the DSA is powered-up to the time the
desired state is set. During this power-up delay,
the device attenuates to the maximum attenuation
setting (31.75 dB) before defaulting to the user
defined state. If the control pins are left floating in
this mode during power-up, the device will default
to the minimum attenuation setting (insertion loss
state).
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
Serial-Addressable Interface
The serial-addressable interface is a 16-bit serial-
in, parallel-out shift register buffered by a
transparent latch. The 16-bits make up two words
comprised of 8-bits each. The first word is the
Attenuation Word, which controls the state of the
DSA. The second word is the Address Word,
which is compared to the static (or programmed)
logical states of the A0, A1 and A2 digital inputs. If
there is an address match, the DSA changes
state; otherwise its current state will remain
unchanged. Fig. 20 illustrates a example timing
diagram for programming a state. It is
recommended that all parallel control inputs be
grounded when the DSA is used in Serial Mode.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0243-04 │ UltraCMOS™ RFIC Solutions
Page 8 of 13
PE43701
Product Specification
Figure 20. Serial-Addressable Timing Diagram
Bits can either be set to logic high or logic low
DI[6:0]
ADD[2:0]
P/S
TDISU
VALID
TASU
TDIH
TAH
TPSSU
TPSH
D[0]
D[1]
TCLKL
D[2]
D[3]
D[4]
D[5]
D[6]
A[0]
A[1]
A[2]
SI
TSISU
TSIH
CLK
LE
TCLKH
TLESU
TLEPW
TPD
VALID
DO[6:0]
Figure 21. Latched-Parallel/Direct-Parallel Timing Diagram
P/S
TPSSU
TPSH
VALID
DI[6:0]
TDISU
TDIH
LE
TLEPW
VALID
TPD
DO[6:0]
TDIPD
Table 11. Serial Interface AC Characteristics
VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Table 12. Parallel and Direct Interface AC
Characteristics
VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Min Max Unit
FCLK
TCLKH
TCLKL
Serial clock frequency
Serial clock HIGH time
Serial clock LOW time
-
10
-
MHz
ns
Symbol
Parameter
Min Max Unit
30
30
Latch Enable minimum
pulse width
TLEPW
30
-
ns
-
ns
Last serial clock rising edge
setup time to Latch Enable
rising edge
TDISU
TDIH
TPSSU
TPSIH
Parallel data setup time
Parallel data hold time
Parallel/Serial setup time
Parallel/Serial hold time
100
100
100
100
-
-
-
-
ns
ns
ns
ns
TLESU
10
-
ns
TLEPW
TSISU
TSIH
Latch Enable min. pulse width
Serial data setup time
Serial data hold time
30
10
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
-
TDISU
TDIH
Parallel data setup time
Parallel data hold time
Address setup time
100
100
100
100
100
100
-
-
Digital register delay
(internal)
TPD
-
-
10
5
ns
ns
-
Digital register delay
(internal, direct mode only)
TASU
TAH
-
TDIPD
Address hold time
-
TPSSU
TPSH
TPD
Parallel/Serial setup time
Parallel/Serial hold time
Digital register delay (internal)
-
-
10
Note:
fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked
at 10 MHz to verify fclk specification.
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Page 9 of 13
PE43701
Product Specification
Figure 22. Evaluation Board Layout
Peregrine Specification 101-0312
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE43701 Digital Step Attenuator.
Direct-Parallel Programming Procedure
For automated direct-parallel programming,
connect the test harness provided with the EVK
from the parallel port of the PC to the J1 & Serial
header pin and set the D0-D6 SP3T switches to the
‘MIDDLE’ toggle position. Position the Parallel/
Serial (P/S) select switch to the Parallel (or left)
position. The evaluation software is written to
operate the DSA in either Parallel or Serial-
Addressable Mode. Ensure that the software is set
to program in Direct-Parallel mode. Using the
software, enable or disable each setting to the
desired attenuation state. The software
Note: Reference Fig. 23 for Evaluation Board Schematic
automatically programs the DSA each time an
attenuation state is enabled or disabled.
Serial-Addressable Programming Procedure
Position the Parallel/Serial (P/S) select switch to
the Serial (or right) position. Prior to
For manual direct-parallel programming,
disconnect the test harness provided with the EVK
from the J1 and Serial header pins. Position the
Parallel/Serial (P/S) select switch to the Parallel (or
left) position. The LE pin on the Serial header must
be tied to VDD. Switches D0-D6 are SP3T switches
which enable the user to manually program the
parallel bits. When any input D0-D6 is toggled
‘UP’, logic high is presented to the parallel input.
When toggled ‘DOWN’, logic low is presented to
the parallel input. Setting D0-D6 to the ‘MIDDLE’
toggle position presents an OPEN, which forces an
on-chip logic low. Table 9 depicts the parallel
programming truth table and Fig. 21 illustrates the
parallel programming timing diagram.
programming, the user must define an address
setting using the ADD header pin. Jump the
middle pins on the ADD header A0-A2 (or lower)
row of pins to set logic high, or jump the middle
pins to the upper row of pins to set logic low. If
the ADD pins are left open, then 000 become the
default address. The evaluation software is
written to operate the DSA in either Parallel or
Serial-Addressable Mode. Ensure that the
software is set to program in Serial-Addressable
mode. Using the software, enable or disable each
setting to the desired attenuation state. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
Latched-Parallel Programming Procedure
For automated latched-parallel programming, the
procedure is identical to the direct-parallel method.
The user only must ensure that Latched-Parallel is
selected in the software.
For manual latched-parallel programming, the
procedure is identical to direct-parallel except now
the LE pin on the Serial header must be logic low
as the parallel bits are applied. The user must then
pulse LE from 0V to VDD and back to 0V to latch the
programming word into the DSA. LE must be logic
low prior to programming the next word.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0243-04 │ UltraCMOS™ RFIC Solutions
Page 10 of 13
PE43701
Product Specification
Figure 23. Evaluation Board Schematic
Peregrine Specification 102-0381
Note: Capacitors C1-C8, C13, & C14 may be omitted.
Figure 24. Package Drawing
QFN 5x5 mm
MAX
NOM
MIN
0.900
0.850
0.800
A
Document No. 70-0243-04 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 13
PE43701
Product Specification
Figure 25. Tape and Reel Drawing
Tape Feed Direction
Pin 1
Top of
Device
Device Orientation in Tape
Figure 26. Marking Specifications
43701
YYWW
ZZZZZ
YYWW = Date Code
ZZZZZ = Last five digits of Lot Number
Table 13. Ordering Information
Order Code Part Marking
Description
Package
Shipping Method
Bulk or tape cut from reel
3000 units / T&R
PE43701MLI
PE43701MLI-Z
EK43701-01
43701
43701
43701
PE43701 G - 32QFN 5x5mm-75A
PE43701 G – 32QFN 5x5mm-3000C
PE43701 G – 32QFN 5x5mm-EK
Green 32-lead 5x5mm QFN
Green 32-lead 5x5mm QFN
Evaluation Kit
1 / Box
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0243-04 │ UltraCMOS™ RFIC Solutions
Page 12 of 13
PE43701
Product Specification
Sales Offices
The Americas
Peregrine Semiconductor Corporation
Peregrine Semiconductor, Asia Pacific (APAC)
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
9380 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
Peregrine Semiconductor, Korea
#B-2607, Kolon Tripolis, 210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-943 South Korea
Tel: +82-31-728-3939
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
Fax: +82-31-728-3940
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-4741-9173
Fax : +33-1-4741-9173
Peregrine Semiconductor K.K., Japan
Teikoku Hotel Tower 10B-6
1-1-1 Uchisaiwai-cho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
High-Reliability and Defense Products
Americas
San Diego, CA, USA
Phone: 858-731-9475
Fax: 848-731-9499
Europe/Asia-Pacific
Aix-En-Provence Cedex 3, France
Phone: +33-4-4239-3361
Fax: +33-4-4239-7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks
of Peregrine Semiconductor Corp.
Document No. 70-0243-04 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 13 of 13
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