PE64102_技术文档

Product Specification

PE64102

UltraCMOS^®Digitally Tunable Capacitor

(DTC) 100 - 3000 MHz

General Description

The PE64102 is a DuNE™-enhanced Digitally Tunable

Capacitor (DTC) based on Peregrine’s UltraCMOS^®

technology. DTC products provide a monolithically

integrated impedance tuning solution for demanding

RF applications. They also offer a linear capacitance

change versus tuning state and excellent harmonic

performance compared to varactor-based tunable

solutions.

Features

 3-wire (SPI compatible) 8-bit serial interface

with built-in bias voltage generation and

stand-by mode for reduces power

consumption

 DuNE^TM-enhanced UltraCMOS^®device

 5-bit 32-state Digitally Tunable Capacitor

This highly versatile product can be mounted in series

or shunt configurations and uses a 3-wire (SPI

compatible) serial interface. It has a high ESD rating of

2 kV HBM on all ports making this the ultimate in

integration and ruggedness. The DTC will be offered in

a standard 12-lead 2.0 x 2.0 x 0.55 mm QFN

commercial package.

 C = 1.88 - 14.0 pF (7.4:1 tuning ratio) in

discrete 391 fF steps

 RF power handing (up to 26 dBm, 6 V_PKRF)

and high linearity

 High quality factor

 Wide power supply range (2.3 to 3.6V) and

low current consumption

Peregrine’s DuNE™ technology enhancements deliver

high linearity and exceptional harmonics performance.

It is an innovative feature of the UltraCMOS^®process,

providing performance superior to GaAs with the

economy and integration of conventional CMOS.

(typ. I_DD= 30 µA @ 2.8V)

 Optimized for shunt configuration, but can

also be used in series configuration

 Excellent 2 kV HBM ESD tolerance on

all pins

 Applications include:

 Antenna tuning

Figure 1. Functional Block Diagram

 Tunable filters

 Phase shifters

 Impedance matching

Figure 2. Package Type

12-lead 2 x 2 x 0.55 mm QFN

71-0066-01

Document No. 70-0428-01 │ www.psemi.com

Page 1 of 13

PE64102

Product Specification

Table 1. Electrical Specifications @ 25°C, V_DD= 2.8V

Parameter

Operating Frequency Range ⁷

Minimum Capacitance

Maximum Capacitance

Tuning Ratio

Configuration

Condition

Min

100

Typ

Max

3000

+10%

Unit

MHz

pF

Both

Shunt ⁶

State = 00000, 100 MHz (RF+ to Grounded RF-)

State = 11111, 100 MHz (RF+ to Grounded RF-)

C_max/C_min, 100 MHz

-10%

1.88

14.0

Shunt ⁶

pF

Shunt ⁶

7.4:1

0.391

Step Size

Shunt ⁶

5 bits (32 states), constant step size (100 MHz)

pF

470 - 582 MHz with L_sremoved

698 - 960 MHz, with L_sremoved

1710 - 2170 MHz, with L_sremoved

50

28

1

Quality Factor (C_min

)

Shunt ⁶

470 - 582 MHz with L_sremoved

698 - 960 MHz, with L_sremoved

1710 - 2170 MHz, with L_sremoved

25

20

5

1

Quality Factor (C_max

)

Shunt ⁶

Shunt ⁷

Shunt ⁶

State 00000

State 11111

4.7

1.6

Self Resonant Frequency

Harmonics (2_foand 3_fo) ⁴

GHz

470 to 582 MHz, Pin +26 dBm, 50Ω

698 to 915 MHz, Pin +26 dBm, 50Ω

1710 to 1910 MHz, Pin +26 dBm, 50Ω

-36

dBm

470 to 582 MHz, Pin +20 dBm, 50Ω

698 to 915 MHz, Pin +20 dBm, 50Ω

1710 to 1910 MHz, Pin +20 dBm, 50Ω

-36

dBm

Series ⁵

IIP3 = (Pblocker + 2*Ptx - [IMD3]) / 2, where IMD3 = -95 dBm,

Ptx = +20 dBm and Pblocker = -15 dBm

3rd Order Intercept Point

Switching Time ^{2, 3}

Start-up Time ²

Shunt ⁶

60

2

dBm

µs

State change to 10/90% delta capacitance between only two

states

10

20

Time from V_DDwithin specification to all performances within

specification

5

µs

State change from standby mode to RF state to all

performances within specification

Wake-up Time ^2,3

5

µs

Note: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit

Q = X_C/ R = (X-X_L) / R, where X = X_L+ X_C, X_L= 2*pi*f*L, X_C= -1 / (2*pi*f*C), which is equal to removing the effect of parasitic inductance L_S

2. DC path to ground at RF+ and RF– must be provided to achieve specified performance

3. State change activated on falling edge of SEN following data word

4. Between 50Ω ports in series or shunt configuration using a pulsed RF input with 4620 vs period, 50% duty cycle, measured per 3GPPTS45.005

5. In series configuration the greater RF power or higher RF voltage should be applied to RF+

6. RF- should be connected to ground

7. DTC operation above SRF is possible

Document No. 70-0428-01 │ UltraCMOS^®RFIC Solutions

Page 2 of 13

PE64102

Product Specification

Table 3. Operating Ranges¹

Figure 3. Pin Configuration (Top View)

Parameter

Symbol Min

Typ

Max Units

Pin 1

V_DDSupply Voltage

V_DD

I_DD

2.3

2.8

3.6

75

V

12

11

10

I_DDPower Supply Current

(Normal mode) ⁶

30

20

µA

I_DDPower Supply Current

(Standby mode) ⁶

I_DD

45

µA

RF+

8

1

2

3

1

2

3

9

SEN

GND

SCLK

Control Voltage High

V_IH

V_IL

1.2

0

3.1

0.2

V

13

GND

RF-

8

Control Voltage Low

7

Peak Operating RF Voltage ⁵

V_Pto V_M

6

V_PK

7

6

V_Pto RFGND

V

_Mto RFGND

RF Input Power (50Ω) ^{3, 4, 5}

shunt

series

+26

+20

dBm

4

5

6

Input Control Current

I_CTL

T_OP

T_ST

1

10

µA

°C

Operating Temperature Range

Storage Temperature Range

-40

-65

+85

Table 2. Pin Descriptions

+150

Pin #

Pin Name

Description

Notes: 1. Operation should be restricted to the limits in the Operating Ranges table

2. The DTC is active when STBY is low (set to 0) and in low-current

stand-by mode when high (set to 1)

1

2

SEN

GND

SCLK

VDD

GND

RF-

Serial Enable

3. Maximum CW power available from a 50Ω source in shunt configuration

4. Maximum CW power available from a 50Ω source in series configuration

5. RF+ to RF- and RF+ and/or RF- to ground. Cannot exceed 6 V_PKor max

RF input power (whichever occurs first)

Digital and RF Ground

Serial Interface Clock Input

Power Voltage

3

6. I_DDcurrent typical value is based on V_DD= 2.8V. Max I_DDis based on

4

V_DD= 3.6V

5

Digital and RF Ground

Negative RF Port ¹

Table 4. Absolute Maximum Ratings

6

Negative RF Port ¹

Symbol

Parameter/Conditions

Min

Max

Units

7

RF-

V_DD

Power supply voltage

-0.3

4.0

V

8

GND

RF+

Digital and RF Ground ³

Positive RF Port ²

9

V_I

Voltage on any DC input

-0.3

4.0

2000

100

V

10

11

12

13

RF+

Positive RF Port ²

ESD Voltage (HBM, MIL_STD

883 Method 3015.7)

V_ESD

GND

SDAT

GND

Digital and RF Ground

Serial Interface Data Input

Digital and RF Ground ³

ESD Voltage (MM, JEDEC

JESD22-A115-A)

Notes: 1. Pins 6 and 7 must be tied together on PCB board to reduce

inductance

Exceeding absolute maximum ratings may cause

permanent damage. Operation between operating

range maximum and absolute maximum for

extended periods may reduce reliability.

2. Pins 9 and 10 must be tied together on PCB board to reduce

inductance

3. Pins 2, 5, 8, 11 and 13 must be connected together on PCB

Moisture Sensitivity Level

Electrostatic Discharge (ESD) Precautions

The Moisture Sensitivity Level rating for the

PE64102 in the 12-lead 2 x 2 QFN package is

MSL1.

When handling this UltraCMOS^®device, observe

the same precautions that you would use with other

ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the specified rating.

Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS^®

devices are immune to latch-up.

Document No. 70-0428-01 │ www.psemi.com

Page 3 of 13

PE64102

Product Specification

Performance Plots @ 25°C and 2.8V unless otherwise specified

Figure 4. Measured Shunt C (@ 100 MHz) vs

State (temperature)

Figure 5. Measured Shunt S₁₁(major states)

Figure 7. Measured Series S₁₁/S₂₂(major states)

Figure 6. Measured Step Size vs State

(frequency)

Figure 8. Measured Shunt C vs

Frequency (major states)

Figure 9. Measured Series S₂₁vs Frequency

(major states)

Document No. 70-0428-01 │ UltraCMOS^®RFIC Solutions

Page 4 of 13

PE64102

Product Specification

Figure 10. Measured Shunt Q vs

Frequency (major states)

Figure 11. Measured 2-Port Shunt S21 vs

Frequency (major states)

Figure 12. Measured Self Resonance

Frequency vs State

Figure 13. Measured Shunt Q vs State

Measured Q vs. State

160

100 MHz

470 MHz

698 MHz

1710 MHz

140

120

100

80

60

40

20

0

5

10

15

State

20

25

30

Document No. 70-0428-01 │ www.psemi.com

Page 5 of 13

PE64102

Product Specification

Serial Interface Operation and Sharing

More than 1 DTC can be controlled by one

The PE64102 is controlled by a three wire SPI-

compatible interface. As shown in Figure 14, the

serial master initiates the start of a telegram by

driving the SEN (Serial Enable) line high. Each bit

of the 8-bit telegram is clocked in on the rising

edge of the SCL (Serial Clock) line. SDA bits are

clocked by most significant bit (MSB) first, as

shown in Table 5 and Figure 14. Transactions on

SDA (Serial Data) are allowed on the falling edge

of SCL. The DTC activates the data on the falling

edge of SEN. The DTC does not count how many

bits are clocked and only maintains the last 8 bits it

received.

interface by utilizing a dedicated enable (SEN) line

for each DTC. SDA, SCL, and V_DDlines may be

shared as shown in Figure 15. Dedicated SEN

lines act as a chip select such that each DTC will

only respond to serial transactions intended for

them. This makes each DTC change states

sequentially as they are programmed.

Alternatively, a dedicated SDA line with common

SEN can be used. This allows all DTCs to change

states simultaneously, but requires all DTCs to be

programmed even if the state is not changed.

Figure 14. Serial Interface Timing Diagram (oscilloscope view)

t_R

t_EPW

t_ESU

t_DSUt_DHD

t_F

1/f_CLK

t_EHD

SEN

SCL

b7

b0

b6

b5

b4

b3

b2

b1

b0

SDA

D_m-2<7:0>

D_m-1<7:0>

D_m<7:0>

DTC Data

Document No. 70-0428-01 │ UltraCMOS^®RFIC Solutions

Page 6 of 13

PE64102

Product Specification

Table 5. 6-Bit Serial Programming Register Map

Figure 15. Recommended Bus sharing

DTC 1

RF+

b7

b6

b5

STB¹

b4

b3

b2

b1

b0

0

d4

d3

d2

d1

d0

V_DD

SDA

SCL

SEN

SDA

SCL

MSB (first in)

LSB (last in)

SEN1

SEN2

Note: 1. The DTC is active when low (set to 0) and in low-current stand-by

mode when high (set to 1)

DGND

GND

RF-

Table 6. Serial Interface AC Characteristics

2.3V < V_DD< 3.6V, -40 °C < T_A< +85 °C, unless otherwise specified

DTC 2

RF+

Symbol

f_CLK

t_R

Parameter

Min Max Unit

V_DD

SDA

SCL

SEN

Serial Clock Frequency

26

6.5

MHz

ns

SCL, SDA, SEN Rise Time

SCL, SDA, SEN Fall Time

SEN rising edge to SCL rising edge

t_F

ns

t_ESU

t_EHD

t_DSU

t_DHD

t_EOW

19.2

ns

DGND

GND

SCL rising edge to SEN falling edge 19.2

ns

RF-

SDA valid to SCL rising edge

SDA valid after SCL rising edge

13.2

ns

SEN falling edge to SEN rising edge 38.4

ns

Document No. 70-0428-01 │ www.psemi.com

Page 7 of 13

PE64102

Product Specification

Figure 16. Equivalent Circuit Model Schematic

Equivalent Circuit Model Description

The DTC Equivalent Circuit Model includes all

parasitic elements and is accurate in both Series

and Shunt configurations, reflecting physical circuit

behavior accurately and providing very close

correlation to measured data. It can easily be used

in circuit simulation programs. Simple equations

are provided for the state dependent parameters.

The Tuning Core capacitance C_Srepresents

capacitance between RF+ and RF- ports. It is

linearly proportional to state (0 to 31 in decimal) in

a discrete fashion. The Series Tuning Ratio is

Table 7. Equivalent Circuit Model Parameters

Variable

C_S

Equation (state = 0, 1, 2…31)

0.394*state + 1.456

15/(state+15/(state+0.4)) + 0.4

-0.0026*state + 0.4155

0.0029*state + 0.4914

4

Unit

pF

Ω

defined as C_Smax/C_Smin

.

R_S

C_P1and C_P2represent the circuit and package

parasitics from RF ports to GND. In shunt

configuration the total capacitance of the DTC is

higher due to parallel combination of C_Pand C_S. In

Series configuration, C_Sand C_Pdo not add in

parallel and the DTC appears as an impedance

transformation network.

C_P1

C_P2

R_P1

R_P2

L_S

pF

Ω

22000 + 6*(state)^3

0.4

Ω

nH

Parasitic inductance due to circuit and package is

modeled as L_Sand causes the apparent

capacitance of the DTC to increase with frequency

until it reaches Self Resonant Frequency (SRF).

The value of SRF depends on state and is

approximately inversely proportional to the square

root of capacitance.

Table 8. Maximum Operating RF Voltage

Condition

V_Pto V_M

Limit

6 V_PK

V_Pto RFGND

V_Mto RFGND

The overall dissipative losses of the DTC are

modeled by R_S, R_P1and R_P2resistors. The

parameter R_Srepresents the Equivalent Series

Resistance (ESR) of the tuning core and is

dependent on state. R_P1and R_P2represent losses

due to the parasitic and biasing networks.

Document No. 70-0428-01 │ UltraCMOS^®RFIC Solutions

Page 8 of 13

PE64102

Product Specification

Table 9. Equivalent Circuit Data

State

DTC Core

Parasitic Elements

Binary

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Decimal

Cs [pF] Rs [Ω] Cp1 [pF] Cp2 [pF]

Rp2 [kΩ]

22.0

Ls [nH] Rp1 [Ω]

0

1.40

1.79

2.19

2.58

2.98

3.37

3.76

4.16

4.55

4.95

5.34

5.73

6.13

6.52

6.92

7.31

7.70

8.10

8.49

8.89

9.28

9.67

10.07

10.46

10.86

11.25

11.64

12.04

12.43

12.83

13.22

13.61

0.80

1.68

2.22

2.42

2.33

2.20

2.06

1.93

1.82

1.71

1.62

1.54

1.46

1.40

1.34

1.29

1.24

1.20

1.16

1.12

1.09

1.06

1.03

1.01

0.99

0.96

0.94

0.93

0.91

0.89

0.88

0.42

0.41

0.40

0.39

0.38

0.37

0.36

0.35

0.34

0.33

0.49

0.50

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

1

22.0

2

22.0

3

22.2

4

22.4

5

22.8

6

23.3

7

24.1

8

25.1

9

26.4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

28.0

30.0

32.4

35.2

38.5

42.3

0.40

4.0

46.6

51.5

55.0

63.2

70.0

77.6

85.9

95.0

104.9

115.8

127.5

140.1

153.7

168.3

184.0

200.7

Document No. 70-0428-01 │ www.psemi.com

Page 9 of 13

PE64102

Product Specification

Evaluation Board

Figure 17. Evaluation Board Layout

The 101-0700 Evaluation Board (EVB) was

designed for accurate measurement of the DTC

impedance and loss. Two configurations are

available: 1 Port Shunt (J3) and 2 Port Shunt (J4,

J5). Three calibration standards are provided. The

open (J2) and short (J1) standards (104 ps delay)

are used for performing port extensions and

accounting for electrical length and transmission

line loss. The Thru (J9, J10) standard can be used

to estimate PCB transmission line losses for scalar

de-embedding of the 2 Port Shunt configuration (J4,

J5).

The board consists of a 4 layer stack with 2 outer

layers made of Rogers 4350B (ε_r= 3.48) and 2

inner layers of FR4 (ε_r= 4.80). The total thickness

of this board is 62 mils (1.57 mm). The inner layers

provide a ground plane for the transmission lines.

Each transmission line is designed using a coplanar

waveguide with ground plane (CPWG) model using

a trace width of 32 mils (0.813 mm), gap of 15 mils

(0.381 mm), and a metal thickness of 1.4 mils

(0.036 mm).

101-0700

Document No. 70-0428-01 │ UltraCMOS^®RFIC Solutions

Page 10 of 13

PE64102

Product Specification

Figure 18. Evaluation Board Schematic

U1

PE6410X_QFN_12L_2X2

3

4

6

7

1

R2

R4

DNI

SCLK

VDD

SEN

SDAT

RF+

J3

12

10

9

SMA CONN

R3

DNI

RF-

RF+

J8

14 PIN HEADER

J9

J10

SMA CONN

14

12

10

8

13

11

9

THRU

14

12

10

8

13

SDA

SEN

SCL

11

9

7

6

5

6

5

4

2

3

4

2

3

1 PORT SHUNT

VDD

1

J2

SMA CONN

OPEN

TP4

J1

C11

C10

C9

C3

SMA CONN

SHORT

100pF

TP5

U2

PE6410X_QFN_12L_2X2

3

1

R13

R14

DNI

SCLK

VDD

SEN

4

6

7

12

SDAT

R1

DNI

10

9

J5

RF-

RF+

SMA CONN

J11

14 PIN HEADER

J4

SMA CONN

14

12

10

8

13

14

12

10

8

13

SDA_1

SEN_1

SCL_1

11

9

11

9

7

6

5

6

5

4

2

3

4

2

3

2 PORT SHUNT

VDD_1

1

C14

100pF

C13

100pF

C12

100pF

C7

100pF

102-0833

Document No. 70-0428-01 │ www.psemi.com

Page 11 of 13

PE64102

Product Specification

Figure 19. Package Drawing

12-lead 2 x 2 x 0.55 mm QFN

Figure 20. Top Marking Specifications

Marking Spec

Symbol

Package

Marking

Definition

PPZZ

YWW

PP

ZZ

CS

Part number marking for PE64102

Last two digits of lot code

00-99

Last digit of year, starting from 2009

(0 for 2010, 1 for 2011, etc)

Y

0-9

WW

01-53

Work week

17-0112

Document No. 70-0428-01 │ UltraCMOS^®RFIC Solutions

Page 12 of 13

PE64102

Product Specification

Figure 21. Tape and Reel Specifications

12-lead 2 x 2 x 0.55 mm QFN

Tape Feed Direction

Device Orientation in Tape

Table 10. Ordering Information

Order Code

PE64102MLAA-Z

EK64102-11

Package

12-lead 2 x 2 x 0.55 mm QFN

Evaluation Kit

Description

Package Part in Tape and Reel

Evaluation Kit

Shipping Method

3000 units/T&R

1 Set/Box

Sales Contact and Information

For sales and contact information please visit www.psemi.com.

Advance Information: The product is in a formative or design stage. The datasheet contains design target No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.

specifications for product development. Specifications and features may change in any manner without notice. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,

or in other applications intended to support or sustain life, or in any application in which the failure of the

Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no

liability for damages, including consequential or incidental damages, arising out of the use of its products in

such applications.

The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE

are trademarks of Peregrine Semiconductor Corp.

Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later

date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best

possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to

change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer

Notification Form).

The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use

of this information. Use shall be entirely at the user’s own risk.

Document No. 70-0428-01 │ www.psemi.com

Page 13 of 13


型号：	PE64102
厂家：	Peregrine Semiconductor
描述：	UltraCMOSÂ® Digitally Tunable Capacitor (DTC) 100 - 3000 MHz UltraCMOSÂ®数字可调电容器（ DTC ） 100 - 3000兆赫电容器
文件：	总13页 (文件大小：999K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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