PE64905MLBB-Z [PSEMI]
UltraCMOS® Digitally Tunable Capacitor (DTC) 100 - 3000 MHz; UltraCMOS®数字可调电容器（ DTC ） 100 - 3000兆赫
| 型号： | PE64905MLBB-Z |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | UltraCMOS® Digitally Tunable Capacitor (DTC) 100 - 3000 MHz |
| 文件： | 总11页 (文件大小：610K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specification
PE64905
UltraCMOS® Digitally Tunable Capacitor
(DTC) 100 - 3000 MHz
Product Description
Features
The PE64905 is a DuNE™-enhanced Digitally Tunable
Capacitor (DTC) based on Peregrine’s UltraCMOS®
technology. DTC products provide a monolithically
integrated impedance tuning solution for demanding RF
applications.
2-wire (I2C compatible) Serial Interface
with built-in bias voltage generation and
ESD protection
DuNE™-enhanced UltraCMOS® device
5-bit 32-state Digitally Tunable Capacitor
The PE64905 offers high RF power handling and
ruggedness, while meeting challenging harmonic and
linearity requirements.
Series configuration C = 0.60 - 4.60 pF
(7.7:1 tuning ratio) in discrete 129 fF steps
Shunt configuration C = 1.10 - 5.10 pF
(4.6:1 tuning ratio) in discrete 129 fF steps
This highly versatile product can be used in series or shunt
configurations to support a wide variety of tuning circuit
topologies.
High RF Power Handling (up to 38 dBm,
30 Vpk RF) and High Linearity
Wide power supply range (2.3 to 3.6V)
and low current consumption
(typ. 140 μA at 2.6V)
The device is controlled through the widely supported 2-wire
(I2C compatible) interface and has two selectable addresses
for implementations with multiple DTCs. All decoding and
biasing is integrated on-chip, and no external bypassing, or
filtering components are required.
Excellent 1.5 kV HBM ESD tolerance on
all pins
2 x 2 x 0.45 mm QFN package
Applications include:
Tunable Filter Networks
Tunable Antennas
Peregrine’s DuNE™ technology enables excellent linearity
and exceptional harmonic performance. DuNE devices
deliver performance superior to GaAs devices with the
economy and integration of conventional CMOS.
RFID
Tunable Matching Networks
Phase Shifters
Figure 1. Functional Block Diagram
Wireless Communications
Figure 2. Package Type
10L 2 x 2 x 0.45 mm QFN package
RF-
RF+
ESD
ESD
CMOS Control
Driver and ESD
Serial
Interface
71-0066-01
Document No. 70-0335-06 │ www.psemi.com
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE64905
Product Specification
Table 1. Electrical Specifications @ 25°C, VDD = 2.6V
Parameter
Configuration
Condition
Min
Typ
Max
Units
Operating Frequency Range
Both
100
3000
MHz
0.49
0.99
0.60
1.10
0.71
1.21
Series
Shunt
State = 00000, 100 MHz (RF+ to RF-)
State = 00000, 100 MHz (RF+ to Grounded RF-)
Minimum Capacitance
pF
4.09
4.59
4.60
5.10
5.11
5.61
Series
Shunt
State = 11111, 100 MHz (RF+ to RF-)
State = 11111, 100 MHz (RF+ to Grounded RF-)
Maximum Capacitance
Parasitic Capacitance
Tuning Ratio
pF
pF
Series
All States, 100 MHz (RF+ to GND, RF- to GND)
0.5
7.7:1
4.6:1
Series
Shunt
100 MHz
100 MHz
Step Size
Both
5 bits (32 states), constant step size (100 MHz)
0.129
pF
State = 00000
State = 11111
1.40
1.33
Equivalent Series Resistance
Series
Ω
100 MHz, with Ls removed
1 GHz, with Ls removed
2 GHz, with Ls removed
3 GHz, with Ls removed
10
35
32
25
1
Quality Factor (Cmin
)
Shunt
Shunt
100 MHz, with Ls removed
1 GHz, with Ls removed
2 GHz, with Ls removed
3 GHz, with Ls removed
27
25
11
6
1
Quality Factor (Cmax
)
State 00000
State 11111
7.5
3.1
Self Resonant Frequency
Shunt
Series
GHz
Harmonics (2fo)2
Harmonics (3fo)2
100 MHz - 3 GHz
100 MHz - 3 GHz
-36
-36
dBm
dBm
Input Intercept Point (2nd Order)
Input Intercept Point (3rd Order)
Series
Series
100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing
100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing
105
65
dBm
dBm
50% CTRL to 10/90% delta capacitance between any two
states
Switching Time3, 4
Start-up Time3
Both
Both
Both
12
µs
µs
µs
Time from VDD within specification to all performances within
specification
100
100
State change from standby mode to RF state to all perfor-
mances within specification
Wake-up Time3, 4
Notes: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit.
Q = XC/R = (X-XL)/R, where X = XL+XC , XL = 2*pi*f*L, XC = -1/(2*pi*f*C), which is equal to removing the effect of parasitic inductance LS.
2. In series or shunt between 50Ω ports. Pulsed RF input with 4620 µs period, 50% duty cycle, measured per 3GPP TS 45.005.
3. DC path to ground at RF+ and RF- must be provided to achieve specified performance.
4. State change activated on rising edge of SCL for ACK bit following data word.
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0335-06 │ UltraCMOS® RFIC Solutions
Page 2 of 11
PE64905
Product Specification
Table 4. Absolute Maximum Ratings
Figure 3. Pin Configuration (Top View)
Symbol
VDD
Parameter/Conditions
Power supply voltage
Min
-0.3
-0.3
Max
4.0
Units
V
V
VI
Voltage on any DC input
4.0
ESD Voltage (HBM, MIL_STD
883 Method 3015.7)
VESD
1500
V
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted
to the limits in the Operating Ranges table.
Operation between operating range maximum and
absolute maximum for extended periods may reduce
reliability.
Electrostatic Discharge (ESD) Precautions
Table 2. Pin Descriptions
When handling this UltraCMOS® device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Pin #
Pin Name
RF-
Description
Negative RF Port1
Negative RF Port1
1
2
RF-
3
DGND
VDD
Ground
4
Power supply pin
5
SCL
Serial interface Clock input
Serial Interface Address Input
Serial interface Data input
Positive RF Port1
6
ADDR
SDA
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS®
devices are immune to latch-up.
7
8
RF+
9
RF+
Positive RF Port1
10
GND
RF Ground
Note 1: Pins 1-2 and 8-9 must be tied together on PCB for optimal performance.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE64905 in the 10-lead 2 x 2 x 0.45 mm QFN
package is MSL1.
Table 3. Operating Ranges
Parameter
VDD Supply Voltage
IDD Power Supply Current (VDD = 2.6V)
DD Standby Current (VDD = 2.6V)
IH Control Voltage High
Min Typ Max Units
2.3
2.6
3.6
V
µA
µA
V
140 200
25
I
V
1.2
0
1.8
0
3.6
VIL Control Voltage Low
0.57
V
RF Input Power (50Ω)1
698 - 915 MHz
1710 -1910 MHz
Peak Operating RF Voltage2
+34 dBm
+32 dBm
VP to VM
VP to RFGND
VM to RFGND
30
30
30
Vpk
Vpk
Vpk
TOP Operating Temperature Range
TST Storage Temperature Range
-40
-65
+85
°C
°C
+150
Notes: 1. Maximum Power Available from 50Ω Source. Pulsed RF input with
4620 µS period, 50% duty cycle, measured per 3GPP TS 45.005.
2. Node voltages defined per Equivalent Circuit Model Schematic
(Figure 18). When DTC is used as a part of reactive network, impedance
transformation may cause the internal RF voltages (VP, VM) to exceed Peak
Operating RF Voltage even with specified RF Input Power Levels. For
operation above about +20 dBm (100 mW), the complete RF circuit must
be simulated using actual input power and load conditions, and internal
node voltages (VP, VM in Figure 18) monitored to not exceed 30 Vpk.
Document No. 70-0335-06 │ www.psemi.com
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE64905
Product Specification
Performance Plots @ 25°C and 2.6V unless otherwise specified
Figure 4. Measured Shunt C (@ 100 MHz) vs
State (temperature)
Figure 5. Measured Shunt S11 (major states)
Measured Shunt C vs. State (Temperature)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
C (pF) at +85C
C (pF) at +25C
C (pF) at -40C
Delta C (%) at +85C
Delta C (%) at -40C
2
1
0
-1
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
State
Figure 7. Measured Series S11/S22 (major states)
Figure 6. Measured Step Size vs
State (frequency)
Figure 8. Measured Shunt C vs
Figure 9. Measured Series S21 vs Frequency
(major states)
Frequency (major states)
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0335-06 │ UltraCMOS® RFIC Solutions
Page 4 of 11
PE64905
Product Specification
Figure 10. Measured Shunt Q vs
Figure 11. Measured Shunt Q (state 0) vs
Frequency (major states)
Frequency (temperature)
Q (C0) at +85C
Q (C0) at -40C
Q (C0) at +25C
Delta Q (%) at +85C
Delta Q (%) at -40C
Figure 12. Measured Shunt Q (state 31) vs
Frequency (temperature)
Document No. 70-0335-06 │ www.psemi.com
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
PE64905
Product Specification
Operation at Frequencies Below 100 MHz
The PE64905 may be operated below the 100 MHz
specified minimum operating frequency. The total
capacitance and peak operating RF voltage are de-
rated down to 1 MHz. Figure 13 shows the total
shunt capacitance from 1 MHz through 100 MHz. As
seen in Figure 14, the maximum RF voltage that can
be placed across the RF terminals or across either
RF terminal to Ground is de-rated as a function of
frequency.
Note: Table 1 performance specifications are not guaranteed below 100 MHz.
Figures 13, 14, and 15 reflect performance of a typical PE64905.
Figure 13. Measured Shunt C vs Frequency
(major states, 1 MHz - 100 MHz)
Figure 14. Voltage Derating vs Frequency
(1 MHz - 100 MHz)
Figure 14. Measured Shunt Q vs Frequency
(major states, 1 MHz - 100 MHz)
35
C0
C1
30
25
20
15
10
5
C2
C4
C8
C16
C31
0
0
10
20
30
40
50
60
70
80
90
100
Frequency (MHz)
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0335-06 │ UltraCMOS® RFIC Solutions
Page 6 of 11
PE64905
Product Specification
Serial Interface Operation and Sharing
Please refer to Peregrine Application note AN28 for
more information regarding the interface.
The Bus Master initiates the start of serial
transaction by driving SDA (Serial Data) low while
CLK (Serial Clock) remains high. Each bit of the
18-bit telegram is clocked in on the rising edge of
SCL. Transitions on SDA are allowed only when
SCL is low. The DTC activates the data on the
rising edge of the clock pulse for the
The DTC can be configured for two different
addresses via ADDR pin. Tying ADDR pin to VDD
sets the address to 113. Tying ADDR to GND sets
the address to 112. Data (SDA), Clock (SCL), and
VDD lines may be shared between each DTC.
acknowledgement bit following the data word.
Figure 16. Serial Interface Timing Diagram (oscilloscope view)
Figure 17. Recommended Bus Sharing
Table 5. Register Map
b7
b6
b5
b4
b3
b2
b1
b0
0
0
STB*
d4
d3
d2
d1
d0
Note 1: The DTC is active when low (set to 0) and in
low-current stand-by mode when high (set to 1)
MSB
(first in)
LSB
(last in)
Table 6. Serial Interface Timing Characteristics
VDD = 2.6V, -40°C < TA < 85°C, unless otherwise specified
Symbol
Parameter
Serial Clock Frequency
SCL, SDA Rise Time
SCL, SDA Fall Time
Min
Max
400
100
100
Units
kHz
nS
fCLK
tR
tF
nS
Table 7. Address Mapping
ADDR
State
Address
(DEC)
Address
Address (BIN)
(HEX)
0x70
0x71
GND
VDD
112
113
1110000
1110001
Document No. 70-0335-06 │ www.psemi.com
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
PE64905
Product Specification
Equivalent Circuit Model Description
Figure 18. Equivalent Circuit Model Schematic
LS
CP
RP1
LS
RS
CS
The DTC Equivalent Circuit Model includes all
parasitic elements and is accurate in both Series
and Shunt configurations, reflecting physical circuit
behavior accurately and providing very close
correlation to measured data. It can easily be used
in circuit simulation programs. Most parameters are
state independent, and simple equations are
provided for the state dependent parameters.
The Tuning Core capacitance CS represents
capacitance between RF+ and RF- ports. It is
linearly proportional to state (0 to 31 in decimal) in
a discrete fashion. The Series Tuning Ratio is
VM
VP
RF+
RF-
CP
RP2
RP2
RP1
RFGND
Table 8. Equivalent Circuit Model Parameters
Variable
Equation (state = 0, 1, 2…31)
Units
CS
0.129*state + 0.600
pF
Ω
defined as CSmax/CSmin
.
RS
20/(state+20/(state+0.7)) + 0.7
CP represents the circuit and package parasitics
from RF ports to GND. In Shunt configuration the
total capacitance of the DTC is higher due to
parallel combination of CP and CS. In Series
configuration, CS and CP do not add in parallel and
the DTC appears as an impedance transformation
network.
RP1
RP2
CP
7
Ω
10
kΩ
pF
nH
0.5
0.27
LS
Table 9. Equivalent Circuit Data
State
DTC Core
Binary
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Decimal
0
Cs [pF]
0.60
0.73
0.86
0.99
1.12
1.25
1.37
1.50
1.63
1.76
1.89
2.02
2.15
2.28
2.41
2.54
2.66
2.79
2.92
3.05
3.18
3.31
3.44
3.57
3.70
3.83
3.95
4.08
4.21
4.34
4.47
4.60
Rs [Ω]
Parasitic inductance due to circuit and package is
modeled as LS and causes the apparent
capacitance of the DTC to increase with frequency
until it reaches Self Resonant Frequency (SRF).
The value of SRF depends on state and is
approximately inversely proportional to the square
root of capacitance.
1.40
2.27
2.83
3.08
3.12
3.05
2.93
2.78
2.64
2.51
2.39
2.27
2.17
2.08
2.00
1.93
1.86
1.80
1.75
1.70
1.65
1.61
1.57
1.54
1.51
1.48
1.45
1.42
1.40
1.37
1.35
1.33
1
2
3
4
5
6
7
8
9
The overall dissipative losses of the DTC are
modeled by RS, RP1 and RP2 resistors. The
parameter RS represents the Equivalent Series
Resistance (ESR) of the tuning core and is
dependent on state. RP1 and RP2 represent losses
due to the parasitic and biasing networks, and are
state-independent.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Table 7. Maximum Operating RF Voltage
Condition
VP to VM
VP to RFGND
M to RFGND
Limit
30 Vpk
30 Vpk
30 Vpk
V
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0335-06 │ UltraCMOS® RFIC Solutions
Page 8 of 11
PE64905
Product Specification
Layout Recommendations
Evaluation Board
For optimal results, place a ground fill directly under
the DTC package on the PCB. Layout isolation is
desired between all control and RF lines. When
using the DTC in a shunt configuration, it is
important to make sure the RF- pin is solidly
grounded to a filled ground plane. Ground traces
should be as short as possible to minimize
inductance. A continuous ground plane is preferred
on the top layer of the PCB. When multiple DTCs
are used together, the physical distance between
them should be minimized and the connection
should be as wide as possible to minimize series
parasitic inductance.
The 101-0597 Evaluation Board (EVB) was designed
for accurate measurement of the DTC impedance
and loss. Two configurations are available: 1 Port
Shunt (J3) and 2 Port Series (J4, J5). Three
calibration standards are provided. The open (J2)
and short (J1) standards (104 ps delay) are used for
performing port extensions and accounting for
electrical length and transmission line loss. The Thru
(J9, J10) standard can be used to estimate PCB
transmission line losses for scalar de-embedding of
the 2 Port Series configuration (J4, J5).
The board consists of a 4 layer stack with 2 outer
layers made of Rogers 4350B (εr = 3.48) and 2 inner
layers of FR4 (εr = 4.80). The total thickness of this
board is 62 mils (1.57 mm). The inner layers provide
a ground plane for the transmission lines. Each
transmission line is designed using a coplanar
waveguide with ground plane (CPWG) model using a
trace width of 32 mils (0.813 mm), gap of 15 mils
(0.381 mm), and a metal thickness of 1.4 mils
(0.051 mm).
Figure 19. Recommended Schematic of
Multiple DTCs
Figure 21. Evaluation Board
Figure 20. Recommended Layout of
Multiple DTCs
101-0597
Document No. 70-0335-06 │ www.psemi.com
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 11
PE64905
Product Specification
Figure 22. Package Drawing
10-lead 2 x 2 x 0.45 mm
19-2002
Figure 23. Marking Specifications
Marking Spec
Symbol
Package
Marking
Definition
PP
ZZ
CF
Part number marking for PE64905
Last two digits of lot code
PPZZ
YWW
00-99
Last digit of year, starting from 2009
(0 for 2010, 1 for 2011, etc)
Y
0-9
WW
01-53
Work week
17-0112
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0335-06 │ UltraCMOS® RFIC Solutions
Page 10 of 11
PE64905
Product Specification
Figure 24. Tape and Reel Specifications
10-lead 2 x 2 x 0.45 mm
Tape Feed Direction
Table 9. Ordering Information
Order Code
Package
Description
Package Part in Tape and Reel
Evaluation Kit
Shipping Method
3000 units/T&R
1 Set/Box
PE64905MLBB-Z
EK64905-12
10-lead QFN 2 x 2 x 0.45 mm
Evaluation Kit
Sales Contact and Information
For sales and contact information please visit www.psemi.com.
No patent rights or licenses to any circuits described in this datasheet are implied or granted to any
third party.
Advance Information: The product is in a formative or design stage. The datasheet contains
design target specifications for product development. Specifications and features may change
in any manner without notice. Preliminary Specification: The datasheet contains preliminary
data. Additional data may be added at a later date. Peregrine reserves the right to change
specifications at any time without notice in order to supply the best possible product. Product
Specification: The datasheet contains final data. In the event Peregrine decides to change the
specifications, Peregrine will notify customers of the intended changes by issuing a CNF
(Customer Notification Form).
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical
implant, or in other applications intended to support or sustain life, or in any application in which the
failure of the Peregrine product could create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including consequential or incidental damages, arising out
of the use of its products in such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch
and DuNE are trademarks of Peregrine Semiconductor Corp. All other trademarks mentioned herein
are the property of their respective companies.
The information in this datasheet is believed to be reliable. However, Peregrine assumes no
liability for the use of this information. Use shall be entirely at the user’s own risk.
Document No. 70-0335-06 │ www.psemi.com
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 11
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