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PE926C31-EK [PSEMI]

Quad RS-422 Differential Line Driver Radiation Hardened; 四路RS - 422差分线路驱动器抗辐射
PE926C31-EK
型号： PE926C31-EK
厂家： Peregrine Semiconductor    Peregrine Semiconductor
描述：

Quad RS-422 Differential Line Driver Radiation Hardened
四路RS - 422差分线路驱动器抗辐射

驱动器
文件： 总7页 (文件大小：126K)
中文：  中文翻译
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Product Specification  
PE926C31  
Quad RS-422 Differential Line  
Driver Radiation Hardened  
Product Description  
The PE926C31 is a high performance monolithic CMOS  
RS-422 line driver. Its operating supply range is 3.0 to 3.6  
V, with an output signal overvoltage range of 0 – 6 V. The  
PE26C31 offers higher speed and lower power than other  
RS-422 driver types. It is packaged in a flat pack and is  
ideal for space applications.  
Features  
• High-speed operation: < 10 nS typical  
• Low power: < 150 uA typical  
(unloaded)  
• 3.3 V operation  
The PE926C31 is manufactured in Peregrine’s patented  
Ultra Thin Silicon (UTSi®) CMOS process, offering the  
performance of GaAs with the economy and integration of  
conventional CMOS.  
• Standard packaging: 16-lead flat pack  
• SEL Immune UTSi CMOS-on-sapphire  
• SEU <10-10 errors / bit-day  
• 300 Krad Total Dose  
Figure 1. Package Drawing  
Document No. 70-0157-01 │ www.psemi.com  
©2005 Peregrine Semiconductor Corp. All rights reserved.  
Page 1 of 7  
PE926C31  
Product Specification  
Figure 2. Pin Configuration (Top View)  
Table 2. Recommended Operating Conditions  
Symbol  
Parameter/Conditions Min Max Units  
A
AQ+  
AQ-  
E+  
1
2
3
4
5
6
7
8
16  
15  
V+  
D
V+  
Supply voltage  
3.0  
-55  
3.6  
V
TOP  
Operating temperature  
range  
125  
°C  
VIN  
Maximum input voltage  
Maximum output voltage  
Maximum output current  
0
0
Vdd  
Vdd  
50  
V
V
VOUT  
IOUT  
14 DQ+  
-50  
mA  
PE926C31  
13  
12  
11  
DQ-  
E-  
BQ-  
BQ+  
B
Electrostatic Discharge (ESD) Precautions  
CQ-  
When handling this UTSi device, observe the  
same precautions that you would use with other  
ESD-sensitive devices. Although this device  
contains circuitry to protect it from damage due to  
ESD, precautions should be taken to avoid  
exceeding the rating specified in Table 2.  
10 CQ+  
V-  
9
C
Table 1. Pin Descriptions  
Latch-Up Avoidance  
Pin  
No.  
Pin  
Name  
Unlike conventional CMOS devices, UltraCMOS™  
devices are immune to latch-up.  
Description  
Channel A Input  
1
2
A
AQ+  
AQ-  
E+  
Device Functional Considerations  
Channel A Noninverting Ouput  
Channel A Inverting Output  
Enable, active high  
The PE926C31 operates at high switching  
speeds. In order to obtain maximum  
performance, it is crucial that pin 16 be supplied  
with a bypass capacitor to ground (pin 8).  
3
4
5
BQ-  
BQ+  
B
Channel B Inverting Output  
Channel B Noninverting Output  
Channel B Input  
6
7
Table 3. Truth Table  
8
V-  
Ground Pin  
E+  
E-  
Data  
Q+  
Q-  
9
C
Channel C Input  
L
H
X
Z
Z
10  
11  
12  
13  
14  
15  
16  
CQ+  
CQ-  
E-  
Channel C Noninverting Output  
Channel C Inverting Ouput  
Enable, active low  
H
X
H
X
X
L
L
L
H
L
X
L
H
H
DQ-  
DQ+  
D
Channel D Inverting Output  
Channel D Noninverting Output  
Channel D Input  
V+  
Supply Pin  
©2005 Peregrine Semiconductor Corp. All rights reserved.  
Document No. 70-0157-01 │ UltraCMOS™ RFIC Solutions  
Page 2 of 7  
PE926C31  
Product Specification  
Table 4. Electrical Specifications  
-55° C < Tcase < 125° C, 3.0 V < V+ < 3.6 V, PreRad, unless otherwise specified  
Param  
Description  
Conditions  
Pin(s)  
Min  
Typ  
Max  
Units  
VD1  
Output Differential Voltage  
No load  
AQ+, AQ-, BQ+, BQ-,  
CQ+, CQ-, DQ+, DQ-  
(V+) -0.3  
(V+)  
(V+)  
V
+0.6  
VD2  
Output Differential Voltage  
RL=100 Ω, Fig DC1  
1.9  
2.3  
0
V
DVD2  
VCM  
Output Differential Voltage Change IOUT 0 – 20mA, Fig DC1  
-0.4  
0.4  
2.0  
0.4  
V
Common Mode Voltage  
RL=100 Ω, Fig DC1  
1.5  
0
V
DVCM  
IOZH  
IOZL  
Common Mode Voltage Change  
Tristate Output Leakage (H)  
Tristate Output Leakage (L)  
Output Short Circuit Current  
Output Leakage Current (H)  
RL=100 Ω, Fig DC1  
-0.4  
-5  
V
VOUT = V+, disabled  
VOUT = 0.0 V, disabled  
VOUT = 0.0 V, Enabled Q=H  
-0.1  
0.1  
-70  
1
uA  
uA  
mA  
uA  
5
IOSC  
IOFFH  
-30  
-100  
100  
VOUT=6.0V,V+ and all inputs  
= 0.0V  
IOFFL  
Output Leakage Current (L)  
VOUT=-0.25V,V+ and all  
inputs = 0.0V  
Iout=-20mA  
-100  
2.0  
-1  
uA  
VOH  
VOL  
VIH  
VIL  
Output High Voltage  
Output Low Voltage  
Input threshold H  
Input Threshold L  
2.4  
0.1  
V
V
V
V
Iout=20mA  
0.5  
0.9  
Vdd=3.6V (VIHMIN=0.7*VDD) A, B, C, D, E+, E-  
2.5  
Vdd=3.0V  
A, B, C, D, E+, E-  
(VILMAX=0.3*VDD)  
IIH  
Input Lkg Current  
A, B, C, D, E+, E-  
A, B, C, D, E+, E-  
A, B, C, D, E+, E-  
A, B, C, D, E+, E-  
-1  
1
1
uA  
uA  
IIL  
Input Lkg Current  
-1  
VIKL  
VIKH  
Input Clamp Diode Voltage  
Input Clamp Diode Voltage  
IIN=-20 mA  
IIN=20 mA  
-1.5  
(V+) +  
1.5 V  
µ
ICC  
Supply Current  
No load, Inputs = 0 V or V+  
V+  
120  
uA  
150 uA  
Notes:  
1. “Line” pins refer to AQ-, AQ+, BQ-, BQ+, CQ-, CQ+, DQ-, DQ+, differential outputs  
2. “Digital Input” or “Enable” pins refer to E+, E-  
3. “Digital Input” pins refer to A, B, C, D  
Document No. 70-0157-01 │ www.psemi.com  
©2005 Peregrine Semiconductor Corp. All rights reserved.  
Page 3 of 7  
PE926C31  
Product Specification  
Table 5. Post-Irradiation DC Electrical Specifications  
Tcase = 25° C, 3.0 V < V+ < 3.6 V, 300 KRad, unless otherwise specified  
Param  
Description  
Conditions  
Pin(s)  
Min  
Typ  
Max  
Units  
VD1  
Output Differential Voltage  
No load  
AQ+, AQ-, BQ+, BQ-,  
CQ+, CQ-, DQ+, DQ-  
(V+) -0.3  
(V+)  
(V+) +0.6  
V
VD2  
Output Differential Voltage  
RL=100 Ω, Fig DC1  
1.9  
2.3  
0
V
V
DVD2  
Output Differential Voltage  
Change  
IOUT 0 – 20mA, Fig DC1  
-0.4  
0.4  
VCM  
Common Mode Voltage  
RL=100 Ω, Fig DC1  
1.5  
0
2.0  
0.4  
V
DVCM  
IOZH  
IOZL  
Common Mode Voltage Change  
Tristate Output Leakage (H)  
Tristate Output Leakage (L)  
Output Short Circuit Current  
Output Leakage Current (H)  
RL=100 Ω, Fig DC1  
-0.4  
-5  
V
VOUT = V+, disabled  
VOUT = 0.0 V, disabled  
VOUT = 0.0 V, Enabled Q=H  
-0.1  
0.1  
-70  
1
uA  
uA  
mA  
uA  
5
IOSC  
IOFFH  
-30  
-100  
100  
VOUT=6.0V,V+ and all inputs  
= 0.0V  
IOFFL  
Output Leakage Current (L)  
VOUT=-0.25V,V+ and all  
inputs = 0.0V  
Iout=-20mA  
-100  
2.0  
-1  
uA  
VOH  
VOL  
VIH  
Output High Voltage  
Output Low Voltage  
Input threshold H  
2.4  
0.1  
V
V
V
Iout=20mA  
0.5  
0.9  
Vdd=3.6V  
A, B, C, D, E+, E-  
A, B, C, D, E+, E-  
2.5  
(VIHMIN=0.7*VDD)  
VIL  
Input Threshold L  
Vdd=3.0V  
V
(VILMAX=0.3*VDD)  
IIH  
Input Lkg Current  
A, B, C, D, E+, E-  
A, B, C, D, E+, E-  
A, B, C, D, E+, E-  
A, B, C, D, E+, E-  
-1  
1
1
uA  
uA  
IIL  
Input Lkg Current  
-1  
VIKL  
VIKH  
Input Clamp Diode Voltage  
Input Clamp Diode Voltage  
IIN=-20 mA  
IIN=20 mA  
-1.5  
(V+) +  
1.5 V  
ICC  
Supply Current  
No load, Inputs = 0 V or V+  
V+  
120  
uA  
150 uA  
Notes:  
1. “Line” pins refer to AQ-, AQ+, BQ-, BQ+, CQ-, CQ+, DQ-, DQ+, differential outputs  
2. “Digital Input” or “Enable” pins refer to E+, E-  
3. “Digital Input” pins refer to A, B, C, D  
4. Output Short Circuit not intended to imply continuous operation  
©2005 Peregrine Semiconductor Corp. All rights reserved.  
Document No. 70-0157-01 │ UltraCMOS™ RFIC Solutions  
Page 4 of 7  
PE926C31  
Product Specification  
Table 6. Pre-irradiation Electrical Specifications  
-55° C < Tcase < 125° C, 3.0 V < V+ < 3.6 V, PreRad, unless otherwise specified  
Param  
TPHL  
Description  
Prop Delay H-L  
Conditions  
RL=100 CL=50 pF  
Pin(s)  
Min  
3
Typ  
9
Max  
15  
Units  
nS  
AQ+,  
AQ-,  
BQ+,  
BQ-,  
CQ+,  
CQ-,  
DQ+,  
DQ-  
TPLH  
TSK1  
TSK2*  
TRISE*  
TFALL*  
TPHZ  
TPZH  
TPLZ  
Prop Delay H-L  
3
9
15  
3
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
Prop Delay Q+/Q-  
Prop Delay Skew Ch/Ch  
Rise Time 20%/80%  
Fall Time 20%/80%  
Prop Delay H-Z  
-3  
-3  
0
0
3
3
10  
10  
20  
20  
20  
20  
3
12  
12  
10  
10  
Prop Delay Z-H  
Prop Delay L-Z  
TPZL  
Prop Delay Z-L  
Table 7. Post-irradiation Electrical Specifications  
25° C, 3.0 V < V+ < 3.6 V, 300 KRad, unless otherwise specified  
Param  
Description  
Conditions  
Pin(s)  
Min  
Typ  
Max  
Units  
TPHL  
Prop Delay H-L  
RL=100 CL=50 pF  
AQ+,  
AQ-,  
BQ+,  
BQ-,  
CQ+,  
CQ-,  
DQ+,  
DQ-  
3
9
15  
15  
3
nS  
TPLH  
TSK1  
TSK2*  
TRISE*  
TFALL*  
TPHZ  
TPZH  
TPLZ  
Prop Delay H-L  
3
9
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
Prop Delay Q+/Q-  
Prop Delay Skew Ch/Ch  
Rise Time 20%/80%  
Fall Time 20%/80%  
Prop Delay H-Z  
-3  
-3  
0
0
3
3
10  
10  
20  
20  
20  
20  
3
20  
20  
10  
10  
Prop Delay Z-H  
Prop Delay L-Z  
TPZL  
Prop Delay Z-L  
*Note: Guaranteed by design, not tested  
Document No. 70-0157-01 │ www.psemi.com  
©2005 Peregrine Semiconductor Corp. All rights reserved.  
Page 5 of 7  
PE926C31  
Product Specification  
Figure 3. TPLH, TPHL Test Circuit Block Diagram  
TPLH, TPHL measured from input 50% to output  
50% thresholds. TRISE, TFALL measured from  
output 20% to output 80% thresholds.  
4,16  
2,6,10,14  
DC  
8,12  
1,7,9,15  
+
I+  
-
VI  
Q-  
0.0 – (V+)  
Q+  
3,5,11,13  
TPLH  
TPLH  
Q-,  
Q+  
Figure 2 : TPLH, TPHL  
TRISE  
TFALL  
Figure 4. TPLZ, TPZL, TPHZ, TPZH Test Circuit Block Diagram  
4
TPZH, TPZL measured from input 50% to output  
50% thresholds. TPHZ, TPLZ measured from  
input 50% to output 10% thresholds.  
16  
E+  
V+  
0 - (V+D)C  
3.3V  
R
110Ω  
L
2,6,10,14  
E-  
13  
1,7,9,15  
E-  
+
-
E+  
(V+) - 0  
Q+,  
Q-  
DC  
CL  
50pF  
VI  
L: 0.0  
3,5,11,13  
H: (V+)  
TPZH  
TPZL  
TPHZ  
TPLZ  
Q+,  
Q-  
Figure 3: TPHZ, TPZH, TPLZ, TPZL  
Table 8. Ordering Information  
Shipping  
Method  
Order Code  
Part Marking  
Description  
Package  
926C31-01  
926C31-21  
926C31-00  
PE926C31-01  
PE926C31-21  
PE926C31-EK  
Engineering Sample  
16-lead FLAT PACK  
16-lead FLAT PACK  
Evaluation Board  
1/Box  
Flight Product, FP  
Evaluation Kit  
25/Tray  
1/Box  
©2005 Peregrine Semiconductor Corp. All rights reserved.  
Document No. 70-0157-01 │ UltraCMOS™ RFIC Solutions  
Page 6 of 7  
PE926C31  
Product Specification  
Sales Offices  
United States  
Japan  
Peregrine Semiconductor Corp.  
9450 Carroll Park Drive  
San Diego, CA 92121  
Peregrine Semiconductor K.K.  
5A-5, 5F Imperial Tower  
1-1-1 Uchisaiwaicho, Chiyoda-ku  
Tokyo 100-0011 Japan  
Tel 1-858-731-9400  
Fax 1-858-731-9499  
Tel: 011-81-3-3502-5211  
Fax: 011-81-3-3502-5213  
Europe  
China  
Peregrine Semiconductor Europe  
Bâtiment Maine  
Peregrine Semiconductor  
28G, Times Square,  
No. 500 Zhangyang Road,  
Shanghai, 200122, P.R. China  
Tel: 011-86-21-5836-8276  
Fax: 011-86-21-5836-7652  
13-15 rue des Quatre Vents  
F- 92380 Garches, France  
Tel: 011- 33-1-47-41-91-73  
Fax : 011-33-1-47-41-91-73  
For a list of representatives in your area, please refer to our Web site at: www.psemi.com  
Data Sheet Identification  
Advance Information  
The information in this data sheet is believed to be reliable.  
However, Peregrine assumes no liability for the use of this  
information. Use shall be entirely at the user’s own risk.  
The product is in a formative or design stage. The data  
sheet contains design target specifications for product  
development. Specifications and features may change in  
any manner without notice.  
No patent rights or licenses to any circuits described in this  
data sheet are implied or granted to any third party.  
Preliminary Specification  
Peregrine’s products are not designed or intended for use in  
devices or systems intended for surgical implant, or in other  
applications intended to support or sustain life, or in any  
application in which the failure of the Peregrine product could  
create a situation in which personal injury or death might occur.  
Peregrine assumes no liability for damages, including  
consequential or incidental damages, arising out of the use of  
its products in such applications.  
The data sheet contains preliminary data. Additional data  
may be added at a later date. Peregrine reserves the right  
to change specifications at any time without notice in order  
to supply the best possible product.  
Product Specification  
The data sheet contains final data. In the event Peregrine  
decides to change the specifications, Peregrine will notify  
customers of the intended changes by issuing a DCN  
(Document Change Notice).  
The Peregrine name, logo, and UTSi are registered trademarks  
and UltraCMOS is a trademark of Peregrine Semiconductor  
Corp.  
Document No. 70-0157-01 │ www.psemi.com  
©2005 Peregrine Semiconductor Corp. All rights reserved.  
Page 7 of 7  

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