PE97022-00 [PSEMI]
3500 MHz UltraCMOS Integer-N PLL Rad Hard for Space Applications; 3500兆赫的UltraCMOS整数N分频PLL抗辐射的空间应用
| 型号： | PE97022-00 |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | 3500 MHz UltraCMOS Integer-N PLL Rad Hard for Space Applications |
| 文件： | 总14页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specification
PE97022
3500 MHz UltraCMOS™ Integer-N PLL
Rad Hard for Space Applications
Product Description
Peregrine’s PE97022 is a high-performance integer-N PLL
capable of frequency synthesis up to 3500 MHz. The
device is designed for superior phase noise performance
while providing an order of magnitude reduction in current
consumption, when compared with existing commercial
space PLLs.
Features
• Low Power - 45 mA at 3.3V
• 3500 MHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector
The PE97022 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hard wired.
• Serial, parallel or hardwired
programmable
• Ultra-Low Phase Noise: -216 dBc/Hz
• SEU < 10-9 errors / bit-day
The PE97022 is optimized for commercial space
applications. Single Event Latch up (SEL) is physically
impossible and Single Event Upset (SEU) is better than
10-9 errors per bit / day. It is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
excellent RF performance and intrinsic radiation tolerance.
• 100 Krad (Si) total dose
• Pin compatible with the PE9702,
packaged in a 44-lead CQFJ
(reference application note AN22 at
www.psemi.com)
Figure 1. Block Diagram
Fin
Fin
Prescaler
10 / 11
Main
Counter
fp
13
D(7:0)
Primary
20-bit
Secon-
dary
20-bit
Latch
8
PD_U
Phase
20
20
20
Sdata
Latch
Detector
PD_D
20
16
Pre_en
M(6:0)
A(3:0)
R(3:0)
6
6
fr
R Counter
fc
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ www.psemi.com
Page 1 of 14
PE97022
Product Specification
Figure 2. Pin Configurations (Top View)
Figure 3. Package Type
44-lead CQFJ
6
5
4
3
2
1
44 43 42 41 40
D0, M0
D1, M1
fc
V
7
8
39
38
37
36
35
34
33
32
31
30
29
DD_fc
D2, M2
PD_U
PD_D
VDD
9
D3, M3
10
11
12
13
14
15
16
17
VDD
VDD
Cext
S_WR, D4, M4
Sdata, D5, M5
Sclk, D6, M6
FSELS, D7, Pre_en
GND
VDD
Dout
VDD_fp
fp
GND
18 19 20 21 22 23 24 25 26 27 28
Table 1. Pin Descriptions
Pin No. Pin Name
Interface Mode
Type
Description
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
1
VDD
ALL
(Note 1)
2
3
4
5
6
R0
Direct
Direct
Direct
Direct
ALL
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
R Counter bit0 (LSB).
R Counter bit1.
R1
R2
R Counter bit2.
R3
R Counter bit3.
GND
D0
Ground.
Parallel
Direct
Parallel
Direct
Parallel
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
7
8
M0
D1
M1
D2
9
Parallel data bus bit2.
M2
Direct
Input
M Counter bit2.
10
D3
Parallel
Direct
ALL
Input
Parallel data bus bit3.
M Counter bit3.
Same as pin 1.
M3
Input
11
12
VDD
VDD
(Note 1)
(Note 1)
ALL
Same as pin 1.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.
S_WR
Serial
Input
Primary register data is transferred to the secondary register on S_WR or Hop_WR
rising edge.
13
D4
M4
Parallel
Direct
Input
Input
Parallel data bus bit4
M Counter bit4
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ UltraCMOS™ RFIC Solutions
Page 2 of 14
PE97022
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. Pin Name
Interface Mode
Type
Description
Sdata
Serial
Input
Binary serial data input. Input data entered MSB first.
D5
Parallel
Direct
Input
Input
Input
Input
Input
Input
Input
Input
Parallel data bus bit5.
M Counter bit5.
14
15
16
M5
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
Sclk
D6
Serial
Parallel
Direct
Parallel data bus bit6.
M Counter bit6.
M6
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
FSELS
D7
Serial
Parallel
Direct
Parallel data bus bit7 (MSB).
Pre_en
GND
FSELP
A0
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
Ground.
17
18
ALL
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
Parallel
Direct
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.
Serial
E_WR
Parallel
Direct
19
A1
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
M2_WR
A2
Parallel
Direct
20
21
A Counter bit2.
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
Smode
A3
Serial, Parallel
Direct
A Counter bit3 (MSB).
Bmode
VDD
Selects direct interface mode (Bmode=1).
Same as pin 1.
22
23
24
25
26
27
ALL
ALL
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising
edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge
of A_WR.
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
M1_WR
A_WR
Hop_WR
Fin
Parallel
Parallel
Serial, Parallel
ALL
Prescaler input from the VCO. 3.5 GHz max frequency.
Prescaler complementary input. A bypass capacitor in series with a 51 Ω resistor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
Fin
28
ALL
Input
29
30
GND
fp
ALL
ALL
Ground.
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
Output
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ www.psemi.com
Page 3 of 14
PE97022
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. Pin Name
Interface Mode
Type
Description
31
32
33
VDD-fp
Dout
VDD
ALL
(Note 1)
VDD for fp. Can be left floating or connected to GND to disable the fp output.
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming.
Serial, Parallel
ALL
Output
(Note 1)
Same as pin 1.
Logical “NAND” of PD_Ū and PD_D¯ terminated through an on chip, 2 kΩ series
resistor. Connecting Cext to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
34
Cext
ALL
Output
35
36
37
38
39
40
41
42
43
44
VDD
ALL
(Note 1)
Output
Same as pin 1.
PD_D¯
PD_Ū
VDD-fc
fc
PD_D¯ is pulse down when fp leads fc.
ALL
ALL
PD_Ū is pulse down when fc leads fp.
ALL
(Note 1)
Output
VDD for fc. Can be left floating or connected to GND to disable the fc output.
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 38.
ALL
GND
GND
fr
ALL
Ground.
ALL
Ground.
ALL
Input
Reference frequency input.
Output,
OD
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD
is high impedance, otherwise LD is a logic low (“0”).
LD
ALL
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
Serial, Parallel
Input
E¯n¯h¯
Note 1: VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
DD pins 31 and 38 are used to enable test modes and should be left floating.
V
Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ UltraCMOS™ RFIC Solutions
Page 4 of 14
PE97022
Product Specification
Table 2. Absolute Maximum Ratings
Table 4. ESD Ratings
Symbol
Parameter/Conditions Min Max Units
Symbol
Parameter/Conditions
Level Units
VDD
Supply voltage
-0.3
-0.3
4.0
V
V
ESD voltage (Human Body Model)
– Note 1
VESD
1000
V
VDD
+ 0.3
VI
Voltage on any input
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
II
DC into any input
DC into any output
-10
-10
+10
+10
mA
mA
IO
Electrostatic Discharge (ESD) Precautions
Storage temperature
range
Tstg
-65
150
°C
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Table 3. Operating Ratings
Symbol Parameter/Conditions Min
Max
Units
VDD
Supply voltage
2.85
3.45
V
Operating ambient
temperature range
Latch-Up Avoidance
TA
-40
85
°C
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. DC Characteristics: VDD = 3.3 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Operational supply current;
Prescaler disabled
Conditions
Min
Typ
Max
Units
15
45
mA
mA
IDD
VDD = 2.85 to 3.45 V
Prescaler enabled
50
Digital Inputs: All except fr, Fin, Fin
VIH
High level input voltage
VDD = 2.85 to 3.45 V
VDD = 2.85 to 3.45 V
VIH = VDD = 3.45 V
0.7 x VDD
V
V
VIL
Low level input voltage
High level input current
Low level input current
0.3 x VDD
70
IIH
µA
µA
IIL
VIL = 0, VDD = 3.45 V
-1
Reference Divider input: fr
IIHR
IILR
High level input current
Low level input current
VIH = VDD = 3.45 V
100
0.4
µA
µA
VIL = 0, VDD = 3.45 V
-100
Counter and phase detector outputs: fc, fp.
VOLD
VOHD
Output voltage LOW
Output voltage HIGH
Iout = 6 mA
Iout = -3 mA
V
V
VDD - 0.4
Lock detect outputs: Cext, LD
VOLC
VOHC
VOLLD
Output voltage LOW, Cext
0.4
0.4
V
V
V
Iout = 100 µA
Iout = -100 µA
Iout = 1 mA
Output voltage HIGH, Cext
Output voltage LOW, LD
VDD - 0.4
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ www.psemi.com
Page 5 of 14
PE97022
Product Specification
Table 6. AC Characteristics: VDD = 3.3 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typical
Max
Units
Control Interface and Latches (see Figures 4, 5, 6)
fClk
tClkH
tClkL
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
(Note 1)
10
MHz
ns
30
30
ns
Sdata set-up time after Sclk rising edge, D[7:0] set-up
time to M1_WR, M2_WR, A_WR, E_WR rising edge
tDSU
10
ns
Sdata hold time after Sclk rising edge, D[7:0] hold
time to M1_WR, M2_WR, A_WR, E_WR rising edge
tDHLD
tPW
tCWR
tCE
10
30
ns
ns
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
Sclk rising edge to S_WR rising edge. S_WR,
M1_WR, M2_WR, A_WR falling edge to Hop_WR
rising edge
30
30
ns
ns
Sclk falling edge to E_WR transition
S_WR falling edge to Sclk rising edge. Hop_WR
falling edge to S_WR, M1_WR, M2_WR, A_WR rising
edge
tWRC
30
30
ns
tEC
E_WR transition to Sclk rising edge
ns
ns
tMDO
MSEL data out delay after Fin rising edge
CL = 12 pf
8
Main Divider (Including Prescaler) (Note 4)
External AC coupling
275 MHz ≤ Freq ≤ 3200MHz
-5
0
5
5
dBm
dBm
PFin
Input level range
External AC coupling
3.2 GHz < Freq ≤ 3.5 GHz
3.15 V ≤ VDD ≤ 3.45 V
Main Divider (Prescaler Bypassed) (Note 4)
Fin
Operating frequency
50
-5
300
5
MHz
dBm
PFin
Input level range
External AC coupling
Reference Divider
fr
Operating frequency
(Note 3)
100
10
MHz
dBm
Pfr
Reference input power (Note 2)
Single-ended input
-2
Phase Detector
fc
Comparison frequency
(Note 3)
50
MHz
SSB Phase Noise (Fin = 1.9 GHz, fr = 20 MHz, fc = 20 MHz, LBW = 50 kHz, VDD = 3.3 V, Temp = 25° C) (Note 4)
Phase Noise
Phase Noise
Phase Noise
100 Hz Offset
1 kHz Offset
10 kHz Offset
-89
-95
dBc/Hz
dBc/Hz
dBc/Hz
ΦN
ΦN
ΦN
-102
SSB Phase Noise (Fin = 1.9 GHz, fr = 20 MHz, fc = 20 MHz, LBW = 50 kHz, VDD = 3.0 V, Temp = 25° C) (Note 4)
Phase Noise
Phase Noise
Phase Noise
100 Hz Offset
1 kHz Offset
10 kHz Offset
-87
-94
dBc/Hz
dBc/Hz
dBc/Hz
ΦN
ΦN
ΦN
-101
Note 1: Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p.
Note 3: Parameter is guaranteed through characterization only and is not tested.
Note 4: Parameters below are not tested for die sales. These parameters are verified during the element evaluation.
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ UltraCMOS™ RFIC Solutions
Page 6 of 14
PE97022
Product Specification
Figure 4. RF Sensitivity versus Frequency (typical device at temperature = 25° C)
2.85V
3.15V
3.30V
5
0
-5
-10
-15
-20
-25
-30
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency (MHz)
Figure 5. Typical Phase Noise for PE97022, VDD = 3.3 V, Temp = 25 C, Fvco = 1.92 GHz,
Fcomp = 20 MHz, Loop Bandwidth = 50 kHz
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ www.psemi.com
Page 7 of 14
PE97022
Product Specification
Functional Description
The PE97022 consists of a prescaler, counters, a
phase detector, and control logic. The dual
modulus prescaler divides the VCO frequency by
either 10 or 11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 20-bit register. An
additional counter (“A”) is used in the modulus
select logic. The phase-frequency detector
generates up and down frequency control signals.
The control logic includes a selectable chip
interface. Data can be written via serial bus,
parallel bus, or hardwired directly to the pins.
There are also various operational and test modes
and a lock detect output.
Figure 6. Functional Block Diagram
R Counter
(6-bit)
fr
fc
D(7:0)
R(5:0)
M(8:0)
A(3:0)
PD_U
PD_D
Phase
Detector
Control
Logic
Sdata
Control
Pins
LD
Cext
Modulus
Select
Fin
Fin
10/11
Prescaler
M Counter
(9-bit)
fp
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ UltraCMOS™ RFIC Solutions
Page 8 of 14
PE97022
Product Specification
Main Counter Chain
Reference Counter
Normal Operating Mode
The reference counter chain divides the
reference frequency, fr, down to the phase
detector comparison frequency, fc.
The main counter chain divides the RF input
frequency, Fin, by an integer derived from the
user-defined values in the “M” and “A” counters. It
is composed of the 10/11 dual modulus prescaler,
modulus select logic, and 9-bit M counter. Setting
Pre_en “low” enables the 10/11 prescaler. Setting
Pre_en “high” allows Fin to bypass the prescaler
and powers down the prescaler.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the
following equation:
fc = fr / (R + 1)
(4)
where 0 ≤ R ≤ 63
The output from the main counter chain, fp, is
related to the VCO frequency, Fin, by the following
equation:
Note that programming R with “0” will pass the
reference frequency, fr, directly to the phase
detector.
fp = Fin / [10 x (M + 1) + A]
(1)
In Direct Interface Mode, R Counter inputs R4
and R5 are internally forced low (“0”). In this
mode, the R value is limited to 0 ≤ R ≤ 15.
where A ≤ M + 1, 1 ≤ M ≤ 511
When the loop is locked, Fin is related to the
reference frequency, fr, by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1))
(2)
Register Programming
where A ≤ M + 1, 1 ≤ M ≤ 511
Parallel Interface Mode
A consequence of the upper limit on A is that Fin
must be greater than or equal to 90 x (fr / (R+1)) to
obtain contiguous channels. Programming the M
Counter with the minimum value of “1” will result in
a minimum M Counter divide ratio of “2”.
Parallel Interface Mode is selected by setting the
Bmode input “low” and the Smode input “low”.
Parallel input data, D[7:0], are latched in a
parallel fashion into one of three 8-bit primary
register sections on the rising edge of M1_WR,
M2_WR, or A_WR per the mapping shown in
Table 7 on page 10. The contents of the
primary register are transferred into a secondary
register on the rising edge of Hop_WR
according to the timing diagram shown in Figure
7. Data is transferred to the counters as shown
in Table 7 on page 10.
In Direct Interface Mode, main counter inputs M7
and M8 are internally forced low. In this mode, the
M value is limited to 1 ≤ M ≤ 127.
Prescaler Bypass Mode
Setting Pre_en “high” allows Fin to bypass and
power down the prescaler. In this mode, the
10/11 prescaler and A register are not active, and
the input VCO frequency is divided by the M
counter directly. The following equation relates Fin
to the reference frequency, fr:
The secondary register acts as a buffer to allow
rapid changes to the VCO frequency. This
double buffering for “ping-pong” counter control
is programmed via the FSELP input. When
FSELP is “high”, the primary register contents
set the counter inputs. When FSELP is “low”,
the secondary register contents are utilized.
Fin = (M + 1) x (fr / (R+1)) )
(3)
where 1 ≤ M ≤ 511
Parallel input data, D[7:0], are latched into the
enhancement register on the rising edge of
E_WR according to the timing diagram shown in
Figure 6. This data provides control bits as
shown in Table 8 on page 10 with bit
functionality enabled by asserting the Enh input
“low”.
In Direct Interface Mode, main counter inputs M7
and M8 are internally forced low. In this mode, the
M value is limited to 1 ≤ M ≤ 127.
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ www.psemi.com
Page 9 of 14
PE97022
Product Specification
Serial Interface Mode
B7, is clocked serially into the enhancement
register on the rising edge of Sclk, MSB (B0) first.
The enhancement register is double buffered to
prevent inadvertent control changes during serial
loading, with buffer capture of the serially-entered
data performed on the falling edge of E_WR
according to the timing diagram shown in
Figure 6. After the falling edge of E_WR, the data
provides control bits as shown in Table 8 with bit
functionality enabled by asserting the Enh input
“low”.
Serial Interface Mode is selected by setting the
Bmode input “low” and the Smode input “high”.
While the E_WR input is “low” and the S_WR
input is “low”, serial input data (Sdata input), B0 to
B19, is clocked serially into the primary register on
the rising edge of Sclk, MSB (B0) first. The
contents from the primary register are transferred
into the secondary register on the rising edge of
either S_WR or Hop_WR according to the timing
diagram shown in Figure 7. Data is transferred to
the counters as shown in Table 7.
The double buffering provided by the primary and
secondary registers allows for “ping-pong” counter
control using the FSELS input. When FSELS is
“high”, the primary register contents set the
counter inputs. When FSELS is “low”, the
secondary register contents are utilized.
Direct Interface Mode
Direct Interface Mode is selected by setting the
Bmode input “high”.
Counter control bits are set directly at the pins as
shown in Table 7. In Direct Interface Mode, main
counter inputs M7 and M8, and R Counter inputs
R4 and R5 are internally forced low (“0”).
While the E_WR input is “high” and the S_WR
input is “low”, serial input data (Sdata input), B0 to
Table 7. Primary Register Programming
Interface
Mode
Smode
R5
R4
M8
M7
M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
Enh
Bmode
Pre_en
M2_WR rising edge load
M1_WR rising edge load
A_WR rising edge load
Parallel
1
0
0
1
0
1
D3
B0
D2
B1
D1
B2
D0
B3
D7
B4
D6
B5
D5
B6
D4
B7
D3
B8
D2
B9
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Serial*
Direct
1
B10
B11
B12
B13
B14
B15
B16
B17
B18 B19
1
X
0
0
0
0
Pre_en M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode
Power
down
Counter
load
MSEL
output
Prescaler
output
Smode
Reserved
Reserved
Reserved
fc, fp OE
Enh
Bmode
E_WR rising edge load
Parallel
Serial*
0
0
0
0
1
D7
B0
D6
B1
D5
B2
D4
D3
D2
B5
D1
B6
D0
B7
0
B3
B4
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
(last in) LSB
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ UltraCMOS™ RFIC Solutions
Page 10 of 14
PE97022
Product Specification
Figure 7. Parallel Interface Mode Timing Diagram
tDSU
tDHLD
[7: 0]
D
tPW
tCWR
tWRC
M1_WR
M2_WR
A_WR
tPW
E_WR
Hop_WR
Figure 8. Serial Interface Mode Timing Diagram
Sdata
E_WR
tEC
tCE
Sclk
S_WR
tDSU
tDHLD
tClkH
tClkL
tCWR
tPW
tWRC
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ www.psemi.com
Page 11 of 14
PE97022
Product Specification
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Bit 1
Bit 2
Bit 3
Reserved**
Reserved**
Reserved**
Power down
Power down of all functions except programming interface.
Immediate and continuous load of counter programming as directed by the Bmode and
Bit 4
Counter load
Smode inputs.
Bit 5
Bit 6
Bit 7
MSEL output
Prescaler output
fp, fc OE
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Drives the raw internal prescaler output (fmain) onto the Dout output.
fp, fc outputs disabled.
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_Ū,
and PD_D¯ . If the divided VCO leads the divided
reference in phase or frequency (fp leads fc), PD_D¯
pulses “low”. If the divided reference leads the
divided VCO in phase or frequency (fr leads fp),
PD_Ū pulses “low”. The width of either pulse is
directly proportional to phase offset between the
two input signals, fp and fc. The phase detector
gain is 430 mV / radian.
PD_Ū pulses result in an increase in VCO
frequency and PD_D¯ results in a decrease in VCO
frequency.
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_Ū and
PD_D¯ waveforms, which is driven through a series
2k ohm resistor. Connecting Cext to an external
shunt capacitor provides integration. Cext also
drives the input of an internal inverting comparator
with an open drain output. Thus LD is an “AND”
function of PD_Ū and PD_D¯ . See Figure 4 for a
schematic of this circuit.
PD_Ū and PD_D¯ are designed to drive an active
loop filter which controls the VCO tune voltage.
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ UltraCMOS™ RFIC Solutions
Page 12 of 14
PE97022
Product Specification
Figure 9. Package Drawing
44-lead CQFJ
All dimensions are in inches
Table 10. Ordering Information
Order Code
Part Marking
Description
Package
Shipping Method
97022-01
PE97022 ES
Engineering Samples
44-pin CQFJ
40 units / Tray
97022-11
97022-99
97022-00
PE97022
Flight Units
44-pin CQFJ
Die
40 units / Tray
100 units / waffle pack
1 / Box
FA97022
Die Production Units
Evaluation Kit
PE97022 EK
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ www.psemi.com
Page 13 of 14
PE97022
Product Specification
Sales Offices
The Americas
Peregrine Semiconductor Corporation
Peregrine Semiconductor, Asia Pacific (APAC)
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
9380 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
Peregrine Semiconductor, Korea
#B-2607, Kolon Tripolis, 210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-943 South Korea
Tel: +82-31-728-3939
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
Fax: +82-31-728-3940
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-4741-9173
Fax : +33-1-4741-9173
Peregrine Semiconductor K.K., Japan
Teikoku Hotel Tower 10B-6
1-1-1 Uchisaiwai-cho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Space and Defense Products
Americas:
Tel: 858-731-9453
Europe, Asia Pacific:
180 Rue Jean de Guiramand
13852 Aix-En-Provence Cedex 3, France
Tel: +33-4-4239-3361
Fax: +33-4-4239-7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS, HaRP and MultiSwitch are trademarks of
Peregrine Semiconductor Corp.
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-04 │ UltraCMOS™ RFIC Solutions
Page 14 of 14
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