PE9704_技术文档

Product Specification

PE9704

3000 MHz UltraCMOS™ Integer-N PLL

Rad Hard for Space Applications

Product Description

Peregrine’s PE9704 is a high-performance integer-N PLL

capable of frequency synthesis up to 3000 MHz. The

device is designed for superior phase noise performance

while providing an order of magnitude reduction in current

consumption, when compared with existing commercial

space PLLs.

Features

• 3000 MHz operation

• ÷10/11 dual modulus prescaler

• Phase detector output

• Serial interface or hardwired

The PE9704 features a ÷10/11 dual modulus prescaler,

counters, and a phase comparator as shown in Figure 1.

Counter values are programmable through a serial

interface, and can also be directly hard wired.

programmable

• Ultra-low phase noise

• SEU < 10^-9errors / bit-day

• 100 Krad (Si) total dose

• 44-lead CQFJ

The PE9704 is optimized for commercial space

applications. Single Event Latch up (SEL) is physically

impossible and Single Event Upset (SEU) is better than

10^-9errors per bit / day. It is manufactured on Peregrine’s

UltraCMOS™ process, a patented variation of silicon-on-

insulator (SOI) technology on a sapphire substrate, offering

excellent RF performance and intrinsic radiation tolerance.

Figure 1. Block Diagram

Prescaler

10 / 11

Main

Counter

F_IN

13

MSEL

20-Bit

Frequency

Register

f_p

Serial

PD_U

PD_D

Phase

Control

3

Detector

20

19*

f_c

M(8:0)

A(3:0)

R(5:0)

Direct

Control

LD

6

C ext

F_R

R Counter

* prescaler bypass not available in Direct mode

Document No. 70-0083-03 │ www.psemi.com

Page 1 of 10

PE9704

Product Specification

Figure 2. Pin Configurations (Top View)

Figure 3. Package Type

44-lead CQFJ

6

5

4

3

2

1

44 43 42 41 40

R₄

R₅

7

8

39

38

37

36

35

34

33

32

31

30

29

C_EXT

V_DD

M₀

PD_U

PD_D

GND

N/C

9

M₁

10

11

12

13

14

15

16

17

V_DD

M₂

V_DD

M₃

D_OUT

V_DD

S_WR, M₄

DATA, M₅

GND

N/C

GND

18 19 20 21 22 23 24 25 26 27 28

Table 1. Pin Descriptions

Pin No.

Pin Name

Interface Mode

Type

Description

Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing

recommended.

1

V_DD

Both

(Note 1)

2

R₀

Direct

Both

Input

R Counter bit0

R Counter bit1

R Counter bit2

R Counter bit3

Ground

3

R₁

Input

4

R₂

Input

5

R₃

Input

6

GND

R₄

(Note 1)

Input

7

Direct

Both

R Counter bit4

R Counter bit5 (MSB)

M Counter bit0

M Counter bit1

Same as pin 1

8

R₅

Input

9

M₀

M₁

V_DD

Input

10

11

Input

(Note 1)

12

13

14

V_DD

M₂

Both

(Note 1)

Input

Same as pin 1

M Counter bit2

M Counter bit3

Direct

M₃

Input

Frequency register load enable input. Buffered data is transferred to the frequency

register on S_WR rising edge.

S_WR

M₄

Serial

Direct

Input

15

16

M Counter bit4

Binary serial data input. Data is entered LSB first, and is clocked serially into the

20-bit frequency control register (E_WR “low”) or the 8-bit enhancement register

(E_WR “high”) on the rising edge of CLOCK.

DATA

M₅

Serial

Direct

Input

M Counter bit5

Document No. 70-0083-03 │ UltraCMOS™ RFIC Solutions

Page 2 of 10

PE9704

Product Specification

Table 1. Pin Descriptions (continued)

Pin No.

Pin Name

Interface Mode

Type

Description

17

GND

Both

Ground

Clock input. Data is clocked serially into either the 20-bit primary register (E_WR

“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of

CLOCK.

CLOCK

Serial

Input

18

M₆

Direct

Both

Input

M Counter bit6

19

20

21

22

23

M₇

Input

M Counter bit7

M₈

Input

M Counter bit8 (MSB)

A₀

Input

A Counter bit0

D_MODE

V_DD

Input

Selects direct interface mode (D_MODE=1) or serial interface mode (D_MODE=0)

Same as pin 1

Both

(Note 1)

Enhancement register write enable. While E_WR is “high”, DATA can be serially

clocked into the enhancement register on the rising edge of CLOCK.

E_WR

Serial

Input

24

A₁

Direct

Both

Input

A Counter bit1.

25

26

27

28

29

30

31

A₂

A Counter bit2

A₃

A Counter bit3 (MSB)

F_IN

RF prescaler input from the VCO. 3.0 GHz maximum frequency.

GND

N/C

V_DD

Both

Ground.

Both

Ground.

No connect.

Same as pin 1

Both

Serial

Both

(Note 1)

Output

Data Out. The Main Counter output, R Counter output, or dual modulus prescaler

select (MSEL) can be routed to D_OUTthrough enhancement register programming.

32

D_OUT

33

34

35

36

37

38

V_DD

(Note 1)

Same as pin 1

N/C

No connect.

GND

PD_D

PD_U

V_DD

Both

Ground.

PD_D pulses down when f_pleads f_c.

PD_U pulses down when f_cleads f_p.

Same as pin 1

Output

(Note 1)

Output

Logical “NAND” of PD_U and PD_D, passed through an on-chip, 2 kΩ series

resistor. Connecting C_EXTto an external capacitor will low pass filter the input to the

inverting amplifier used for driving LD.

39

C_EXT

Both

40

41

42

GND

F_R

Both

Ground

Input

Reference frequency input

Enhancement mode. When asserted low (“0”), enhancement register bits are

functional.

ENH

43

44

Both

Output, OD

Lock detect output, the open-drain logical inversion of C_EXT. When the loop is

locked, LD is high impedance; otherwise LD is a logic low (“0”).

LD

Serial

Output

Note 1: V_DDpins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.

Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.

Document No. 70-0083-03 │ www.psemi.com

Page 3 of 10

PE9704

Product Specification

Table 2. Absolute Maximum Ratings

Table 4. ESD Ratings

Symbol

Parameter/Conditions

Level Units

Symbol

Parameter/Conditions Min Max Units

ESD voltage (Human Body

Model) – Note 1

V_DD

V_I

I_I

Supply voltage

-0.3

-10

4.0

V

V_ESD

1000

V

V_DD

+ 0.3

Voltage on any input

DC into any input

DC into any output

Note 1: Periodically sampled, not 100% tested. Tested per MIL-

STD-883, M3015 C2

+10

mA

Electrostatic Discharge (ESD) Precautions

I_O

Storage temperature

range

When handling this UltraCMOS™ device, observe

the same precautions that you would use with

other ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the specified rating in Table 4.

T_stg

-65

150

°C

Table 3. Operating Ratings

Symbol

Parameter/Conditions Min Max Units

V_DD

Supply voltage

2.85

-40

3.15

85

V

Latch-Up Avoidance

Operating ambient

temperature range

T_A

°C

Unlike conventional CMOS devices, UltraCMOS™

devices are immune to latch-up.

Table 5. DC Characteristics: V_DD= 3.0 V, -40° C < T_A< 85° C, unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Operational supply current;

Prescaler disabled

Prescaler enabled

I_DD

V_DD= 2.85 to 3.15 V

10

24

mA

31

Digital Inputs: All except F_R, F_IN(all digital inputs have 70 kΩ pull-up resistors)

V_IH

V_IL

I_IH

High level input voltage

Low level input voltage

High level input current

Low level input current

V_DD= 2.85 to 3.15 V

V_IH= V_DD= 3.15 V

0.7 x V_DD

V

0.3 x V_DD

+70

µA

I_IL

V_IL= 0, V_DD= 3.15 V

-1

Reference Divider input: F_R

I_IHRHigh level input current

I_ILRLow level input current

Counter and phase detector outputs: f_c, f_p.

V_IH= V_DD= 3.15 V

+100

0.4

µA

V_IL= 0, V_DD= 3.15 V

-100

V_OLD

V_OHD

Output voltage LOW

Output voltage HIGH

I_out= 6 mA

I_out= -3 mA

V

V_DD- 0.4

Lock detect outputs: C_EXT, LD

V_OLC

V_OHC

V_OLLD

Output voltage LOW, C_EXT

I_out= 100 µA

I_out= -100 µA

I_out= 6 mA

0.4

V

Output voltage HIGH, C_EXT

Output voltage LOW, LD

V_DD- 0.4

Document No. 70-0083-03 │ UltraCMOS™ RFIC Solutions

Page 4 of 10

PE9704

Product Specification

Table 6. AC Characteristics: V_DD= 3.0 V, -40° C < T_A< 85° C, unless otherwise specified

Symbol

Parameter

Conditions

Min

Max

Units

Control Interface and Latches (see Figures 1and 3)

f_Clk

t_ClkH

t_ClkL

t_DSU

t_DHLD

t_PW

CLOCK Serial data clock frequency

CLOCK Serial clock HIGH time

(Note 1)

10

MHz

ns

30

10

30

CLOCK Serial clock LOW time

DATA set-up time after CLOCK rising edge

DATA hold time after CLOCK rising edge

S_WR pulse width

t_CWR

t_CE

t_WRC

t_EC

CLOCK rising edge to S_WR rising edge.

CLOCK falling edge to E_WR transition

S_WR falling edge to CLOCK rising edge.

E_WR transition to CLOCK rising edge

MSEL data out delay after F_INrising edge

t_MDO

C_L= 12 pf

8

Main Divider (Including Prescaler)

F_IN

Operating frequency

Input level range

500

-5

3000

5

MHz

dBm

P_Fin

External AC coupling

Main Divider (Prescaler Bypassed)

F_IN

Operating frequency

Input level range

50

-5

300

5

MHz

dBm

P_Fin

Reference Divider

F_R

Operating frequency

(Note 3)

100

20

MHz

dBm

P_Fr

Reference input power (Note 2)

Single-ended input

-2

Phase Detector

f_c

Comparison frequency

(Note 3)

MHz

Note 1: Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk

specification.

Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5V_p-p

.

Note 3: Parameter is guaranteed through characterization only and is not tested.

Document No. 70-0083-03 │ www.psemi.com

Page 5 of 10

PE9704

Product Specification

Prescaler Bypass Mode

Functional Description

The PE9704 consists of a prescaler, counters, a

phase detector, and control logic. The dual

modulus prescaler divides the VCO frequency by

either 10 or 11, depending on the value of the

modulus select. Counters “R” and “M” divide the

reference and prescaler output, respectively, by

integer values stored in a 20-bit register. An

additional counter (“A”) is used in the modulus

select logic. The phase-frequency detector

generates up and down frequency control signals.

The control logic includes a selectable chip

interface. Data can be written via a serial bus or

hardwired directly to the pins. There are also

various operational and test modes and a lock

detect output.

Setting the enhancement register bit PB “high”

allows F_INto bypass the ÷10/11 prescaler. In

this mode, the prescaler and A counter are

powered down, and the input VCO frequency is

divided by the M counter directly. This mode is

only available when using the serial port to set

the frequency control bits. The following

equation relates F_INto the reference frequency

F_R:

F_IN= (M + 1) x (F_R/ (R+1)) )

(3)

where 1 ≤ M ≤ 511

Reference Counter

The reference counter chain divides the

reference frequency F_Rdown to the phase

detector comparison frequency f_c.

Main Counter Chain

Normal Operating Mode

The output frequency of the 6-bit R Counter is

related to the reference frequency by the

following equation:

Setting the PB control bit “low” enables the ÷10/11

prescaler. The main counter chain then divides

the RF input frequency (F_IN) by an integer derived

from the values in the “M” and “A” counters.

f_c= F_R/ (R + 1)

(4)

where 0 ≤ R ≤ 63

In this mode, the output from the main counter

chain (f_p) is related to the VCO frequency (F_IN) by

the following equation:

Note that programming R with “0” will pass the

reference frequency (F_R) directly to the phase

detector.

f_p= F_IN/ [10 x (M + 1) + A]

(1)

where A ≤ M + 1, 1 ≤ M ≤ 511

When the loop is locked, F_INis related to the

reference frequency (F_R) by the following

equation:

F_IN= [10 x (M + 1) + A] x (F_R/ (R+1))

(2)

where A ≤ M + 1, 1 ≤ M ≤ 511

A consequence of the upper limit on A is that F_IN

must be greater than or equal to 90 x (F_R/ (R+1))

to obtain contiguous channels. The A counter can

accept values as high as 15, but in typical

operation it will cycle from 0 to 9 between

increments in M.

Programming the M counter with the minimum

allowed value of “1” will result in a minimum M

counter divide ratio of “2”.

Document No. 70-0083-03 │ UltraCMOS™ RFIC Solutions

Page 6 of 10

PE9704

Product Specification

Register Programming

in Figure 4. After the falling edge of E_WR, the

data provides control bits as shown in Table 8.

These bits are active when the Enh input is “low”.

Serial Interface Mode

Serial Interface Mode is selected by setting the

D_MODEinput “low”.

Direct Interface Mode

While the E_WR input is “low”, serial data (DATA

input), B₀to B₁₉, is clocked into a buffer register on

the rising edge of CLOCK, LSB (B₀) first. The

contents from this buffer register are transferred

into the frequency control register on the rising

edge of S_WR according to the timing diagram

shown in Figure 4. This data controls the

counters as shown in Table 7.

Direct Interface Mode is selected by setting

the D_MODEinput “high”. In this mode, the counter

values are set directly at external pins as shown in

Table 7 and Figure 2. All frequency control

register bits are addressable except PB (it is not

possible to bypass the ÷10/11 dual modulus

prescaler in Direct Mode).

While the E_WR input is “high”, serial data (DATA

input), B₀to B₇, is clocked into a buffer register on

the rising edge of CLOCK, LSB (B₀) first. The

contents from this buffer register are transferred

into the enhancement register on the falling edge

of E_WR according to the timing diagram shown

Table 7. Frequency Register Programming

Interface

Mode

D_MODE

R₅

R₄

M₈

M₇

X

M₆

M₅

M₄

M₃

M₂

M₁

M₀

R₃

R₂

R₁

R₀

A₃

A₂

A₁

A₀

Enh

Serial*

1

0

B₀

B₁

B₂

B₃

B₄

B₅

B₆

B₇

B₈

B₉

B₁₀

B₁₁

B₁₂

B₁₃

B₁₄

B₁₅

B₁₆

B₁₇

B₁₈

B₁₉

0

Direct

1

R₅

R₄

M₈

M₇

M₆

M₅

M₄

M₃

M₂

M₁

M₀

R₃

R₂

R₁

R₀

A₃

A₂

A₁

A₀

* Data is clocked serially on CLOCK rising edge while E_WR is “low” and transferred to frequency register on S_WR rising edge.

MSB (first in)

(last in) LSB

Table 8. Enhancement Register Programming

Interface

Mode

Power

down

Counter

load

MSEL

output

fc output

D_MODE

Reserved*

fp output

PB

Enh

Serial**

0

X

B₀

B₁

B₂

B₃

B₄

B₅

B₆

B₇

* Program to 0

* Data is clocked serially on CLOCK rising edge while E_WR is “low” and transferred to frequency register on S_WR rising edge.

MSB (first in)

(last in) LSB

Document No. 70-0083-03 │ www.psemi.com

Page 7 of 10

PE9704

Product Specification

Figure 4. Serial Interface Mode Timing Diagram

DATA

E_WR

t_EC

t_CE

CLOCK

S_WR

t_DSU

t_DHLD

t_ClkH

t_ClkL

t_CWR

t_PW

t_WRC

Enhancement Register

The functions of the enhancement register bits are shown below. All bits are active high. Operation is

undefined if more than one output is sent to D_OUT

Table 9. Enhancement Register Bit Functionality

.

Bit Function

Description

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Reserved**

f_poutput

Drives the M counter output onto the D_OUToutput.

Power down

Counter load

MSEL output

f_coutput

Power down of all functions except programming interface.

Immediate and continuous load of counter programming.

Drives the internal dual modulus prescaler modulus select (MSEL) onto the D_OUToutput.

Drives the R counter output onto the D_OUToutput

PB

Allows Fin to bypass the 10/11 prescaler

** Program to 0

Phase Detector Outputs

PD_U pulses result in an increase in VCO

frequency and PD_D results in a decrease in VCO

frequency.

The phase detector is triggered by rising edges

from the main counter (f_p) and the reference

counter (f_c). It has two outputs, PD_U, and PD_D.

If the divided VCO leads the divided reference in

phase or frequency (f_pleads f_c), PD_D pulses

“low”. If the divided reference leads the divided

VCO in phase or frequency (f_cleads f_p), PD_U

pulses “low”. The width of either pulse is directly

proportional to phase offset between the two input

signals, f_pand f_c. The phase detector gain is

430 mV / radian.

Software tools for designing the active loop filter

can be found at Peregrine’s web site:

www.psemi.com

Lock Detect Output

A lock detect signal is provided at pin LD, via the

pin C_EXT(see Figure 1). C_EXTis the logical “NAND”

of PD_U and PD_D waveforms, driven through a

series 2 kΩ resistor. Connecting C_EXTto an

external shunt capacitor provides integration of

this signal.

PD_U and PD_D are designed to drive an active

loop filter which controls the VCO tune voltage.

Document No. 70-0083-03 │ UltraCMOS™ RFIC Solutions

Page 8 of 10

PE9704

Product Specification

Figure 5. Package Drawing

44-lead CQFJ

All dimensions are in mils

Table 10. Ordering Information

Order Code

9704-01

Part Marking

PE9704 ES

PE9704

Description

Package

Shipping Method

40 units / Tray

1 / Box

Engineering Samples

44-pin CQFJ

9704-11

Flight Units

9704-00

PE9704 EK

Evaluation Kit

Document No. 70-0083-03 │ www.psemi.com

Page 9 of 10

PE9704

Product Specification

Sales Offices

The Americas

Peregrine Semiconductor Corporation

Peregrine Semiconductor, Asia Pacific (APAC)

Shanghai, 200040, P.R. China

Tel: +86-21-5836-8276

Fax: +86-21-5836-7652

9450 Carroll Park Drive

San Diego, CA 92121

Tel: 858-731-9400

Fax: 858-731-9499

Peregrine Semiconductor, Korea

#B-2607, Kolon Tripolis, #210

Geumgok-dong, Bundang-gu, Seongnam-si

Gyeonggi-do, 463-480 S. Korea

Tel: +82-31-728-4300

Europe

Peregrine Semiconductor Europe

Bâtiment Maine

Fax: +82-31-728-4305

13-15 rue des Quatre Vents

F-92380 Garches, France

Tel: +33-1-4741-9173

Fax : +33-1-4741-9173

Peregrine Semiconductor K.K., Japan

Teikoku Hotel Tower 10B-6

1-1-1 Uchisaiwai-cho, Chiyoda-ku

Tokyo 100-0011 Japan

Tel: +81-3-3502-5211

Fax: +81-3-3502-5213

Space and Defense Products

Americas:

Tel: 858-731-9453

Europe, Asia Pacific:

180 Rue Jean de Guiramand

13852 Aix-En-Provence Cedex 3, France

Tel: +33-4-4239-3361

Fax: +33-4-4239-7227

For a list of representatives in your area, please refer to our Web site at: www.psemi.com

Data Sheet Identification

Advance Information

The information in this data sheet is believed to be reliable.

However, Peregrine assumes no liability for the use of this

information. Use shall be entirely at the user’s own risk.

The product is in a formative or design stage. The data

sheet contains design target specifications for product

development. Specifications and features may change in

any manner without notice.

No patent rights or licenses to any circuits described in this

data sheet are implied or granted to any third party.

Preliminary Specification

Peregrine’s products are not designed or intended for use in

devices or systems intended for surgical implant, or in other

applications intended to support or sustain life, or in any

application in which the failure of the Peregrine product could

create a situation in which personal injury or death might occur.

Peregrine assumes no liability for damages, including

consequential or incidental damages, arising out of the use of

its products in such applications.

The data sheet contains preliminary data. Additional data

may be added at a later date. Peregrine reserves the right

to change specifications at any time without notice in order

to supply the best possible product.

Product Specification

The data sheet contains final data. In the event Peregrine

decides to change the specifications, Peregrine will notify

customers of the intended changes by issuing a DCN

(Document Change Notice).

The Peregrine name, logo, and UTSi are registered trademarks

and UltraCMOS and HaRP are trademarks of Peregrine

Semiconductor Corp.

Document No. 70-0083-03 │ UltraCMOS™ RFIC Solutions

Page 10 of 10


型号：	PE9704
厂家：	Peregrine Semiconductor
描述：	3000 MHz UltraCMOS™ Integer-N PLL Rad Hard for Space Applications 3000兆赫的UltraCMOS ？整数N分频PLL抗辐射的空间应用
文件：	总10页 (文件大小：246K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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