ASM2P2310A-24TT [PULSECORE]
Low Skew Clock Driver, 2310 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 0.173 INCH, TSSOP-24;
| 型号： | ASM2P2310A-24TT |
| 厂家： | 
PulseCore Semiconductor |
| 描述： | Low Skew Clock Driver, 2310 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 0.173 INCH, TSSOP-24 光电二极管 |
| 文件： | 总11页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2005
rev 0.2
ASM2P2310A
2.5-V TO 3.3-V High-Performance Clock Buffer
Product Description
Features
The ASM2P2310A is a high-performance, low-skew clock
buffer that operates up to 200MHz. Two banks of five
outputs each provide low-skew copies of CLK. After power
up, the default state of the outputs is low regardless of the
state of the control pins. For normal operation, the outputs
of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state
when the control pins (1G or 2G, respectively) are held low
and a negative clock edge is detected on the CLK input.
The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into
the buffer mode when the control pins (1G and 2G) are
held high and a negative clock edge is detected on the CLK
input. The device operates in a 2.5V and 3.3V environment.
The built-in output enable glitch suppression ensures a
synchronized output enable sequence to distribute full
period clock signals.
• High-Performance 1:10 Clock Driver for General Purpose
applications. Operates up to 200 MHz at 3.3V Supply
Voltage
• Pin-to-Pin Skew < 100 pS at 3.3V Supply Voltage
• Supply Range : 2.3V to 3.6V
• Operating Temperature Range : -40°C to 85°C
• Output Enable Glitch Suppression
• Distributes One Clock Input to Two Banks of Five
Outputs
• 25Ω On Chip Series Damping Resistors
• Packaged in 24 Pin TSSOP Package
The ASM2P2310A is characterized for operation from
-40°C to 85°C.
Block Diagram
CLK
24
21
3
2Y0
1Y0
1Y1
1Y2
1Y3
1Y4
25ꢀ
25ꢀ
25ꢀ
4
20
2Y1
25ꢀ
5
16
2Y2
2Y3
25ꢀ
25ꢀ
25ꢀ
8
25ꢀ
9
12
2Y4
25ꢀ
25ꢀ
LOGIC CONTROL
1G
13
LOGIC CONTROL
2G
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
October 2005
ASM2P2310A
rev 0.2
Pin Configuration
CLK
VDD
1
2
3
24
23
22
GND
VDD
VDD
1Y0
4
5
6
21
20
19
2Y0
1Y1
1Y2
GND
2Y1
GND
7
18
GND
2Y2
GND
1Y3
1Y4
VDD
8
9
17
16
2Y3
VDD
10
15
VDD
2G
11
12
14
13
1G
2Y4
Pin Description
Pin #
1
2
3
4
5
6
7
Pin Name
GND
VDD
Type
P
P
O
O
O
P
P
O
Description
Ground Pin
DC Power supply, 2.3 V – 3.6V
Buffered Output Clock
Buffered Output Clock
Buffered Output Clock
Ground Pin
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VDD
Ground Pin
8
9
10
Buffered Output Clock
Buffered Output Clock
DC power supply, 2.3V – 3.6V
O
P
Output enable control for 1Y[0:4] outputs. This output enable is active-high,
meaning the 1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic
high.
11
12
13
1G
2Y4
2G
I
O
I
Buffered Output Clock
Output enable control for 2Y[0:4] outputs. This output enable is active-high,
meaning the 2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic
high.
14
15
16
17
18
19
20
21
22
23
24
VDD
VDD
P
P
O
O
P
P
O
O
P
P
I
DC power supply, 2.3V – 3.6V
DC power supply, 2.3V – 3.6V
Buffered Output Clock
Buffered Output Clock
Ground Pin
2Y3
2Y2
GND
GND
2Y1
2Y0
VDD
Ground Pin
Buffered Output Clock
Buffered Output Clock
DC power supply, 2.3V – 3.6V
DC power supply, 2.3V – 3.6V
Input reference frequency
VDD
CLK
2.5-V TO 3.3-V High-Performance Clock Buffer
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Notice: The information in this document is subject to change without notice.
October 2005
rev 0.2
ASM2P2310A
Function Table
Input
2G
L
L
H
Output
1G
L
H
L
H
CLK
1Y[0:4]
L
2Y[0:4]
L
↓
↓
↓
↓
CLK1
L
L
CLK1
CLK1
H
CLK1
Note: 1 After detecting one negative edge on the CLK input, the output follows the input CLK if the control pin is held high.
Detailed Description
Output Enable Glitch Suppression Circuit
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the clock input
such that the output buffer is enabled or disabled on the next full period of the input clock (negative edge triggered by the
input clock) (see Figure 1).
The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for predictable
operation.
CLK
Gn
Yn
th(en)
tsu(en)
a) Enable Mode
CLK
Gn
Yn
th(dis)
tsu(dis)
b) Disable Mode
Figure 1. Enable and Disable Mode Relative to CLK↓
2.5-V TO 3.3-V High-Performance Clock Buffer
3 of 11
Notice: The information in this document is subject to change without notice.
October 2005
ASM2P2310A
rev 0.2
Absolute Maximum Ratings
Parameter
Rating
-0.5V to 4.6V
Supply Voltage range, VDD
Input Voltage range, VI1,2
Output Voltage range, VO
-0.5 V to VDD + 0.5 V
-0.5 V to VDD + 0.5 V
±50 mA
1,2
Continuous total output current, IO (VO = 0 to VDD
)
Package thermal impedance, θ 3: PW package
120°C/W
-65°C to 150°C
2KV
JA
Storage temperature range Tstg
Static Discharge Voltage , tDV (As per JEDEC STD22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Notes :
1 The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2 This value is limited to 4.6 V maximum.
3 The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions1
Parameter
Min
Typ
Max
-
3.6
0.8
0.7
-
Unit
2.3
2.5
Supply voltage, VDD
V
-
-
-
2
1.7
0
-
-
3.3
-
-
-
-
-
-
-
-
-
-
VDD = 3V to 3.6V
VDD = 2.3V to 2.7V
VDD = 3V to 3.6V
VDD = 2.3V to 2.7V
Low-level input voltage, VIL
High-level input voltage, VIH
V
V
V
-
VDD
12
6
12
6
Input voltage, VI
VDD = 3V to 3.6V
VDD = 2.3 V to 2.7V
VDD = 3V to 3.6V
High-level output current, IOH
mA
-
-
Low-level output current, IOL
mA
°C
V
DD = 2.3V to 2.7V
–40
85
Operating free-air temperature, TA
Note:1 Unused inputs must be held high or low to prevent them from floating.
2.5-V TO 3.3-V High-Performance Clock Buffer
4 of 11
Notice: The information in this document is subject to change without notice.
October 2005
rev 0.2
ASM2P2310A
Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ1 Max Unit
-
-
-
Input voltage
-
-
-1.2
±5
80
-
V
VIK
VDD = 3V,
VI = 0V or VDD
II = -18 mA
Input current
µA
µA
pF
pF
II
IDD
2
Static device current
Input capacitance
Output capacitance
-
CLK = 0V or VDD
,
IO = 0 mA
-
-
2.5
2.8
CI
CO
VDD = 2.3V to 3.6V,
VDD = 2.3V to 3.6V,
VI = 0V or VDD
VI = 0V or VDD
-
Note: 1 All typical values are at respective nominal VDD
.
2 For ICC over frequency, see Figure 6.
VDD = 3.3 V ±0.3 V
Symbol
Parameter
Test Conditions
Min
VDD - 0.2
Typ1
Max
Unit
-
-
VDD = Min to Max, IOH = -100 µA
High-level output
voltage
VOH
V
IOH = -12 mA
IOH = -6 mA
VDD = Min to Max, IOL = -100 µA
IOL = 12mA
2.1
2.4
-
-
-
-
-
-
-
-
VDD = 3 V
0.2
0.8
Low-level output
voltage
VOL
IOH
IOL
V
VDD = 3V
IOL = 6 mA
-
-
0.55
VDD = 3V,
VDD = 3.3V,
VDD = 3.6V,
VDD = 3V,
VDD = 3.3V,
VDD = 3.6V,
.
VO = 1V
-28
-
-
28
-
-
-
-36
-
-
36
-
-
High-level output
current
VO = 1.65V
VO = 3.135V
VO = 1.95V
VO = 1.65V
VO = 0.4V
mA
mA
-14
-
Low-level output
current
-
14
-
Note: 1 All typical values are at respective nominal VDD
VDD = 2.5 V ±0.2 V
Symbol
Parameter
Test Conditions
Min
Typ1
Max Unit
VDD - 0.2
-
-
VDD = Min to Max,
IOH = -100 µA
IOH = -6 mA
IOL = 100 µA
IOL = 6 mA
VO = 1V
VO = 1.25V
VO = 2.375V
VO = 1.2V
VOH
High-level output voltage
V
1.8
-
-
-17
-
-
17
-
-
-
-
-
-
VDD = 2.3V
0.2
0.55
VDD = Min to Max,
VDD = 2.3V
VDD = 2.3V,
VDD = 2.5V,
VOL
Low-level output voltage
High-level output current
V
-
-
IOH
mA
mA
-25
-
-
25
-
-
-10
-
VDD = 2.7V,
VDD = 2.3V,
VDD = 2.5V,
IOL
Low-level output current
-
VO = 1.25V
VO = 0.3V
10
V
DD = 2.7V,
Note: 1 All typical values are at respective nominal VDD
.
2.5-V TO 3.3-V High-Performance Clock Buffer
5 of 11
Notice: The information in this document is subject to change without notice.
October 2005
rev 0.2
ASM2P2310A
Timing Requirements
Over recommended ranges of supply voltage and operating free-air temperature
Symbol
Parameter
Test Conditions
VDD = 3 V to 3.6V
DD = 2.3 V to 2.7V
Min
0
0
Typ
Max
200
170
Unit
fclk
Clock frequency
MHz
V
Switching Characteristics
Over recommended operating free-air temperature range (unless otherwise noted)
VDD = 3.3 V ±0.3 V (See Figure 2)
Symbol
Parameter
Test Conditions
f = 0 MHz to 200 MHz
For circuit load,
see Figure 2.
Min
Typ
Max
Unit
tPLH
CLK to Yn
1.3
-
2.8
nS
tPHL
tsk(o)
tsk(p)
tsk(pp)
tr
Output skew (Ym to Yn)1(see Figure 4)
Pulse skew (see Figure 5)
Part-to-part skew
Rise time (see Figure 3)
-
-
-
-
-
-
-
-
-
-
-
-
100
250
500
2
2
-
-
-
pS
pS
pS
V/nS
V/nS
nS
nS
nS
nS
VO = 0.4V to 2V
VO = 2 V to 0.4V
0.7
0.7
0.1
0.1
0.4
0.4
tf
Fall time (see Figure 3)
tsu(en)
tsu(dis)
th(en)
th(dis)
Enable setup time,G_high before CLK↓
Disable setup time, G_low before CLK↓
Enable hold time, G_high after CLK ↓
Disable hold time, G_low after CLK ↓
-
Note: 1 The tsk(o) specification is only valid for equal loading of all outputs
VDD = 2.5 V ±0.2 V (See Figure 2)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
f = 0MHz to 170MHz
For circuit load,
see Figure 2.
tPLH
1.5
-
3.5
nS
CLK to Yn
tPHL
tsk(o)
Output skew (Ym to Yn)1(see Figure 4)
Pulse skew (see Figure 5)
Part-to-part skew
Rise time (see Figure 3)
170
400
600
1.4
1.4
-
-
pS
pS
pS
V/nS
V/nS
nS
nS
nS
nS
-
-
-
-
-
-
-
-
-
-
-
-
tsk(p)
tsk(pp)
tr
0.5
0.5
0.1
0.1
0.4
0.4
VO = 0.4V to 1.7V
VO = 1.7V to 0.4V
tf
Fall time (see Figure 3)
tsu(en
tsu(dis)
th(en)
th(dis)
Enable setup time,G_high before CLK↓
Disable setup time, G_low before CLK↓
Enable hold time, G_high after CLK ↓
Disable hold time, G_low after CLK ↓
-
-
Note: 1 The tsk(o) specification is only valid for equal loading of all outputs.
2.5-V TO 3.3-V High-Performance Clock Buffer
6 of 11
Notice: The information in this document is subject to change without notice.
October 2005
ASM2P2310A
rev 0.2
Parameter Measurement Information
From Output
Under Test
CL = 25 pF on Yn
500ꢀ
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 200 MHz, ZO = 50ꢀ, tr < 1.2 ns, tf < 1.2 ns.
Figure 2. Test Load Circuit
VDD
50% VDD
CLK
0 V
tPLH
tPHL
VOH
50% VDD
1.7V or 2V
Yn
0.4V
tr
0.4V
VOL
tf
Figure 3. Voltage Waveforms Propagation Delay Times
VDD
CLK
0 V
VOH
50% VDD
Any Y
VOL
VOH
50% VDD
Any Y
VOL
tSK(O)
tSK(O)
Figure 4. Output Skew
2.5-V TO 3.3-V High-Performance Clock Buffer
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Notice: The information in this document is subject to change without notice.
October 2005
rev 0.2
ASM2P2310A
VDD
50% VDD
CLK
Yn
0 V
VOH
tPLH
tPHL
50% VDD
VOL
NOTE: tsk(p) = | tPLH − tPHL
|
Figure 5. Pulse Skew
SUPPLY CURRENT
vs
FREQUENCY
f – Frequency – MHz
Figure 6.
2.5-V TO 3.3-V High-Performance Clock Buffer
8 of 11
Notice: The information in this document is subject to change without notice.
October 2005
ASM2P2310A
rev 0.2
Package Information
24L TSSOP Package (173 mil)
Dimensions
Millimeters
Symbol
Inches
Min
Max
0.043
0.0059
0.041
0.311
0.030
Min
…
0.05
0.80
7.70
0.50
Max
1.2
0.15
1.05
7.90
0.75
A
A1
A2
D
….
0.0020
0.031
0.3031
0.020
L
E
0.252 BSC
6.40 BSC
E1
R
R1
b
0.169
0.004
0.004
0.007
0.004
0.177
….
….
0.012
0.008
4.30
0.09
0.09
0.19
0.09
4.50
…..
…..
0.30
0.20
c
L1
e
a
0.039 REF
0.026 BSC
0°
1.0 REF
0.65 BSC
0°
8°
8°
2.5-V TO 3.3-V High-Performance Clock Buffer
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Notice: The information in this document is subject to change without notice.
October 2005
ASM2P2310A
rev 0.2
Ordering Information
Part Number
Marking
2P2310AF
2P2310AF
2P2310AG
2P2310AG
2P2310A
2P2310A
2I2310AF
2I2310AF
2I2310AG
2I2310AG
2I2310A
Package Type
24-Pin TSSOP, TAPE & REEL, Pb Free
24-Pin TSSOP, TUBE, Pb Free
24-Pin TSSOP, TAPE & REEL, Green
24-Pin TSSOP, TUBE, Green
24-Pin TSSOP, TAPE & REEL
24-Pin TSSOP, TUBE
Temperature
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
ASM2P2310AF-24TR
ASM2P2310AF-24TT
ASM2P2310AG-24TR
ASM2P2310AG-24TT
ASM2P2310A-24TR
ASM2P2310A-24TT
ASM2I2310AF-24TR
ASM2I2310AF-24TT
ASM2I2310AG-24TR
ASM2I2310AG-24TT
ASM2I2310A-24TR
ASM2I2310A-24TT
24-Pin TSSOP, TAPE & REEL, Pb Free
24-Pin TSSOP, TUBE, Pb Free
24-Pin TSSOP, TAPE & REEL, Green
24-Pin TSSOP, TUBE, Green
24-Pin TSSOP, TAPE & REEL
24-Pin TSSOP, TUBE
Industrial
Industrial
Industrial
Industrial
2I2310A
Industrial
Device Ordering Information
A S M 2 P 2 3 1 0 A F - 2 4 T R
R = Tape & reel, T = Tube or Tray
O = SOT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
D = QSOP
X = SC-70
Q = QFN
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(0C to +70C)
(-40C to +125C) (-40C to +85C)
1 = Reserved
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent Nos 5,488,627 and 5,631,920.
2.5-V TO 3.3-V High-Performance Clock Buffer
10 of 11
Notice: The information in this document is subject to change without notice.
October 2005
rev 0.2
ASM2P2310A
Copyright © Alliance Semiconductor
Alliance Semiconductor Corporation
2575 Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
All Rights Reserved
Advance Information
Part Number: ASM2P2310A
Document Version: v0.2
Fax: 408-855-4999
www.alsc.com
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
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potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
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2.5-V TO 3.3-V High-Performance Clock Buffer
11 of 11
Notice: The information in this document is subject to change without notice.
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