ASM2P3805E-20-DR [PULSECORE]

Low Skew Clock Driver, 3805 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20;


型号：	ASM2P3805E-20-DR
厂家：	PulseCore Semiconductor
描述：	Low Skew Clock Driver, 3805 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20 驱动光电二极管逻辑集成电路
文件：	总12页 (文件大小：191K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

January 2006

rev 0.2

ASM2P3805E

3.3V CMOS Dual 1-To-5 Clock Driver

Functional Description

Features

•

Advanced CMOS Technology

The ASM2P3805E is a 3.3V clock driver built using

advanced CMOS technology. The device consists of two

banks of drivers, each with a 1:5 fanout and its own output

enable control. The device has a "heartbeat" monitor for

diagnostics and PLL driving. The MON output is identical to

all other outputs and complies with the output specifications

in this document. The ASM2P3805E offers low capacitance

inputs. The ASM2P3805E is designed for high speed clock

distribution where signal quality and skew are critical. The

ASM2P3805E also allows single point-to-point transmission

line driving in applications such as address distribution,

where one signal must be distributed to multiple receivers

with low skew and high signal quality.

Guaranteed low skew < 200pS (max)

Very low propagation delay < 2.5nS (max)

Very low duty cycle distortion < 270pS (max)

Very low CMOS power levels

Operating frequency up to 166MHz

TTL compatible inputs and outputs

Inputs can be driven from 3.3V or 5V components

Two independent output banks with 3-state control

1:5 fanout per bank

"Heartbeat" monitor output

V_CC= 3.3V ± 0.3V

Available in SSOP and QSOP Packages

Block Diagram

Pin Diagram

OE_A

IN_A

V_CCA

OA₁

OA₁– OA₅

V_CCB

OB₁

OA₂

OB₂

OB₃

GND_B

OB₄

OB₅

OA₃

IN_B

OB₁– OB₅

MON

GND_A

OA₄

ASM2P3805E

OE_B

OA₅

GND_Q

OE_A

IN_A

MON

OE_B

IN_B

Alliance Semiconductor

2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

January 2006

ASM2P3805E

rev 0.2

Pin Description

Pin #

Pin Names

Description

9,12

O¯¯E_A, O¯¯E_B

IN_A, IN_B

3-State Output Enable Inputs (Active LOW)

Clock Inputs

10,11

2,3,4,6,7

OA₁-OA₅

OB₁-OB₅

Clock Outputs from Bank A

Clock Outputs from Bank B

19,18,17,15,14

V_CCA

V_CCB

Power supply for Bank A

Power supply for Bank B

Ground for Bank A

Ground for Bank B

Ground

GND_A

GND_B

GND_Q

MON

Monitor Output

Function Table¹

Inputs

Outputs

O¯¯E_A, O¯¯E_B

IN_A, IN_B

OA_n, OB_n

MON

Note: 1 H = HIGH; L = LOW; Z = High-Impedance

Capacitance (T_A= +25°C, f = 1.0MHz)

Symbol

C_IN

Parameter¹

Conditions

V_IN= 0V

Typ

Max

Unit

Input Capacitance

Output Capacitance

C_OUT

V_OUT= 0V

Note: 1 This parameter is measured at characterization but not tested.

3.3V CMOS Dual 1-To-5 Clock Driver

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Notice: The information in this document is subject to change without notice.

January 2006

ASM2P3805E

rev 0.2

Absolute Maximum Ratings¹

Symbol

Description

Max

Unit

V_CC

V_I

Input Power Supply Voltage

-0.5 to +4.6

-0.5 to +5.5

Input Voltage

V_O

T_J

Output Voltage

-0.5 to V_CC+0.5

150

Junction Temperature

Storage Temperature

° C

T_STG

-65 to +165

Static Discharge Voltage

(As per JEDEC STD22- A114-B)

T_DV

Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect

device reliability.

DC Electrical Characteristics over Operating Range

Following Conditions Apply Unless Otherwise Specified

Industrial: T_A= -40°C to +85°C, V_CC= 3.3V ± 0.3V

Symbol

Parameter

Test Conditions¹

Min

Typ²Max

Unit

V_IH

V_IL

Input HIGH Level

5.5

0.8

±1

Input LOW Level

Input HIGH Current

Input LOW Current

-0.5

I_IH

V_CC= Max.

V_I= 5.5V

I_IL

V_I= GND

V_O= V_CC

V_O= GND

±1

µA

I_OZH

I_OZL

V_IK

I_ODH

I_ODL

I_OS

±1

High Impedance Output Current

(3-State Outputs Pins)

V_CC= Max.

±1

Clamp Diode Voltage

Output HIGH Current

Output LOW Current

Short Circuit Current

V_CC= Min., I_IN= –18mA

_CC= 3.3V, V_IN= V_IHor V_IL, V_O= 1.5V^3,4

_CC= Max., V_O= GND^3,4

I_OL= 12mA

-45

-0.7

-74

-135

-1.2

-180

200

-240

-60

2.4⁵

V_CC- 0.2

V_CC= Min.

V_OH

Output HIGH Voltage

Output LOW Voltage

I_OH= –8mA

_OH= –100µA

V_IN= V_IHor V_IL

I_OL= 12mA

I_OL= 8mA

0.3

0.2

0.4

V_CC= Min.

V_OL

_IN= V_IHor V_IL

_OL= 100µA

0.2

Notes:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V_CC= 3.3V, 25°C ambient.

3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

4. This parameter is guaranteed but not tested.

5. V_OH= V_CC-0.6V at rated current.

3.3V CMOS Dual 1-To-5 Clock Driver

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Notice: The information in this document is subject to change without notice.

January 2006

ASM2P3805E

rev 0.2

Power Supply Characteristics

Symbol

Parameter

Test Conditions¹

Min

Typ²

Max

Unit

I_CCL

I_CCH

I_CCZ

Quiescent Power Supply

Current

V_CC= Max. V_IN= GND or V_CC

0.1

µA

Power Supply Current per

Input HIGH

V_CC= Max.

∆I_CC

300

120

µA

V_IN= V_CC–0.6V

V_CC= Max.

Dynamic Power Supply

Current per Output³

V_IN= V_CC

I_CCD

C_L= 15pF

µA/MHz

V_IN= GND

All Outputs Toggling

V_IN= V_CC

V_CC= Max.

210

260

240

310

_IN= GND

C_L= 15pF

All Outputs Toggling

f_i= 133MHz

V_IN= V_CC–0.6V

V_IN= GND

Total Power Supply

Current⁴

I_C

V_IN= V_CC

V_CC= Max.

V_IN= GND

C_L= 15pF

All Outputs Toggling

f_i= 166MHz

_IN= V_CC–0.6V

260

310

V_IN= GND

Notes:

1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V_CC= 3.3V, +25°C ambient.

3. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

4. I_C= IQUIESCENT + IINPUTS + IDYNAMIC

I_C= I_CC+ ∆I_CCD_HN_T+ I_CCD(f_ON_O)

I_CC= Quiescent Current (I_CCL, I_CCHand I_CCZ

)

∆I_CC= Power Supply Current for a TTL High Input (V_IN= V_CC-0.6V)

D_H= Duty Cycle for TTL Inputs High

N_T= Number of TTL Inputs at D_H

_CCD= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

f_O= Output Frequency

NO = Number of Outputs at f_O

3.3V CMOS Dual 1-To-5 Clock Driver

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Notice: The information in this document is subject to change without notice.

January 2006

ASM2P3805E

rev 0.2

Switching Characteristics Over Operating Range – ASM2P3805E^3,4

Symbol

Parameter

Conditions^1,8

Min²

Max

Unit

t_PLH

t_PHL

Propagation Delay

0.5

2.5

IN_Ato OA_n, INB to OB_n

Output Rise Time

t_R

t_F

(Measured from 0.7V to 1.7V)

Output Fall Time

(Measured from 1.7V to 0.7V)

t_SK(O)

t_SK(P)

Same device output pin to pin skew⁵

200

270

550

C_L= 15pF

Pulse skew^6,9

f ≤166MHz

t_SK(PP)

Part to part skew⁷

Output Enable Time

t_PZL

t_PZH

t_PLZ

t_PHZ

5.2

¯¯

OE_Ato OA_n, OE_Bto OB_n

Output Disable Time

5.2

¯¯

OE_Ato OA_n, OE_Bto OB_n

f_MAX

Input Frequency

166

MHz

Notes:

1. See test circuits and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. t_{PLH ,}t_PHLand t_SK(O)are production tested. All other parameters guaranteed but not production tested.

4. Propagation delay range indicated by Min and Max limit is due to V_CC, operating temperature and process parameters. These propagation delay limits do not

imply skew.

5. Skew measured between all outputs under identical transitions and load conditions.

6. Skew measured is difference between propagation delay times t_PHLand t_PLHof same outputs under identical load conditions.

7. Part to part skew for all outputs given identical transitions and load conditions at identical V_CClevels and temperature.

8. Airflow of 1m/s is recommended for frequencies above 133MHz.

9. This parameter is measured using f = 1MHz.

3.3V CMOS Dual 1-To-5 Clock Driver

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Notice: The information in this document is subject to change without notice.

January 2006

ASM2P3805E

rev 0.2

Test Circuits and Waveforms

V_CC

Open

GND

500Ω

V_IN

V_OUT

Pulse

D.U.T

Generator

R_L

C_L

R_T

500Ω

Enable and Disable Time Circuit

V_CC

1.5V

INPUT

t_PHL1

t_PLH1

V_IN

V_OH

1.5V

V_OL

V_OUT

OUTPUT 1

OUTPUT 2

Pulse

D.U.T

Generator

R_L

C_L

t_SK(O)

R_T

t_SK(O)

V_OH

1.5V

V_OL

t_PHL2

t_PLH2

C_L= 15pF Test Circuit

t_SK(O)= | t_PLH2- t_PLH1| or | t_PHL2- t_PHL1

Output Skew – t_SK(o)

Switch Position

Test

Test Conditions

Symbol

V_CC= 3.3V ±0.3V

Unit

Switch

C_L

R_T

R_L

Disable Low

Enable Low

Z_OUTof pulse generator

Ω

Disable High

Enable High

Ω

GND

t_R/ t_F

1 (0V to 3V or 3V to 0V)

Definitions:

C_L= Load capacitance: includes jig and probe capacitance.

R_T= Termination resistance: should be equal to Z_OUTof the Pulse

Generator.

_R/ t_F= Rise/Fall time of the input stimulus from the Pulse Generator.

3.3V CMOS Dual 1-To-5 Clock Driver

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Notice: The information in this document is subject to change without notice.

January 2006

ASM2P3805E

rev 0.2

Test Circuits and Waveforms

ENABLE

DISABLE

1.5V

INPUT

1.5V

CONTROL

INPUT

t_PHL1

t_PLH1

t_PZL

V_OH

1.5V

V_OL

t_PLZ

V_OH

Package 1

OUTPUT

V_OH

V_OL

OUTPUT

NORMALLY

LOW

1.5V

SWITCH

CLOSED

0.3V

t_SK(PP)

t_PHZ

V_OH

t_PZH

Package 2

OUTPUT

1.5V

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

V_OL

V_OH

V_OL

1.5V

V_OL

t_PHL2

t_PLH2

t_SK(PP)= | t_PLH2- t_PLH1| or | t_PHL2- t_PHL1

Enable and Disable Times

Part-to- Part Skew

Note: 1. Diagram shown for input Control Enable-LOW and input Control

Note: Part-to- Part Skew is for package and speed grade.

Disable-HIGH

INPUT

1.5V

t_PHL

t_PLH

V_OH

1.5V

V_OL

V_OH

2.0V

0.8V

OUTPUT

1.5V

V_OL

t_SK(P)= | t_PLH- t_PLH

t_R

t_F

Pulse Skew

Propagation Delay

3.3V CMOS Dual 1-To-5 Clock Driver

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Notice: The information in this document is subject to change without notice.

January 2006

ASM2P3805E

rev 0.2

Package Information

20-lead SSOP ( 209 mil ) Package

Dimensions

Millimeters

Symbol

Inches

Min

Max

0.079

…

Min

…

Max

2.0

…..

….

0.002

0.065

0.275

0.004

0.295

0.197

0.021

0.05

1.65

7.00

0.09

7.50

5.00

0.55

0.073

0.291

0.010

0.319

0.220

0.037

1.85

7.40

0.25

8.10

5.60

0.95

0.050 REF

1.25 REF

0.009

0.004

0°

0.015

….

0.22

0.09

0°

0.38

….

8°

0.0197 BASE

0.65 BASE

3.3V CMOS Dual 1-To-5 Clock Driver

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Notice: The information in this document is subject to change without notice.

January 2006

rev 0.2

ASM2P3805E

20-lead QSOP Package

Dimensions

Millimeters

Symbol

Inches

Min

Max

0.068

0.008

0.012

0.010

0.344

0.157

Min

1.52

0.10

0.23

0.18

8.56

3.81

Max

1.73

0.20

0.30

0.25

8.74

3.99

0.060

0.004

0.009

0.007

0.337

0.150

0.025 BSC

0.64 BSC

0.230

0.010

0.016

0.056

0°

0.244

0.016

0.035

0.060

8°

5.84

0.25

0.41

1.42

0°

6.20

0.41

0.89

1.52

8°

3.3V CMOS Dual 1-To-5 Clock Driver

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Notice: The information in this document is subject to change without notice.

January 2006

ASM2P3805E

rev 0.2

Ordering Information

Part Number

ASM2P3805EG-20-AR

ASM2P3805EG-20-AT

ASM2P3805EG-20-DR

ASM2P3805EG-20-DT

ASM2I3805EG-20-AR

ASM2I3805EG-20-AT

ASM2I3805EG-20-DR

ASM2I3805EG-20-DT

ASM2P3805E-20-AR

ASM2P3805E-20-AT

ASM2P3805E-20-DR

ASM2P3805E-20-DT

ASM2I3805E-20-AR

ASM2I3805E-20-AT

ASM2I3805E-20-DR

ASM2I3805E-20-DT

Marking

2P3805EG

Package Type

20-Pin SSOP, TAPE & REEL, Green

20-Pin SSOP, TUBE, Green

20-Pin QSOP, TAPE & REEL, Green

20-Pin QSOP, TUBE, Green

20-Pin SSOP, TAPE & REEL, Green

20-Pin SSOP, TUBE, Green

20-Pin QSOP, TAPE & REEL, Green

20-Pin QSOP, TUBE, Green

20-Pin SSOP, TAPE & REEL

20-Pin SSOP, TUBE

Temperature

Commercial

Industrial

2P3805EG

2I3805EG

2P3805E

2I3805E

Industrial

Commercial

Industrial

20-Pin QSOP, TAPE & REEL

20-Pin QSOP, TUBE

20-Pin SSOP, TAPE & REEL

20-Pin SSOP, TUBE

2I3805E

Industrial

2I3805E

20-Pin QSOP, TAPE & REEL

20-Pin QSOP, TUBE

Industrial

2I3805E

Industrial

3.3V CMOS Dual 1-To-5 Clock Driver

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Notice: The information in this document is subject to change without notice.

January 2006

ASM2P3805E

rev 0.2

Device Ordering Information

A S M 2 P 3 8 0 5 E G - 2 0 - A T

R = Tape & reel, T = Tube or Tray

O = SOT

U = MSOP

E = TQFP

L = LQFP

U = MSOP

P = PDIP

S = SOIC

T = TSSOP

A = SSOP

V = TVSOP

B = BGA

D = QSOP

X = SC-70

Q = QFN

DEVICE PIN COUNT

F = LEAD FREE AND RoHS COMPLIANT PART

G = GREEN PACKAGE

PART NUMBER

X= Automotive

I= Industrial

P or n/c = Commercial

(0C to +70C)

(-40C to +125C) (-40C to +85C)

1 = Reserved

6 = Power Management

7 = Power Management

8 = Power Management

9 = Hi Performance

0 = Reserved

2 = Non PLL based

3 = EMI Reduction

4 = DDR support products

5 = STD Zero Delay Buffer

ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT

Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.

3.3V CMOS Dual 1-To-5 Clock Driver

11 of 12

Notice: The information in this document is subject to change without notice.

January 2006

rev 0.2

ASM2P3805E

Alliance Semiconductor Corporation

2575 Augustine Drive,

Santa Clara, CA 95054

Tel# 408-855-4900

Part Number: ASM2P3805E

Document Version: 0.2

Fax: 408-855-4999

www.alsc.com

Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003

trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their

respective companies. Alliance reserves the right to make changes to this document and its products at any time without

notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein

represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this

data at any time, without notice. If the product described herein is under development, significant changes to these

specifications are possible. The information in this product data sheet is intended to be general descriptive information for

potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or

customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product

described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products

including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual

property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).

All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of

products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any

other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical

components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant

injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer

assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

3.3V CMOS Dual 1-To-5 Clock Driver

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Notice: The information in this document is subject to change without notice.

ASM2P3805E-20-DR [PULSECORE]

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