ASM3P4201AG-28-TR [PULSECORE]
Multi-Output Custom Clock Generator; 多路输出定制时钟发生器型号: | ASM3P4201AG-28-TR |
厂家: | PulseCore Semiconductor |
描述: | Multi-Output Custom Clock Generator |
文件: | 总7页 (文件大小:322K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
July 2006
rev 0.2
ASM3P4201A
Multi-Output Custom Clock Generator
Features
clock generator. The five high frequency Clock outputs
are generated using an inexpensive 20MHz Crystal or
external reference clock. The accuracy of the 20MHz
Input Clock should be within ±50ppm. The output clocks
consist of a low EMI spread spectrum clock and other
non-spread clocks. Three Select bits choose the
combination of Output Clock Frequency. Refer to the
Output Frequency Selection Table for the values. Output
clocks can be disabled using the STBY pin. The device
operates from a Supply Voltage of 3.3V±0.3V with a
tolerable ripple voltage of 50mV . The device is available
in a 20 pin TSSOP JEDEC package.
• Generates five clock outputs from an inexpensive
20MHz crystal or external reference clock.
• Output Frequencies are selectable through select bits
• Generates an EMI optimized clock signal at the output.
• ±1.5% (Typ) Centre Spread for Spread Spectrum Clock
Outputs
• Operates with a 3.3V ± 0.3V Supply Voltage
• Output Clocks disable feature using STBY pin
• Available in 20-pin TSSOP.
Product Description
The ASM3P4201A is a versatile multi output custom
Block Diagram
STBY
S0 S1 S2
VDD
CLK6
CLK1
XIN
Crystal
XOUT
Oscillator
PLL
CLK5
CLK2
CLK3
CLK4
GND
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
July 2006
ASM3P4201A
rev 0.2
Pin Assignment
20
19
18
17
16
15
XOUT
VDD
1
2
3
4
XIN
S0
STBY
S1
S2
CLK6
VDD
5
6
VDD
GND
CLK1
NC
ASM3P4201A
GND
14
13
12
11
CLK3
7
8
CLK4
CLK5
NC
9
CLK2
GND
10
20 pin TSSOP
Pin Description
Pin #
1
Pin Name Pin Type
Pin Description
Crystal connection or external reference frequency input. It can be connected to
a 20MHz Fundamental mode crystal or to an external reference clock.
XIN
Input
Input
Input
Select Bit for Desired Output Frequency at different output pins. Refer to the
Output Frequency Selection Table for details. Has an internal pull down resistor
Select Bit for Desired Output Frequency at different output pins. Refer to the
Output Frequency Selection Table for details. Has an internal pull down resistor
2
S0
3
S1
4
5
6
7
8
CLK6
VDD
GND
CLK1
NC
Output
Power
Power
Output
-
Clock Output. Refer to the Output Frequency Selection Table for details.
Connect to +3.3V.
Connect to ground.
Clock Output. Refer to the Output Frequency Selection Table for details.
No connect
9
CLK2
GND
NC
Output
Power
-
Clock Output. Refer to the Output Frequency Selection Table for details.
Connect to ground.
No connect
10
11
12
CLK5
Output
Clock Output. Refer to the Output Frequency Selection Table for details.
Spread Spectrum Clock Output. Refer to the Output Frequency Selection Table
13
CLK4
Output
for details.
Spread Spectrum Clock Output. Refer to the Output Frequency Selection Table
14
CLK3
Output
for details.
15
16
GND
VDD
Power
Power
Connect to ground.
Connect to +3.3V.
Select Bit for Desired Output Frequency at different output pins. Refer to the
17
S2
Input
Output Frequency Selection Table for details. Has an internal pull down resistor
18
19
STBY
VDD
Input
Power
When this pin is made is HIGH, all the output clocks are enabled.
Connect to +3.3V.
Crystal connection. If an external reference clock is used, this pin must be left
20
XOUT
Output
unconnected.
Multi-Output Custom Clock Generator
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Notice: The information in this document is subject to change without notice.
July 2006
rev 0.2
ASM3P4201A
Output Frequency Selection Table
Selection
CLK1
CLK2
(MHz)
CLK3*
(MHz)
CLK4*
(MHz)
CLK5
CLK6
(MHz)
Bits
(MHz)
(MHz)
S2
0
S1
0
0
S0
0
1
39.5
39.5
39.5
39.5
20
20
20
20
65
60
50
75
20
20
20
20
84
84
36
84
36.6
36.6
36.6
36.6
0
0
1
1
0
1
0
* CLK3 and CLK4 are Spread Spectrum Clocks
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
VDD
VIN
TSTG
TA
Ts
TJ
Power Supply Voltage relative to Ground
Input Voltage relative to Ground (Input Pins)
Storage temperature
-0.5 to +4.6
-0.5 to VDD+0.3
-65 to +150
-20 to +85
260
V
°C
°C
°C
°C
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
125
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
TDV
2
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
DC Electrical Characteristics
(Test condition: All parameters are measured at room temperature (+ 25°C) unless otherwise stated)
Symbol
VIL
Parameter
Min
GND - 0.3
Typ
-
-
-
-
3
3
-
-
TBD
TBD
3.3
-
Max
0.8
VDD + 0.3
Unit
V
V
µA
µA
mA
mA
V
Input low voltage
Input high voltage
Input low current
Input high current
VIH
IIL
IIH
2.0
-
-
-
-
-
2.5
-
-
3.0
-
-
-35
35
-
-
0.4
-
-
-
IXOL
IXOH
VOL
VOH
IDD
ICC
VDD
tON
XOUT output low current (VXOL@0.4V, VDD=3.3V)
XOUT output high current (VXOH @2.5V, VDD=3.3V)
Output low voltage (VDD = 3.3V, IOL =12mA)
Output high voltage (VDD = 3.3V, IOH =12mA)
Static supply current*
Dynamic supply current ( VDD =3.3V )
Operating Voltage
Power-up time (first locked cycle after power-up)**
Output impedance
V
mA
mA
V
mS
Ω
3.6
5
-
ZOUT
17
* XIN and STBY Pins are pulled low
** VDD and XIN input are stable,
Multi-Output Custom Clock Generator
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Notice: The information in this document is subject to change without notice.
July 2006
rev 0.2
ASM3P4201A
AC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max Unit
CLKIN
Input frequency
-
20
-
MHz
Output Frequency =20MHz (Pin 13)
Output Frequency = 50MHz
Output Frequency = 60MHz
Output Frequency = 65MHz
Output Frequency = 75MHz
fd
Spread Percentage
-
±1.5
-
%
tLH*
Output rise time (Measured from 0.8V to 2.0V)
Output fall time ( Measured from 2.0V to 0.8V)
Jitter (Cycle to cycle)
-
-
-
1
1
nS
nS
pS
pS
%
tHL
*
-
tJC
tp
-
±250
±150
50
-
Jitter( Period)
-
-
tD
Output duty cycle
45
55
*tLH and tHL are measured into a capacitive load of 30pF
Multi-Output Custom Clock Generator
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Notice: The information in this document is subject to change without notice.
July 2006
ASM3P4201A
rev 0.2
Package Information
20-lead Thin Shrunk Small Outline Package (4.40-MM Body) – JEDEC Standard
Dimensions
Millimeters
Symbol
Inches
Min
Max
0.043
0.0059
0.041
0.26
Min
…
0.05
0.80
6.40
0.50
Max
1.2
0.15
1.05
6.60
0.75
A
A1
A2
D
….
0.0020
0.031
0.252
0.020
L
0.030
E
0.252 BSC
6.40 BSC
E1
R1
b
0.169
0.004
0.007
0.004
0.177
….
0.012
0.008
4.30
0.09
0.19
0.09
4.50
…..
0.30
0.20
c
L1
e
a
0.039 REF
0.026 BSC
0°
1.0 REF
0.65 BSC
0° 8°
8°
Multi-Output Custom Clock Generator
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Notice: The information in this document is subject to change without notice.
July 2006
rev 0.2
ASM3P4201A
Ordering Information
Part Number
Marking
Package
Temperature
Commercial
Commercial
ASM3P4201AG-28-TT
ASM3P4201AG-28-TR
3P4201AG
3P4201AG
20-Pin TSSOP, Tube, Green
20-Pin TSSOP, Tape and Reel, Green
Device Ordering Information
A S M 3 P 4 2 0 1 A G - 2 0 - T T
OR – TSOT23 -6,T/R
TT – TSSOP, TUBE
TR – TSSOP, T/R
VT – TVSOP, TUBE
VR – TVSOP, T/R
ST – SOIC, TUBE
AR – SSOP, T/R
SR – SOIC, T/R
QR – QFN, T/R
QT – QFN, TRAY
BT – BGA, TRAY
BR – BGA, T/R
UR – SOT-23, T/R
DR – QSOP, T/R
DT – QSOP, TUBE
AT – SSOP, TUBE
PIN COUNT
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER
X = Automotive
(-40C to +125C)
I = Industrial
P or n/c = Commercial
(0C to +70C)
(-40C to +85C)
1 – reserved
6 – power management
7 – power management
8 – power management
9 – Hi performance
0 - reserved
2 – Non PLL based
3 – EMI Reduction
4 – DDR support products
5 – STD Zero Delay Buffer
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent Nos 5,488,627 and 5,631,920
Multi-Output Custom Clock Generator
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Notice: The information in this document is subject to change without notice.
July 2006
rev 0.2
ASM3P4201A
.
Copyright © PulseCore Semiconductor
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200
Campbell, CA 95008
All Rights Reserved
Part Numbers: ASM3P4201A
Document Version: 0.2
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
© Copyright 2003 PulseCore Semiconductor. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of PulseCore. All other brand and product names may be the trademarks of their
respective companies. PulseCore reserves the right to make changes to this document and its products at any time without
notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein
represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct
this data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from
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The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights,
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for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result
in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the
manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use
Multi-Output Custom Clock Generator
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Notice: The information in this document is subject to change without notice.
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