5962-8766503XX [PYRAMID]
Microprocessor, 16-Bit, 30MHz, CMOS, BRAZE, DIP-64;
| 型号： | 5962-8766503XX |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | Microprocessor, 16-Bit, 30MHz, CMOS, BRAZE, DIP-64 |
| 文件： | 总24页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PACE1750A
SINGLE CHIP, 15MHz to 40MHz,
CMOS 16-BIT PROCESSOR
FEATURES
Implements the MIL-STD-1750A Instruction Set
Architecture
Single Chip PACE Technology CMOS 16-Bit
Processor with 32 and 48-Bit Floating Point
Arithmetic
DAIS Instruction Mix Execution Performance
Including Floating Point Arithmetic
15, 20, 30, and 40 MHz Operation over the
Military Temperature Range
Extensive Error and Fault Management and
Interrupt Capability
24 User Accessible Registers
Single 5V ± 10% Power Supply
TM
Power Dissipation over Military Temperature
Range
1.3 MIPS at 20 MHz
1.9 MIPS at 30 MHz
2.6 MIPS at 40 MHz
< 0.30 watts at 20 MHz
< 0.35 watts at 30 MHz
< 0.40 watts at 40 MHz
TTL Signal Level Compatible Inputs and
Outputs
Multiprocessor and Co-processor Capability
Built-In Function (BIF) for User Defined
Instructions
Two programmable Timers
Available in:
– 64-Pin DIP or Gull Wing (50 Mil Pin Centers)
– 68-Pin Pin Grid Array (PGA)
– 68-Lead Quad Pack (Leaded Chip Carrier)
Integer DAIS Mix Performance
3.9 MIPS at 40 MHz
Conventional Integer Processing Mix
Performance
5.0 MIPS at 40 MHz
Instruction Execution at 40 MHz over the
Military Temperature Range
0.10 µsec Integer Add/Sub
0.57 µsec Integer Multiply
0.70 µsec Floating Point Add/Sub
1.07 µsec Floating Point Multiply
GENERAL DESCRIPTION
levels of prioritized internal and external interrupts, and a
faults and exceptions handler controlling internally and
externally generated faults.
The PACE1750A is a general purpose, single chip, 16-bit
CMOS microprocessor designed for high performance
floating point and integer arithmetic, with extensive real
timeenvironmentsupport. Itoffersavarietyofdatatypes,
includingbits, bytes, 16-bitand32-bitintegers, and32-bit
and48-bitfloatingpointnumbers. Itprovides13addressing
modes, including direct, indirect, indexed, based, based
indexed and immediate long and short, and it can access
2 MWords of segmented memory space (64 KWords
segments).
Themicroprocessorachievesveryhighthroughputof2.6
MIPS for a standard real time integer/floating point
instructionmixata40MHzclock. ItexecutesintegerAdd
in 0.1 µs, integer Multiply in 0.575 µs, Floating Point Add
in 0.7 µs, and Floating Point Multiply in 1.075 µs, for
register operands at a 40 MHz clock speed.
ThePACE1750Ausesasinglemultiplexed16-bitparallel
bus. Status signals are provided to determine whether
the processor is in the memory or I/O bus cycle, reading
and writing, and whether the bus cycle is for data or
instructions.
The PACE1750A offers a well-rounded instruction set
with 130 instruction types, including a comprehensive
integer,floatingpoint,integer-to-floatingpointandfloating
point-to-integer set, a variety of stack manipulation
instructions, high level language support instructions
such as Compare Between Bounds and Loop Control
Instructions. It also offers some unique instructions such
as vectored l/O, supports executive and user modes, and
providesanescapemechanismwhichallowsuser-defined
instructions using a coprocessor.
Thebasicbuscycleis4clockslong. ThePACE1750Awill
extend the cycle by insertion of wait states in the address
and data phases (in response to RDYA and RDYD
signals, repectively) and will hold the machine in HI-Z if
this CPU has not acquired the bus. A typical non-bus
cycle is three clocks long. However, variable length
cyclesareusedforsuchrepetitiveoperationsasmultiply,
divide, scale and normalize, reducing significantly the
numberofCPUCLOCKSperoperationstepandresulting
in very fast integer and floating point execution times.
The chip includes 16 general purpose registers, 8 other
user-accessible registers, and an array of real time
application support resources, such as 2 programmable
timers, a complete interrupt controller supporting 16
Do c um e nt # MICRO-3 Re v. C
Re vise d Oc to b e r 2005
PACE1750A
1
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range
-0.5V to 7.0V
-0.5V to V + 0.5V
Thermal resistance, junction-to-case (Θ ), Note 5:
JC
Cases X and T
Cases Y and U
Case Z
8°C/W
5°C/W
6°C/W
Input Voltage Range
CC
Storage Temperature Range -65°C to + 150°C
Input Current Range
-30mA to +5mA
-0.5V to VCC + 0.5V
Voltage Applied to Inputs
Current Applied to Outputs
RECOMMENDED OPERATING
CONDITIONS
3
150 mA
Supply Voltage Range
4.5V to 5.5V
2
Maximum Power Dissipation 1.5W
Case Operating Temperature -55°C to +125°C
Range
Operating worst case power dissipation (outputs
open):
Device type 01
Device type 02
Device type 03
0.25W at 15 MHz
0.30W at 20 MHz
0.35W at 30 MHz
Device type 04
0.40W at 40 MHz
300°C
Lead Temperature Range
(soldering 10 seconds)
NOTE 1:
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability.
NOTE 2:
Must withstand the added power dissipation due to short circuit test e.g., I
OS
NOTE 3:
Duration one second or less.
NOTE 4: Device Type Definitions from 5962-87665 SMD:
Device Type 01: 15 MHz
Device Type 02: 20 MHz
Device Type 03: 30 MHz
Device Type 04: 40 MHz
NOTE 5: Case Definitions from 5962-87665 SMD:
Case X: Dual In-Line
Case T: Dual In-Line with Gull-Wing Leads
Case Y: Leaded Chip Carrier with Gull-Wing Leads
Case U: Leaded Chip Carrier with Unformed Leads
Case Z: Pin Grid Array
Do c um e nt # MICRO-3 Re v. C
Pa g e 2 o f 24
PACE1750A
DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions)
1
Symbol
Parameter
Min
Max
V + 0.5
CC
Unit
Conditions
V
V
V
Input HIGH Level Voltage
2.0
V
IH
2
Input LOW Level Voltage
–0.5
0.8
V
IL
Input Clamp Diode Voltage
–1.2
V
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5V, I = –18mA
IN
CD
2.4
V
= 4.5V
= 4.5V
= 4.5V
= 4.5V
I
I
I
I
= –8.0mA
= –300µA
= 8.0mA
= 300µA
OH
OH
OL
OL
V
Output HIGH Level Voltage
OH
OL
V
– 0.2
V
CC
0.5
0.2
V
V
Output LOW Level Voltage
Input HIGH Level Current,
V
I
I
I
I
except IB – IB ,
10
50
µA
µA
µA
µA
V
IN
V
IN
V
IN
V
IN
= V , V = 5.5V
CC CC
IH1
0
15
BUS BUSY, BUS LOCK
Input HIGH Level Current,
IB – IB ,
= V , V = 5.5V
CC CC
IH2
IL1
IL2
0
15
BUS BUSY, BUS LOCK
Input LOW Level Current,
except IB – IB ,
–10
–50
= GND, V = 5.5V
CC
0
15
BUS BUSY, BUS LOCK
Input LOW Level Current,
IB – IB ,
= GND, V = 5.5V
CC
0
15
BUS BUSY, BUS LOCK
Output Three-State Current
Output Three-State Current
I
I
50
µA
µA
V
V
V
= 2.4V, V = 5.5V
CC
OZH
OUT
–50
= 0.5V, V = 5.5V
CC
OZL
OUT
Quiescent Power Supply
Current (CMOS Input
Levels)
< 0.2V or < V – 0.2V,
CC
IN
I
10
50
mA
mA
f = 0MHz, Outputs Open,
CCQC
V
CC
= 5.5V
Quiescent Power Supply
Current (TTL Input
Levels)
V
IN
< 3.4V, f = 0MHz,
I
I
Outputs Open,
CCQT
V
CC
= 5.5V
Dynamic Power
Supply Current
15 MHz
40
50
60
70
mA
mA
mA
mA
mA
pF
V = 0V to V , tr = tf = 2.5 ns,
IN CC
CCD
20 MHz
30 MHz
Outputs Open,
V
CC
= 5.5V
40 MHz
3
I
Output Short Circuit Current
–25
V = GND, V = 5.5V
OUT CC
OS
C
C
C
Input Capacitance
10
15
15
IN
Output Capacitance
pF
OUT
Bi-directional Capacitance
pF
I/O
Notes
1. 4.5V ≤ V ≤ 5.5V, –55°C ≤ T ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
CC
C
2. V = –3.0V for pulse widths less than or equal to 20ns.
IL
3. Duration of the short should not exceed one second; only one output may be shorted at a time.
Do c um e nt # MICRO-3 Re v. C
Pa g e 3 o f 24
PACE1750A
SIGNAL PROPAGATION DELAYS1,2
15 MHz
20 MHz
30 MHz
40 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Symbol
tC(BR)L
tC(BR)H
tBGV(C)
tC(BG)X
tC(BB)L
tC(BB)H
tBBV(C)
tC(BB)X
tC(BL)L
Parameter
Unit
BUS REQ
BUS REQ
BUS GNT
BUS GNT
45
45
33
33
25
25
22
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
setup
hold
5
5
5
5
5
5
5
5
LOW
BUS BUSY
BUS BUSY
BUS BUSY
BUS BUSY
BUS LOCK
BUS LOCK
BUS LOCK
BUS LOCK
35
35
25
25
24
20
20
15
HIGH
setup
hold
5
5
5
5
5
5
5
5
LOW
HIGH
setup
hold
50
50
30
30
25
25
21
17
tC(BL)H
tBLV(C)
tC(BL)X (IN)
tC(ST)V
tC(ST)V
5
5
5
5
5
5
5
5
M/ , R/ Status
IO W
45
40
30
25
25
20
20
20
AS0-AS3, AK0-AK3, D/I Status
AS0-AS3, AK0-AK3, D/I Status,
M/ , R/
tC(ST)X
0
0
0
0
ns
IO
W
STRBA HIGH
25
25
22
22
17
17
16
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tC(SA)H
tC(SA)L
tSAL(IBA)X
tRAV(C)
STRBA LOW
Address hold from STRBA LOW
RDYA setup
5
5
5
5
5
5
5
5
5
5
5
5
RDYA hold
tC(RA)X
LOW write
STRBD
25
25
25
22
22
22
17
17
17
14
14
14
tC(SDW)L
tC(SD)H
HIGH
STRBD
LOW read
STRBD
tFC(SDR)L
tSDRH(IBD)X
tSDWH(IBD)X
tSDL(SD)H
tRDV(C)
HIGH
STRBD
0
45
50
5
0
30
40
5
0
25
35
5
0
17
20
5
HIGH
STRBD
write
STRBD
RDYD setup
RDYD hold
5
5
5
5
tC(RD)X
IB0-IB15
45
30
25
20
tC(IBA)V
IB0-IB15
0
5
8
0
0
5
7
0
0
5
6
0
0
5
5
0
tFC(IBA)X
tIBDRV(C)
tC(IBD)X
IB0-IB15 setup
IB0-IB15 hold (read)
Data valid out (write)
tC(IBD)X
Do c um e nt # MICRO-3 Re v. C
Pa g e 4 o f 24
PACE1750A
1,2 (continued)
SIGNAL PROPAGATION DELAYS
15 Mhz
20 MHz
30 MHz
40 MHz
Min
Max
45
45
45
45
45
45
75
65
Min
Max
Min
Max
Min
Max
Symbol
tFC(IBD)V
tC(SNW)
Parameter
Unit
IB0-IB15
SNEW
30
30
30
40
40
40
60
50
25
26
26
35
35
35
50
40
20
ns
22
22
30
30
30
45
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TRIGO RST
DMA enable
DMA enable
tFC(TGO)
tRSTL(DMA ENL)
tC(DME)
Normal power up
tFC(NPU)
tC(ER)
Clock to major error unrecoverable
RESET
tRSTL(NPU)
tREQV(C)
tC(REQ)X
tFV(BB)H
tBBH(F)X
tIRV(C)
Console request
0
10
5
0
10
5
0
10
5
0
10
5
Console request
Level sensitive faults
Level sensitive faults
IOL1-2INT user interrupt (0-5)
5
5
5
5
0
0
0
0
Power down interrupt level sensitive
hold
tC(IR)X
10
30
10
25
10
20
10
15
ns
Reset pulse width
ns
ns
ns
ns
t
RSTL (tRSTH)
Clock to three-state
Edge sensitiive pulse width
Clock rise and fall
30
5
22
5
17
5
13
5
tC(XX)Z
f(F), t1(1)
tr, tf
5
5
5
5
t
Notes
1. 4.5V ≤ V ≤ 5.5V, –55°C ≤ T ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
CC
C
2. All timing parameters are composed of Three elements. The first "t" stands for timing. The second represents the "from" signal. The third in
parenthesesindicates"to"signal. WhentheCPUclockisoneofthesignalelements, eithertherisingedge"C"orthefallingedge"FC"isreferenced.
When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high
impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.
Do c um e nt # MICRO-3 Re v. C
Pa g e 5 o f 24
PACE1750A
MINIMUM WRITE BUS CYCLE TIMING DIAGRAM
Note:
All time measurements on active signals relate to the 1.5 volt level.
Do c um e nt # MICRO-3 Re v. C
Pa g e 6 o f 24
PACE1750A
MINIMUM READ BUS CYCLE TIMING DIAGRAM
Note:
All time measurements on active signals relate to the 1.5 volt level.
Do c um e nt # MICRO-3 Re v. C
Pa g e 7 o f 24
PACE1750A
MINIMUM WRITE BUS CYCLE, FOLLOWED BY A NON-BUS CYCLE, TIMING DIAGRAM
Note:
All time measurements on active signals relate to the 1.5 volt level.
Do c um e nt # MICRO-3 Re v. C
Pa g e 8 o f 24
PACE1750A
TRIGO RST DISCRETE TIMING DIAGRAM
DMA EN DISCRETE
TIMING DIAGRAM
NORMAL POWER UP DISCRETE TIMING DIAGRAM
XIO OPERATIONS
SNEW DISCRETE TIMING DIAGRAM
Note:
All time measurements on active signals relate to the 1.5 volt level.
Do c um e nt # MICRO-3 Re v. C
Pa g e 9 o f 24
PACE1750A
EXTERNAL FAULTS AND INTERRUPTS TIMING DIAGRAM
Edge-sensitive interrupts and faults (SYSFLT ,
Level-sensitive interrupts
0
SYSFLT ) min. pulse width
1
Note:
tC(IR) max = 35 clocks
X
Level-sensitive faults
CON REQ
Note:
All time measurements on active signals relate to the 1.5 volt level.
Do c um e nt # MICRO-3 Re v. C
Pa g e 10 o f 24
PACE1750A
BUS ACQUISITION
Note:
A CPU contending for the BUS will assert the BUS REQ line, and will acquire it when BUS GNT is assserted and the BUS is not locked
(BUS LOCK is high).
SWITCHING TIME TEST CIRCUITS
Standard Output (Non-Three-State)
Three-State
Note:
All time measurements on active signals relate to the 1.5 volt level.
Parameter
V0
≥ 3V
0V
VMEA
0.5V
t
PLZ
t
t
t
V
CC
– 0.5V
PHZ
PXL
PXH
V
V
/2
/2
1.5V
1.5V
CC
CC
Do c um e nt # MICRO-3 Re v. C
Pa g e 11 o f 24
PACE1750A
SIGNAL DESCRIPTIONS
CLOCKS AND EXTERNAL REQUESTS
Mnemonic
Name
Description
CPU CLK
CPU clock
Asinglephaseinputclocksignal(0-40MHz, 40percentto60percentduty
cycle.
TIMER CLK
Timer clock
A 100 KHz input that, after synchronization with CPU CLK, provides the
clock for timer A and timer B. If timers are used, the CPU CLK signal
frequency must be > 300 KHz.
RESET
Reset
An active LOW input that initializes the device.
CON REQ
Console request
An active LOW input that initiates console operations after completion of
the current instruction.
INTERRUPT INPUTS
Mnemonic
Name
Description
PWRDN INT
Power down interrupt An interrupt request input that cannot be masked or disabled. This signal
is active on the positive going edge or the high level, according to the
interrupt mode bit in the configuration register.
USR INT -
User interrupt
Interrupt request input signals that are active on the positive going edge
or the high level, according to the interrupt mode bit in the configuration
register.
0
USR INT
5
IOL INT -
I/O level interrupts
Active HIGH interrupt request inputs that can be used to expand the
number of user interrupts.
1
IOL INT
2
FAULTS
Mnemonic
MEM PRT ER
Name
Description
Memory protect error
An active LOW input generated by the MMU or BPU, or both and sampled
by the BUS BUSY signal into the Fault Register (bit 0 CPU bus cycle, bit
1 if non-CPU bus cycle).
MEM PAR ER
EXT ADR ER
Memory parity error
AnactiveLOWinputsampledbytheBUSBUSYsignalintobit2ofthefault
register.
External address error An active LOW input sampled by the BUS BUSY signal into the Fault
register (bit 5 or 8), depending on the cycle (memory or I/O).
SYSFLT
SYSFLT
System fault ,
Asynchronous, positive edge-sensitive inputs that set bit 7 (SYSFLT )
0
0
1
0
System fault ,
or bits 13 and 15 (SYSFLT ) in the Fault register.
1
1
ERROR CONTROL
Mnemonic
Name
Description
UNRCV ER
Unrecoverable error
An active HIGH output that indicates the occurrence of an error classified
as unrecoverable.
MAJ ER
Major error
An active HIGH output that indicates the occurrence of an error classified
as major.
Do c um e nt # MICRO-3 Re v. C
Pa g e 12 o f 24
PACE1750A
SIGNAL DESCRIPTIONS (Continued)
BUS CONTROL
Mnemonic
Name
Description
D/I
Data or instruction
Anoutputsignalthatindicateswhetherthecurrentbuscycleaccessisfor
Data (HIGH) or Instruction (LOW). It is three-state during bus cycles not
assigned to the CPU. This line can be used as an additional memory
address bit for systems that require separate data and program memory.
R/W
Read or write
An output signal that indicates direction of data flow with respect to the
current bus master. A HIGH indicates a read or input operation and a
LOWindicatesawriteoroutputoperation. Thesignalisthree-stateduring
bus cycles not assigned to the CPU.
M/IO
Memory or I/O
Address strobe
Address ready
Data strobe
An output signal that indicates whether the current bus cycle is memory
(HIGH) or I/O (LOW). This signal is three-state during bus cycles not
assigned to the CPU.
STRBA
RDYA
STRBD
RDYD
An active HIGH output that can be used to externally latch the memory or
I/O address at the HIGH-to-LOW transition of the strobe. The signal is
three-state during bus cycles not assigned to the CPU.
An active HIGH input that can be used to extend the address phase of a
buscycle. WhenRDYAisnotactive,waitstatesareinsertedbythedevice
to accommodate slower memory or I/O devices.
AnactiveLOWoutputthatcanbeusedtostrobedatainmemoryandXIO
cycles. This signal is three-state during bus cycles not assigned to the
CPU.
Data ready
An active HIGH input that extends the data phase of a bus cycle. When
RDYDisnotactive,waitstatesareinsertedbythedevicetoaccommodate
slower memory or I/O devlces.
INFORMATION BUS
Mnemonic Name
IB - IB
Description
Information bus
A bidirectional time-multiplexed address/data bus that is three-state
0
15
during bus cycles not assigned to the CPU. IB is the most significant bit.
0
STATUS BUS
Mnemonic
Name
Description
AK - AK
Access key
Outputs used to match the access lock in the MMU for memory accesses
(a mismatch will cause the MMU to pull the MEM PRT ER signal LOW),
and also indicates processor state (PS). Privileged instructions can be
executed with PS = 0 only. These signals are three-state during bus
cycles not assigned to the CPU.
0
3
AS - AS
Address state
Outputs that select the page register group in the MMU. It is three-state
during bus cycles not assigned to the CPU. [These outputs together with
D/I can be used to expand the device direct addressing space to 4
MBytes, in a nonprotected mode (no MMU)]. However, using this
addressingmodemayproducesituationsnotspecifiedinMIL-STD-1750.
0
3
Do c um e nt # MICRO-3 Re v. C
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PACE1750A
SIGNAL DESCRIPTIONS (Continued)
BUS ARBITRATION
Mnemonic
Name
Description
BUS REQ
Bus request
An active LOW output that indicates the CPU requires the bus. It
becomes inactive when the CPU has acquired the bus and started the
bus cycle.
BUS GNT
Bus grant
An active LOW input from an external arbiter that indicates the CPU
currently has the highest priority bus request. If the bus is not used and
not locked, the CPU may begin a bus cycle, commencing with the next
CPU clock. A HIGH level will hold the CPU in Hi-Z state (Bz), three-
stating the IB bus status lines (D/I, R/W, M/IO), strobes (STRBA,
STRBD), and all the other lines that go three-state when this CPU does
not have the bus.
BUS BUSY
Bus busy
Bus lock
An active LOW, bidirectional signal used to establish the beginning and
end of a bus cycle. The trailing edge (LOW-to-HIGH transition) is used
for sampling bits into the fault register. It is three-state in bus cycles not
assigned to this CPU. However, the CPU monitors the BUS BUSY line
for latching non-CPU bus cycle faults into the fault register.
BUS LOCK
An active low, bi-directional signal used to lock the bus for successive
buscycles. Duringnon-lockedbuscycles,theBUSLOCK signalmimics
the BUS BUSY signal. It is three-state during bus cycles not assigned to
the CPU. The following instructions will lock the bus: INCM, DECM, SB,
RB, TSB, SRM, STUB and STLB.
DISCRETE CONTROL
Mnemonic
Name
Description
DMA EN
Direct memory
Access enable
An active HIGH output that indicates the DMA is enabled. It is
disabled when the CPU is initialized (reset) and can be enabled or
disabled under program control (I/O commands DMAE, DMAD).
An active HIGH output that is set when the CPU has successfully
completed the built-in self test in the initialization sequence. It can be
reset by the I/O command RNS.
NML PWRUP
Normal power up
SNEW
Start new
An active HIGH output that indicates a new instruction is about to start
executing in the next cycle.
TRIGO RST
Trigger-go reset
An active LOW discrete output. This signal can be pulsed low under
program control I/O address 400B (Hex) and is automatically pulsed
during processor initialization.
Do c um e nt # MICRO-3 Re v. C
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PACE1750A
TERMINAL CONNECTIONS
Case Outline: Pin Grid Array (Case Z)
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
G1
G2
H1
H2
J1
V
L5
DMA EN
D11
D10
C11
C10
B11
A10
B10
A9
AS
AS
AS
CC
1
2
3
IB
IB
IB
IB
IB
IB
IB
K5
CON REQ
14
13
12
11
10
9
L6
V
CC
K6
SNEW
BUS LOCK
BUS GNT
BUS BUSY
M/IO
IOL INT
2
L7
V
CC
K7
GND
IOL INT
L8
1
K8
USR INT
5
8
GND
L9
D/I
B9
USR INT
4
IB
IB
IB
IB
IB
IB
IB
IB
K9
R/W
A8
USR INT
3
7
6
5
4
3
2
1
0
L10
K11
K10
J11
J10
H11
H10
G11
G10
F11
F10
E11
E10
GND
B8
USR INT
2
RDYD
A7
USR INT
1
RDYA
B7
USR INT
0
BUS REQ
STRBD
STRBA
CPU CLK
A6
PWRDN INT
GND
B6
J2
A5
MAJ ER
K1
L2
K2
L3
K3
L4
K4
B5
SYSFLT
SYSFLT
1
GND
AK
AK
AK
AK
A4
0
1
2
3
0
UNRCV ER
TIMER CLK
NML PWRUP
RESET
B4
EXT ADR ER
MEM PAR ER
MEM PRT ER
A3
B3
GND
AS
A2
IB
15
TRIGO RST
0
Do c um e nt # MICRO-3 Re v. C
Pa g e 15 o f 24
PACE1750A
TERMINAL CONNECTIONS
Case Outlines: Leaded Chip Carrier with unformed leads (Case U) and Leaded Chip Carrier with Gull-
Wing Leads (Case Y)
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
1
2
GND
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
IB
IB
IB
IB
IB
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
AS
AS
AS
11
12
13
14
15
2
1
0
CON REQ
DMA EN
TRIGO RST
RESET
3
4
GND
5
AK
AK
3
2
6
NML PWRUP
TIMER CLK
UNRCV ER
GND
MEM PRT ER
MEM PAR ER
EXT ADR ER
7
VCC
8
AK
AK
1
0
9
SYSFLT
SYSFLT
MAJ ER
GND
0
1
10
11
12
13
14
15
16
17
18
19
20
21
22
IB
IB
IB
IB
IB
IB
IB
IB
CPU CLK
STRBA
STRBD
BUS REQ
RDYA
0
1
2
3
4
5
6
7
VCC
PWRDN INT
USR INT
RDYD
0
USR INT
R/W
1
USR INT
D/I
2
GND
USR INT
M/IO
3
IB
IB
USR INT
BUS BUSY
BUS GNT
BUS LOCK
8
9
4
USR INT
5
VCC
IB
IOL INT
1
44
45
IOL INT
67
68
SNEW
VCC
10
2
AS
3
Do c um e nt # MICRO-3 Re v. C
Pa g e 16 o f 24
PACE1750A
TERMINAL CONNECTIONS
Case Outlines: Dual-In-Line (Case X) and Dual-In-Line with Gull-Wing Leads (Case T)
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
1
GND
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
IB
IB
IB
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AS
AS
13
14
15
1
0
2
CON REQ
DMA EN
3
GND
4
TRIGO RST
RESET
MEM PRT ER
MEM PAR ER
EXT ADR ER
AK
AK
AK
AK
3
2
1
0
5
6
NML PWRUP
TIMER CLK
UNRCV ER
7
SYSFLT
SYSFLT
MAJ ER
GND
0
8
CPU CLK
STRBA
STRBD
BUS REQ
RDYA
1
9
IB
IB
IB
IB
IB
IB
IB
IB
IB
IB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PWRDN INT
USR INT
0
USR INT
RDYD
1
USR INT
R/W
2
USR INT
D/I
3
USR INT
M/IO
4
USR INT
BUS BUSY
BUS GNT
BUS LOCK
SNEW
VCC
5
IOL INT
1
VCC
IOL INT
2
IB
IB
IB
AS
AS
10
11
12
3
2
Note: For the 30 MHz and 40 MHz devices, Pins 19 and 46 are connected as shown. For the 15 MHz and 20 MHz devices, these pins are not internally connected to the die.
Do c um e nt # MICRO-3 Re v. C
Pa g e 17 o f 24
PACE1750A
ORDERING INFORMATION
Standardized Military
Pyramid Semiconductor
Pyramid Semiconductor
Drawing Part Number
5962-8766501TX
5962-8766501UX
5962-8766501XX
5962-8766501YX
5962-8766501ZX
5962-8766502TX
5962-8766502UX
5962-8766502XX
5962-8766502YX
5962-8766502ZX
5962-8766503TX
5962-8766503UX
5962-8766503XX
5962-8766503YX
5962-8766503ZX
5962-8766504TX
5962-8766504UX
5962-8766504XX
5962-8766504YX
5962-8766504ZX
CAGE Number
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
Part Number
P1750A-15GMB
P1750A-15QLMB
P1750A-15CMB
P1750A-15QGMB
P1750A-15PGMB
P1750A-20GMB
P1750A-20QLMB
P1750A-20CMB
P1750A-20QGMB
P1750A-20PGMB
P1750A-30GMB
P1750A-30QLMB
P1750A-30CMB
P1750A-30QGMB
P1750A-30PGMB
P1750A-40GMB
P1750A-40QLMB
P1750A-40CMB
P1750A-40QGMB
P1750A-40PGMB
Do c um e nt # MICRO-3 Re v. C
Pa g e 18 o f 24
PACE1750A
CASE OUTLINE X:
64 Lead Top Brazed DIP Package, Straight Lead Version (Ordering Code C)
Inches
.002
.005
.008
.010
.015
.016
.018
.025
.040
.050
.185
.265
.470
.530
.590
.620
.645
1.550
1.563
mm
0.05
0.12
0.20
0.25
0.38
0.40
0.45
0.63
1.01
1.27
4.70
6.73
11.93
13.46
14.98
15.74
16.38
39.37
39.70
NOTES:
1) Dimensions are in inches.
2) Metric equivalents are given for general information only.
3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals.
Do c um e nt # MICRO-3 Re v. C
Pa g e 19 o f 24
PACE1750A
CASE OUTLINE T:
64 Lead Top Brazed DIP Package, Gullwing Lead Version (Ordering Code G)
Inches
.001
.003
.005
.008
.010
.015
.016
.022
.030
.040
.050
.150
.470
.530
.590
.620
.868
1.663
mm
0.03
0.08
0.12
0.20
0.25
0.38
0.41
0.55
0.76
1.01
1.27
3.81
11.93
13.46
14.98
15.74
22.04
42.24
NOTES:
1) Dimensions are in inches.
2) Metric equivalents are given for general information only.
3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals.
4) Case T is derived from Case X by forming the leads to the shown gullwing configuration.
Do c um e nt # MICRO-3 Re v. C
Pa g e 20 o f 24
PACE1750A
CASE OUTLINE U:
68 Lead Quad Pack with Straight Leads (Ordering Code QL)
Inches
.002
.004
.006
.010
.012
.020
.050
.100
.116
.250
.560
.570
.800
.955
1.090
mm
0.05
0.10
0.15
0.25
0.30
0.51
1.27
2.54
2.95
6.40
14.22
14.48
20.32
24.25
27.69
NOTES:
1) Dimensions are in inches.
2) Metric equivalents are given for general information only.
3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals.
4) Pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner.
5) Corners indicated as notched may be either notched or square.
Do c um e nt # MICRO-3 Re v. C
Pa g e 21 o f 24
PACE1750A
CASE OUTLINE Y:
68 Lead Quad Pack with Gullwing Leads (Ordering Code QG)
Inches
.004
.005
.008
.010
.012
.015
.016
.020
.024
.040
.050
.100
.115
.570
.800
.955
1.010
1.090
mm
0.10
0.12
0.20
0.25
0.30
0.38
0.41
0.50
0.60
1.02
1.27
2.54
2.92
14.48
20.32
24.25
25.65
27.68
NOTES:
1) Dimensions are in inches.
2) Metric equivalents are given for general information only.
3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals.
4) Pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner.
5) Corners indicated as notched my be either notched or square (with radius).
6) Case Y is derived from Case U by forming the leads to the shown gullwing configuration.
Do c um e nt # MICRO-3 Re v. C
Pa g e 22 o f 24
PACE1750A
CASE OUTLINE Z:
68-Pin Pin Grid Array (PGA) (Ordering Code PG)
Inches
.016
.020
.040
.050
.059
.060
.098
.100
.120
.150
.170
1.010
1.089
1.160
mm
0.41
0.50
1.01
1.27
1.49
1.52
2.49
2.54
3.04
3.81
4.32
25.65
27.66
29.46
NOTES:
1) Dimensions are in inches.
2) Metric equivalents are given for general information only.
3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals.
4) Corners except pin number 1 (ref.) can be either rounded or square.
5) All pins must be on the .100" grid.
Do c um e nt # MICRO-3 Re v. C
Pa g e 23 o f 24
PACE1750A
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
MICRO-3
PACE1750A CMOS 16-BIT PROCESSOR
ISSUE
REV.
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
DATE
ORIG
A
May-89
Jul-04
RKK
New Data Sheet
JDB
JDB
Added Pyramid logo
B
C
Aug-05
Oct-05
Re-created electronic version
JDB
Altered case outline drawing for case X and case T
Do c um e nt # MICRO-3 Re v. C
Pa g e 24 o f 24
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