P3C1256L70TCLF [PYRAMID]

Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, ROHS COMPLIANT, TSOP-28;


型号：	P3C1256L70TCLF
厂家：	PYRAMID SEMICONDUCTOR CORPORATION
描述：	Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, ROHS COMPLIANT, TSOP-28 静态存储器光电二极管内存集成电路
文件：	总11页 (文件大小：729K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P3C1256L

LOW POWER 32K x 8

STATIC CMOS RAM

FEATURES

V_CCCurrent (Commercial/Industrial)

— Operating: 70mA/85mA

— CMOS Standby: 100µA/100µA

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Automatic Power Down

Packages

Access Times

—55/70/85

— 28-Pin 600 mil DIP

— 28-Pin 330 mil SOP

— 28-Pin TSOP

Wide Range Power Supply: 2.7V to 3.6V

Easy Memory Expansion Using CE and OE Inputs

Common Data I/O

DESCRIPTIOꢀ

The P3C1256L is a 262,144-bit low power CMOS

static RAM organized as 32Kx8. The CMOS memory

requires no clocks or refreshing, and has equal access and

cycle times. Inputs are fully TTL-compatible. The RAM

operates with a wide range power supply (2.7V to 3.6V).

with matching access and cycle times. Memory locations

are speciﬁed on address pinsA₀toA₁₄. Reading is accom-

plished by device selection (CE and output enabling (OE)

while write enable (WE) remains HIGH. By presenting the

address under these conditions, the data in the addressed

memory location is presented on the data input/output pins.

The input/output pins stay in the HIGH Z state when either

CE or OE is HIGH or WE is LOW.

Access times of 55 ns and 70 ns are available. CMOS is

utilized to reduce power consumption to a low level.

The P3C1256L device provides asynchronous operation

FUꢀCTIOꢀAL BLOCꢁ DIAꢂRAM

PIꢀ COꢀFIꢂURATIOꢀS

DIP (P6), SOP (S11-3)

TOP VIEW

Document # SRAM143 REV A

Revised October 2011

P3C1256L - 32K x 8 STATIC CMOS RAM

RECOMMEꢀDED OPERATIꢀꢂ TEMPERATURE AꢀD SUPPLꢄ VOLTAꢂE

Temperature Range (Ambient)

Commercial (0°C to 70°C)

Industrial (-40°C to 85°C)

Military (-55°C to 125°C)

Supply Voltage

2.7V ≤ V_CC≤ 3.6V

MAꢃIMUM RATIꢀꢂS⁽¹⁾

Sym

Parameter

Min

Max

Unit

V_CC

Supply Voltage with Respect to GND

-0.5

-55

-65

7.0

V_TERM

T_A

Terminal Voltage with Respect to GND (up to 7.0V)

Operating Ambient Temperature

Storage Temperature

V_CC+ 0.5

125

°C

S_TG

I_OUT

I_LAT

150

°C

Output Current into Low Outputs

Latch-up Current

> 200

DC ELECTRICAL CHARACTERISTICS

(Over Recommended Operating Temperature & Supply Voltage)⁽²⁾

Sym Parameter

Test Conditions

I_OH= -1mA, V_CC= 3.0V

I_OL= 2.1mA

Min

Max

Unit

V_OHOutput High Voltage (I/O₀- I/O₇)

V_OLOutput Low Voltage (I/O₀- I/O₇)

V_IHInput High Voltage

2.4

0.4

V_CC+ 0.3

0.8

2.2

-0.5⁽³⁾

-2

V_ILInput Low Voltage

Com

Ind

I_LI

Input Leakage Current

GND ≤ V_IN≤ V_CC

-5

µA

Mil

Com

Ind

-2

-5

GND ≤ V_OUT≤ V_CC

I_LOOutput Leakage Current

CE = V_IH

Mil

V_CCCurrent

I_SBTTL Standby Current

(TTL Input Levels)

V_CC= 3.6V, I_OUT= 0 mA

µA

CE = V_IH

V_CCCurrent

I_SB1CMOS Standby Current

(CMOS Input Levels)

V_CC= 3.6V, I_OUT= 0 mA

100

CE ≥ V_CC- 0.2V

N/A = Not applicable

Document # SRAM143 REV A

Page 2

P3C1256L - 32K x 8 STATIC CMOS RAM

CAPACITAꢀCES⁽⁴⁾

(V_CC= 3.3V, T_A= 25°C, f = 1.0MHz)

Symbol

C_IN

Parameter

Test Conditions

V_IN=0V

Max

Unit

Input Capacitance

Output Capacitance

C_OUT

V_OUT=0V

POWER DISSIPATIOꢀ CHARACTERISTICS VS. SPEED

Sym Parameter

Temperature Range

Unit

-55

-70

-85

-55

-70

-85

Commercial

Industrial

Military

I_CC

Dynamic Operating Current*

100

* Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously

enabled for writing, i.e. CE and WE ≤ V_IL(max), OE is high. Switching inputs are 0V and 3V.

** As above but @ f=1 MHz and V_IL/V_IH= 0V/V_CC.

AC ELECTRICAL CHARACTERISTICS—READ CꢄCLE

(Over Recommended Operating Temperature & Supply Voltage)

-55

-70

-85

Sym

Parameter

Unit

Min

Max

Min

Max

Min

Max

t_RC

t_AA

Read Cycle Time

Address Access Time

t_AC

t_OH

t_LZ

Chip Enable Access Time

Output Hold from Address Change

Chip Enable to Output in Low Z

Chip Disable to Output in High Z

Output Enable Low to Data Valid

Output Enable Low to Low Z

Output Enable High to High Z

Chip Enable to Power Up Time

Chip Disable to Power Down Time

t_HZ

t_OE

t_OLZ

t_OHZ

t_PU

t_PD

Document # SRAM143 REV A

Page 3

P3C1256L - 32K x 8 STATIC CMOS RAM

TIMIꢀꢂ WAVEFORM OF READ CꢄCLE ꢀO. 1 (OE COꢀTROLLED)⁽⁵⁾

TIMIꢀꢂ WAVEFORM OF READ CꢄCLE ꢀO. 2 (ADDRESS COꢀTROLLED)^(5,6)

TIMIꢀꢂ WAVEFORM OF READ CꢄCLE ꢀO. 3 (ADDRESS COꢀTROLLED)^(5,7)

ꢀotes:

1. Stresses greater than those listed under MAꢀIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this speciﬁcation

is not implied. Exposure to MAꢀIMUM rating conditions for extended

periods may affect reliability.

4. This parameter is sampled and not 100% tested.

5. WE is HIGH for READ cycle.

6. CE is LOW and OE is LOW for READ cycle.

7. ADDRESS must be valid prior to, or coincident with CE transition

LOW.

8. Transition is measured ± 200 mV from steady state voltage prior to

change,withloadingasspeciﬁedinFigure1. Thisparameterissampled

and not 100% tested.

2. Extended temperature operation guaranteed with 400 linear feet per

minute of air ﬂow.

9. Read Cycle Time is measured from the last valid address to the ﬁrst

transitioning address.

3. Transient inputs with V_ILand I_ILnot more negative than –3.0V and

–100mA, respectively, are permissible for pulse widths up to 20ns.

Document # SRAM143 REV A

Page 4

P3C1256L - 32K x 8 STATIC CMOS RAM

AC CHARACTERISTICS—WRITE CꢄCLE

(Over Recommended Operating Temperature & Supply Voltage)

-55

-70

-85

Symbol Parameter

Min

Unit

Max

Min

Max

Min

Max

t_WC

t_CW

t_AW

t_AS

Write Cycle Time

Chip Enable Time to End of Write

Address Valid to End of Write

Address Setup Time

t_WP

t_AH

t_DW

t_DH

t_WZ

t_OW

Write Pulse Width

Address Hold Time

Data Valid to End of Write

Data Hold Time

Write Enable to Output in High Z

Output Active from End of Write

TIMIꢀꢂ WAVEFORM OF WRITE CꢄCLE ꢀO. 1 (WE COꢀTROLLED)^(10,11)

Notes:

10. CE and WE must be LOW for WRITE cycle.

13. Write Cycle Time is measured from the last valid address to the ﬁrst

11. OE is LOW for this WRITE cycle to show t_WZand t_OW

12. If CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state

transitioning address.

Document # SRAM143 REV A

Page 5

P3C1256L - 32K x 8 STATIC CMOS RAM

TIMIꢀꢂ WAVEFORM OF WRITE CꢄCLE ꢀO. 2 (CE COꢀTROLLED)⁽¹⁰⁾

AC TEST COꢀDITIOꢀS

Input Pulse Levels

TRUTH TABLE

GND to 3.0V

Mode

ꢀ

I/O

Power

Standby

Active

Input Rise and Fall Times

Input Timing Reference Level

Output Timing Reference Level

Output Load

3ns

1.5V

Standby

D_OUTDisabled

Read

ꢀ

High Z

D_OUT

ꢀ

1.5V

See Figures 1 and 2

Active

Write

ꢀ

High Z

Active

Figure 1. Output Load

Figure 2. Thevenin Equivalent

* including scope and test ﬁxture.

ꢀote:

Because of the high speed of the P3C1256L, care must be taken when

testing this device; an inadequate setup can cause a normal function-

ing part to be rejected as faulty. Long high-inductance leads that cause

supply bounce must be avoided by bringing the V_CCand ground planes

directly up to the contactor ﬁngers. A 0.01 µF high frequency capacitor

is also required between V_CCand ground. To avoid signal reﬂections,

proper termination must be used; for example, a 50Ω test environment

should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at

the comparator input, and a 589Ω resistor must be used in series with

D_OUTto match 639Ω (Thevenin Resistance).

Document # SRAM143 REV A

Page 6

P3C1256L - 32K x 8 STATIC CMOS RAM

DATA RETEꢀTIOꢀ CHARACTERISTICS

Typ.*

V_CC

Max

V_CC=

Sym

Parameter

Test Conditions

Min

Unit

2.0V

3.0V

2.0V

3.0V

V_DR

V_CCfor Data Retention

Data Retention Current

2.0

I_CCDR

120

µA

CE ≥ V_CC- 0.2V,

V_IN≥ V_CC- 0.2V

or V_IN≤ 0.2V

Chip Deselect to Data Reten-

tion Time

t_CDR

†

t_R

Operation Recovery Time

t_RC

* TA = +25°C

t_RC^§= Read Cycle Time

† = This parameter is guaranteed but not tested.

DATA RETEꢀTIOꢀ WAVEFORM

Document # SRAM143 REV A

Page 7

P3C1256L - 32K x 8 STATIC CMOS RAM

ORDERIꢀꢂ IꢀFORMATIOꢀ

Document # SRAM143 REV A

Page 8

P3C1256L - 32K x 8 STATIC CMOS RAM

PLASTIC DUAL Iꢀ-LIꢀE PACꢁAꢂE

Pkg #

# Pins

28 (600 mil)

Symbol

Min

Max

0.090

0.000

0.014

0.015

0.008

1.380

0.485

0.600

0.200

0.070

0.020

0.065

0.012

1.430

0.550

0.625

0.100 BSC

0.600 TYP

0.100 0.180

0° 15°

SOIC/SOP SMALL OUTLIꢀE IC PACꢁAꢂE

Pkg #

S11-3

# Pins

28 (330 Mil)

Symbol

Min

Max

0.094

0.002

0.014

0.008

0.702

0.120

0.014

0.020

0.012

0.728

0.050 BSC

0.291

0.463

0.010

0.020

0°

0.340

0.477

0.029

0.050

8°

Document # SRAM143 REV A

Page 9

P3C1256L - 32K x 8 STATIC CMOS RAM

TSOP THIꢀ SMALL OUTLIꢀE PACꢁAꢂE

Pkg #

# Pins

Symbol

Min

Max

0.047

0.040

0.011

0.469

0.319

A₂

0.039

0.036

0.007

0.461

0.311

0.022 BSC

0.520 0.535

H_D

Document # SRAM143 REV A

Page 10

P3C1256L - 32K x 8 STATIC CMOS RAM

REVISIOꢀS

DOCUMEꢀT ꢀUMBER SRAM143

DOCUMEꢀT TITLE

P3C1256L LOW POWER 32K x 8 STATIC CMOS RAM

REV ISSUE DATE

ORIꢂIꢀATOR DESCRIPTIOꢀ OF CHAꢀꢂE

Jul-2011

Oct-2011

JDB

New Data Sheet

Added wide range power supply

Document # SRAM143 REV A

Page 11

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