P4C1256-25PI [PYRAMID]
Standard SRAM, 32KX8, 25ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28;
| 型号： | P4C1256-25PI |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 32KX8, 25ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C1256
HIGH SPEED 32K x 8
STATIC CMOS RAM
FEATURES
Three-State Outputs
High Speed (Equal Access and Cycle Times)
— 12/15/20/25/35 ns (Commercial)
— 15/20/25/35/45 ns (Industrial)
— 20/25/35/45/55/70 ns (Military)
Low Power
— 880 mW Active (Commercial)
Single 5V±10% Power Supply
Easy Memory Expansion Using CE and OE
Inputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast tOE
Automatic Power Down
Packages
—28-Pin 300 mil DIP and SOJ
—28-Pin 600 mil Ceramic DIP
—28-Pin LCC(350 mil x 550 mil)
—32-Pin LCC (450 mil x 550 mil)
Common Data I/O
DESCRIPTION
The P4C1256 is a 262,144-bit high-speed CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
The P4C1256 device provides asynchronous operation with
matching access and cycle times. Memory locations are
specified on address pins A0 to A14. Reading is accom-
plished by device selection (CE and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE or OE is HIGH or WE is LOW.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The
P4C1256 is a member of a family of PACE RAM™ prod-
ucts offering fast access times.
Package options for the P4C1256 include 28-pin 300 mil
DIP and SOJ packages. For military temperature range,
Ceramic DIP and LCC packages are available.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
A0
A1
A2
A3
A4
A5
A6
VCC
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
WE
262,144-BIT
MEMORY
ARRAY
(8)
A
4
5
3
2
32
31 30
29
3
A14
A
A
A
A
A
A
A
A
A
A
1
13
12
11
3
4
5
6
7
8
9
A13
A12
4
6
7
8
9
28
27
26
25
24
5
A
11
6
I/O
NC
1
7
OE
INPUT
DATA
CONTROL
OE
A
A7
A8
A9
A
10
8
COLUMN I/O
10
11
12
13
10
9
CE
I/O
2
23
22
21
CE
I/O
10
11
12
13
14
I/0
I/0
I/0
I/0
I/0
8
NC
8
7
6
5
4
I/01
I/O
I/O
1
7
I/02
14 15 16 17 18 19 20
COLUMN
SELECT
I/03
GND
WE
CE
OE
• • • • • •
DIP (P5, C5, D5-1), SOJ (J5)
TOP VIEW
32 LCC (L6)
TOP VIEW
A
(7)
A
See Selection Guide page for 28-pin LCC
Means Quality, Service and Speed
1Q97
117
P4C1256
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TBIAS
Temperature Under
Bias
–55 to +125
°C
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
TSTG
PT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150
°C
W
VTERM
TA
V
1.0
50
IOUT
mA
Operating Temperature –55 to +125 °C
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
VCC
Grade(2)
GND
Parameter
Typ.
Symbol
Conditions
Unit
Temperature
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
Military
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
VIN = 0V
pF
pF
0V
0V
0V
CIN
Input Capacitance
Output Capacitance
8
Industrial
VOUT = 0V
COUT
10
Commercial
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
P4C1256
Symbol
Parameter
Test Conditions
Unit
Min
Max
VIH
Input High Voltage
VCC +0.5
2.2
V
V
V
–0.5(3)
VIL
Input Low Voltage
0.8
VCC –0.2
VHC
VLC
VCC +0.5
CMOS Input High Voltage
CMOS Input Low Voltage
–0.5(3)
2.4
0.2
0.4
V
V
VOL
VOH
ILI
Output Low Voltage
(TTL Load)
IOL = +8 mA, VCC = Min.
IOH = –4 mA, VCC = Min.
VCC = Max.
Output High Voltage
(TTL Load)
V
Input Leakage Current
Mil.
Ind./Com’l.
–10
–5
+10
+5
µA
VIN = GND to VCC
ILO
–10
–5
+10
+5
Output Leakage Current
VCC = Max., CE = VIH,
VOUT = GND to VCC Ind./Com’l.
Mil.
µA
___
___
ISB
CE ≥ VIH or
CE2 ≤VIL, VCC= Max Ind./Com’l.
Mil.
45
30
Standby Power Supply
Current (TTL Input Levels)
mA
f = Max., Outputs Open
___
___
ISB1
Standby Power Supply
Current
(CMOS Input Levels)
20
10
mA
CE ≥ VHC or
CE2 ≤VLC, VCC= Max Ind./Com’l.
f = 0, Outputs Open
Mil.
VIN ≤ VLC or VIN ≥ VHC
n/a = Not Applicable
Notes:
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
118
P4C1256
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Symbol
Parameter
Unit
Range
–15 –20 –25 –35 –45 –55 –70
–12
mA
160 155 150 N/A N/A mA
N/A N/A 170 165 160 155 150 150 mA
Commercial
150 145 N/A N/A N/A
170 160 155
ICC
Dynamic Operating Current*
N/A
Industrial
Military
170 165
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
-25
-35
-45
-55
-70
Sym.
Parameter
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tRC
tAA
20
25
35
55
Read Cycle Time 12
15
45
70
ns
45
45
Address Access
Time
12
12
15
15
20
20
25
25
35
35
55
55
70 ns
tAC
70 ns
Chip Enable
Access Time
Output Hold from
2
Address Change
ns
ns
2
2
2
2
3
3
3
3
3
3
3
3
3
3
tOH
tLZ
tHZ
tOE
Chip Enable to
Output in Low Z
2
30 ns
30 ns
Chip Disable to
Output in High Z
5
5
8
7
9
9
11
10
15
15
20
20
25
25
Output Enable
Low to Data
Valid
tOLZ
tOHZ
tPU
tPD
0
0
0
0
0
0
ns
Output Enable
Low to Low Z
0
0
0
0
0
0
0
0
0
0
30 ns
Output Enable
High to High Z
5
7
9
11
20
15
20
20
25
25
30
Chip Enable to
Power Up Time
ns
Chip Disable to
Power Down
Time
12
15
20
35 ns
119
P4C1256
READ CYCLE NO. 1 (OE CONTROLLED)(1)
(5)
t
RC
ADDRESS
t
AA
OE
t
t
OH
OE
(4)
t
OLZ
CE
(4)
t
t
AC
OHZ
(4)
AC
(4)
t
t
HZ
DATA OUT
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5)
t
RC
ADDRESS
t
AA
t
OH
PREVIOUS DATA VALID
DATA VALID
DATA OUT
READ CYCLE NO. 3 (CE CONTROLLED)
t
RC
CE
t
HZ
t
AC
(8)
t
LZ
DATA OUT
DATA VALID
HIGH IMPEDANCE
t
t
PD
I
PU
CC
V
SUPPLY
CC
CURRENT
I
SB
Notes:
1. WE is HIGH for READ cycle.
2. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with CE1 transition
LOW .
4. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
120
P4C1256
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
-25
-35
-45
-55
-70
Parameter
Unit
Sym.
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tWC
tCW
20
15
25
18
35
22
55
35
Write Cycle Time 12
15
10
45
30
70
40
ns
ns
Chip Enable
Time to End of
Write
9
tAW
tAS
Address Valid to
End of Write
10
15
20
25
35
40
45
ns
9
0
9
0
8
Address Set-up
Time
0
11
0
0
15
0
0
22
0
0
25
0
0
30
0
0
35
0
ns
ns
ns
ns
0
18
0
tWP
tAH
tDW
Write Pulse
Width
Address Hold
Time
Data Valid to
End of Write
11
13
15
25
9
20
30
tDH
tWZ
0
3
0
0
3
Date Hold Time
0
3
0
5
0
0
0
0
ns
Write Enable to
Output in High Z
7
8
10
11
15
18
25
30 ns
tOW
Output Active
3
5
0
ns
from End of Write
WRITE CYCLE NO. 1 (WE CONTROLLED)(6)
(9)
t
WC
ADDRESS
t
CW
CE
t
AW
t
t
AH
WP
WE
t
t
t
DH
AS
DW
DATAVALID
DATAIN
(4,7)
(4)
WZ
t
t
OW
(7)
DATA OUT
DATAUNDEFINED
HIGH IMPEDANCE
Notes:
6. CE1 and WE must be LOW for WRITE cycle.
7. OE is LOW for this WRITE cycle to show tWZ and tOW
9. Write Cycle Time is measured from the last valid address to the first
transitioning address.
.
8. IfCE1 goesHIGHsimultaneouslywith WE HIGH, theoutputremains
in a high impedance state.
121
P4C1256
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(6)
(9)
t
WC
ADDRESS
t
t
CW
AS
CE
t
AH
t
AW
t
WP
WE
t
t
DW
DH
DATAVALID
DATAIN
(6)
DATAOUT
HIGH IMPEDANCE
AC TEST CONDITIONS
TRUTH TABLE
Mode
CE1 CE2 OE WE
I/O
Power
Input Pulse Levels
GND to 3.0V
3ns
Standby
Standby
H
X
X
L
X
X
X
X
High Z Standby
High Z Standby
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
1.5V
DOUT
Disabled
1.5V
L
L
L
H
H
H
H
L
H
H
L
High Z Active
See Figures 1 and 2
Read
Write
DOUT
Active
X
High Z Active
+5V
R
= 166.5 Ω
TH
480Ω
V
= 1.73 V
D
TH
OUT
D
OUT
30pF* (5pF* for t , t , t
,
HZ LZ OHZ
255Ω
,
30pF* (5pF* for t , t
t
,
HZ LZ OHZ
,
)
t
t
and t
OLZ WZ OW
,
)
t
t
and t
OLZ WZ OW
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1256, care must be taken
when testing this device; an inadequate setup can cause a normal
functioningparttoberejectedasfaulty. Longhigh-inductanceleadsthat
cause supply bounce must be avoided by bringing the VCC and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
capacitor is also required between VCC and ground. To avoid signal
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with DOUT to match 166Ω (Thevenin Resistance).
122
P4C1256
PACKAGE SUFFIX
TEMPERATURE RANGE SUFFIX
Package
Description
Suffix
Temperature
Description
Range Suffix
P
J
C
Plastic DIP, 300 mil wide standard
C
Commercial Temperature Range,
0°C to +70°C.
Industrial Temperature Range,
–40˚C to +85˚C.
Plastic SOJ, 300 mil wide standard
Sidebrazed DIP, 300 mil wide
CERDIP, 300 mil wide
I
D
DW
L28
L32
CERDIP, 600 mil wide
Leadless Chip Carrier, 350 x 550 mils
Leadless Chip Carrier, 450 x 550 mils
M
Military Temperature Range,
–55°C to +125°C.
Mil. Temp. with MIL-STD-883
Class B compliance.
MB
ORDERING INFORMATION
Performance Semiconductor's part numbering scheme is as follows:
1256 ss
p
t
P4C
Temperature Range
Package Code
Speed (Access/Cycle Time)
Device Number
Static RAM Prefix
I = Ultra-low standby power designator L, if available.
ss = Speed (access/cycle time in ns). e.g. 25, 35.
p = Package code, i.e., P, J, C, D, DW, L28, L32.
t = Temperature range, i.e., C, M. MB.
The P4C1256 is also available per SMD 5962-88662
123
P4C1256
SELECTION GUIDE
The P4C1256 is available in the following temperature, speed and package options. The P4C1256L is available only
over the military temperature range.
Temp.
Speed
Range Package
12
15
20
25
35
45
55
70
Com'l
Ind.
Plastic DIP
Plastic SOJ
-12PC
-12JC
-15PC
-15JC
-20PC
-20JC
-25PC
-25JC
-35PC
-35JC
N/A
N/A
N/A
N/A
N/A
N/A
-20PI
-20JI
-25PI
-25JI
-35PI
-35JI
-45PI
-425JI
N/A
N/A
N/A
N/A
Plastic DIP
Plastic SOJ
N/A
N/A
-15PI
-15JI
Mil.
Temp.
Sidebrazed (300 mil)
CERDIP (300 mil)
CERDIP (600 mil)
L28
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-20CM
-20DM
-25CM
-25DM
-20DWM -25DWM
-20L28M -25L28M
-20L32M -25L32M
-35CM
-35DM
-35DWM
-35L28M
-35L32M
-45CM
-45DM
-45DWM
-45L28M
-45L32M
-55CM
-55DM
-55DWM
-55L28M
-55L32M
-70CM
-70DM
-70DWM
-70L28M
-70L32M
L32
Military Sidebrazed (300 mil)
Proc'd* CERDIP (300 mil)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-20CMB
-20DMB
-25CMB
-25DMB
-35CMB
-35DMB
-45CMB
-45DMB
-55CMB
-55DMB
-70CMB
-70DMB
CERDIP (600 mil)
L28
L32
-20DWMB -25DWMB -35DWMB -45DWMB -55DWMB -70DWMB
-20L28MB -25L28MB -35L28MB -45L28MB -55L28MB -70L28MB
-20L32MB -25L32MB -35L32MB -45L32MB -55L32MB -70L32MB
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not Available
28 LCC PIN CONFIGURATION
3
27
26
A
A
A
A
A
A
4
5
A
A
A
A
2
28
3
4
5
6
7
8
14
13
12
11
1
25
24
23
22
21
20
19
18
6
7
8
OE
A
9
10
A
I/O
I/O
10
11
12
CE
I/O
I/O
9
1
2
8
7
14 15 16
13
17
28 LCC (L5)
TOP VIEW
124
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