P4C1256-35P6I [PYRAMID]
Standard SRAM, 32KX8, 35ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28;
| 型号： | P4C1256-35P6I |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 32KX8, 35ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 静态存储器 光电二极管 |
| 文件： | 总16页 (文件大小：1155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C1256
HIGH SPEED 32K x 8
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
– 12/15/20/25/35 ns (Commercial)
– 15/20/25/35/45 ns (Industrial)
– 20/25/35/45/55/70 ns (Military)
Low Power
Single 5V±10% Power Supply
Easy Memory Expansion Using CE and OE Inputs
Common Data I/O
Fast tOE
Automatic Power Down
Packages
– 28-Pin 300 mil DIP, SOJ, TSOP
– 28-Pin 300 mil Ceramic DIP
– 28-Pin 600 mil Plastic and Ceramic DIP
– 28-Pin CERPACK
– 28-Pin Solder Seal Flat Pack
– 28-Pin SOP
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
ꢀ Advanced CMOS Technology
– 28-Pin LCC (350 mil x 550 mil)
– 32-Pin LCC (450 mil x 550 mil)
DESCRIPTIOꢀ
The P4C1256 is a 262,144-bit high-speed CMOS static
RAM organized as 32K x 8. The CMOS memory requires
no clocks or refreshing, and has equal access and cycle
times. InputsarefullyTTL-compatible. TheRAMoperates
from a single 5V±10% tolerance power supply.
with matching access and cycle times. Memory locations
are specified on address pinsA0 toA14. Reading is accom-
plished by device selection (CE) and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memorylocationispresentedonthedatainput/outputpins.
The input/output pins stay in the HIGH Z state when either
CE or OE is HIGH or WE is LOW.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1256
is a member of a family of PACE RAM™ products offering
fast access times.
PackageoptionsfortheP4C1256include28-pinDIP,SOJ,
and TSOP packages. For military temperature range,
Ceramic DIP and LCC packages are available.
The P4C1256 devices provides asynchronous operation
FUꢀCTIOꢀAL BLOCK DIAꢁRAM
PIꢀ COꢀFIꢁURATIOꢀS
DIP (P5, P6, C5, C5-1, D5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)
CERPACK (F4, FS-5) SIMILAR
LCC and TSOP configurations at end of datasheet
Document # SRAM119 REV I
Revised July 2010
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
MAꢂIMUM RATIꢀꢁS(1)
RECOMMEꢀDED OPERATIꢀꢁ COꢀDITIOꢀS
Sym Parameter
Value
Unit
ꢁrade(2)
Ambient Temp
0°C to 70°C
ꢁꢀD
0V
VCC
Power Supply Pin with
VCC
Commercial
Industrial
Military
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
-0.5 to +7
V
Respect to GND
-40°C to +85°C
-55°C to +125°C
0V
Terminal Voltage with
VTERM Respect to GND (up to
7.0V)
-0.5 to VCC + 0.5
V
0V
CAPACITAꢀCES(4)
TA
Operating Temperature
-55 to +125
-55 to +125
-65 to +150
1.0
°C
°C
°C
W
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
TBIAS Temperature Under Bias
TSTG Storage Temperature
Sym Parameter
Conditions Typ Unit
PT
Power Dissipation
CIN
Input Capacitance
VIN=0V
8
pF
pF
IOUT DC Output Current
50
mA
COUT
Output Capacitance
VOUT=0V
10
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
P4C1256
P4C1256L
Sym Parameter
Test Conditions
Unit
Min
2.2
Max
Min
2.2
Max
VIH Input High Voltage
VCC + 0.5
0.8
VCC + 0.5
0.8
V
V
V
V
VIL Input Low Voltage
-0.5(3)
-0.5(3)
VHC CMOS Input High Voltage
VLC CMOS Input Low Voltage
VCC - 0.2 VCC + 0.5 VCC - 0.2 VCC + 0.5
-0.5(3)
0.2
0.4
-0.5(3)
0.2
0.4
Output Low Voltage (TTL
Load)
VOL
IOL = +8 mA, VCC = Min
IOH = - 4 mA, VCC = Min
V
V
Output High Voltage (TTL
Load)
VOH
2.4
-10
-5
2.4
-5
MIL
IND/COM
MIL
+10
+5
+5
N/A
+5
VCC = Max,
VIN = GND to VCC
ILI
Input Leakage Current
µA
µA
N/A
-5
-10
-5
+10
+5
VCC = Max, CE = VIH,
VOUT = GND to VCC
ILO Output Leakage Current
IND/COM
MIL
N/A
—
N/A
30
—
45
CE ≥ VIH, VCC = Max, f = Max,
Standby Power Supply
ISB
mA
mA
Current (TTL Input Levels)
Outputs Open
IND/COM
MIL
—
30
—
N/A
10
CE ≥ VHC, VCC = Max, f = 0,
Outputs Open
—
20
—
Standby Power Supply
ISB1 Current (CMOS Input
Levels)
IND/COM
—
10
—
N/A
VIN ≤ VLC or VIN ≥ VHC
N/A = Not applicable
Document # SRAM119 REV I
Page 2
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
DATA RETEꢀTIOꢀ CHARACTERISTICS (P4C1256L Military Temperature Only)
Typ* VCC=
2.0V 3.0V
Max VCC=
Sym Parameter
Test Conditions
Min
Unit
2.0V
3.0V
VDR VCC for Data Retention
2.0
V
ICCDR Data Retention Current
10
15
100
200
µA
ns
ns
CE ≥ VCC -0.2V,
VIN ≥ VCC -0.2V
or VIN ≤ 0.2V
tCDR Chip Deselect to Data Retention Time
0
†
§
tR
Operation Recovery Time
tRC
* TA = +25°C
§ tRC = Read Cycle Time
† This Parameter is guaranteed but not tested
DATA RETEꢀTIOꢀ WAVEFORM
POWER DISSIPATIOꢀ CHARACTERISTICS VS. SPEED
Sym Parameter
Temperature Range
Commercial
Industrial
-12
170
N/A
N/A
-15
160
170
N/A
-20
155
165
170
-25
-35
-45
-55
-70
Unit
150
160
165
145
155
160
N/A
150
155
N/A
N/A
150
N/A
N/A
150
mA
mA
mA
Dynamic Operating
Current*
ICC
Military
* VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
-25
-35
-45
-55
-70
Unit
Sym Parameter
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tRC
tAA
tAC
Read Cycle Time
12
15
20
25
35
45
55
70
ns
ns
ns
Address Access Time
12
12
15
15
20
20
25
25
35
35
45
45
55
55
70
70
Chip Enable Access Time
Output Hold from Address
Change
tOH
tLZ
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to Output in
Low Z
Chip Disable to Output in
High Z
tHZ
5
5
8
7
9
9
11
15
15
20
20
25
25
30
30
Output Enable Low to
Data Valid
tOE
tOLZ
tOHZ
tPU
tPD
10
Output Enable Low to
Low Z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Output Enable High to
High Z
5
7
9
11
15
20
25
30
Chip Enable to Power Up
Time
Chip Disable to Power
Down Time
12
15
20
20
20
25
30
35
Document # SRAM119 REV I
Page 3
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
TIMIꢀꢁ WAVEFORM OF READ CYCLE ꢀO. 1 (OE COꢀTROLLED)(5)
TIMIꢀꢁ WAVEFORM OF READ CYCLE ꢀO. 2 (ADDRESS COꢀTROLLED)(5,6)
TIMIꢀꢁ WAVEFORM OF READ CYCLE ꢀO. 3 (CE COꢀTROLLED)
ꢀotes:
1. Stresses greater than those listed under MAꢀIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAꢀIMUM rating conditions for extended
periods may affect reliability.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change,withloadingasspecifiedinFigure1. Thisparameterissampled
and not 100% tested.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
Document # SRAM119 REV I
Page 4
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
-25
-35
-45
-55
-70
Sym Parameter
tWC Write Cycle Time
tCW
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
12
9
15
20
25
35
22
45
55
35
70
40
ns
ns
Chip Enable Time to End
of Write
10
15
18
30
Address Valid to End of
Write
tAW
9
10
15
20
25
35
40
45
ns
tAS
tWP
tAH
tDW
tDH
Address Setup Time
Write Pulse Width
0
9
0
8
0
0
11
0
0
15
0
0
18
0
0
22
0
0
25
0
0
30
0
0
35
0
ns
ns
ns
ns
ns
Address Hold Time
Data Valid to End of Write
Data Hold Time
9
11
0
13
0
15
0
20
0
25
0
30
0
0
Write Enable to Output in
High Z
tWZ
tOW
7
8
10
11
15
18
25
30
ns
ns
Output Active from End of
Write
3
3
3
3
3
3
3
3
TIMIꢀꢁ WAVEFORM OF WRITE CYCLE ꢀO. 1 (WE COꢀTROLLED)(10,11)
Notes:
10. CE and WE must be LOW for WRITE cycle.
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
11. OE is LOW for this WRITE cycle to show tWZ and tOW
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
.
Document # SRAM119 REV I
Page 5
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
TIMIꢀꢁ WAVEFORM OF WRITE CYCLE ꢀO. 2 (CE COꢀTROLLED)(10)
AC TEST COꢀDITIOꢀS
Input Pulse Levels
TRUTH TABLE
GND to 3.0V
Mode
CE
H
L
OE
X
WE
X
I/O
Power
Standby
Active
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
Standby
DOUT Disabled
Read
High Z
High Z
DOUT
H
H
1.5V
L
L
H
Active
See Figures 1 and 2
Write
L
X
L
High Z
Active
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
ꢀote:
Becauseoftheultra-highspeedoftheP4C1256,caremustbetakenwhen
testing this device; an inadequate setup can cause a normal function-
ing part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOUT to match 166Ω (Thevenin Resistance).
Document # SRAM119 REV I
Page 6
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
ORDERIꢀꢁ IꢀFORMATIOꢀ
Document # SRAM119 REV I
Page 7
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
LCC PIꢀ COꢀFIꢁURATIOꢀS
28-Pin LCC (L5)
32-Pin LCC (L6)
TSOP (T1)
Document # SRAM119 REV I
Page 8
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
SIDE BRAZED CERAMIC DUAL Iꢀ-LIꢀE PACKAꢁE (300 MILS)
Pkg #
C5
# Pins
28 (300 mil)
Symbol
Min
-
Max
A
b
0.225
0.026
0.065
0.018
1.485
0.310
0.014
0.045
0.008
-
b2
C
D
E
0.240
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
0.015
0.005
0.005
0.070
S1
S2
-
-
SIDE BRAZED CERAMIC DUAL Iꢀ-LIꢀE PACKAꢁE (600 MILS)
Pkg #
C5-1
# Pins
28 (600 mil)
Symbol
Min
-
Max
A
b
0.232
0.026
0.065
0.018
1.490
0.610
0.014
0.045
0.008
-
b2
C
D
E
0.500
eA
e
0.600 BSC
0.100 BSC
L
0.125
0.200
Q
0.015
0.005
0.005
0.060
S1
S2
-
-
Document # SRAM119 REV I
Page 9
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
CERDIP DUAL Iꢀ-LIꢀE PACKAꢁE
Pkg #
D5-1
# Pins
28 (600 mil)
Symbol
Min
-
Max
0.232
0.026
0.065
0.018
1.490
0.610
A
b
0.014
0.045
0.008
-
b2
C
D
E
0.500
eA
e
0.600 BSC
0.100 BSC
L
0.125
0.200
0.060
-
Q
S1
α
0.015
0.005
0°
15°
CERDIP DUAL Iꢀ-LIꢀE PACKAꢁE
Pkg #
D5-2
# Pins
28 (300 mil)
Symbol
Min
-
Max
0.225
0.026
0.065
0.018
1.485
0.310
A
b
0.014
0.045
0.008
-
b2
C
D
E
0.240
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.060
-
Q
S1
α
0.015
0.005
0°
15°
Document # SRAM119 REV I
Page 10
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
CERPACK CERAMIC FLAT PACKAꢁE
Pkg #
F4
# Pins
28
Symbol
Min
0.060
0.015
0.004
-
Max
A
b
0.090
0.022
0.009
0.730
0.380
c
D
E
e
0.330
0.050 BSC
k
0.005
0.018
0.370
0.045
0.085
-
L
0.250
0.026
-
Q
S
S1
0.005
SOLDER SEAL FLAT PACK
Pkg #
FS-5
# Pins
28
Symbol
Min
Max
0.130
0.022
0.009
0.740
0.420
0.440
-
A
b
0.090
0.015
0.004
c
D
E
0.380
-
E1
E2
E3
e
0.180
0.030
-
0.050 BSC
L
0.250
0.370
0.045
-
Q
S1
0.026
0.000
Document # SRAM119 REV I
Page 11
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
SOJ SMALL OUTLIꢀE IC PACKAꢁE
Pkg #
J5
# Pins
28 (300 mil)
Symbol
Min
Max
0.148
-
A
A1
b
0.120
0.078
0.014
0.007
0.700
0.020
0.011
0.730
C
D
e
0.050 BSC
E
0.292
0.335
0.262
0.025
0.300
0.347
0.272
-
E1
E2
Q
RECTAꢀꢁULAR LEADLESS CHIP CARRIER (28 PIꢀS)
Pkg #
# Pins
Symbol
A
L5
28
Min
Max
0.060
0.050
0.022
0.342
0.075
0.065
0.028
0.358
A1
B1
D
D1
D2
D3
E
0.200 BSC
0.100 BSC
-
0.358
0.560
0.540
E1
E2
E3
e
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
h
j
L
0.045
0.055
0.055
0.095
L1
0.045
0.075
L2
ND
NE
5
9
Document # SRAM119 REV I
Page 12
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
RECTAꢀꢁULAR LEADLESS CHIP CARRIER (32 PIꢀS)
Pkg #
# Pins
Symbol
A
L6
32
Min
Max
0.060
0.050
0.022
0.442
0.075
0.065
0.028
0.458
A1
B1
D
D1
D2
D3
E
0.300 BSC
0.150 BSC
-
0.458
0.560
0.540
E1
E2
E3
e
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
h
j
L
0.045
0.055
0.055
0.095
L1
0.045
0.075
L2
ND
NE
7
9
PLASTIC DUAL Iꢀ-LIꢀE PACKAꢁE
Pkg #
P5
# Pins
28 (300 mil)
Symbol
Min
Max
0.210
-
A
A1
b
-
0.014
0.045
0.008
1.345
0.270
0.300
0.023
0.070
0.014
1.400
0.300
0.380
b2
C
D
E1
E
e
0.100 BSC
eB
L
-
0.430
0.150
15°
0.115
0°
α
Document # SRAM119 REV I
Page 13
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
PLASTIC DUAL Iꢀ-LIꢀE PACKAꢁE
Pkg #
P6
# Pins
28 (600 mil)
Symbol
Min
Max
A
A1
b
0.090
0.000
0.014
0.015
0.008
1.380
0.485
0.600
0.200
0.070
0.020
0.065
0.012
1.480
0.550
0.625
b2
C
D
E1
E
e
0.100 BSC
0.600 TYP
0.100 0.200
eB
L
α
0°
15°
TSOP THIꢀ SMALL OUTLIꢀE PACKACꢁE (8 x 13.4 mm)
Pkg #
T1
# Pins
28
Symbol
Min
Max
0.047
0.040
0.011
0.469
0.319
A
A2
b
0.039
0.036
0.007
0.461
0.311
D
E
e
0.022 BSC
0.520 0.535
HD
Document # SRAM119 REV I
Page 14
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
SOIC/SOP SMALL OUTLIꢀE IC PACKAꢁE
Pkg #
S11-1
# Pins
28 (300 Mil)
Symbol
Min
Max
A
A1
b2
C
D
e
0.093
0.004
0.013
0.009
0.696
0.104
0.012
0.020
0.012
0.712
0.050 BSC
E
0.291
0.394
0.010
0.016
0°
0.299
0.419
0.029
0.050
8°
H
h
L
α
SOIC/SOP SMALL OUTLIꢀE IC PACKAꢁE
Pkg #
S11-3
# Pins
28 (300 Mil)
Symbol
Min
Max
0.110
0.014
0.020
0.012
0.710
A
A1
B
0.094
0.002
0.014
0.008
0.702
C
D
e
0.050 BSC
E
0.291
0.463
0.010
0.020
0°
0.300
0.477
0.029
0.042
8°
H
h
L
Document # SRAM119 REV I
Page 15
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
REVISIOꢀS
DOCUMEꢀT ꢀUMBER SRAM 119
DOCUMEꢀT TITLE
P4C1256 HIGH SPEED 32K x 8 STATIC CMOS RAM
REV ISSUE DATE
ORIꢁIꢀATOR DESCRIPTIOꢀ OF CHAꢀꢁE
OR
A
B
C
D
E
F
1997
RKK
JDB
JDB
JDB
JDB
JDB
JDB
JDB
JDB
JDB
New Data Sheet
Oct-2005
Oct-2005
Apr-2006
May-2006
Jun-2006
Aug-2006
Jun-2007
July-2009
July 2010
Changed logo to Pyramid
Added SOP package
Added Lead-Free to ordering information
Added PDIP to ordering information
Added ceramic DIP package
Updated SOJ package information
Corrected SOP package information
Added 28-pin 600 mil CERDIP, 600 mil PDIP.
Added 28-pin Solder Seal Flat Pack
G
H
I
Document # SRAM119 REV I
Page 16
相关型号：
SI9130DB
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