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P4C1256L-55L32MB [PYRAMID]

Standard SRAM, 32KX8, 55ns, CMOS, 0.450 X 0.550 INCH, LCC-32;
P4C1256L-55L32MB
型号： P4C1256L-55L32MB
厂家： PYRAMID SEMICONDUCTOR CORPORATION    PYRAMID SEMICONDUCTOR CORPORATION
描述：

Standard SRAM, 32KX8, 55ns, CMOS, 0.450 X 0.550 INCH, LCC-32

静态存储器
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中文：  中文翻译
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P4C1256L  
LOW POWER 32K X 8  
STATIC CMOS RAM  
FEATURES  
VCC Current (Commercial/Industrial)  
— Operating: 70mA/85mA  
— CMOS Standby: 100µA/100µA  
Three-State Outputs  
Fully TTL Compatible Inputs and Outputs  
Advanced CMOS Technology  
Automatic Power Down  
Packages  
— 28-Pin 600 mil DIP  
Access Times  
—55/70/85  
— 28-Pin 300 mil CERDIP  
— 28-Pin 300 mil Narrow Body SOP  
— 28-Pin 330 mil SOP  
— 28-Pin LCC (350x550mil)  
— 32-Pin LCC (450x550mil)  
Single 5 Volts ±10% Power Supply  
Easy Memory Expansion Using CE and OE Inputs  
Common Data I/O  
DESCRIPTION  
The P4C1256L is a 262,144-bit low power CMOS  
static RAM organized as 32Kx8. The CMOS memory  
requires no clocks or refreshing, and has equal access  
and cycle times. Inputs are fully TTL-compatible. The  
RAM operates from a single 5V±10% tolerance power  
supply.  
with matching access and cycle times. Memory locations  
are specified on address pinsA0 toA14. Reading is accom-  
plished by device selection (CE and output enabling (OE)  
while write enable (WE) remains HIGH. By presenting the  
address under these conditions, the data in the addressed  
memory location is presented on the data input/output pins.  
The input/output pins stay in the HIGH Z state when either  
CE or OE is HIGH or WE is LOW.  
Access times of 55 ns and 70 ns are available. CMOS is  
utilized to reduce power consumption to a low level.  
The P4C1256L device provides asynchronous operation  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATIONS  
DIP (P6, D5-2), SOP (S11-2, S11-3)  
TOP VIEW  
LCC PIN CONFIGURATIONS AT END OF DATASHEET  
Document # SRAM121 REV G  
Revised July 2012  
P4C1256L - 32K x 8 STATIC CMOS RAM  
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE  
Temperature Range (Ambient)  
Commercial (0°C to 70°C)  
Industrial (-40°C to 85°C)  
Military (-55°C to 125°C)  
Supply Voltage  
4.5V ≤ VCC ≤ 5.5V  
4.5V ≤ VCC ≤ 5.5V  
4.5V ≤ VCC ≤ 5.5V  
MAXIMUM RATINGS(1)  
Sym  
Parameter  
Min  
Max  
Unit  
VCC  
Supply Voltage with Respect to GND  
-0.5  
-0.5  
-55  
-65  
7.0  
V
VTERM  
TA  
Terminal Voltage with Respect to GND (up to 7.0V)  
Operating Ambient Temperature  
Storage Temperature  
VCC + 0.5  
125  
V
°C  
STG  
IOUT  
ILAT  
150  
°C  
Output Current into Low Outputs  
Latch-up Current  
25  
mA  
mA  
> 200  
DC ELECTRICAL CHARACTERISTICS  
(Over Recommended Operating Temperature & Supply Voltage)(2)  
Sym Parameter  
Test Conditions  
IOH = -1mA, VCC = 4.5V  
IOL = 2.1mA  
Min  
Max  
Unit  
V
VOH Output High Voltage (I/O0 - I/O7)  
VOL Output Low Voltage (I/O0 - I/O7)  
VIH Input High Voltage  
2.4  
0.4  
VCC + 0.3  
0.8  
V
2.2  
-0.5(3)  
-2  
V
VIL Input Low Voltage  
V
Com  
Ind  
+2  
ILI  
Input Leakage Current  
GND ≤ VIN ≤ VCC  
-5  
+5  
µA  
µA  
Mil  
Com  
Ind  
-2  
-5  
+2  
+5  
GND ≤ VOUT ≤ VCC  
ILO Output Leakage Current  
CE = VIH  
Mil  
VCC Current  
ISB TTL Standby Current  
(TTL Input Levels)  
VCC = 5.5V, IOUT = 0 mA  
3
mA  
µA  
CE = VIH  
VCC Current  
ISB1 CMOS Standby Current  
(CMOS Input Levels)  
VCC = 5.5V, IOUT = 0 mA  
100  
CE ≥ VCC - 0.2V  
N/A = Not applicable  
Document # SRAM121 REV G  
Page 2  
P4C1256L - 32K x 8 STATIC CMOS RAM  
CAPACITANCES(4)  
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)  
Symbol  
CIN  
Parameter  
Test Conditions  
VIN=0V  
Max  
7
Unit  
pF  
Input Capacitance  
Output Capacitance  
COUT  
VOUT=0V  
9
pF  
POWER DISSIPATION CHARACTERISTICS VS. SPEED  
*
**  
Sym Parameter  
Temperature Range  
Unit  
-55  
70  
-70  
70  
-85  
-55  
15  
25  
35  
-70  
15  
25  
35  
-85  
15  
25  
35  
Commercial  
Industrial  
Military  
70  
85  
mA  
mA  
mA  
ICC  
Dynamic Operating Current*  
85  
85  
100  
100  
100  
* Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously  
enabled for writing, i.e. CE and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V.  
** As above but @ f=1 MHz and VIL/VIH = 0V/VCC.  
AC ELECTRICAL CHARACTERISTICS—READ CYCLE  
(Over Recommended Operating Temperature & Supply Voltage)  
-55  
-70  
-85  
Sym  
Parameter  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
tRC  
tAA  
Read Cycle Time  
55  
70  
85  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
55  
55  
70  
70  
85  
85  
tAC  
tOH  
tLZ  
Chip Enable Access Time  
Output Hold from Address Change  
Chip Enable to Output in Low Z  
Chip Disable to Output in High Z  
Output Enable Low to Data Valid  
Output Enable Low to Low Z  
Output Enable High to High Z  
Chip Enable to Power Up Time  
Chip Disable to Power Down Time  
5
5
5
5
5
5
tHZ  
20  
30  
25  
35  
30  
40  
tOE  
tOLZ  
tOHZ  
tPU  
tPD  
5
0
5
0
5
0
20  
55  
25  
70  
30  
85  
Document # SRAM121 REV G  
Page 3  
P4C1256L - 32K x 8 STATIC CMOS RAM  
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)  
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)  
TIMING WAVEFORM OF READ CYCLE NO. 3 (ADDRESS CONTROLLED)(5,7)  
Notes:  
1. Stresses greater than those listed under MAXIMUM RATINGS may  
cause permanent damage to the device. This is a stress rating only  
and functional operation of the device at these or any other conditions  
above those indicated in the operational sections of this specification  
is not implied. Exposure to MAXIMUM rating conditions for extended  
periods may affect reliability.  
2. Extended temperature operation guaranteed with 400 linear feet per  
minute of air flow.  
3. Transient inputs with VIL and IIL not more negative than –3.0V and  
–100mA, respectively, are permissible for pulse widths up to 20ns.  
4. This parameter is sampled and not 100% tested.  
5. WE is HIGH for READ cycle.  
6. CE is LOW and OE is LOW for READ cycle.  
7. ADDRESS must be valid prior to, or coincident with CE transition LOW.  
8. Transition is measured ± 200 mV from steady state voltage prior to  
change,withloadingasspecifiedinFigure1. Thisparameterissampled  
and not 100% tested.  
9. Read Cycle Time is measured from the last valid address to the first  
transitioning address.  
Document # SRAM121 REV G  
Page 4  
P4C1256L - 32K x 8 STATIC CMOS RAM  
AC CHARACTERISTICS—WRITE CYCLE  
(Over Recommended Operating Temperature & Supply Voltage)  
-55  
-70  
-85  
Symbol Parameter  
Min  
Unit  
Max  
Min  
Max  
Min  
Max  
tWC  
tCW  
tAW  
tAS  
Write Cycle Time  
55  
50  
50  
0
70  
85  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Enable Time to End of Write  
Address Valid to End of Write  
Address Setup Time  
60  
60  
0
75  
75  
0
tWP  
tAH  
tDW  
tDH  
tWZ  
tOW  
Write Pulse Width  
40  
0
50  
0
60  
0
Address Hold Time  
Data Valid to End of Write  
Data Hold Time  
25  
0
30  
0
35  
0
Write Enable to Output in High Z  
Output Active from End of Write  
25  
30  
35  
5
5
5
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11)  
Notes:  
10. CE and WE must be LOW for WRITE cycle.  
13. Write Cycle Time is measured from the last valid address to the first  
11. OE is LOW for this WRITE cycle to show tWZ and tOW  
12. If CE goes HIGH simultaneously with WE HIGH, the output remains  
in a high impedance state  
.
transitioning address.  
Document # SRAM121 REV G  
Page 5  
P4C1256L - 32K x 8 STATIC CMOS RAM  
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10)  
AC TEST CONDITIONS  
Input Pulse Levels  
TRUTH TABLE  
GND to 3.0V  
Mode  
CE  
OE  
X
WE  
X
I/O  
Power  
Standby  
Standby  
Active  
Input Rise and Fall Times  
Input Timing Reference Level  
Output Timing Reference Level  
Output Load  
3ns  
1.5V  
Standby  
Standby  
DOUT Disabled  
Read  
H
X
L
L
L
High Z  
High Z  
High Z  
DOUT  
X
X
1.5V  
H
L
H
See Figures 1 and 2  
H
Active  
Write  
X
L
High Z  
Active  
Figure 1. Output Load  
Figure 2. Thevenin Equivalent  
* including scope and test fixture.  
Note:  
Because of the high speed of the P4C1256L, care must be taken when  
testing this device; an inadequate setup can cause a normal function-  
ing part to be rejected as faulty. Long high-inductance leads that cause  
supply bounce must be avoided by bringing the VCC and ground planes  
directly up to the contactor fingers. A 0.01 µF high frequency capacitor  
is also required between VCC and ground. To avoid signal reflections,  
proper termination must be used; for example, a 50Ω test environment  
should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at  
the comparator input, and a 589Ω resistor must be used in series with  
DOUT to match 639Ω (Thevenin Resistance).  
Document # SRAM121 REV G  
Page 6  
P4C1256L - 32K x 8 STATIC CMOS RAM  
DATA RETENTION CHARACTERISTICS  
Typ.*  
VCC  
Max  
VCC =  
=
Sym  
Parameter  
Test Conditions  
Min  
Unit  
2.0V  
3.0V  
2.0V  
3.0V  
VDR  
VCC for Data Retention  
Data Retention Current  
2.0  
V
ICCDR  
10  
15  
80  
120  
µA  
CE ≥ VCC - 0.2V,  
VIN ≥ VCC - 0.2V  
or VIN ≤ 0.2V  
Chip Deselect to Data Reten-  
tion Time  
tCDR  
0
ns  
ns  
†
§
tR  
Operation Recovery Time  
tRC  
* TA = +25°C  
tRC§ = Read Cycle Time  
† = This parameter is guaranteed but not tested.  
DATA RETENTION WAVEFORM  
LCC PIN CONFIGURATIONS  
28-Pin LCC (L5)  
32-Pin LCC (L6)  
Document # SRAM121 REV G  
Page 7  
P4C1256L - 32K x 8 STATIC CMOS RAM  
ORDERING INFORMATION  
Document # SRAM121 REV G  
Page 8  
P4C1256L - 32K x 8 STATIC CMOS RAM  
CERDIP DUAL IN-LINE PACKAGE  
Pkg #  
D5-2  
# Pins  
28 (300 mil)  
Symbol  
Min  
-
Max  
A
b
0.225  
0.026  
0.065  
0.018  
1.485  
0.310  
0.014  
0.045  
0.008  
-
b2  
C
D
E
0.240  
eA  
e
0.300 BSC  
0.100 BSC  
L
0.125  
0.200  
0.060  
-
Q
S1  
0.015  
0.005  
RECTANGULAR LEADLESS CHIP CARRIER  
Pkg #  
# Pins  
Symbol  
A
L5  
28  
Min  
Max  
0.060  
0.050  
0.022  
0.342  
0.075  
0.065  
0.028  
0.358  
A1  
B1  
D
D1  
D2  
D3  
E
0.200 BSC  
0.100 BSC  
-
0.358  
0.560  
0.540  
E1  
E2  
E3  
e
0.400 BSC  
0.200 BSC  
-
0.558  
0.050 BSC  
0.040 REF  
0.020 REF  
h
j
L
0.045  
0.055  
0.055  
0.095  
L1  
0.045  
0.075  
L2  
ND  
5
Document # SRAM121 REV G  
Page 9  
P4C1256L - 32K x 8 STATIC CMOS RAM  
RECTANGULAR LEADLESS CHIP CARRIER  
Pkg #  
# Pins  
Symbol  
A
L6  
32  
Min  
Max  
0.060  
0.050  
0.022  
0.442  
0.075  
0.065  
0.028  
0.458  
A1  
B1  
D
D1  
D2  
D3  
E
0.300 BSC  
0.150 BSC  
-
0.458  
0.560  
0.540  
E1  
E2  
E3  
e
0.400 BSC  
0.200 BSC  
-
0.558  
0.050 BSC  
0.040 REF  
0.020 REF  
h
j
L
0.045  
0.055  
0.055  
0.095  
L1  
0.045  
0.075  
L2  
ND  
7
PLASTIC DUAL IN-LINE PACKAGE  
Pkg #  
P6  
# Pins  
28 (600 mil)  
Symbol  
Min  
Max  
A
A1  
b
0.090  
0.000  
0.014  
0.015  
0.008  
1.380  
0.485  
0.600  
0.200  
0.070  
0.020  
0.065  
0.012  
1.480  
0.550  
0.625  
b2  
C
D
E1  
E
e
0.100 BSC  
0.600 TYP  
0.100 0.200  
0° 15°  
eB  
L
α
Document # SRAM121 REV G  
Page 10  
P4C1256L - 32K x 8 STATIC CMOS RAM  
SOIC/SOP SMALL OUTLINE IC PACKAGE  
Pkg #  
S11-2  
# Pins  
28 (330 Mil)  
Symbol  
Min  
-
Max  
0.112  
-
A
A1  
b2  
C
D
e
0.004  
0.014  
0.008  
0.693  
0.020  
0.014  
0.733  
0.050 BSC  
E
0.321  
0.453  
0.010  
0.028  
0°  
0.341  
0.477  
0.029  
0.044  
8°  
H
h
L
α
SOIC/SOP SMALL OUTLINE IC PACKAGE (NARROW BODY)  
Pkg #  
S11-3  
28 (300 Mil)  
# Pins  
Symbol  
Min  
Max  
0.110  
0.014  
0.020  
0.012  
0.710  
A
A1  
B
C
D
e
0.094  
0.002  
0.014  
0.008  
0.702  
0.050 BSC  
E
H
h
0.291  
0.463  
0.010  
0.020  
0°  
0.300  
0.477  
0.029  
0.042  
8°  
L
α
Document # SRAM121 REV G  
Page 11  
P4C1256L - 32K x 8 STATIC CMOS RAM  
REVISIONS  
DOCUMENT NUMBER SRAM121  
DOCUMENT TITLE  
P4C1256L LOW POWER 32K x 8 STATIC CMOS RAM  
REV ISSUE DATE  
ORIGINATOR DESCRIPTION OF CHANGE  
OR  
A
1997  
DAB  
JDB  
JDB  
JDB  
New Data Sheet  
Oct-2005  
Jun-2006  
Aug-2006  
Changed logo to Pyramid  
Added 28-pin ceramic DIP  
Added Lead Free designation  
B
C
Corrected Narrow SOP width in Ordering Information and Selection  
Guide  
D
Mar-2007  
JDB  
E
F
Jun-2007  
Sep-2010  
Jul-2012  
JDB  
JDB  
JDB  
Corrected Narrow SOP package dimensions  
Added 28-pin and 32-pin LCC packages  
Added 28-pin 330 mil SOP  
G
Document # SRAM121 REV G  
Page 12  

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