P4C148-15LSC [PYRAMID]
ULTRA HIGH SPEED 1K x 4 STATIC CMOS RAMS; 超高速1K ×4的静态CMOS RAMS
| 型号： | P4C148-15LSC |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | ULTRA HIGH SPEED 1K x 4 STATIC CMOS RAMS |
| 文件： | 总10页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C148, P4C149
ULTRA HIGH SPEED 1K x 4
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
Two Options
– P4C148 Low Power Standby Mode
– P4C149 Fast Chip Select Control
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35/45/55 ns (Commercial)
– 15/20/25/35/45/55 ns (P4C148 Military)
Common Input/Output Ports
Three-State Outputs
Low Power Operation
Fully TTL Compatible Inputs and Outputs
Single 5V ± 10% Power Supply
Standard Pinout (JEDEC Approved)
– 18 Pin 300 mil DIP
– 18 Pin LCC (295 x 335 mil) [P4C148 only]
– 18 Pin LCC (290 x 430 mil)
DESCRIPTION
TheP4C148andP4C149are4,096-bitultrahigh-speed
static RAMs organized as 1K x 4. Both devices have
common input/output ports. The P4C148 enters the
standby mode when the chip enable (CE) goes HIGH;
withCMOSinputlevels,powerconsumptionisextremely
low in this mode. The P4C149 features a fast chip select
capability using CS. The CMOS memories require no
clocks or refreshing, and have equal access and cycle
times. Inputs are fully TTL-compatible. The RAMs
operate from a single 5V ± 10% tolerance power supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption when
active;fortheP4C148,consumptionisfurtherreducedin
the standby mode.
The P4C148 and P4C149 are available in 18-pin 300 mil
DIP packages, as well as 2 different LCC packages,
providing excellent board level densities.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
P4C148 DIP (C9, D1, P1)
P4C149 DIP (P1)
P4C148 LCC (L7, L7-1)
P4C149 LCC (L7)
Document # SRAM104 REV B
Revised April 2007
1
P4C148/P4C149
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125 °C
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TSTG
PT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150 °C
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
VTERM
TA
V
1.0
50
W
IOUT
mA
Operating Temperature –55 to +125 °C
RECOMMENDED OPERATING
CONDITIONS
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Grade(2)
Commercial
Military
Ambient Temp
0°C to 70°C
Gnd
VCC
Symbol
CIN
Parameter
Conditions Typ. Unit
Input Capacitance VIN = 0V
Output Capacitance VOUT= 0V
5
7
pF
pF
0V 5.0V ± 10%
0V 5.0V ± 10%
-55°C to +125°C
COUT
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage (2)
P4C148
P4C149
Sym.
VOH
Test Conditions
Unit
Parameter
Min.
Min.
Max.
Max.
Output High Voltage
(TTL Load)
IOH = –4 mA, VCC = Min.
2.4
2.4
V
V
Output Low Voltage
(TTL Load)
VOL
IOL = +8 mA, VCC = Min
0.4
0.4
VIH Input High Voltage
2.2 VCC+0.5 2.2 VCC+0.5
V
V
–0.5(3)
0.8
–0.5(3)
0.8
Input Low Voltage
VIL
ILI
–10
–5
+10
+5
Mil.
–10
Comm’l –5
+10
+5
VCC = Max., VIN = GND to VCC
µA
Input Leakage Current
VCC = Max., CE, CS = VIH,
VOUT = GND to VCC
Mil. –10
Comm’l –5
+10
+5
–10
–5
+10
+5
ILO Output Leakage Current
µA
Standby Power Supply
ISB
mA
CE ≥ VIH, VCC = Max.,
f=Max., Outputs Open
Mil.
Comm’l
30
23
N/A
N/A
Current (TTL Input Levels)
Standby Power Supply
Current
CE ≥ VHC, VCC = Max., f= 0,
Outputs Open
Mil.
Comm’l
15
10
mA
N/A
N/A
ISB1
(CMOS Input Levels)
VIN ≤ 0.2V or VIN ≥ VCC –0.2V
N/A = Not Applicable
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Parameter
Temperature Range
Commercial
-10 -12 -15 -20 -25 -35 -45 -55
Unit
Symbol
130 130 120 115 100 100 95 95 mA
N/A N/A 145 135 125 120 115 115 mA
Dynamic Operating Current
ICC
Military
Document # SRAM104 REV B
Page 2 of 10
P4C148/P4C149
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-10
-12
-15
-20
-25
-35
-45
-55
Sym
tRC
Parameter
Read Cycle Time
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
10
12
15
20
25
35
45
55
tAA
tAC
tAC
tOH
tLZ
Address Access Time
10
10
8
12
12
10
15
15
12
20
20
14
25
25
15
35
35
20
45
45
20
55
55
25
Chip Enable Access Time (P4C148)
Chip Enable Access Time (P4C149)
Output Hold from Address Change
Chip Enable to Output in Low Z (P4C149)
Chip Disable to Output in High Z (P4C149)
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
tHZ
4
5
6
8
10
25
14
35
18
45
20
55
tRCS Read Command Setup Time
tRCH Read Command Hold Time
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
tPU
tPD
Chip Enable to Power Up Time (P4C148)
Chip Disable to Power Down Time (P4C148)
10
12
15
20
TIMING WAVEFORM OF READ CYCLE
TIMING WAVEFORM OF READ CYCLE NO. 2(6)
Notes:
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
5. CE is LOW and WE is HIGH for READ cycle.
6. WE is HIGH, and address must be valid prior to or coincident with
CE transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is
sampled and not 100% tested.
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to MAXIMUM rating condi-
tions for extended periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet
per minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM104 REV B
Page 3 of 10
P4C148/P4C149
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-10
-12
-15
-20
-25
-35
-45
-55
Sym
Parameter
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tWC Write Cycle Time
10
8
12
10
10
0
15
12
12
0
20
16
16
0
25
20
20
0
35
25
25
0
45
30
30
0
55
35
35
0
tCW Chip Enable Time to End of Write
tAW Address Valid to End of Write
tAS Address Set-up Time
8
0
tWP Write Pulse Width
8
10
0
12
0
16
0
20
0
25
0
30
0
35
0
tAH Address Hold Time from End of Write
tDW Data Valid to End of Write
tDH Data Hold Time
0
5
6
7
9
12
0
16
0
20
0
25
0
0
0
0
0
tWZ Write Enable to Output in High Z
tOW Output Active from End of Write
5
6
7
7
8
12
15
20
0
0
0
0
0
0
0
0
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(9)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE/CS CONTROLLED)(9)
Notes:
9. CE and WE must be LOW for WRITE cycle.
10. If CE goes HIGH simultaneously with WE high, the output remains in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first transition address.
Document # SRAM104 REV B
Page 4 of 10
P4C148/P4C149
AC TEST CONDITIONS
TRUTH TABLE
Mode
Standby
Read
CE
H
L
WE
X
Output
High Z
DOUT
Power
Standby
Active
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
H
Write
L
L
High Z
Active
1.5V
See Figures 1 and 2
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Due to the ultra-high speed of the P4C148/149, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the VCC and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
capacitor is also required between VCC and ground. To avoid signal
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with DOUT to match 166Ω (Thevenin Resistance).
Document # SRAM104 REV B
Page 5 of 10
P4C148/P4C149
ORDERING INFORMATION
SELECTION GUIDE
The P4C148/P4C149 are available in the following temperature, speed and package options.
Speed (ns)
20
Temperature
Range
Package
10
-10PC
-10CC
N/A
12
-12PC
-12CC
N/A
15
25
35
45
55
Plastic DIP
-15PC
-20PC
-20CC
-25PC
-25CC
-35PC
-35CC
-35DM
-35CM
-35LM
-45PC
-45CC
-45DM
-45CM
-45LM
-55PC
-55CC
-55DM
-55CM
-55LM
Commercial
Temperature
Side Brazed DIP
CERDIP
-15CC
-15DM
-15CM
-15LM
-20DM
-25DM
Side Brazed DIP
LCC (290 x 430 mil)
LCC (295 x 335 mil)
CERDIP
N/A
N/A
-20CM
-25CM
Military
Temperature
N/A
N/A
-20LM
-25LM
N/A
N/A
-15LSM
-15DMB
-15CMB
-15LMB
-15LSMB
-20LSM
-20DMB
-20CMB
-20LMB
-20LSMB
-25LSM
-25DMB
-25CMB
-25LMB
-25LSMB
-35LSM
-35DMB
-35CMB
-35LMB
-45LSM -55LSM
-45DMB -55DMB
-45CMB -55CMB
N/A
N/A
Side Brazed DIP
LCC (290 x 430 mil)
LCC (295 x 335 mil)
N/A
N/A
Military
Processed*
N/A
N/A
-45LMB
-55LMB
N/A
N/A
-35LSMB -45LSMB -55LSMB
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not Available
Document # SRAM104 REV B
Page 6 of 10
P4C148/P4C149
SIDE BRAZED DUAL IN-LINE PACKAGES
Pkg #
C9
# Pins
18 (300 Mil)
Symbol
Min
-
0.014
0.030
0.008
-
Max
A
b
b2
C
D
E
0.200
0.026
0.065
0.018
0.960
0.320
0.220
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.070
-
-
CERDIP DUAL IN-LINE PACKAGES
Pkg #
# Pins
Symbol
D1
18 (300 Mil)
Min
-
0.014
0.045
0.008
-
Max
A
b
b2
C
D
E
0.200
0.026
0.065
0.018
0.960
0.310
0.220
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.070
-
Q
S1
α
0.015
0.005
0°
15°
Document # SRAM104 REV B
Page 7 of 10
P4C148/P4C149
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
L7
# Pins
Symbol
A
18
Min
Max
0.060
0.050
0.022
0.280
0.075
0.065
0.028
0.305
A1
B1
D
D1
D2
D3
E
.150 BSC
.075 BSC
-
0.305
0.440
0.417
E1
E2
E3
e
h
j
0.200 BSC
0.100 BSC
-
0.440
0.050 BSC
0.040 REF
0.020 REF
L
L1
L2
0.045
0.075
0.075
0.055
0.090
0.148
ND
NE
4
5
RECTANGULAR LEADLESS CHIP CARRIER (SMALL)
Pkg #
# Pins
Symbol
A
L7-1
18
Min
Max
0.060
0.050
0.022
0.280
0.075
0.065
0.028
0.305
A1
B1
D
D1
D2
D3
E
.150 BSC
.075 BSC
-
0.305
0.365
0.345
E1
E2
E3
e
h
j
0.200 BSC
0.100 BSC
-
0.365
0.050 BSC
0.040 REF
0.020 REF
L
L1
L2
0.045
0.045
0.075
0.055
0.055
0.125
ND
NE
4
5
Document # SRAM104 REV B
Page 8 of 10
P4C148/P4C149
PLASTIC DUAL IN-LINE PACKAGE
Pkg #
P1
# Pins
18 (300 Mil)
Symbol
Min
-
Max
0.210
-
0.022
0.070
0.014
0.920
0.280
0.325
A
A1
b
b2
C
D
E1
E
0.015
0.014
0.045
0.008
0.880
0.240
0.300
e
0.100 BSC
eB
L
α
-
0.430
0.150
15°
0.115
0°
Document # SRAM104 REV B
Page 9 of 10
P4C148/P4C149
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM104
P4C148/P4C149 ULTRA HIGH SPEED 1K x 4 STATIC CMOS RAMS
ORIG. OF
CHANGE
ISSUE
REV.
DESCRIPTION OF CHANGE
DATE
OR
1997
DAB
New Data Sheet
A
B
Oct-05
Apr-07
JDB
JDB
Change logo to Pyramid
Added 45 and 55 ns speeds
Document # SRAM104 REV B
Page 10 of 10
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