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P4C164L-12DMBLF [PYRAMID]

Standard SRAM, 8KX8, 12ns, CMOS, CDIP28, 0.300 INCH, ROHS COMPLIANT, CERAMIC, DIP-28;
P4C164L-12DMBLF
型号： P4C164L-12DMBLF
厂家： PYRAMID SEMICONDUCTOR CORPORATION    PYRAMID SEMICONDUCTOR CORPORATION
描述：

Standard SRAM, 8KX8, 12ns, CMOS, CDIP28, 0.300 INCH, ROHS COMPLIANT, CERAMIC, DIP-28

CD 静态存储器 内存集成电路
文件： 总16页 (文件大小：1094K)
中文：  中文翻译
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P4C164  
ULTRA HIGH SPEED 8K X 8  
STATIC CMOS RAMS  
FEATURES  
Full CMOS, 6T Cell  
Common Data I/O  
ꢀ
High Speed (Equal Access and Cycle Times)  
– 8/10/12/15/20/25/35/70/100 ns (Commercial)  
– 10/12/15/20/25/35/70/100 ns(Industrial)  
– 12/15/20/25/35/45/70/100 ns (Military)  
Fully TTL Compatible Inputs and Outputs  
ꢀ
Standard Pinout (JEDEC Approved)  
– 28-Pin 300 mil Plastic DIP, SOJ  
– 28-Pin 600 mil Plastic DIP  
– 28-Pin 300 mil SOP (70 & 100ns)  
– 28-Pin 300 mil Ceramic DIP  
– 28-Pin 600 mil Ceramic DIP  
– 28-Pin 350 x 550 mil LCC  
– 32-Pin 450 x 550 mil LCC  
– 28-Pin CERPACK  
Low Power Operation  
Output Enable and Dual Chip Enable Control  
Functions  
Single 5V±10% Power Supply  
Data Retention with 2.0V Supply, 10 µA Typical  
Current (P4C164L Military)  
DESCRIPTIOꢀ  
The P4C164 is a 65,536-bit ultra high-speed static RAM  
organizedas8Kx8.TheCMOSmemoryrequiresnoclocks  
orrefreshingandhasequalaccessandcycletimes. Inputs  
are fullyTTL-compatible. The RAM operates from a single  
5V±10%tolerancepowersupply. Withbatterybackup,data  
integrity is maintained with supply voltages down to 2.0V.  
Current drain is typically 10 µA from a 2.0V supply.  
Access times as fast as 8 nanoseconds are available,  
permitting greatly enhanced system operating speeds.  
The P4C164 is available in 28-pin 300 mil DIP and SOJ,  
28-pin600milplasticandceramicDIP,28-pin350x550mil  
LCC, 32-pin 450 x 550 mil LCC, and 28-pin CERPACK.  
FUꢀCTIOꢀAL BLOCK DIAꢁRAM  
PIꢀ COꢀFIꢁURATIOꢀS  
DIP (P5, P6, C5, C5-1, D5-1, D5-2),  
SOJ (J5), CERPACK (F4), SOP (S6)  
SEE PAGE 8 FOR LCC PIN CONFIGURATIONS  
Document # SRAM115 REV G  
Revised September 2010  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
MAꢂIMUM RATIꢀꢁS(1)  
RECOMMEꢀDED OPERATIꢀꢁ COꢀDITIOꢀS  
Sym Parameter  
Value  
Unit  
ꢁrade(2)  
Ambient Temp  
0°C to 70°C  
ꢁꢀD  
0V  
VCC  
Power Supply Pin with  
VCC  
Commercial  
Industrial  
Military  
5.0V ± 10%  
5.0V ± 10%  
5.0V ± 10%  
-0.5 to +7  
V
Respect to GND  
-40°C to +85°C  
-55°C to +125°C  
0V  
Terminal Voltage with  
VTERM Respect to GND (up to  
7.0V)  
-0.5 to VCC + 0.5  
V
0V  
CAPACITAꢀCES(4)  
TA  
Operating Temperature  
-55 to +125  
-55 to +125  
-65 to +150  
1.0  
°C  
°C  
°C  
W
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)  
TBIAS Temperature Under Bias  
TSTG Storage Temperature  
Sym Parameter  
Conditions Typ Unit  
PT  
Power Dissipation  
CIN  
Input Capacitance  
VIN=0V  
5
7
pF  
pF  
IOUT DC Output Current  
50  
mA  
COUT  
Output Capacitance  
VOUT=0V  
DC ELECTRICAL CHARACTERISTICS  
(Over Recommended Operating Temperature & Supply Voltage)(2)  
P4C164  
P4C164L  
Sym Parameter  
Test Conditions  
Unit  
Min  
2.2  
Max  
Min  
2.2  
Max  
VCC + 0.5  
0.8  
VIH  
VIL  
Input High Voltage  
Input Low Voltage  
VCC + 0.5  
0.8  
V
V
V
V
V
V
V
-0.5(3)  
VCC - 0.2  
-0.5(3)  
-0.5(3)  
VCC - 0.2  
-0.5(3)  
VHC CMOS Input High Voltage  
VLC CMOS Input Low Voltage  
VCC + 0.5  
0.2  
VCC + 0.5  
0.2  
VCD Input Clamp Diode Voltage  
VCC = Min, IIN = -18 mA  
IOL = +8 mA, VCC = Min  
-1.2  
-1.2  
VOL Output Low Voltage (TTL Load)  
0.4  
0.4  
VOH Output High Voltage (TTL Load) IOH = -4 mA, VCC = Min  
2.4  
-10  
-5  
2.4  
-5  
MIL  
IND/COM  
MIL  
+10  
+5  
+5  
N/A  
+5  
VCC = Max,  
VIN = GND to VCC  
ILI  
Input Leakage Current  
Output Leakage Current  
µA  
µA  
N/A  
-5  
-10  
-5  
+10  
+5  
VCC = Max, CE1 = VIH,  
VOUT = GND to VCC  
ILO  
IND/COM  
MIL  
N/A  
—
N/A  
40  
—
40  
CE1 ≥ VIH or CE2 ≤ VIL,  
Standby Power Supply Current  
(TTL Input Levels)  
ISB  
mA  
VCC=Max, f=Max, Outputs Open  
IND/COM  
—
30  
—
N/A  
CE1 ≥ VHC or CE2 ≤ VLC,  
VCC = Max, f = 0, Outputs Open  
VIN ≤ VLC or VIN ≥ VHC  
MIL  
—
—
25  
15  
—
—
1
Standby Power Supply Current  
(CMOS Input Levels)  
ISB1  
mA  
IND/COM  
N/A  
N/A = Not applicable  
ꢀotes:  
2. Extended temperature operation guaranteed with 400 linear feet per  
minute of air flow.  
3. Transient inputs with VIL and IIL not more negative than –3.0V and  
–100mA, respectively, are permissible for pulse widths up to 20ns.  
4. This parameter is sampled and not 100% tested.  
1. Stresses greater than those listed under MAꢀIMUM RATINGS may  
cause permanent damage to the device. This is a stress rating only  
and functional operation of the device at these or any other conditions  
above those indicated in the operational sections of this specification  
is not implied. Exposure to MAꢀIMUM rating conditions for extended  
periods may affect reliability.  
Document # SRAM115 REV G  
Page 2  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
POWER DISSIPATIOꢀ CHARACTERISTICS VS. SPEED  
Sym Parameter Temperature Range  
-8  
-10  
180  
190  
N/A  
-12  
170  
180  
180  
-15  
160  
170  
170  
-20  
155  
160  
160  
-25  
150  
155  
155  
-35  
145  
150  
150  
-45  
N/A  
N/A  
145  
-70  
130  
145  
145  
-100 Unit  
Commercial  
Dynamic  
200  
N/A  
N/A  
125  
140  
145  
mA  
mA  
mA  
ICC  
Operating  
Current*  
Industrial  
Military  
* VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH.  
DATA RETEꢀTIOꢀ CHARACTERISTICS (P4C164L Military Temperature Only)  
Typ* VCC=  
2.0V 3.0V  
Max VCC=  
Sym Parameter  
Test Conditions  
Min  
Unit  
2.0V  
3.0V  
VDR VCC for Data Retention  
ICCDR Data Retention Current  
2.0  
V
10  
15  
200  
300  
µA  
ns  
ns  
CE1 ≥ VCC -0.2V or  
tCDR Chip Deselect to Data Retention Time CE2 ≤ 0.2V, VIN ≥ VCC -0.2V  
0
or VIN ≤ 0.2V  
†
§
tR  
Operation Recovery Time  
tRC  
* TA = +25°C  
§ tRC = Read Cycle Time  
† This Parameter is guaranteed but not tested  
DATA RETEꢀTIOꢀ WAVEFORM  
Document # SRAM115 REV G  
Page 3  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
AC ELECTRICAL CHARACTERISTICS—READ CYCLE  
(VCC = 5V ± 10%, All Temperature Ranges)(2)  
Sym Parameter  
tRC Read Cycle Time  
tAA  
-8  
-10  
-12  
-15  
-20  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
8
10  
12  
15  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
8
8
10  
10  
12  
12  
15  
15  
20  
20  
tAC  
tOH  
tLZ  
Chip Enable Access Time  
Output Hold from Address Change  
Chip Enable to Output in Low Z  
Chip Disable to Output in High Z  
Output Enable Low to Data Valid  
Output Enable Low to Low Z  
Output Enable High to High Z  
3
2
3
2
3
2
3
2
3
2
tHZ  
5
5
6
6
7
7
8
9
8
tOE  
tOLZ  
tOHZ  
10  
2
0
2
0
2
0
2
0
2
0
5
6
7
9
9
tPU  
tPD  
Chip Enable to Power Up Time  
Chip Disable to Power Down Time  
8
10  
12  
15  
20  
-25  
-35  
-45  
-70  
-100  
Sym Parameter  
tRC Read Cycle Time  
tAA  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
25  
35  
45  
70  
100  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
25  
25  
35  
35  
45  
45  
70  
70  
100  
100  
tAC  
tOH  
tLZ  
Chip Enable Access Time  
Output Hold from Address Change  
Chip Enable to Output in Low Z  
Chip Disable to Output in High Z  
Output Enable Low to Data Valid  
Output Enable Low to Low Z  
Output Enable High to High Z  
3
2
3
2
3
2
3
2
3
2
tHZ  
10  
13  
15  
18  
20  
20  
35  
35  
45  
45  
tOE  
tOLZ  
tOHZ  
2
0
2
0
2
0
2
0
2
0
12  
20  
15  
20  
20  
25  
35  
35  
45  
45  
tPU  
tPD  
Chip Enable to Power Up Time  
Chip Disable to Power Down Time  
Document # SRAM115 REV G  
Page 4  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
TIMIꢀꢁ WAVEFORM OF READ CYCLE ꢀO. 1 (OE COꢀTROLLED)(5)  
TIMIꢀꢁ WAVEFORM OF READ CYCLE ꢀO. 2 (ADDRESS COꢀTROLLED)(5,6)  
TIMIꢀꢁ WAVEFORM OF READ CYCLE ꢀO. 3 (CE1, CE2 COꢀTROLLED)(5,7,10)  
5. WE is HIGH for READ cycle.  
9. Read Cycle Time is measured from the last valid address to the first  
6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.  
7. ADDRESS must be valid prior to, or coincident with CE1 transition LOW  
and CE2 transition HIGH.  
transitioning address.  
10. Transitions caused by a chip enable control have similar delays ir-  
respective of whether CE1 or CE2 causes them.  
8. Transition is measured ± 200 mV from steady state voltage prior to  
change,withloadingasspecifiedinFigure1. Thisparameterissampled  
and not 100% tested.  
Document # SRAM115 REV G  
Page 5  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
AC CHARACTERISTICS—WRITE CYCLE  
(VCC = 5V ± 10%, All Temperature Ranges)(2)  
-8  
-10  
-12  
-15  
-20  
Sym Parameter  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Write Cycle Time  
tWC  
tCW  
tAW  
tAS  
8
10  
12  
15  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Enable Time to End of Write  
Address Valid to End of Write  
Address Setup Time  
6
7
0
7
0
6
0
7
8
0
8
0
7
0
8
10  
0
12  
12  
0
15  
15  
0
Write Pulse Width  
tWP  
tAH  
tDW  
tDH  
tWZ  
tOW  
9
12  
0
15  
0
Address Hold Time  
0
Data Valid to End of Write  
Data Hold Time  
8
9
11  
0
0
0
Write Enable to Output in High Z  
Output Active from End of Write  
6
7
7
7
8
3
3
3
3
3
-25  
-35  
-45  
-70  
-100  
Sym Parameter  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Write Cycle Time  
tWC  
tCW  
tAW  
tAS  
25  
35  
45  
70  
100  
70  
70  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Enable Time to End of Write  
Address Valid to End of Write  
Address Setup Time  
18  
18  
0
25  
25  
0
33  
33  
0
50  
50  
0
Write Pulse Width  
tWP  
tAH  
tDW  
tDH  
tWZ  
tOW  
18  
0
20  
0
25  
0
40  
0
50  
0
Address Hold Time  
Data Valid to End of Write  
Data Hold Time  
13  
0
15  
0
20  
0
30  
0
40  
0
Write Enable to Output in High Z  
Output Active from End of Write  
10  
14  
18  
30  
40  
3
3
3
3
3
Document # SRAM115 REV G  
Page 6  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
TIMIꢀꢁ WAVEFORM OF WRITE CYCLE ꢀO. 1 (WE COꢀTROLLED)(11)  
TIMIꢀꢁ WAVEFORM OF WRITE CYCLE ꢀO. 2 (CE COꢀTROLLED)(11)  
Notes:  
11. CE and WE must be LOW, and CE2 HIGH for WRITE cycle.  
12. OE is LOW for this WRITE cycle to show tWZ and tOW  
14. Write Cycle Time is measured from the last valid address to the first  
.
transitioning address.  
13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH,  
the output remains in a high impedance state  
Document # SRAM115 REV G  
Page 7  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
AC TEST COꢀDITIOꢀS  
Input Pulse Levels  
TRUTH TABLE  
GND to 3.0V  
Mode  
CE1 CE2 OE WE I/O  
Power  
Standby  
Standby  
Active  
Input Rise and Fall Times  
Input Timing Reference Level  
Output Timing Reference Level  
Output Load  
3ns  
Standby  
Standby  
DOUT Disabled  
Read  
H
ꢀ
L
L
L
ꢀ
L
ꢀ
ꢀ
H
L
ꢀ
ꢀ
H
H
L
High Z  
High Z  
High Z  
DOUT  
1.5V  
1.5V  
H
H
H
See Figures 1 and 2  
Active  
Write  
ꢀ
High Z  
Active  
Figure 1. Output Load  
Figure 2. Thevenin Equivalent  
* including scope and test fixture.  
ꢀote:  
Because of the high speed of the P4C164/L, care must be taken when  
testing this device; an inadequate setup can cause a normal function-  
ing part to be rejected as faulty. Long high-inductance leads that cause  
supply bounce must be avoided by bringing the VCC and ground planes  
directly up to the contactor fingers. A 0.01 µF high frequency capacitor  
is also required between VCC and ground. To avoid signal reflections,  
proper termination must be used; for example, a 50Ω test environment  
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at  
the comparator input, and a 116Ω resistor must be used in series with  
DOUT to match 166Ω (Thevenin Resistance).  
LCC PIꢀ COꢀFIꢁURATIOꢀS  
LCC (L5)  
"L" - STANDARD PIN-OUT  
LCC (L5)  
"LS" - SPECIAL PIN-OUT  
LCC (L6)  
Document # SRAM115 REV G  
Page 8  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
ORDERIꢀꢁ IꢀFORMATIOꢀ  
Document # SRAM115 REV G  
Page 9  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
SIDEBRAZED DUAL Iꢀ-LIꢀE PACKAꢁE (300 mils)  
Pkg #  
C5  
# Pins  
28 (300 mil)  
Symbol  
Min  
-
Max  
A
b
0.225  
0.026  
0.065  
0.018  
1.485  
0.310  
0.014  
0.045  
0.008  
-
b2  
C
D
E
0.240  
eA  
e
0.300 BSC  
0.100 BSC  
L
0.125  
0.200  
Q
0.015  
0.005  
0.005  
0.070  
S1  
S2  
-
-
SIDEBRAZED DUAL Iꢀ-LIꢀE PACKAꢁE (600 mils)  
Pkg #  
C5-1  
# Pins  
28 (600 mil)  
Symbol  
Min  
-
Max  
A
b
0.232  
0.026  
0.065  
0.018  
1.490  
0.610  
0.014  
0.045  
0.008  
-
b2  
C
D
E
0.500  
eA  
e
0.600 BSC  
0.100 BSC  
L
0.125  
0.200  
Q
0.015  
0.005  
0.005  
0.060  
S1  
S2  
-
-
Document # SRAM115 REV G  
Page 10  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
CERDIP DUAL Iꢀ-LIꢀE PACKAꢁE  
Pkg #  
D5-1  
# Pins  
28 (600 mil)  
Symbol  
Min  
-
Max  
0.232  
0.026  
0.065  
0.018  
1.490  
0.610  
A
b
0.014  
0.045  
0.008  
-
b2  
C
D
E
0.500  
eA  
e
0.600 BSC  
0.100 BSC  
L
0.125  
0.200  
0.060  
-
Q
S1  
α
0.015  
0.005  
0°  
15°  
CERDIP DUAL Iꢀ-LIꢀE PACKAꢁE  
Pkg #  
D5-2  
# Pins  
28 (300 mil)  
Symbol  
Min  
-
Max  
0.225  
0.026  
0.065  
0.018  
1.485  
0.310  
A
b
0.014  
0.045  
0.008  
-
b2  
C
D
E
0.240  
eA  
e
0.300 BSC  
0.100 BSC  
L
0.125  
0.200  
0.060  
-
Q
S1  
α
0.015  
0.005  
0°  
15°  
Document # SRAM115 REV G  
Page 11  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
CERPACK CERAMIC FLAT PACKAꢁE  
Pkg #  
F4  
# Pins  
28  
Symbol  
Min  
0.060  
0.015  
0.004  
-
Max  
A
b
0.090  
0.022  
0.009  
0.730  
0.380  
c
D
E
e
0.330  
0.050 BSC  
k
0.005  
0.018  
0.370  
0.045  
0.085  
-
L
0.250  
0.026  
-
Q
S
S1  
0.005  
SOJ SMALL OUTLIꢀE IC PACKAꢁE  
Pkg #  
J5  
# Pins  
28 (300 mil)  
Symbol  
Min  
Max  
0.148  
-
A
A1  
b
0.120  
0.078  
0.014  
0.007  
0.700  
0.020  
0.011  
0.730  
C
D
e
0.050 BSC  
E
0.292  
0.335  
0.262  
0.025  
0.300  
0.347  
0.272  
-
E1  
E2  
Q
Document # SRAM115 REV G  
Page 12  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
RECTAꢀꢁULAR LEADLESS CHIP CARRIER  
Pkg #  
# Pins  
Symbol  
A
L5  
28  
Min  
Max  
0.060  
0.050  
0.022  
0.342  
0.075  
0.065  
0.028  
0.358  
A1  
B1  
D
D1  
D2  
D3  
E
0.200 BSC  
0.100 BSC  
-
0.358  
0.560  
0.540  
E1  
E2  
E3  
e
0.400 BSC  
0.200 BSC  
-
0.558  
0.050 BSC  
0.040 REF  
0.020 REF  
h
j
L
0.045  
0.055  
0.055  
0.095  
L1  
0.045  
0.075  
L2  
ND  
NE  
5
9
RECTAꢀꢁULAR LEADLESS CHIP CARRIER  
Pkg #  
# Pins  
Symbol  
A
L6  
32  
Min  
Max  
0.060  
0.050  
0.022  
0.442  
0.075  
0.065  
0.028  
0.458  
A1  
B1  
D
D1  
D2  
D3  
E
0.300 BSC  
0.150 BSC  
-
0.458  
0.560  
0.540  
E1  
E2  
E3  
e
0.400 BSC  
0.200 BSC  
-
0.558  
0.050 BSC  
0.040 REF  
0.020 REF  
h
j
L
0.045  
0.055  
0.055  
0.095  
L1  
0.045  
0.075  
L2  
ND  
NE  
7
9
Document # SRAM115 REV G  
Page 13  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
PLASTIC DUAL Iꢀ-LIꢀE PACKAꢁE (300 mils)  
Pkg #  
P5  
# Pins  
28 (300 mil)  
Symbol  
Min  
Max  
0.210  
-
A
A1  
b
-
0.014  
0.045  
0.008  
1.345  
0.270  
0.300  
0.023  
0.070  
0.014  
1.400  
0.300  
0.380  
b2  
C
D
E1  
E
e
0.100 BSC  
eB  
L
-
0.430  
0.150  
15°  
0.115  
0°  
α
PLASTIC DUAL Iꢀ-LIꢀE PACKAꢁE (600 mils)  
Pkg #  
P6  
# Pins  
28 (600 mil)  
Symbol  
Min  
Max  
A
A1  
b
0.090  
0.000  
0.014  
0.015  
0.008  
1.380  
0.485  
0.600  
0.200  
0.070  
0.020  
0.065  
0.012  
1.480  
0.550  
0.625  
b2  
C
D
E1  
E
e
0.100 BSC  
0.600 TYP  
0.100 0.200  
0° 15°  
eB  
L
α
Document # SRAM115 REV G  
Page 14  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
SOIC/SOP SMALL OUTLIꢀE IC PACKAꢁE (Sꢀ)  
Pkg #  
S6  
# Pins  
28 (300 mil)  
Symbol  
Min  
Max  
0.110  
0.010  
0.020  
0.012  
0.716  
A
A1  
B
0.090  
0.003  
0.012  
0.004  
0.700  
C
D
e
0.050 BSC  
E
0.290  
0.465  
0.016  
0°  
0.300  
0.485  
0.050  
9°  
H
L
α
Document # SRAM115 REV G  
Page 15  
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM  
REVISIOꢀS  
DOCUMEꢀT ꢀUMBER SRAM115  
DOCUMEꢀT TITLE  
P4C164 ULTRA HIGH SPEED 8Kx8 STATIC CMOS RAM  
REV ISSUE DATE  
ORIꢁIꢀATOR DESCRIPTIOꢀ OF CHAꢀꢁE  
OR  
A
1997  
DAB  
JDB  
JDB  
JDB  
JDB  
JDB  
JDB  
JDB  
New Data Sheet  
Oct-2005  
Jun-2006  
Aug-2006  
Aug-2006  
Aug-2006  
Jun-2007  
Sep-2010  
Changed logo to Pyramid  
Added 28-pin ceramic DIP  
B
C
D
E
Added Lead-Free designation  
Added "LS" - Special Pin-Out  
Updated SOJ package information  
Corrected SOP package details  
F
G
Added P4C164L for non-military temp. Format update.  
Document # SRAM115 REV G  
Page 16  

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