HYS64T128020EDL-3S-C2 [QIMONDA]

DDR DRAM Module, 128MX64, 0.45ns, CMOS, GREEN, SODIMM-200;


型号：	HYS64T128020EDL-3S-C2
厂家：	QIMONDA AG
描述：	DDR DRAM Module, 128MX64, 0.45ns, CMOS, GREEN, SODIMM-200 动态存储器双倍数据速率
文件：	总39页 (文件大小：903K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

July 2008

HYS64T128020EDL–[25F/2.5/3S](–)C2

HYS64T256020EDL–[25F/2.5/3S](–)C2

200-Pin SO-DIMM DDR2 SDRAM Modules

SO-DIMM SDRAM

EU RoHS Compliant

Internet Data Sheet

Rev. 1.00

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

HYS64T128020EDL–[25F/2.5/3S](–)C2, HYS64T256020EDL–[25F/2.5/3S](–)C2

Revision History: 2008-07, Rev. 1.00

Page

Subjects (major changes since last revision)

Removed product type HYS64T[128/256]020-EDL-3-C2 and adapted to internet edition.

All

Previous Revision: Rev 0.60, 2008-06

30-39 SPD codes updated.

Previous Revision: Rev 0.52, 2007-12

26, 27 IDD updated.

Previous Revision: Rev 0.51, 2007-12

30-39 SPD codes updated.

Previous Revision: Rev 0.50, 2007-10

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

techdoc@qimonda.com

qag_techdoc_A4, 4.20, 2008-01-25

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Overview

This chapter gives an overview of the 200-pin Small-Outline DDR2 SDRAM modules product family and describes its main

characteristics.

1.1

Features

•

200-Pin PC2-6400 and PC2-5300 DDR2 SDRAM memory

modules.

•

Auto Refresh for temperatures above 85 °C t_REFI= 3.9 μs.

Programmable self refresh rate via EMRS2 setting.

Programmable partial array refresh via EMRS2 settings.

DCC enabling via EMRS2 setting.

Two rank 128M × 64, 256M × 64 module organization, and

64M × 16, 128M × 8 chip organization.

2GB, 1GB Modules built with 1 Gbit DDR2 SDRAMs in

chipsize packages PG-TFBGA-84, PG-TFBGA-60.

Standard Double-Data-Rate-Two Synchronous DRAMs

(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power

supply.

All speed grades faster than DDR2-400 comply with

DDR2-400 timing specifications.

Programmable CAS Latencies (3, 4, 5, 6 and 7), Burst

Length (8 & 4).

All inputs and outputs SSTL_1.8 compatible.

Off-Chip Driver Impedance Adjustment (OCD) and On-Die

Termination (ODT).

•

Serial Presence Detect with E²PROM.

SO-DIMM Dimensions (nominal): 30 mm high, 67.6 mm

wide

•

Based on standard reference layouts Raw Cards 'F' and

'A'.

RoHS compliant products¹⁾.

Auto Refresh (CBR) and Self Refresh.

TABLE 1

Performance Table

QAG Speed Code

–25F

–800D

–2.5

–3S

Unit

Note

DRAM Speed Grade

Module Speed Grade

DDR2

PC2

–800E

–6400E

6–6–6

–667D

–5300D

5–5–5

–6400D

5–5–5

CAS-RCD-RP latencies

t_CK

Max. Clock Frequency

CL3

CL4

CL5

CL6

f_CK3

f_CK4

f_CK5

f_CK6

t_RCD

t_RP

200

266

400

–

200

266

333

400

200

266

333

–

MHz

Min. RAS-CAS-Delay

Min. Row Precharge Time

Min. Row Active Time

Min. Row Cycle Time

12.5

t_RAS

t_RC

57.5

1)2)

Precharge-All (8 banks) command period t_PREA

17.5

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit

www.qimonda.com/green_products .

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

1) This t_PREAvalue is the minimum value at which this chip will be functional.

2) Precharge-All command for an 8 bank device will equal to t_RP+ 1 × t_CKor t_nRP+ 1 × nCK, depending on the speed bin,

where t_nRP= RU{ t_RP/ t_CK(avg)} and t_RPis the value for a single bank precharge.

1.2

Description

The Qimonda HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

module family are Small-Outline DIMM modules “SO-DIMMs”

with 30 mm height based on DDR2 technology. DIMMs are

The memory array is designed with 1 Gbit Double-Data-

Rate-Two (DDR2) Synchronous DRAMs. Decoupling

capacitors are mounted on the PCB board. The DIMMs

feature serial presence detect based on a serial E²PROM

device using the 2-pin I²C protocol. The first 128 bytes are

programmed with configuration data and are write protected;

the second 128 bytes are available to the customer.

available as non-ECC modules

in128M × 64 (1GB),

256M × 64 (2GB) in organization and density, intended for

mounting into 200-pin connector sockets.

TABLE 2

Ordering Information

Product Type¹⁾

Compliance Code²⁾

Description

SDRAM Technology

PC2-6400 (5-5-5)

HYS64T256020EDL-25FC2 2GB 2R×8 PC2–6400S–555–12–F0

HYS64T128020EDL-25FC2 1GB 2R×16 PC2–6400S–555–12–A0

PC2-6400 (6-6-6)

2 Ranks, Non-ECC

1Gbit (×8)

1Gbit (×16)

HYS64T256020EDL-2.5C2 2GB 2R×8 PC2–6400S–666–12–F0

HYS64T128020EDL-2.5C2 1GB 2R×16 PC2–6400S–666–12–A0

PC2-5300 (5-5-5)

2 Ranks, Non-ECC

1Gbit (×8)

1Gbit (×16)

HYS64T256020EDL-3S-C2 2GB 2R×8 PC2–5300S–555–12–F0

HYS64T128020EDL-3S-C2 1GB 2R×16 PC2–5300S–555–12–A0

2 Ranks, Non-ECC

1Gbit (×8)

1Gbit (×16)

1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.

2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400S–555–12–F0" where 6400S

means Small-Outline DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency

=5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the Industry Standard SPD Revision 1.2 and

produced on the Raw Card "F".

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

TABLE 3

Address Format

DIMM

Density

Module

Organization

Memory

Ranks

ECC/

Non-ECC

# of SDRAMs # of row/bank/column

bits

Raw

Card

2GB

1GB

256M × 64

128M × 64

Non-ECC

14/3/10

13/3/10

TABLE 4

Components on Modules

DRAM Organisation

Product Type¹⁾²⁾

DRAM Components¹⁾

DRAM Density

HYS64T256020EDL

HYB18T1G800C2F

HYB18T1G160C2F

1Gbit

128M × 8

64M × 16

HYS64T128020EDL

1) Green Product

2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Pin Configurations

2.1

Pin Configurations

The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The abbreviations

used in columns Pin Type and Buffer Type are explained in Table 6 and Table 7 respectively. The Pin numbering is depicted

in Figure 1

TABLE 5

Pin Configuration of SO-DIMM

Pin No.

Name

Buffer

Function

Type Type

Clock Signals

CK0

CK1

CK0

CK1

SSTL

Clock Signals 1:0, Complement Clock Signals 1:0

The system clock inputs. All address and command lines

are sampled on the cross point of the rising edge of CK and

the falling edge of CK. A Delay Locked Loop (DLL) circuit is

driven from the clock inputs and output timing for read

operations is synchronized to the input clock.

164

166

CKE0

CKE1

SSTL

Clock Enable Rank 1:0

Activates the DDR2 SDRAM CK signal when HIGH and

deactivates the CK signal when LOW. By deactivating the

clocks, CKE LOW initiates the Power Down Mode or the

Self Refresh Mode.

Note: 2 Ranks module

Not Connected

—

Note: 1-rank module

Control Signals

110

115

SSTL

Chip Select Rank 1:0

Enables the associated DDR2 SDRAM command decoder

when LOW and disables the command decoder when

HIGH. When the command decoder is disabled, new

commands are ignored but previous operations continue.

Rank 0 is selected by S0; Rank 1 is selected by S1. Ranks

are also called "Physical banks".2 Ranks module

—

Not Connected

Note: 1-rank module

108

113

RAS

SSTL

Row Address Strobe

When sampled at the cross point of the rising edge of CK,

and falling edge of CK, RAS, CAS and WE define the

operation to be executed by the SDRAM.

CAS

SSTL

Column Address Strobe

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Pin No.

Name

Buffer

Function

Type Type

109

SSTL

Write Enable

Address Signals

107

106

BA0

BA1

SSTL

Bank Address Bus 2:0

Selects which DDR2 SDRAM internal bank of four or eight

is activated.

BA2

SSTL

Bank Address Bus 2

Greater than 512Mb DDR2 SDRAMS

SSTL

Less than 1Gb DDR2 SDRAMS

102

101

100

Address Bus 12:0

During a Bank Activate command cycle, defines the row

address when sampled at the cross-point of the rising edge

of CK and falling edge of CK. During a Read or Write

command cycle, defines the column address when sampled

at the cross point of the rising edge of CK and falling edge

of CK. In addition to the column address, AP is used to

invoke autoprecharge operation at the end of the burst read

or write cycle. If AP is HIGH, autoprecharge is selected and

BA0-BAn defines the bank to be precharged. If AP is LOW,

autoprecharge is disabled. During a Precharge command

cycle, AP is used in conjunction with BA0-BAn to control

which bank(s) to precharge. If AP is HIGH, all banks will be

precharged regardless of the state of BA0-BAn inputs. If AP

is LOW, then BA0-BAn are used to define which bank to

precharge.

105

A10

A11

A12

Address Signal 12

Note: Module based on 256 Mbit or larger dies

Address Signal 13

116

A13

SSTL

—

Note: 1 Gbit based module

Not Connected

Note: Module based on 512 Mbit or smaller dies

Address Signal 14

A14

SSTL

—

Note: 2 Gbit based module

Not Connected

Note: Module based on 1 Gbit or smaller dies

Data Signals

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

I/O

SSTL

Data Bus 63:0

Note: Data Input / Output pins

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Pin No.

Name

Buffer

Function

Type Type

DQ9

I/O

SSTL

Data Bus 63:0

Note: Data Input / Output pins

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

123

125

135

137

124

126

134

136

141

143

151

153

140

142

152

154

157

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Pin No.

Name

Buffer

Function

Type Type

159

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O

SSTL

Data Bus 63:0

Note: Data Input / Output pins

173

175

158

160

174

176

179

181

189

191

180

182

192

194

Data Strobe Signals

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

I/O

SSTL

Data Strobe Bus 7:0 and Complementary Data Strobe

Bus 7:0

The data strobes, associated with one data byte, sourced

with data transfers. In Write mode, the data strobe is

sourced by the controller and is centered in the data

window. In Read mode the data strobe is sourced by the

DDR2 SDRAM and is sent at the leading edge of the data

window. DQS signals are complements, and timing is

relative to the cross-point of respective DQS and DQS. If the

module is to be operated in single ended strobe mode, all

DQS signals must be tied on the system board to V_SSand

DDR2 SDRAM mode registers programmed appropriately.

131

129

148

146

169

167

188

186

Data Mask Signals

DM0

DM1

DM2

DM3

DM4

DM5

DM6

SSTL

Data Mask Bus 7:0

The data write masks, associated with one data byte. In

Write mode, DM operates as a byte mask by allowing input

data to be written if it is LOW but blocks the write operation

if it is HIGH. In Read mode, DM lines have no effect.

130

147

170

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Pin No.

Name

DM7

SCL

Type Type

Buffer

Function

185

SSTL

Data Mask Bus 7:0

EEPROM

197

CMOS Serial Bus Clock

This signal is used to clock data into and out of the SPD

EEPROM and Thermal sensor.

195

SDA

I/O

Serial Bus Data

This is a bidirectional pin use to transfer data into and out of

the SPD EEPROM and Thermal sensor. A resistor must be

connected from SDA to V_DDSPDon the motherboard to act as

a pull-up.

198

200

SA0

SA1

CMOS Serial Address Select Bus 1:0

Address pins used to select the SPD and Thermal sensor

CMOS

base address.

EVENT

The optional EVENT pin is reserved for use to flag critical

module temperature and is used in conjunction with

Thermal Sensor.

Not Connected

Not connected on modules without temperature sensors.

Power Supplies

V_REF

—

I/O Reference Voltage

Reference voltage for the SSTL-18 inputs.

199

V_DDSPDPWR

EEPROM Power Supply

Power supplies for Serial Presence Detect, Thermal Sensor

and ground for the module.

81,82,87,88,95,96,103,104,

111,112,117,118

V_DD

V_SS

PWR

GND

—

Power Supply

Power supplies for core, I/O and ground for the module.

2,3,8,9,12,15,18,21,24,27,28,

33,34,39,40,41,42,47,48,53,

54,59,60,65,66,71,72,77,78,

121,122,127,128,132,133,138,13

9,144,145,149,150,155,156,

161,162,165,168, 171,172,177,

178,183,184,187,190,193,196

Ground Plane

Power supplies for core, I/O, Serial Presence Detect,

Thermal Sensor and ground for the module.

Other pins

114

ODT0

ODT1

SSTL

On-Die Termination Control 1:0

119

On-Die Termination Control 1

Asserts on-die termination for DQ, DM, DQS, and DQS

signals if enabled via the DDR2 SDRAM mode register.

Note: 2 Rank modules

Not Connected

—

Note: 1 Rank modules

69,83,84,120,163

Not connected

Pins not connected on Qimonda SO-DIMMs

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

TABLE 6

Abbreviations for pin Type

Abbreviation

Description

Standard input-only pin. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

I/O

PWR

GND

Ground

Not Connected

TABLE 7

Abbreviations for Buffer Type

Abbreviation

Description

SSTL

Serial Stub Terminated Logic (SSTL_18)

Low Voltage CMOS

LV-CMOS

CMOS

CMOS Levels

Open Drain. The corresponding pin has 2 operational states, active low and tri-state, and

allows multiple devices to share as a wire-OR.

Rev. 1.00, 2008-07

12032007-B13H-E3X1

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Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

FIGURE 1

Pin Configuration SO-DIMM (200 pin)

9ꢀ

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Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Electrical Characteristics

This chapter contains speed grade definition, AC timing parameter and ODT tables.

3.1

Absolute Maximum Ratings

Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

TABLE 8

Absolute Maximum Ratings

Symbol

Parameter

Rating

Min.

Unit

Note

Max.

V_DD

Voltage on V_DDpin relative to V_SS

Voltage on V_DDQpin relative to V_SS

Voltage on V_DDLpin relative to V_SS

Voltage on any pin relative to V_SS

–1.0

–0.5

+2.3

V_DDQ

V_DDL

V_IN, V_OUT

1) When V_DDand V_DDQand V_DDLare less than 500 mV; V_REFmay be equal to or less than 300 mV.

TABLE 9

Environmental Requirements

Parameter

Symbol

Values

Min.

Unit

Note

Max.

Operating temperature (ambient)

Storage Temperature

T_OPR

T_STG

PBar

H_OPR

H_STG

+65

+100

+105

°C

kPa

– 50

+69

Barometric Pressure (operating & storage)

Operating Humidity (relative)

Storage Humidity (without condensation)

1) Storage Temperature is the case surface temperature on the center/top side of the DRAM.

2) Up to 3000 m.

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

TABLE 10

DRAM Component Operating Temperature Range

Symbol

Parameter

Rating

Unit

Note

Min.

Max.

1)2)3)4)

T_CASE

Operating Temperature

°C

1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.

2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case

temperature must be maintained between 0 - 95 °C under all other specification parameters.

3) Above 85 °C the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 μs

4) When operating this product in the 85 °C to 95 °C T_CASEtemperature range, the High Temperature Self Refresh has to be enabled by

setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of I_DD6by approximately 50%

3.2

Operating Conditions

TABLE 11

Supply Voltage Levels and AC / DC Operating Conditions

Parameter

Symbol

Values

Unit

Note

Min.

Typ.

Max.

Device Supply Voltage

Output Supply Voltage

Input Reference Voltage

SPD Supply Voltage

DC Input Logic High

DC Input Logic Low

V_DD

1.7

1.8

1.9

μA

V_DDQ

V_REF

1.7

1.8

1.9

0.49 × V_DDQ

0.5 × V_DDQ

0.51 × V_DDQ

V_DDSPD

V_IH(DC)

V_{IL (DC}

V_IH(AC)

V_{IL (AC}

I_L

1.7

—

3.6

_REF+ 0.125

_DDQ+ 0.3

)

– 0.30

_REF– 0.125

_DDQ+ V_PEAK

_REF–0.200

AC Input Logic High

AC Input Logic Low

_REF+ 0.200

_SSQ– V_PEAK

)

In / Output Leakage Current

– 5

1) Under all conditions, V_DDQmust be less than or equal to V_DD

2) Peak to peak AC noise on V_REFmay not exceed ± 2% V_REF(DC).V_REFis also expected to track noise in V_DDQ

3) Input voltage for any connector pin under test of 0 V ≤ V_IN≤ V_DDQ+ 0.3 V; all other pins at 0 V. Current is per pin

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

3.3

Speed Grade Definitions

TABLE 12

Speed Grade Definition

Speed Grade

DDR2–800D

–25F

DDR2–800E

–2.5

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

Parameter

5–5–5

Min.

6–6–6

t_CK

Symbol

Max.

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Period

@ CL = 3

t_CK

@ CL = 4

@ CL = 5

@ CL = 6

t_CK

3.75

2.5

3.75

t_CK

2.5

Row Active Time

Row Cycle Time

RAS-CAS-Delay

t_RAS

t_RC

t_RCD

t_RP

70k

—

70k

—

57.5

12.5

Row Precharge Time

TABLE 13

Speed Grade Definition

Speed Grade

DDR2–667D

–3S

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

Parameter

5–5–5

Min.

t_CK

Symbol

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Period

@ CL = 3

t_CK

@ CL = 4

@ CL = 5

t_CK

3.75

t_CK

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70k

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode.

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQ

4) The output timing reference voltage level is V_TT.

5) t_RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

3.4

Component AC Timing Parameters

TABLE 14

DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667

Parameter

Symbol DDR2–800

DDR2–667

Unit

Note¹⁾²⁾³

)4)5)6)7)

Min.

Max.

Min.

Max.

DQ output access time from CK / CK t_AC

–400

+400

—

–450

+450

—

CAS to CAS command delay

Average clock high pulse width

Average clock period

t_CCD

t_CH.AVG

t_CK.AVG

nCK

t_CK.AVG

9)10)

11)

0.48

2500

0.52

8000

—

0.48

3000

0.52

8000

—

CKE minimum pulse width ( high and t_CKE

nCK

low pulse width)

9)10)

Average clock low pulse width

t_CL.AVG

t_DAL

0.48

0.52

—

0.48

0.52

—

t_CK.AVG

12)13)

Auto-Precharge write recovery +

precharge time

WR + t_nRP

nCK

Minimum time clocks remain ON after t_DELAY

CKE asynchronously drops LOW

t_IS+ t_{CK .AVG}––

+ t_IH

t_IS+

t_{CK .AVG}+ t_IH

––

14)18)19)

DQ and DM input hold time

t_DH.BASE

125

––

—

175

––

—

DQ and DM input pulse width for each t_DIPW

0.35

t_CK.AVG

input

DQS input high pulse width

DQS output access time from CK / CK t_DQSCK

DQS input low pulse width t_DQSL

t_DQSH

0.35

–350

0.35

—

0.35

–400

0.35

—

t_CK.AVG

+350

—

+400

—

15)

16)

DQS-DQ skew for DQS & associated t_DQSQ

DQ signals

200

240

DQS latching rising transition to

associated clock edges

t_DQSS

– 0.25

+ 0.25

– 0.25

+ 0.25

t_CK.AVG

17)18)19)

16)

DQ and DM input setup time

t_DS.BASE

––

—

100

0.2

––

—

DQS falling edge hold time from CK t_DSH

DQS falling edge to CK setup time t_DSS

0.2

t_CK.AVG

16)

0.2

34)

Four Activate Window for 1KB page t_FAW

37.5

size products

34)

Four Activate Window for 2KB page t_FAW

size products

—

20)

CK half pulse width

t_HP

Min(t_CH.ABS

t_CL.ABS

Min(t_CH.ABS

t_CL.ABS)

)

8)21)

22)24)

Data-out high-impedance time from t_HZ

CK / CK

—

t_AC.MAX

—

t_AC.MAX

Address and control input hold time t_IH.BASE

250

0.6

—

275

0.6

—

Control & address input pulse width t_IPW

t_CK.AVG

for each input

23)24)

Address and control input setup time t_IS.BASE

175

—

200

—

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Parameter

Symbol DDR2–800

Min.

DDR2–667

Min.

Unit

Note¹⁾²⁾³

)4)5)6)7)

Max.

8)21)

DQ low impedance time from CK/CK t_LZ.DQ

2 × t_AC.MIN

t_AC.MAX

2 × t_AC.MIN

t_AC.MAX

DQS/DQS low-impedance time from t_LZ.DQS

t_AC.MIN

CK / CK

34)

MRS command to ODT update delay t_MOD

—

Mode register set command cycle

time

t_MRD

nCK

34)

OCD drive mode output delay

t_OIT

μs

25)

DQ/DQS output hold time from DQS t_QH

t_HP– t_QHS

—

_HP– t_QHS

—

26)

DQ hold skew factor

t_QHS

t_REFI

—

300

7.8

3.9

—

340

7.8

3.9

—

27)28)

27)29)

30)

Average periodic refresh Interval

—

Auto-Refresh to Active/Auto-Refresh t_RFC

127.5

command period

31)32)

31)33)

34)

Read preamble

Read postamble

t_RPRE

t_RPST

0.9

0.4

7.5

1.1

0.6

—

0.9

0.4

7.5

1.1

0.6

—

t_CK.AVG

Active to active command period for t_RRD

1KB page size products

34)

Active to active command period for t_RRD

2KB page size products

—

Internal Read to Precharge command t_RTP

7.5

delay

Write preamble

t_WPRE

t_WPST

t_WR

0.35

0.4

—

0.6

—

0.35

0.4

—

0.6

—

t_CK.AVG

Write postamble

Write recovery time

34)

34)35)

Internal write to read command delay t_WTR

7.5

Exit active power down to read

command

t_XARD

t_XARDS

t_XP

nCK

Exit active power down to read

command (slow exit, lower power)

8 – AL

—

7 – AL

—

nCK

Exit precharge power-down to any

command

34)

Exit self-refresh to a non-read

command

t_XSNR

t_RFC+10

Exit self-refresh to read command

t_XSRD

200

nCK

Write command to DQS associated

clock edges

RL – 1

RL–1

1) V_DDQ= 1.8 V ± 0.1V; V_DD= 1.8 V ± 0.1 V.

2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode.

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

5) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

6) The output timing reference voltage level is V_TT.

7) New units, ‘t_CK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘t_CK.AVG‘ represents the actual t_CK.AVGof the input clock

under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and

DDR2–533, ‘t_CK‘ is used for both concepts. Example: t_XP= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command

may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x t_CK.AVG+ t_{ERR.2PER(Min)}

8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_ERR(6-10per)of the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_{ERR(6-10PER).MIN}= – 272

ps and t_{ERR(6- 10PER).MAX}= + 293 ps, then t_{DQSCK.MIN(DERATED)}= t_DQSCK.MIN– t_{ERR(6-10PER).MAX}= – 400 ps – 293 ps = – 693 ps and

_{DQSCK.MAX(DERATED)}= t_DQSCK.MAX– t_{ERR(6-10PER).MIN}= 400 ps + 272 ps = + 672 ps. Similarly, t_LZ.DQfor DDR2–667 derates to t_{LZ.DQ.MIN(DERATED)}

= - 900 ps – 293 ps = – 1193 ps and t_{LZ.DQ.MAX(DERATED)}= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)

9) Input clock jitter spec parameter. The jitter specified is a random jitter meeting a Gaussian distribution.

10) These parameters are specified per their average values, however it is understood that the relationship between the average timing and

the absolute instantaneous timing holds all the times.

11) t_CKE.MINof 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the

entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during

the time period of t_IS+ 2 x t_CK+ t_IH.

12) DAL = WR + RU{t_RP(ns) / t_CK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For t_RP, if the result

of the division is not already an integer, round up to the next highest integer. t_CKrefers to the application clock period. Example: For

DDR2–533 at t_CK= 3.75 ns with t_WRprogrammed to 4 clocks. t_DAL= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.

13) t_DAL.nCK= WR [nCK] + t_nRP.nCK= WR + RU{t_RP[ps] / t_CK.AVG[ps] }, where WR is the value programmed in the EMR.

14) Input waveform timing t_DHwith differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to

the input signal crossing at the V_IH.DClevel for a falling signal and from the differential data strobe crosspoint to the input signal crossing

at the V_IL.DClevel for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between V_IL.DC.MAXand

_IH.DC.MIN. See Figure 3.

15) t_DQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output

slew rate mismatch between DQS / DQS and associated DQ in any given cycle.

16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.

The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC, etc.), as these are relative to the clock signal

crossing. That is, these parameters should be met whether clock jitter is present or not.

17) Input waveform timing t_DSwith differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the V_IH.AClevel

to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V_IL.AClevel to the differential data strobe

crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between V_il(DC)MAXand V_ih(DC)MIN. See

Figure 3.

18) If t_DSor t_DHis violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.

19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal

((L/U/R)DQS / DQS) crossing.

20) t_HPis the minimum of the absolute half period of the actual input clock. t_HPis an input parameter but not an input specification parameter.

It is used in conjunction with t_QHSto derive the DRAM output timing t_QH. The value to be used for t_QHcalculation is determined by the

following equation; t_HP= MIN (t_CH.ABS, t_CL.ABS), where, t_CH.ABSis the minimum of the actual instantaneous clock high time; t_CL.ABSis the

minimum of the actual instantaneous clock low time.

21) t_HZand t_LZtransitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level

which specifies when the device output is no longer driving (t_HZ), or begins driving (t_LZ) .

22) input waveform timing is referenced from the input signal crossing at the V_IL.DClevel for a rising signal and V_IH.DCfor a falling signal applied

to the device under test. See Figure 4.

23) Input waveform timing is referenced from the input signal crossing at the V_IH.AClevel for a rising signal and V_IL.ACfor a falling signal applied

to the device under test. See Figure 4.

24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to

its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC

etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should

be met whether clock jitter is present or not.

25) t_QH= t_HP– t_QHS, where: t_HPis the minimum of the absolute half period of the actual input clock; and t_QHSis the specification value under

the max column. {The less half-pulse width distortion present, the larger the t_QHvalue is; and the larger the valid data eye will be.}

Examples: 1) If the system provides t_HPof 1315 ps into a DDR2–667 SDRAM, the DRAM provides t_QHof 975 ps minimum. 2) If the system

provides t_HPof 1420 ps into a DDR2–667 SDRAM, the DRAM provides t_QHof 1080 ps minimum.

26) t_QHSaccounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual t_HPat the input is

transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next

transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation

of the output drivers.

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

27) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C

and 95 °C.

28) 0 °C≤ T_CASE≤ 85 °C.

29) 85 °C < T_CASE≤ 95 °C.

30) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between

any Refresh command and the next Refresh command is 9 x t_REFI

31) t_RPSTend point and t_RPREbegin point are not referenced to a specific voltage level but specify when the device output is no longer driving

(t_RPST), or begins driving (t_RPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (t_RPST), or begins

driving (t_RPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the

calculation is consistent.

32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.PERof the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.PER.MIN= – 72 ps

and t_JIT.PER.MAX= + 93 ps, then t_{RPRE.MIN(DERATED)}= t_RPRE.MIN+ t_JIT.PER.MIN= 0.9 x t_CK.AVG– 72 ps = + 2178 ps and t_{RPRE.MAX(DERATED)}= t_RPRE.MAX

+ t_JIT.PER.MAX= 1.1 x t_CK.AVG+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).

33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.DUTYof the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.DUTY.MIN= – 72 ps

and t_JIT.DUTY.MAX= + 93 ps, then t_{RPST.MIN(DERATED)}= t_RPST.MIN+ t_JIT.DUTY.MIN= 0.4 x t_CK.AVG– 72 ps = + 928 ps and t_{RPST.MAX(DERATED)}= t_RPST.MAX

+ t_JIT.DUTY.MAX= 0.6 x t_CK.AVG+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).

34) For these parameters, the DDR2 SDRAM device is characterized and verified to support t_nPARAM= RU{t_PARAM/ t_CK.AVG}, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support t_nRP= RU{t_RP/ t_CK.AVG}, which is in

clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which t_RP= 15 ns, the device will support

_nRP= RU{t_RP/ t_CK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at

Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.

35) t_WTRis at lease two clocks (2 x t_CK) independent of operation frequency.

FIGURE 2

Method for Calculating Transitions and Endpoint

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Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

FIGURE 3

Differential Input Waveform Timing - t_DSand t_DH

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Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

3.5

ODT AC Electrical Characteristics

This chapter describes the ODT AC electrical characteristics.

TABLE 15

ODT AC Characteristics and Operating Conditions for DDR2-667 , DDR2-800

Symbol

Parameter / Condition

Values

Unit

Note

Min.

Max.

t_AOND

t_AON

ODT turn-on delay

n_CK

1)2)

ODT turn-on

t_AC.MIN

t_AC.MAX+ 0.7 ns

t_AONPD

t_AOFD

t_AOF

ODT turn-on (Power-Down Modes)

ODT turn-off delay

_AC.MIN+ 2 ns

2 t_CK+ t_AC.MAX+ 1 ns

2.5

n_CK

1)3)

ODT turn-off

t_AC.MIN

t_AC.MAX+ 0.6 ns

t_AOFPD

t_ANPD

t_AXPD

ODT turn-off (Power-Down Modes)

ODT to Power Down Mode Entry Latency

ODT Power Down Exit Latency

_AC.MIN+ 2 ns

2.5 t_CK+ t_AC.MAX+ 1 ns ns

—

n_CK

1) New units, “t_CK.AVG” and “n_CK”, are introduced in DDR2-667 and DDR2-800 Unit “t_CK.AVG” represents the actual t_CK.AVGof the input clock

under operation. Unit “n_CK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and

DDR2-533, “t_CK” is used for both concepts. Example: t_XP= 2 [n_CK] means; if Power Down exit is registered at T_m, an Active command may

be registered at T_m+ 2, even if (T_m+ 2 - T_m) is 2 x t_CK.AVG+ t_{ERR.2PER(Min)}

2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when

the ODT resistance is fully on. Both are measured from t_AOND, which is interpreted differently per speed bin. For DDR2-667/800 t_AONDis

2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.

3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.

Both are measured from t_AOFD, which is interpreted differently per speed bin. For DDR2-667/800, if t_CK(avg)= 3 ns is assumed,

_AOFDis 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by

counting the actual input clock edges.

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

3.6

I_DDSpecifications and Conditions

List of tables defining I_DDSpecifications and Conditions.

TABLE 16

_DDMeasurement Conditions

Parameter

Symbol Note¹⁾²⁾

3)4)5)

Operating Current 0

I_DD0

One bank Active - Precharge; t_CK= t_CK.MIN, t_RC= t_RC.MIN, t_RAS= t_RAS.MIN, CKE is HIGH, CS is HIGH between

valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.

Operating Current 1

I_DD1

One bank Active - Read - Precharge; I_OUT= 0 mA, BL = 4, t_CK= t_CK.MIN, t_RC= t_RC.MIN, t_RAS= t_RAS.MIN

_RCD= t_RCD.MIN, AL = 0, CL = CL_MIN; CKE is HIGH, CS is HIGH between valid commands. Address and

control inputs are SWITCHING, Databus inputs are SWITCHING.

Precharge Standby Current

I_DD2N

All banks idle; CS is HIGH; CKE is HIGH; t_CK= t_CK.MIN; Other control and address inputs are SWITCHING,

Databus inputs are SWITCHING.

Precharge Power-Down Current

Other control and address inputs are STABLE, Data bus inputs are FLOATING.

I_DD2P

I_DD2Q

Precharge Quiet Standby Current

All banks idle; CS is HIGH; CKE is HIGH; t_CK= t_CK.MIN; Other control and address inputs are STABLE,

Data bus inputs are FLOATING.

Active Standby Current

I_DD3N

Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_MIN; t_CK= t_CK.MIN

;

_RAS= t_RAS.MAX, t_RP= t_RP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are

SWITCHING; Data Bus inputs are SWITCHING; I_OUT= 0 mA.

Active Power-Down Current

All banks open; t_CK= t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs

are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);

I_DD3P(0)

I_DD3P(1)

I_DD4R

Active Power-Down Current

All banks open; t_CK= t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs

are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);

Operating Current - Burst Read

All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_MIN; t_CK= t_CKMIN; t_RAS= t_RASMAX

;

_RP= t_RPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data

bus inputs are SWITCHING; I_OUT= 0mA.

Operating Current - Burst Write

I_DD4W

All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL_MIN; t_CK= t_CK.MIN

;

_RAS= t_RAS.MAX., t_RP= t_RP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are

SWITCHING; Data Bus inputs are SWITCHING;

Burst Refresh Current

I_DD5B

_CK= t_CK.MIN., Refresh command every t_RFC= t_RFC.MINinterval, CKE is HIGH, CS is HIGH between valid

commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.

Distributed Refresh Current

I_DD5D

_CK= t_CK.MIN., Refresh command every t_RFC= t_REFIinterval, CKE is LOW and CS is HIGH between valid

commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Parameter

Symbol Note¹⁾²⁾

3)4)5)

Self-Refresh Current

I_DD6

CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data

bus inputs are FLOATING. I_DD6current values are guaranteed up to T_CASEof 85 °C max.

All Bank Interleave Read Current

I_DD7

All banks are being interleaved at minimum t_RCwithout violating t_RRDusing a burst length of 4. Control

and address bus inputs are STABLE during DESELECTS. I_out= 0 mA.

_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ± 0.1 V

_DDspecifications are tested after the device is properly initialized and I_DDparameter are specified with ODT disabled.

3) Definitions for I_DDsee Table 17

4) For two rank modules: All active current measurements in the same I_DDcurrent mode. The other rank is in I_DD2PPrecharge Power-Down

Mode.

5) For details and notes see the relevant Qimonda component data sheet.

_DD1, I_DD4Rand I_DD7current measurements are defined with the outputs disabled (I_OUT= 0 mA). To achieve this on module level the output

buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.

TABLE 17

Definitions for I_DD

Parameter

LOW

Description

V_IN≤ V_IL(ac).MAX, HIGH is defined as V_IN≥ V_IH(ac).MIN

Inputs are stable at a HIGH or LOW level.

Inputs are V_REF= V_DDQ/2

STABLE

FLOATING

SWITCHING

Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control

signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ

signals not including mask or strobes.

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HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

TABLE 18

_DDSpecification for HYS64T[128/256]020EDL–[25F/2.5]C2

Product Type

Unit

Note¹⁾²⁾

Organization

1 GB

2 GB

2 Ranks

(×16)

(×8)

×64

-3S

×64

-3S

-25F

Max.

-2.5

Max.

-25F

Max.

-2.5

Max.

Symbol

Max.

I_DD0

472

512

472

104

456

536

336

160

744

800

964

128

472

512

472

104

456

536

336

160

744

800

964

128

452

488

432

104

416

496

320

160

672

720

948

128

808

768

808

864

208

832

992

640

320

1192

1232

1896

256

112

2024

I_DD1

856

I_DD2N

944

I_DD2P

208

I_DD2Q

I_DD3N

912

1072

672

1072

672

4)5)

4)6)

I_{DD3P_0 (fast)}

I_{DD3P_1 (slow)}

I_DD4R

320

1320

1360

1928

256

1320

1360

1928

256

I_DD4W

I_DD5B

4)7)

I_DD5D

I_DD6

112

I_DD7

1360

1276

2112

1) Calculated values from component data. ODT disabled. I_DD1,

2) I_{DDX (rank)}= Number of components x I_{DDX (component)}

3) I_DDX= I_{DDX (rank)}+ I_{DD2P (rank)}

_DD4Rand I_DD7are defined with the outputs disabled.

4) I_DDX= 2 x I_{DDX (rank)}

5) Fast: MRS(12)=0

6) Slow: MRS(12)=1

7) I_DD5Dand I_DD6values are for 0°C ≤ T_Case≤ 85°C

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

SPD Codes

This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands

for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.

List of SPD Code Tables

•

Table 19 “HYS64T[128/256]020EDL-[25F/2.5]C2” on Page 25

Table 20 “HYS64T[128/256]020EDL-3S-C2” on Page 30

TABLE 19

HYS64T[128/256]020EDL-[25F/2.5]C2

Product Type

Organization

1 GByte

2 GByte

×64

2 Ranks

2 Ranks (×8) 2 Ranks (×8)

(×16)

Label Code

PC2–

6400S–555 6400S–666 6400S–555 6400S–666

JEDEC SPD Revision

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Byte#

Description

Programmed SPD Bytes in EEPROM

Total number of Bytes in EEPROM

Memory Type (DDR2)

Number of Row Addresses

Number of Column Addresses

DIMM Rank and Stacking Information

Data Width

Not used

Interface Voltage Level

t_CK@ CL_MAX(Byte 18) [ns]

t_ACSDRAM @ CL_MAX(Byte 18) [ns]

Error Correction Support (non-ECC, ECC)

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Product Type

Organization

1 GByte

2 GByte

×64

2 Ranks

2 Ranks (×8) 2 Ranks (×8)

(×16)

Label Code

PC2–

6400S–555 6400S–666 6400S–555 6400S–666

JEDEC SPD Revision

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Byte#

Description

Refresh Rate and Type

Primary SDRAM Width

Error Checking SDRAM Width

Not used

Burst Length Supported

Number of Banks on SDRAM Device

Supported CAS Latencies

DIMM Mechanical Characteristics

DIMM Type Information

DIMM Attributes

Component Attributes

_CK@ CL_MAX-1 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-1 [ns]

_CK@ CL_MAX-2 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-2 [ns]

_RP.MIN[ns]

_RRD.MIN[ns]

_RCD.MIN[ns]

_RAS.MIN[ns]

Module Density per Rank

_AS.MINand t_CS.MIN[ns]

_AH.MINand t_CH.MIN[ns]

_DS.MIN[ns]

_DH.MIN[ns]

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Product Type

Organization

1 GByte

2 GByte

×64

2 Ranks

2 Ranks (×8) 2 Ranks (×8)

(×16)

Label Code

PC2–

6400S–555 6400S–666 6400S–555 6400S–666

JEDEC SPD Revision

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Byte#

Description

_WR.MIN[ns]

_WTR.MIN[ns]

_RTP.MIN[ns]

Analysis Characteristics

_RCand t_RFCExtension

_RC.MIN[ns]

_RFC.MIN[ns]

_CK.MAX[ns]

_DQSQ.MAX[ns]

_QHS.MAX[ns]

PLL Relock Time

_CASE.MAXDelta / ΔT_4R4WDelta

Psi(T-A) DRAM

ΔT₀(DT0)

ΔT_2N(DT2N, UDIMM) or ΔT_2Q(DT2Q, RDIMM)

ΔT_2P(DT2P)

ΔT_3N(DT3N)

ΔT_3P.fast(DT3P fast)

ΔT_3P.slow(DT3P slow)

ΔT_4R(DT4R) / ΔT_4R4WSign (DT4R4W)

ΔT_5B(DT5B)

ΔT₇(DT7)

Psi(ca) PLL

Psi(ca) REG

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Product Type

Organization

1 GByte

2 GByte

×64

2 Ranks

2 Ranks (×8) 2 Ranks (×8)

(×16)

Label Code

PC2–

6400S–555 6400S–666 6400S–555 6400S–666

JEDEC SPD Revision

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Byte#

Description

ΔT_PLL(DTPLL)

ΔT_REG(DTREG) / Toggle Rate

SPD Revision

Checksum of Bytes 0-62

Manufacturer’s JEDEC ID Code (1)

Manufacturer’s JEDEC ID Code (2)

Manufacturer’s JEDEC ID Code (3)

Manufacturer’s JEDEC ID Code (4)

Manufacturer’s JEDEC ID Code (5)

Manufacturer’s JEDEC ID Code (6)

Manufacturer’s JEDEC ID Code (7)

Manufacturer’s JEDEC ID Code (8)

Module Manufacturer Location

Product Type, Char 1

Product Type, Char 2

Product Type, Char 3

Product Type, Char 4

Product Type, Char 5

Product Type, Char 6

Product Type, Char 7

Product Type, Char 8

Product Type, Char 9

Product Type, Char 10

Product Type, Char 11

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Product Type

Organization

1 GByte

2 GByte

×64

2 Ranks

2 Ranks (×8) 2 Ranks (×8)

(×16)

Label Code

PC2–

6400S–555 6400S–666 6400S–555 6400S–666

JEDEC SPD Revision

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Byte#

Description

Product Type, Char 12

Product Type, Char 13

Product Type, Char 14

Product Type, Char 15

Product Type, Char 16

Product Type, Char 17

Product Type, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

95 - 98 Module Serial Number

99 - 127 Not used

128 -

255

Blank for customer use

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

TABLE 20

HYS64T[128/256]020EDL-3S-C2

Product Type

Organization

1 GByte

×64

2 GByte

×64

2 Ranks (×16)

2 Ranks (×8)

Label Code

PC2–5300S–555 PC2–5300S–555

JEDEC SPD Revision

Rev. 1.2

HEX

Rev. 1.2

HEX

Byte#

Description

Programmed SPD Bytes in EEPROM

Total number of Bytes in EEPROM

Memory Type (DDR2)

Number of Row Addresses

Number of Column Addresses

DIMM Rank and Stacking Information

Data Width

Not used

Interface Voltage Level

t_CK@ CL_MAX(Byte 18) [ns]

t_ACSDRAM @ CL_MAX(Byte 18) [ns]

Error Correction Support (non-ECC, ECC)

Refresh Rate and Type

Primary SDRAM Width

Error Checking SDRAM Width

Not used

Burst Length Supported

Number of Banks on SDRAM Device

Supported CAS Latencies

DIMM Mechanical Characteristics

DIMM Type Information

DIMM Attributes

Component Attributes

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Product Type

Organization

1 GByte

×64

2 GByte

×64

2 Ranks (×16)

2 Ranks (×8)

Label Code

PC2–5300S–555 PC2–5300S–555

JEDEC SPD Revision

Rev. 1.2

HEX

Rev. 1.2

HEX

Byte#

Description

_CK@ CL_MAX-1 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-1 [ns]

_CK@ CL_MAX-2 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-2 [ns]

_RP.MIN[ns]

_RRD.MIN[ns]

_RCD.MIN[ns]

_RAS.MIN[ns]

Module Density per Rank

_AS.MINand t_CS.MIN[ns]

_AH.MINand t_CH.MIN[ns]

_DS.MIN[ns]

_DH.MIN[ns]

_WR.MIN[ns]

_WTR.MIN[ns]

_RTP.MIN[ns]

Analysis Characteristics

_RCand t_RFCExtension

_RC.MIN[ns]

_RFC.MIN[ns]

_CK.MAX[ns]

_DQSQ.MAX[ns]

_QHS.MAX[ns]

PLL Relock Time

_CASE.MAXDelta / ΔT_4R4WDelta

Psi(T-A) DRAM

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Product Type

Organization

1 GByte

×64

2 GByte

×64

2 Ranks (×16)

2 Ranks (×8)

Label Code

PC2–5300S–555 PC2–5300S–555

JEDEC SPD Revision

Rev. 1.2

HEX

Rev. 1.2

HEX

Byte#

Description

ΔT₀(DT0)

ΔT_2N(DT2N, UDIMM) or ΔT_2Q(DT2Q, RDIMM)

ΔT_2P(DT2P)

ΔT_3N(DT3N)

ΔT_3P.fast(DT3P fast)

ΔT_3P.slow(DT3P slow)

ΔT_4R(DT4R) / ΔT_4R4WSign (DT4R4W)

ΔT_5B(DT5B)

ΔT₇(DT7)

Psi(ca) PLL

Psi(ca) REG

ΔT_PLL(DTPLL)

ΔT_REG(DTREG) / Toggle Rate

SPD Revision

Checksum of Bytes 0-62

Manufacturer’s JEDEC ID Code (1)

Manufacturer’s JEDEC ID Code (2)

Manufacturer’s JEDEC ID Code (3)

Manufacturer’s JEDEC ID Code (4)

Manufacturer’s JEDEC ID Code (5)

Manufacturer’s JEDEC ID Code (6)

Manufacturer’s JEDEC ID Code (7)

Manufacturer’s JEDEC ID Code (8)

Module Manufacturer Location

Product Type, Char 1

Product Type, Char 2

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Product Type

Organization

1 GByte

×64

2 GByte

×64

2 Ranks (×16)

2 Ranks (×8)

Label Code

PC2–5300S–555 PC2–5300S–555

JEDEC SPD Revision

Rev. 1.2

HEX

Rev. 1.2

HEX

Byte#

Description

Product Type, Char 3

Product Type, Char 4

Product Type, Char 5

Product Type, Char 6

Product Type, Char 7

Product Type, Char 8

Product Type, Char 9

Product Type, Char 10

Product Type, Char 11

Product Type, Char 12

Product Type, Char 13

Product Type, Char 14

Product Type, Char 15

Product Type, Char 16

Product Type, Char 17

Product Type, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

Module Serial Number

Not used

95 - 98

99 - 127

128 - 255 Blank for customer use

Rev. 1.00, 2008-07

12032007-B13H-E3X1

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Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Package Outlines

FIGURE 5

Package Outline L-DIM-200-31 Raw Card A

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Notes

1. Thermal Sensor (Optional)

2. SPD or Combidevice (if used then no Thermal Sensor needed)

Rev. 1.00, 2008-07

12032007-B13H-E3X1

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Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

FIGURE 6

Package Outline L-DIM-200-34 Raw Card F

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Notes

1. SPD or Combidevice(if used then no Thermal Sensor needed).

2. Thermal Sensor (Optional)

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Product Type Nomenclature

Qimonda’s nomenclature uses simple coding combined with

some proprietary coding. Table 21 provides examples for

module and component product type number as well as the

field number. The detailed field description together with

possible values and coding explanation is listed for modules

in Table 22 and for components in Table 23.

TABLE 21

Nomenclature Fields and Examples

Example for

Field Number

Micro-DIMM

DDR2 DRAM

HYS

HYB

64/128

–5

–A

512/1G 16

TABLE 22

DDR2 DIMM Nomenclature

Field

Description

Values

Coding

Qimonda Module Prefix

Module Data Width [bit]

HYS

Constant

Non-ECC

ECC

DRAM Technology

DDR2

Memory Density per I/O [Mbit];

Module Density¹⁾

256 MByte

512 MByte

1 GByte

2 GByte

4 GByte

128

256

512

0 .. 9

0, 2, 4

0 .. 9

A .. Z

Raw Card Generation

Number of Module Ranks

Product Variations

Look up table

1, 2, 4

Look up table

SO-DIMM

Package, Lead-Free Status

Module Type

Micro-DIMM

Registered

Unbuffered

Fully Buffered

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Field

Description

Values

Coding

Speed Grade

–19F

–1.9

–25F

–2.5

–3

PC2–8500 6–6–6

PC2–8500 7–7–7

PC2–6400 5–5–5

PC2–6400 6–6–6

PC2–5300 4–4–4

PC2–5300 5–5–5

PC2–4200 4–4–4

PC2–3200 3–3–3

First

–3S

–3.7

–5

Die Revision

–A

–B

Second

1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall

module memory density in MBytes as listed in column “Coding”.

TABLE 23

DDR2 DRAM Nomenclature

Field

Description

Values

Coding

Qimonda Component Prefix

Interface Voltage [V]

HYB

Constant

SSTL_18

DRAM Technology

DDR2

Component Density [Mbit]

256

512

256 Mbit

512 Mbit

1 Gbit

2 Gbit

5+6

Number of I/Os

×4

×8

×16

Product Variations

Die Revision

0 .. 9

Look up table

First

Second

Package, Lead-Free Status

Speed Grade

FBGA, lead-containing

FBGA, lead-free

PC2–8500 6–6–6

PC2–8500 7–7–7

PC2–6400 5–5–5

PC2–6400 6–6–6

PC2–5300 4–4–4

PC2–5300 5–5–5

PC2–4200 4–4–4

PC2–3200 3–3–3

–19F

–1.9

–25F

–2.5

–3

–3S

–3.7

–5

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2

SO-DIMM DDR2 SDRAM Module

Contents

1.1

1.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1

Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

I_DDSpecifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1

3.2

3.3

3.4

3.5

3.6

SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Rev. 1.00, 2008-07

12032007-B13H-E3X1

Internet Data Sheet

Edition 2008-07

Published by Qimonda AG

Gustav-Heinemann-Ring 212

D-81739 München, Germany

Legal Disclaimer

THE INFORMATION GIVEN IN THIS INTERNET DATA SHEET SHALL IN NO EVENT BE REGARDED AS A GUARANTEE

OF CONDITIONS OR CHARACTERISTICS. WITH RESPECT TO ANY EXAMPLES OR HINTS GIVEN HEREIN, ANY

TYPICAL VALUES STATED HEREIN AND/OR ANY INFORMATION REGARDING THE APPLICATION OF THE DEVICE,

QIMONDA HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND, INCLUDING WITHOUT

LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please

contact your nearest Qimonda Office.

Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a

failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect

the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human

body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health

of the user or other persons may be endangered.

www.qimonda.com

HYS64T128020EDL-3S-C2 [QIMONDA]

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