HYS72D64320 概述
184-Pin Registered Double Data Rate SDRAM Module 184引脚均录得双数据速率SDRAM模块
HYS72D64320 数据手册
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PDF下载March 2007
HYS72D32300[G/H]BR–[5/6/7]–C
HYS72D64300[G/H]BR–[5/6/7]–C
HYS72D64320[G/H]BR–[5/6]–C
HYS72D128320[G/H]BR–[6/7]–C
184-Pin Registered Double Data Rate SDRAM Module
Reg DIMM
DDR SDRAM
Internet Data Sheet
Rev. 1.32
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
HYS72D32300[G/H]BR–[5/6/7]–C, HYS72D64300[G/H]BR–[5/6/7]–C, HYS72D64320[G/H]BR–[5/6]–C,
HYS72D128320[G/H]BR–[6/7]–C
Revision History: Rev. 1.32, 2007-03
Page
All
Subjects (major changes since last revision)
Adapted internet edition
Table updated
6
Previous Revision: Rev. 1.31, 2006-09
All Qimonda update
Previous Revision: Rev. 1.3, 2005-11
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03292006-Q22P-G7TH
2
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
1
Overview
This chapter gives an overview of the 184-pin Registered Double Data Rate DDR2 SDRAM Modules with parity bit product
family and describes its main characteristics.
1.1
Features
•
184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM
Module for “1U” PC, Workstation and Server main memory
applications
One rank 32M × 72 and 64M × 72 and two ranks 64M × 72
and 128M × 72 organization
JEDEC standard Double Data Rate Synchronous DRAMs
(DDR SDRAM) with a single + 2.5 V (± 0.2 V) power
supply and + 2.6 V (± 0.1 V) power supply for DDR400
Built with 256-Mbit DDR SDRAMs in P--TFBGA-60-1
packages
•
•
•
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Re-drive for all input signals using register and PLL
devices.
•
•
•
•
Serial Presence Detect with E2PROM
Low Profile Modules form factor: 133.35 mm × 28.58 mm
× 4.00 mm / 2.64 mm and for 1GB 133.35 mm × 30.48 mm
(1.2”)× 4.00 mm
•
•
•
•
JEDEC standard reference layout for one rank 256 MB,
512 MB and two ranks 512 MB, 1 GB: PC 2700 and
PC 3200 Registered DIMM Raw Cards A,B,C,D
Gold plated contacts
Programmable CAS Latency, Burst Length, and Wrap
Sequence (Sequential & Interleave)
TABLE 1
Performance
Part Number Speed Code
-5
–6
-7
Unit
Speed Grade Component
Module
DDR400B
PC3200-3033
200
DDR333B
PC2700–2533
166
DDR266A
—
PC2100-2033
—
max. Clock
Frequency
@CL3
@CL2.5
@CL2
fCK3
—
MHz
MHz
MHz
fCK2.5
fCK2
166
166
143
133
133
133
1.2
Description
The HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C and devices and a PLL for the clock distribution. This reduces
HYS72D64320GBR–5–C are low profile versions of the
standard Registered DIMM modules suitable for 1U Server
Applications. The Low Profile DIMM versions are available as
32M × 72 (256 MB), 64M × 72 (512 MB), 128M × 72 (1 GB)
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. A variety of decoupling capacitors are
mounted on the PC board. The DIMMs feature serial
presence detect based on a serial E2PROM device using the
2-pin I2C protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer.
The memory array is designed with Double Data Rate
Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register
Rev. 1.32, 2007-03
3
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 2
Ordering Information for Lead-Containing Products
Product Type
Compliance Code
Description
SDRAM
Technology
PC3200 (CL = 3.0)
HYS72D32300GBR–5–C
HYS72D64300GBR–5–C
HYS72D64320GBR–5–C
PC2700 (CL = 2.5)
PC3200R–30330–A0
PC3200R–30330–C0
PC3200R–30330–B0
1 Rank 256 MB Registered DIMM ECC
1 Rank 512 MB Registered DIMM ECC
2 Ranks 512 MB Registered DIMM ECC
256 Mbit (×8)
256 Mbit (×4)
256 Mbit (×8)
HYS72D32300GBR–6–C
HYS72D64300GBR–6–C
HYS72D64320GBR–6–C
HYS72D128320GBR–6–C
PC2100 (CL = 2.0)
PC2700R–25330–A0
PC2700R–25330–C0
PC2700R–25330–B0
PC2700R–25330–D0
1 Rank 256 MB Registered DIMM ECC
1 Rank 512 MB Registered DIMM ECC
2 Ranks 512 MB Registered DIMM ECC
2 Ranks 1 GB Registered DIMM ECC
256 Mbit (×8)
256 Mbit (×4)
256 Mbit (×8)
256 Mbit (×4)
HYS72D32300GBR–7–C
HYS72D64300GBR–7–C
HYS72D128320GBR–7–C
PC2100R–20330–A0
PC2100R–20330–C0
PC2100R–20330–D0
1 Rank 256 MB Registered DIMM ECC
1 Rank 512 MB Registered DIMM ECC
2 Ranks 1 GB Registered DIMM ECC
256 Mbit (×8)
256 Mbit (×4)
256 Mbit (×4)
Rev. 1.32, 2007-03
4
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 3
Ordering Information for Lead-Free (RoHS Compliant) Products
Product Type 1)
Compliance Code2) Description
SDRAM
Note3)
Technology
PC3200 (CL = 3.0)
HYS72D32300HBR–5–C
HYS72D64300HBR–5–C
HYS72D64320HBR–5–C
PC2700 (CL = 2.5)
PC3200R–30330–A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (×8)
PC3200R–30330–C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (×4)
PC3200R–30330–B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D32300HBR–6–C
HYS72D64300HBR–6–C
HYS72D64320HBR–6–C
PC2700R–25330–A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (×8)
PC2700R–25330–C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (×4)
PC2700R–25330–B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D128320HBR–6–C PC2700R–25330–D0 2 Ranks 1 GB Registered DIMM ECC
256 Mbit (×4)
PC2100 (CL = 2.0)
HYS72D32300HBR–7–C
HYS72D64300HBR–7–C
PC2100R–20330–A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (×8)
PC2100R–20330–C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (×4)
256 Mbit (×4)
HYS72D128320HBR–7–C PC2100R–20330–D0 2 Ranks 1 GB Registered DIMM ECC
1) All product types end with a place code designating the silicon-die revision. Reference information available on request.
Example: HYS72D128300GBR-5-B, indicating Rev.B die are used for SDRAM components.
2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC2100R”), the latencies (for example
“20330” means CAS latency of 2.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), JEDEC
SPD code definition version 0, and the Raw Card used for this module.
3) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.32, 2007-03
5
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
2
Pin Configuration
The pin configuration of the Registered DDR SDRAM DIMM
is listed by function in Table 4 (184 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 5
and Table 6 respectively. The pin numbering is depicted in
Figure 1.
Pin Name
#
Pin
Type Type
Buffer Function
125 A6
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Bus 11:0
29
122 A8
27 A9
A7
TABLE 4
Pin Configuration of RDIMM
141 A10
AP
Pin Name
#
Pin
Type Type
Buffer Function
118 A11
115 A12
Clock Signals
137 CK0
Address Signal 12
Note: Module based on
256 Mbit or larger
dies
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Clock Signal
138 CK0
Complement Clock
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
21
CKE0
NC
NC
I
—
Note: 128 Mbit based
module
111 CKE1
167 A13
SSTL
Address Signal 13
NC
NC
SSTL
Note: 1 Gbit based
module
Control Signals
157 S0
158 S1
I
I
SSTL
SSTL
Chip Select of Rank 0
Chip Select of Rank 1
Note: 2-ranks module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
NC
NC
—
Note: Module based on
512 Mbit or smaller
dies
Data Signals
NC
NC
—
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
154 RAS
I
I
I
I
SSTL
SSTL
SSTL
4
65
63
10
CAS
6
WE
8
RESET
LV-
CMOS
Register Reset
94
95
98
99
12
13
19
20
Address Signals
59
52
48
43
41
BA0
BA1
A0
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Address Bus 11:0
A1
A2
130 A3
37
32
A4
A5
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
6
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin Name
#
Pin
Type Type
Buffer Function
Pin Name
#
Pin
Type Type
Buffer Function
105 DQ12
106 DQ13
109 DQ14
110 DQ15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
165 DQ52
166 DQ53
170 DQ54
171 DQ55
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
23
24
28
31
DQ16
DQ17
DQ18
DQ19
83
84
87
88
DQ56
DQ57
DQ58
DQ59
114 DQ20
117 DQ21
121 DQ22
123 DQ23
174 DQ60
175 DQ61
178 DQ62
179 DQ63
33
35
39
40
DQ24
DQ25
DQ26
DQ27
44
45
49
51
CB0
CB1
CB2
CB3
Check Bits 7:0
126 DQ28
127 DQ29
131 DQ30
133 DQ31
134 CB4
135 CB5
142 CB6
144 CB7
53
55
57
60
DQ32
DQ33
DQ34
DQ35
5
DQS0
Data Strobes 8:0
14
25
36
56
67
78
86
47
97
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DM0
146 DQ36
147 DQ37
150 DQ38
151 DQ39
Data Strobes 8:0
61
64
68
69
DQ40
DQ41
DQ42
DQ43
Data Mask 0
Note: ×8 based module
Data Strobe 9
DQS9
I/O
I
SSTL
SSTL
SSTL
Note: ×4 based module
Data Mask 1
153 DQ44
155 DQ45
161 DQ46
162 DQ47
107 DM1
Note: ×8 based module
Data Strobe 10
DQS10 I/O
Note: ×4 based module
72
73
79
80
DQ48
DQ49
DQ50
DQ51
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
7
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin Name
#
Pin
Type Type
Buffer Function
Pin Name
#
Pin
Type Type
Buffer Function
119 DM2
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Mask 2
15, VDDQ
22,
30,
54,
62,
PWR
—
I/O Driver Power Supply
Note: ×8 based module
Data Strobe 11
DQS11 I/O
Note: ×4 based module
Data Mask 3
129 DM3
I
77,
96,
Note: ×8 based module
Data Strobe 12
104,
112,
128,
136,
143,
156,
164,
172,
180
DQS12 I/O
Note: ×4 based module
Data Mask 4
149 DM4
I
Note: ×8 based module
Data Strobe 13
DQS13 I/O
Note: ×4 based module
Data Mask 5
159 DM5
I
Note: ×8 based module
Data Strobe 14
7,
VDD
PWR
—
Power Supply
DQS14 I/O
38,
46,
70,
85,
108,
120,
148,
168
Note: ×4 based module
Data Mask 6
169 DM6
I
Note: ×8 based module
Data Strobe 15
DQS15 I/O
Note: ×4 based module
Data Mask 7
177 DM7
I
3,
VSS
GND
—
Ground Plane
Note: ×8 based module
Data Strobe 16
11,
18,
26,
34,
42,
50,
58,
66,
DQS16 I/O
Note: ×4 based module
Data Mask 8
140 DM8
I
Note: ×8 based module
Data Strobe 17
DQS17 I/O
Note: ×4 based module
E2PROM
74,
81,
89,
93,
92
91
SCL
SDA
I
CMOS Serial Bus Clock
OD Serial Bus Data
I/O
181 SA0
182 SA1
183 SA2
I
I
I
CMOS Slave Address Select
100,
116,
124,
132,
139,
145,
152,
160,
176
Bus 2:0
CMOS
CMOS
Power Supplies
VREF AI
1
—
—
I/O Reference Voltage
E2PROM Power Supply
184 VDDSPD PWR
Rev. 1.32, 2007-03
8
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin Name
#
Pin
Type Type
Buffer Function
TABLE 5
Abbreviations for Pin Type
Other Pins
Abbreviatio Description
n
82
VDDID
O
OD
—
V
DD Identification
9,
16,
17,
NC
NC
Not connected
I
Standard input-only pin. Digital levels.
Output. Digital levels.
O
71,
75,
76,
I/O
AI
I/O is a bidirectional input/output signal.
Input. Analog levels.
PWR
GND
NU
NC
Power
90,
101,
102,
103,
113,
163,
173
Ground
Not Usable (JEDEC Standard)
Not Connected (JEDEC Standard)
TABLE 6
Abbreviations for Buffer Type
Abbreviatio Description
n
SSTL
Serial Stub Terminalted Logic (SSTL2)
LV-CMOS
CMOS
OD
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding pin has 2
operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
9
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
FIGURE 1
Pin Configuration 184 Pins, Reg
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TABLE 7
Address Table
Density Organization
Memory SDRAMs
Ranks
# of SDRAMs
# of row/rank/
columns bits
Refresh
Period
Interval
256 MB 32 M ×72
512 MB 64 M ×72
512 MB 64 M ×72
1
1
2
2
32 M ×8
64 M ×4
32 M ×8
64 M ×4
9
13 / 2 / 10
13 / 2 / 11
13 / 2 / 10
13 / 2 / 11
8 K
8 K
8 K
8 K
64 ms
64 ms
64 ms
64 ms
7.8 µs
7.8 µs
7.8 µs
7.8 µs
18
18
36
1 GB
128 M ×72
Rev. 1.32, 2007-03
10
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
3
Electrical Characteristics
This chapter lists the electrical characteristics.
3.1
Operating Conditions
This chapter contains the operating conditions tables.
TABLE 8
Absolute Maximum Ratings
Parameter
Symbol
Values
typ.
Unit Note/ Test
Condition
min.
max.
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
VIN, VOUT
VIN
–0.5
–1
–1
–1
0
—
—
—
—
—
—
1
V
DDQ +0.5
V
+3.6
+3.6
+3.6
+70
+150
—
V
VDD
V
VDDQ
TA
V
°C
°C
W
mA
TSTG
PD
–55
—
Power dissipation (per SDRAM component)
Short circuit output current
IOUT
—
50
—
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress
rating only, and functional operation should be restricted to recommended operation conditions. Exposure
to absolute maximum rating conditions for extended periods of time may affect device reliability and
exceeding only one of the values may cause irreversible damage to the integrated circuit.
TABLE 9
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Values
Unit Note1)/Test Condition
Min.
Typ.
Max.
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
E2PROM supply voltage
VDD
2.3
2.5
2.3
2.5
2.3
0
2.5
2.6
2.5
2.6
2.5
—
2.7
2.7
2.7
2.7
3.6
0
V
V
V
V
V
V
fCK ≤ 166 MHz
CK > 166 MHz 2)
fCK ≤ 166 MHz 3)
CK > 166 MHz 2)3)
VDD
f
VDDQ
VDDQ
VDDSPD
f
Supply Voltage, I/O Supply
Voltage
VSS,
VSSQ
4)
5)
Input Reference Voltage
VREF
VTT
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ
REF – 0.04 REF + 0.04
V
V
I/O Termination Voltage
(System)
V
—
V
Rev. 1.32, 2007-03
11
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Parameter
Symbol
Values
Typ.
Unit Note1)/Test Condition
Min.
Max.
6)
Input High (Logic1) Voltage VIH(DC)
Input Low (Logic0) Voltage VIL(DC)
V
REF + 0.15
—
—
—
V
DDQ + 0.3
REF – 0.15
V
V
V
6)
6)
–0.3
–0.3
V
V
Input Voltage Level, CK and VIN(DC)
DDQ + 0.3
CK Inputs
6)7)
8)
Input Differential Voltage, CK VID(DC)
and CK Inputs
0.36
0.71
–2
—
—
—
V
DDQ + 0.6
V
VI-Matching Pull-up Current VIRatio
to Pull-down Current
1.4
2
—
µA
Input Leakage Current
II
Any input 0 V ≤ VIN ≤ VDD; All
other pins not under test = 0 V
6)9)
Output Leakage Current
IOZ
–5
—
—
—
5
µA
DQs are disabled; 0 V ≤ VOUT ≤
VDDQ
Output High Current, Normal IOH
Strength Driver
—
–16.2
—
mA
mA
V
OUT = 1.95 V
OUT = 0.35 V
Output Low Current, Normal IOL
16.2
V
Strength Driver
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ
5) TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF
6) Inputs are not recognized as valid until VREF stabilizes.
7) ID is the magnitude of the difference between the input level on CK and the input level on CK.
.
.
V
.
V
8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
9) Values are shown per DDR SDRAM component
Rev. 1.32, 2007-03
12
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
3.2
Current Conditions
This chapter describes the Conditions.
TABLE 10
IDD Conditions
Parameter
Symbol
Operating Current 0
IDD0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
IDD1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
IDD2F
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN
;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current
IDD2Q
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX
.
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
IDD3N
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
;
Operating Current Read
IDD4R
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50 % of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
Operating Current Write
IDD4W
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50 % of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
IDD5
IDD6
IDD7
t
RC = tRFCMIN, burst refresh
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
Rev. 1.32, 2007-03
13
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
3.3
Current Specifications
This chapter describes the Specifications.
TABLE 11
IDD Specification for HYS72D[128/64/32]3xxx[G/H]BR–5–C
Product Type
Unit
Note/ Test Conditions1) 2)
Organization
256 MB
×72
512 MB
×72
512 MB
×72
1 Rank
–5
1 Rank
–5
2 Ranks
–5
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
3)
IDD0
1140
1360
390
1370
1600
440
2070
2380
730
2480
2800
790
1780
2000
730
2080
2310
790
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)4)
5)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
5)
880
990
1450
1020
890
1620
1200
720
1450
1020
890
1620
1200
1020
1780
2310
2350
2830
700
5)
540
650
5)
470
560
5)
950
1080
1600
1650
2120
370
1590
2470
2560
3190
640
1780
2800
2890
4130
700
1590
2040
2090
2270
640
3)4)
3)
1400
1450
1630
330
3)
5)
IDD6
3)4)
IDD7
2530
2950
4720
5500
3170
3660
1) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
2) Module IDD is calculated on the basis of component IDD and includes Register and PLL
3) The module IDD values are calculated from the component IDD datasheet values are: n * IDD × [component] for single bank modules
(n: number of components per module bank) n * IDD × [component] + n * IDD3N [component] for two bank modules (n: number of
components per module bank)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
5) The module IDD values are calculated from the component IDD datasheet values are: n * IDD × [component] for single bank modules
(n: number of components per module bank)2 * n * IDD × [component] for single two bank modules (n: number of components per module
bank)
Rev. 1.32, 2007-03
14
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 12
IDD Specification for HYS72D[256/128/64/32]3xxx[G/H]BR–6–C
Product Type
Unit Note/ Test Conditions1) 2)
Organization
256 MB
×72
512 MB
×72
512 MB
×72
1 GB
×72
1 Rank
–6
1 Rank
–6
2 Ranks
–6
2 Ranks
–6
Symbol
Typ. Max. Typ. Max. Typ. Max. Typ. Max.
3)
IDD0
1000 1190 1790 2110 1540 1780 2870 3290 mA
1210 1410 2090 2420 1750 2000 3160 3600 mA
3)4)
5)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
370
780
480
430
840
410
880
580
500
950
650
710
650
710
1220 1300 mA
5)
1250 1400 1250 1400 2200 2440 mA
5)
890
780
1050 890
640 780
1050 1690 1980 mA
890 1480 1660 mA
5)
5)
1380 1540 1380 1540 2450 2730 mA
3)4)
3)
1210 1410 2090 2420 1750 2000 3160 3600 mA
1250 1450 2180 2510 1790 2040 3250 3690 mA
1420 1820 2750 3510 1960 2410 3830 4690 mA
3)
5)
IDD6
320
370
580
640
580
640
1110 1190 mA
3)4)
IDD7
2200 2580 4070 4760 2740 3170 5140 5940 mA
1) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
2) Module IDD is calculated on the basis of component IDD and includes Register and PLL
3) The module IDD values are calculated from the component IDD datasheet values are: n * IDD × [component] for single bank modules
(n: number of components per module bank)n * IDD × [component] + n * IDD3N [component] for two bank modules (n: number of
components per module bank)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
5) The module IDD values are calculated from the component IDD datasheet values are: n * IDD × [component] for single bank modules
(n: number of components per module bank)2 * n * IDD × [component] for single two bank modules (n: number of components per module
bank)
Rev. 1.32, 2007-03
15
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 13
IDD Specification for HYS72D[128/64/32]3xxx[G/H]BR–7–C
Product Type
Unit
Note/ Test Conditions1) 2)
Organization
256 MB
×72
512 MB
×72
1 GB
×72
1 Rank
–7
1 Rank
–7
2 Ranks
–7
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
3)
IDD0
860
1040
1250
370
1510
1890
560
1830
2120
610
2410
2790
1010
1810
1440
1230
2100
2700
2790
3210
940
2870
3170
1080
2010
1690
1400
2440
3080
3170
4110
1030
4880
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)4)
5)
IDD1
1100
330
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
5)
670
760
1050
770
1180
910
5)
440
520
5)
380
450
660
570
5)
740
870
1200
1800
1890
2310
520
1390
2030
2120
3060
580
3)4)
3)
1060
1100
1210
300
1200
1250
1600
350
3)
5)
IDD6
3)4)
IDD7
1780
2100
3240
3830
4140
1) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
2) Module IDD is calculated on the basis of component IDD and includes Register and PLL
3) The module IDD values are calculated from the component IDD datasheet values are: n * IDD × [component] for single bank modules
(n: number of components per module bank)n * IDD × [component] + n * IDD3N [component] for two bank modules (n: number of
components per module bank)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
5) The module IDD values are calculated from the component IDD datasheet values are: n * IDD × [component] for single bank modules
(n: number of components per module bank)2 * n * IDD × [component] for single two bank modules (n: number of components per module
bank)
Rev. 1.32, 2007-03
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03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
3.4
AC Characteristics
This chapter describes the AC characteristics.
TABLE 14
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol –5
–6
Unit Note/ Test
Condition 1)
DDR400B
Min.
DDR333
Min.
Max.
Max.
2)3)4)5)
DQ output access time from CK/CK tAC
–0.5
0.45
5
+0.5
0.55
8
–0.7
0.45
6
+0.7
0.55
12
ns
2)3)4)5)
CK high-level width
Clock cycle time
tCH
tCK
tCK
ns
ns
ns
tCK
tCK
CL = 3.0 2)3)4)5)
CL = 2.5 2)3)4)5)
CL = 2.0 2)3)4)5)
6
12
6
12
7.5
0.45
12
7.5
0.45
12
2)3)4)5)
CK low-level width
tCL
0.55
0.55
2)3)4)5)6)
Auto precharge write recovery +
precharge time
tDAL
(tWR/tCK)+(tRP/tCK)
2)3)4)5)
DQ and DM input hold time
tDH
0.4
—
—
0.45
1.75
—
—
ns
ns
2)3)4)5)6)
DQ and DM input pulse width (each tDIPW
1.75
input)
2)3)4)5)
2)3)4)5)
DQS output access time from CK/CK tDQSCK
–0.6
0.35
+0.6
—
–0.6
0.35
+0.6
—
ns
DQS input low (high) pulse width
(write cycle)
tDQSL,H
tCK
DQS-DQ skew (DQS and associated tDQSQ
DQ signals)
Write command to 1st DQS latching tDQSS
—
+0.40
1.25
—
+0.40
1.25
ns
TFBGA 2)3)4)5)
2)3)4)5)
0.72
0.75
tCK
transition
2)3)4)5)
2)3)4)5)
DQ and DM input setup time
tDS
0.4
0.2
—
—
0.45
0.2
—
—
ns
DQS falling edge hold time from CK tDSH
tCK
(write cycle)
2)3)4)5)
DQS falling edge to CK setup time
(write cycle)
tDSS
tHP
0.2
—
0.2
—
tCK
2)3)4)5)
Clock Half Period
min. (tCL, tCH) —
min. (tCL, tCH
)
—
ns
ns
2)3)4)5)6)
Data-out high-impedance time from tHZ
—
+0.7
–0.7
+0.7
CK/CK
Address and control input hold time tIH
0.6
0.7
2.2
—
—
—
0.75
0.8
—
—
—
ns
ns
ns
fast slew rate
3)4)5)6)7)
slow slew
rate3)4)5)6)7)
2)3)4)5)8)
Control and Addr. input pulse width tIPW
2.2
(each input)
Rev. 1.32, 2007-03
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Parameter
Symbol –5
DDR400B
–6
Unit Note/ Test
Condition 1)
DDR333
Min.
Max.
Min.
Max.
Address and control input setup time tIS
0.6
—
0.75
—
ns
fast slew rate
3)4)5)6)7)
0.7
–0.7
2
—
0.8
–0.7
2
—
ns
ns
tCK
slow slew rate
3)4)5)6)7)
2)3)4)5)6)
2)3)4)5)
2)3)4)5)
Data-out low-impedance time from
CK/CK
tLZ
+0.7
—
+0.7
—
Mode register set command cycle
time
tMRD
DQ/DQS output hold time
Data hold skew factor
tQH
t
HP –tQHS
—
t
HP –tQHS
—
ns
ns
ns
tQHS
tRAP
tRAS
tRC
—
+0.50
—
—
+0.50
—
TFBGA 2)3)4)5)
2)3)4)5)
Active to Autoprecharge delay
Active to Precharge command
tRCD
40
tRCD
42
2)3)4)5)
2)3)4)5)
70E+3
—
70E+3 ns
Active to Active/Auto-refresh
command period
55
60
—
ns
2)3)4)5)
2)3)4)5)9)
2)3)4)5)
Active to Read or Write delay
tRCD
tREFI
15
—
65
—
18
—
72
—
ns
µs
ns
Average Periodic Refresh Interval
7.8
—
7.8
—
Auto-refresh to Active/Auto-refresh tRFC
command period
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Precharge command period
Read preamble
tRP
15
—
18
—
ns
tCK
tCK
ns
tRPRE
tRPST
tRRD
0.9
0.40
10
1.1
0.60
—
0.9
0.40
12
1.1
0.60
—
Read postamble
Active bank A to Active bank B
command
2)3)4)5)
2)3)4)5)8)
2)3)4)5)8)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
—
0.25
0
—
tCK
ns
tCK
ns
tCK
ns
Write preamble setup time
Write postamble
—
—
0.40
15
2
0.60
—
0.40
15
1
0.60
—
Write recovery time
Internal write to read command delay tWTR
—
—
Exit self-refresh to non-read
command
tXSNR
75
—
75
—
2)3)4)5)
Exit self-refresh to read command
tXSRD
200
—
200
—
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac)
.
8) These parameters guarantee device timing, but they are not necessarily tested on each device.
9) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Rev. 1.32, 2007-03
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03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 15
AC Timing - Absolute Specifications for PC2700
Parameter
Symbol –7
Unit
Note/Test
Condition 1)
DDR266A
Min.
Max.
2)3)4)5)
2)3)4)5)
DQ output access time from CK/CK
CK high-level width
tAC
tCH
tCK
–0.75
+0.75
0.55
12
ns
tCK
ns
ns
tCK
tCK
ns
ns
ns
tCK
ns
tCK
ns
tCK
tCK
ns
ns
ns
0.45
Clock cycle time
7.5
CL = 2.52)3)4)5)
CL = 2.02)3)4)5)
7.5
12
2)3)4)5)
CK low-level width
tCL
0.45
0.55
—
2)3)4)5)6)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Auto precharge write recovery + precharge time tDAL
(tWR/tCK)+(tRP/tCK)
DQ and DM input hold time
tDH
0.5
—
DQ and DM input pulse width (each input)
DQS output access time from CK/CK
DQS input low (high) pulse width (write cycle)
tDIPW
tDQSCK
tDQSL,H
1.75
–0.75
0.35
—
—
+0.75
—
DQS-DQ skew (DQS and associated DQ signals) tDQSQ
Write command to 1st DQS latching transition
+0.5
1.25
—
FBGA2)3)4)5)
2)3)4)5)
tDQSS
tDS
0.75
0.5
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)6)
DQ and DM input setup time
DQS falling edge hold time from CK (write cycle) tDSH
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
0.2
—
Clock Half Period
tHP
tHZ
tIH
min. (tCL, tCH
)
—
Data-out high-impedance time from CK/CK
Address and control input hold time
–0.75
+0.75
—
0.9
fast slew rate
3)4)5)6)7)
1.0
—
ns
slow slew rate
3)4)5)6)8)
2)3)4)5)8)
Control and Addr. input pulse width (each input) tIPW
2.2
0.9
—
—
ns
ns
Address and control input setup time
tIS
fast slew rate
3)4)5)6)8)
1.0
—
ns
slow slew rate
3)4)5)6)8)
2)3)4)5)6)
2)3)4)5)
2)3)4)5)
Data-out low-impedance time from CK/CK
Mode register set command cycle time
DQ/DQS output hold time
tLZ
–0.75
2
+0.75
—
ns
tCK
ns
ns
ns
ns
ns
ns
µs
ns
tMRD
tQH
t
HP – tQHS
Data hold skew factor
tQHS
tRAP
tRAS
tRC
—
0.75
—
FBGA2)3)4)5)
2)3)4)5)
Active to Read w/AP delay
tRCD or tRASmin
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)8)
2)3)4)5)
Active to Precharge command
Active to Active/Auto-refresh command period
Active to Read or Write delay
45
65
20
7.8
75
120E+3
—
tRCD
tREFI
tRFC
—
Average Periodic Refresh Interval
—
Auto-refresh to Active/Auto-refresh command
period
—
Rev. 1.32, 2007-03
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03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Parameter
Symbol –7
DDR266A
Unit
Note/Test
Condition 1)
Min.
Max.
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)9)
2)3)4)5)10)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)
Precharge command period
Read preamble
tRP
20
0.9
0.4
15
0.25
0
—
1.1
0.6
—
—
—
—
—
—
—
—
ns
tRPRE
tRPST
tRRD
tCK
tCK
ns
Read postamble
Active bank A to Active bank B command
Write preamble
tWPRE
tWPRES
tWPST
tWR
tCK
ns
tCK
ns
Write preamble setup time
Write postamble
0.4
15
1
Write recovery time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
tWTR
tCK
ns
tXSNR
tXSRD
75
200
tCK
1)
VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V ; 0 °C ≤ TA ≤ 70 °C
2) Input slew rate ≥ 1 V/ns
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
6) HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
7) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac)
.
t
.
8) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS
.
10) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
11) In all circumstances, tXSNR can be satisfied using tXSNR = tRFC,min + 1 × tCK
Rev. 1.32, 2007-03
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03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
•
•
•
Table 16 “HYS72D[32/64]3x0GBR-5-C” on Page 21
Table 17 “HYS72D[32/64/128]3x0GBR-6-C” on Page 25
Table 18 “HYS72D[32/64/128]3x0GBR-7-C” on Page 29
Table 19 “HYS72D[32/64]3x0HBR-5-C” on Page 33
Table 20 “HYS72D[32/64/128]3x0HBR-6-C” on Page 37
Table 21 “HYS72D[32/64/128]3x0HBR-7-C” on Page 41
TABLE 16
HYS72D[32/64]3x0GBR-5-C
Product Type
Organization
256MB
×72
512MB
512MB
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331 PC3200R–30331 PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
1
2
3
4
5
6
7
8
9
10
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0A
01
48
00
04
50
50
80
08
07
0D
0B
01
48
00
04
50
50
80
08
07
0D
0A
02
48
00
04
50
50
Data Width (LSB)
Data Width (MSB)
Interface Voltage Levels
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
Rev. 1.32, 2007-03
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03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331 PC3200R–30331 PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Error Correction Support
Refresh Rate
02
82
08
08
01
0E
04
1C
01
02
26
C1
60
50
75
50
3C
28
3C
28
40
60
60
40
40
00
37
02
82
04
04
01
0E
04
1C
01
02
26
C1
60
50
75
50
3C
28
3C
28
80
60
60
40
40
00
37
02
82
08
08
01
0E
04
1C
01
02
26
C1
60
50
75
50
3C
28
3C
28
40
60
60
40
40
00
37
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
t
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
t
tRPmin [ns]
t
RRDmin [ns]
RCDmin [ns]
t
tRASmin [ns]
Module Density per Rank
tAS, tCS [ns]
tAH, tCH [ns]
t
DS [ns]
DH [ns]
t
36 - 40 Not used
41 RCmin [ns]
t
Rev. 1.32, 2007-03
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03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331 PC3200R–30331 PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
42
43
44
45
46
47
tRFCmin [ns]
tCKmax [ns]
41
28
28
50
00
01
00
10
26
7F
7F
7F
7F
7F
51
00
00
xx
41
28
28
50
00
01
00
10
5F
7F
7F
7F
7F
7F
51
00
00
xx
41
28
28
50
00
01
00
10
27
7F
7F
7F
7F
7F
51
00
00
xx
t
DQSQmax [ns]
QHSmax [ns]
t
not used
DIMM PCB Height
48 - 61 Not used
SPD Revision
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
37
32
44
33
32
33
30
30
47
37
32
44
36
34
33
30
30
47
37
32
44
36
34
33
32
30
47
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Rev. 1.32, 2007-03
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03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331 PC3200R–30331 PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
82
83
84
85
86
87
88
89
90
91
92
93
94
Part Number, Char 10
42
52
35
43
20
20
20
20
20
1x
xx
xx
xx
xx
00
42
52
35
43
20
20
20
20
20
1x
xx
xx
xx
xx
00
42
52
35
43
20
20
20
20
20
1x
xx
xx
xx
xx
00
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 1.32, 2007-03
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 17
HYS72D[32/64/128]3x0GBR-6-C
Product Type
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
Data Width (LSB)
80
08
07
0D
0A
01
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
26
C1
80
08
07
0D
0B
01
48
00
04
60
70
02
82
04
04
01
0E
04
0C
01
02
26
C1
80
08
07
0D
0A
02
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
26
C1
80
08
07
0D
0B
02
48
00
04
60
70
02
82
04
04
01
0E
04
0C
01
02
26
C1
1
2
3
4
5
6
7
Data Width (MSB)
8
Interface Voltage Levels
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
Rev. 1.32, 2007-03
25
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
tCK @ CLmax -0.5 (Byte 18) [ns]
75
70
00
00
48
30
48
2A
40
75
75
45
45
00
3C
48
30
28
50
00
00
00
00
0F
7F
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
28
50
00
00
00
00
48
7F
75
70
00
00
48
30
48
2A
40
75
75
45
45
00
3C
48
30
28
50
00
00
00
00
10
7F
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
28
50
00
00
00
00
49
7F
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
t
AC SDRAM @ CLmax -1 [ns]
RPmin [ns]
t
tRRDmin [ns]
t
RCDmin [ns]
RASmin [ns]
t
Module Density per Rank
t
AS, tCS [ns]
AH, tCH [ns]
t
tDS [ns]
DH [ns]
t
36 - 40 Not used
41
42
43
44
45
46
47
tRCmin [ns]
t
RFCmin [ns]
CKmax [ns]
t
tDQSQmax [ns]
QHSmax [ns]
t
not used
DIMM PCB Height
48 - 61 Not used
62
63
64
SPD Revision
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Rev. 1.32, 2007-03
26
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
7F
7F
7F
7F
51
00
00
xx
7F
7F
7F
7F
51
00
00
xx
7F
7F
7F
7F
51
00
00
xx
7F
7F
7F
7F
51
00
00
xx
37
32
44
33
32
33
30
30
47
42
52
36
43
20
20
20
20
37
32
44
36
34
33
30
30
47
42
52
36
43
20
20
20
20
37
32
44
36
34
33
32
30
47
42
52
36
43
20
20
20
20
37
32
44
31
32
38
33
32
30
47
42
52
36
43
20
20
20
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Rev. 1.32, 2007-03
27
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
90
91
92
93
94
Part Number, Char 18
20
1x
xx
xx
xx
xx
00
20
1x
xx
xx
xx
xx
00
20
1x
xx
xx
xx
xx
00
20
1x
xx
xx
xx
xx
00
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 1.32, 2007-03
28
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 18
HYS72D[32/64/128]3x0GBR-7-C
Product Type
Organization
256MB
×72
512MB
×72
1 GByte
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330 PC2100R–20331 PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 1.0
HEX
Rev. 0.0
HEX
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0A
01
48
00
04
70
75
02
82
08
08
01
0E
04
0C
01
02
26
C1
75
80
08
07
0D
0B
01
48
00
04
70
75
02
82
04
04
01
0E
04
0C
01
02
26
C1
75
80
08
07
0D
0B
02
48
00
04
70
75
02
82
04
04
01
0E
04
0C
01
02
26
C1
75
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
tCK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns]
Rev. 1.32, 2007-03
29
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
×72
512MB
×72
1 GByte
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330 PC2100R–20331 PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 1.0
HEX
Rev. 0.0
HEX
Byte#
Description
24
25
26
27
28
29
30
31
32
33
34
35
tAC SDRAM @ CLmax -0.5 [ns]
75
00
00
50
3C
50
2D
40
90
90
50
50
00
41
4B
30
32
75
00
00
00
00
CB
7F
7F
7F
75
00
00
50
3C
50
2D
80
90
90
50
50
00
41
4B
30
32
75
00
00
00
10
14
7F
7F
7F
75
00
00
50
3C
50
2D
80
90
90
50
50
00
41
4B
30
32
75
00
00
00
00
05
7F
7F
7F
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
RASmin [ns]
t
Module Density per Rank
tAS, tCS [ns]
t
AH, tCH [ns]
DS [ns]
t
tDH [ns]
36 - 40 Not used
41
42
43
44
45
46
47
tRCmin [ns]
tRFCmin [ns]
tCKmax [ns]
tDQSQmax [ns]
tQHSmax [ns]
not used
DIMM PCB Height
48 - 61 Not used
62
63
64
65
66
SPD Revision
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Rev. 1.32, 2007-03
30
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
×72
512MB
×72
1 GByte
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330 PC2100R–20331 PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 1.0
HEX
Rev. 0.0
HEX
Byte#
Description
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
7F
7F
51
00
00
xx
7F
7F
51
00
00
xx
7F
7F
51
00
00
xx
37
32
44
33
32
33
30
30
47
42
52
37
43
20
20
20
20
20
1x
xx
37
32
44
36
34
33
30
30
47
42
52
37
43
20
20
20
20
20
0x
xx
37
32
44
31
32
38
33
32
30
47
42
52
37
43
20
20
20
20
1x
xx
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Rev. 1.32, 2007-03
31
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
×72
512MB
×72
1 GByte
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330 PC2100R–20331 PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 1.0
HEX
Rev. 0.0
HEX
Byte#
Description
93
94
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
00
xx
xx
xx
00
xx
xx
xx
00
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 1.32, 2007-03
32
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 19
HYS72D[32/64]3x0HBR-5-C
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331 PC3200R–30331 PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
Data Width (LSB)
80
08
07
0D
0A
01
48
00
04
50
50
02
82
08
08
01
0E
04
1C
01
02
26
C1
60
80
08
07
0D
0B
01
48
00
04
50
50
02
82
04
04
01
0E
04
1C
01
02
26
C1
60
80
08
07
0D
0A
02
48
00
04
50
50
02
82
08
08
01
0E
04
1C
01
02
26
C1
60
1
2
3
4
5
6
7
Data Width (MSB)
8
Interface Voltage Levels
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns]
Rev. 1.32, 2007-03
33
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331 PC3200R–30331 PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
24
25
26
27
28
29
30
31
32
33
34
35
tAC SDRAM @ CLmax -0.5 [ns]
50
75
50
3C
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
01
00
10
26
7F
7F
7F
7F
50
75
50
3C
28
3C
28
80
60
60
40
40
00
37
41
28
28
50
00
01
00
10
5F
7F
7F
7F
7F
50
75
50
3C
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
01
00
10
27
7F
7F
7F
7F
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
RASmin [ns]
t
Module Density per Rank
tAS, tCS [ns]
t
AH, tCH [ns]
DS [ns]
t
tDH [ns]
36 - 40 Not used
41
42
43
44
45
46
47
tRCmin [ns]
tRFCmin [ns]
tCKmax [ns]
tDQSQmax [ns]
tQHSmax [ns]
not used
DIMM PCB Height
48 - 61 Not used
62
63
64
65
66
67
SPD Revision
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Rev. 1.32, 2007-03
34
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331 PC3200R–30331 PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
7F
51
00
00
xx
37
32
44
33
32
33
30
30
48
42
52
35
43
20
20
20
20
20
1x
xx
xx
xx
7F
51
00
00
xx
37
32
44
36
34
33
30
30
48
42
52
35
43
20
20
20
20
20
1x
xx
xx
xx
7F
51
00
00
xx
37
32
44
36
34
33
32
30
48
42
52
35
43
20
20
20
20
20
1x
xx
xx
xx
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Rev. 1.32, 2007-03
35
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331 PC3200R–30331 PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
95 - 98 Module Serial Number
99 - 127 Not used
xx
xx
xx
00
00
00
Rev. 1.32, 2007-03
36
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 20
HYS72D[32/64/128]3x0HBR-6-C
Product Type
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0A
01
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
26
C1
80
08
07
0D
0B
01
48
00
04
60
70
02
82
04
04
01
0E
04
0C
01
02
26
C1
80
08
07
0D
0A
02
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
26
C1
80
08
07
0D
0B
02
48
00
04
60
70
02
82
04
04
01
0E
04
0C
01
02
26
C1
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
tCK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
Rev. 1.32, 2007-03
37
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
tCK @ CLmax -0.5 (Byte 18) [ns]
75
70
00
00
48
30
48
2A
40
75
75
45
45
00
3C
48
30
28
50
00
00
00
00
0F
7F
7F
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
28
50
00
00
00
00
48
7F
7F
75
70
00
00
48
30
48
2A
40
75
75
45
45
00
3C
48
30
28
50
00
00
00
00
10
7F
7F
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
28
50
00
00
00
00
49
7F
7F
t
AC SDRAM @ CLmax -0.5 [ns]
CK @ CLmax -1 (Byte 18) [ns]
t
tAC SDRAM @ CLmax -1 [ns]
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
RASmin [ns]
t
Module Density per Rank
tAS, tCS [ns]
t
AH, tCH [ns]
DS [ns]
t
tDH [ns]
36 - 40 Not used
41
42
43
44
45
46
47
tRCmin [ns]
tRFCmin [ns]
tCKmax [ns]
tDQSQmax [ns]
tQHSmax [ns]
not used
DIMM PCB Height
48 - 61 Not used
62
63
64
65
SPD Revision
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Rev. 1.32, 2007-03
38
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
37
32
44
33
32
33
30
30
48
42
52
36
43
20
20
20
20
20
1x
37
32
44
36
34
33
30
30
48
42
52
36
43
20
20
20
20
20
1x
37
32
44
36
34
33
32
30
48
42
52
36
43
20
20
20
20
20
1x
37
32
44
31
32
38
33
32
30
48
42
52
36
43
20
20
20
20
1x
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Rev. 1.32, 2007-03
39
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
92
93
94
Test Program Revision Code
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 1.32, 2007-03
40
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 21
HYS72D[32/64/128]3x0HBR-7-C
Product Type
Organization
256MB
×72
512MB
×72
1 GByte
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330 PC2100R–20331 PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 1.0
HEX
Rev. 0.0
HEX
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0A
01
48
00
04
70
75
02
82
08
08
01
0E
04
0C
01
02
26
C1
75
80
08
07
0D
0B
01
48
00
04
70
75
02
82
04
04
01
0E
04
0C
01
02
26
C1
75
80
08
07
0D
0B
02
48
00
04
70
75
02
82
04
04
01
0E
04
0C
01
02
26
C1
75
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
tCK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns]
Rev. 1.32, 2007-03
41
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
×72
512MB
×72
1 GByte
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330 PC2100R–20331 PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 1.0
HEX
Rev. 0.0
HEX
Byte#
Description
24
25
26
27
28
29
30
31
32
33
34
35
tAC SDRAM @ CLmax -0.5 [ns]
75
00
00
50
3C
50
2D
40
90
90
50
50
00
41
4B
30
32
75
00
00
00
00
CB
7F
7F
7F
75
00
00
50
3C
50
2D
80
90
90
50
50
00
41
4B
30
32
75
00
00
00
10
14
7F
7F
7F
75
00
00
50
3C
50
2D
80
90
90
50
50
00
41
4B
30
32
75
00
00
00
00
05
7F
7F
7F
t
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
t
tRPmin [ns]
t
RRDmin [ns]
RCDmin [ns]
t
tRASmin [ns]
Module Density per Rank
tAS, tCS [ns]
tAH, tCH [ns]
t
DS [ns]
DH [ns]
t
36 - 40 Not used
41
42
43
44
45
46
47
tRCmin [ns]
RFCmin [ns]
tCKmax [ns]
t
t
DQSQmax [ns]
QHSmax [ns]
t
not used
DIMM PCB Height
48 - 61 Not used
62
63
64
65
66
SPD Revision
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Rev. 1.32, 2007-03
42
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
×72
512MB
×72
1 GByte
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330 PC2100R–20331 PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 1.0
HEX
Rev. 0.0
HEX
Byte#
Description
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
7F
7F
51
00
00
xx
7F
7F
51
00
00
xx
7F
7F
51
00
00
xx
37
32
44
33
32
33
30
30
48
42
52
37
43
20
20
20
20
20
1x
xx
37
32
44
36
34
33
30
30
48
42
52
37
43
20
20
20
20
20
0x
xx
37
32
44
31
32
38
33
32
30
48
42
52
37
43
20
20
20
20
1x
xx
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Rev. 1.32, 2007-03
43
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Product Type
Organization
256MB
×72
512MB
×72
1 GByte
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330 PC2100R–20331 PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 1.0
HEX
Rev. 0.0
HEX
Byte#
Description
93
94
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
00
xx
xx
xx
00
xx
xx
xx
00
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 1.32, 2007-03
44
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
5
Package Outlines
This chapter contains the package outlines of the products.
5.1
Raw Card A
FIGURE 2
Package Outlines – Raw Card A HYS72D32300[G/H]BR–[5/6/7]–C (1 Rank × 8)
133.35
0.15 A B C
128.95
2.64 MAX.
A
1
2.5
92
6.62
2.175
B
C
0.1
ø0.1 A B C
64.77
0.4
6.35
0.1
1.27
49.53
95 x 1.27 = 120.65
0.1
1.8
0.1 A B C
93
184
3 MIN.
Detail of contacts
1.27
0.05
1
0.1 A B C
Burr max. 0.4 allowed
Rev. 1.32, 2007-03
45
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
5.2
Raw Card B
FIGURE 3
Package Outlines – Raw Card B HYS72D64320GBR–[5/6]–C (2 Ranks ×8)
133.35
0.15 A B C
128.95
4 MAX.
A
1
2.5
92
6.62
2.175
B
C
0.1
ø0.1 A B C
64.77
0.4
6.35
0.1
1.27
49.53
95 x 1.27 = 120.65
0.1
1.8
0.1 A B C
93
184
3 MIN.
Detail of contacts
1.27
0.05
1
0.1 A B C
Burr max. 0.4 allowed
Rev. 1.32, 2007-03
46
03292006-Q22P-G7TH
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
5.3
Raw Card C
FIGURE 4
Package Outlines – Raw Card C HYS72D64300[G/H]BR–[5/6/7]–C (1 Rank × 4)
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Rev. 1.32, 2007-03
03292006-Q22P-G7TH
47
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
5.4
Raw Card D
FIGURE 5
Package Outlines – Raw Card D HYS72D128320[G/H]BR–[6/7]–C (2 Ranks ×4)
133.35
0.15 A B C
128.95
4 MAX.
A
1
2.5
92
6.62
2.175
B
C
0.1
ø0.1 A B C
0.4
6.35
0.1
1.27
64.77
49.53
95 x 1.27 = 120.65
0.1
1.8
0.1 A B C
93
184
3 MIN.
Detail of contacts
1.27
0.05
1
0.1 A B C
Burr max. 0.4 allowed
Rev. 1.32, 2007-03
48
03292006-Q22P-G7TH
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
3.2
3.3
3.4
4
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Raw Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Raw Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Raw Card C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Raw Card D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.1
5.2
5.3
5.4
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Rev. 1.32, 2007-03
49
03292006-Q22P-G7TH
Internet Data Sheet
Edition 2007-03
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
www.qimonda.com
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