HYS72T128020EP-2.5-B2 [QIMONDA]
DDR DRAM Module, 128MX72, 0.2ns, CMOS, GREEN, RDIMM-240;
| 型号： | HYS72T128020EP-2.5-B2 |
| 厂家： | 
QIMONDA AG |
| 描述： | DDR DRAM Module, 128MX72, 0.2ns, CMOS, GREEN, RDIMM-240 动态存储器 双倍数据速率 |
| 文件： | 总64页 (文件大小：3435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2008
HYS72T[64/128/256]xx0EP–[2.5/25F]–B2
HYS72T[64/128/256]xx0EP–[3/3S]–B2
HYS72T[64/128/256]xx0EP–3.7–B2
240-Pin Registered DDR2 SDRAM Modules
RDIMM SDRAM
EU RoHS Compliant
Internet Data Sheet
Rev. 1.02
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
HYS72T[64/128/256]xx0EP–[2.5/25F]–B2, HYS72T[64/128/256]xx0EP–[3/3S]–B2, HYS72T[64/128/256]xx0EP–3.7–B2
Revision History: 2008-06, Rev. 1.02
Page
Subjects (major changes since last revision)
All
Editorial change and adapted to internet edition.
Previous Revision: 2008-01, Rev. 1.01
All Editorial change.
Previous Revision: 2007-07, Rev. 1.0
All Final document.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
07312007-HYD2-P177
2
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 240-pin Registered DDR2 SDRAM modules product family with parity bit for address and
control bus and describes its main characteristics.
1.1
Features
•
•
240-Pin PC2-6400, PC2-5300 and PC2-4200 DDR2
SDRAM memory modules.
One rank 128M × 72, 64M × 72 and , two rank 128M × 72,
256M × 72 module organization, and 64M × 8, 128M × 4
chip organization.
2GB, 1GB, 512MB Modules built with 512MBit DDR2
SDRAMs in chipsize packages PG-TFBGA-60.
Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply.
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh.
Auto Refresh for temperatures above 85 °C tREFI = 3.9 μs.
Programmable self refresh rate via EMRS2 setting.
Programmable partial array refresh via EMRS2 settings.
DCC enabling via EMRS2 setting.
All inputs and outputs SSTL_1.8 compatible.
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT).
•
•
•
•
•
Serial Presence Detect with E2PROM.
Dimensions (nominal): 30 mm high, 133.35 mm wide
Based on standard reference layouts Raw Cards 'F', 'L', 'G'
and 'H'.
•
•
All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
Programmable CAS Latencies (3, 4, 5, 6 and 7 ), Burst
Length (8 & 4).
•
RoHS compliant products1).
TABLE 1
Performance Table
QAG Speed Code
–25F
–2.5
–3
–3S
–3.7
Unit
Note
DRAM Speed Grade
Module Speed Grade
DDR2
PC2
–800D
–6400D
5–5–5
–800E
–6400E
6–6–6
–667C
–5300C
4–4–4
–667D
–5300D
5–5–5
–533C
–4200C
4–4–4
tCK
CAS-RCD-RP latencies
Max. Clock Frequency
CL3
CL4
CL5
CL6
fCK3
fCK4
fCK5
fCK6
tRCD
tRP
200
266
400
–
200
266
333
400
15
200
333
333
–
200
266
333
–
200
266
266
–
MHz
MHz
MHz
MHz
ns
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Active Time
Min. Row Cycle Time
12.5
12.5
45
12
15
15
15
12
15
15
ns
1)
2)
1)
tRAS
tRAS
tRC
45
45
45
45
ns
40
40
40
40
40
ns
57.5
60
57
60
60
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit
www.qimonda.com/green_products .
Rev. 1.02, 2008-06
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07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
QAG Speed Code
–25F
–2.5
–3
–3S
–3.7
Unit
Note
DRAM Speed Grade
Module Speed Grade
DDR2
PC2
–800D
–6400D
5–5–5
–800E
–6400E
6–6–6
–667C
–5300C
4–4–4
–667D
–5300D
5–5–5
–533C
–4200C
4–4–4
tCK
CAS-RCD-RP latencies
2)
Min. Row Cycle Time
tRC
52.5
12.5
55
15
52
12
55
15
55
15
ns
ns
Precharge-All (4 banks) command tPREA
period
1) Product released after 2007-08-01 will support tRAS = 40 ns for all DDR2 speed sort.
2) For products after 2007-08-01.
1.2
Description
The
Qimonda
HYS72T[64/128/256]xx0EP–
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB board. The DIMMs feature serial presence detect
based on a serial E2PROM device using the 2-pin I2C
protocol. The first 128 bytes are programmed with
configuration data and are write protected; the second
128 bytes are available to the customer.
[2.5/25F/3/3S/3.7]–B2 module family are Registered DIMM
modules “RDIMMs” with parity bit for address and control bus
and 30 mm height based on DDR2 technology. DIMMs are
available as ECC modules
in 128M × 72 (1GB),
256M × 72 (2GB), 64M × 72 (512MB) in organization and
density, intended for mounting into 240-pin connector
sockets.
The memory array is designed with 512MBit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. All control and
TABLE 2
Ordering Information
Product Type1)
Compliance Code2)
Description
SDRAM Technology
PC2-6400 (5-5-5)
HYS72T256220EP-25F-B2 2GB 2R×4 PC2–6400P–555–12–L0
HYS72T128020EP-25F-B2 1GB 2R×8 PC2–6400P–555–12–G0
HYS72T128000EP-25F-B2 1GB 1R×4 PC2–6400P–555–12–H0
2 Ranks, ECC
2 Ranks, ECC
1 Rank, ECC
1 Rank, ECC
512Mbit (×4)
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
HYS72T64000EP-25F-B2
512MB 1R×8 PC2–6400P–555–12–F0
PC2-6400 (6-6-6)
HYS72T256220EP-2.5-B2 2GB 2R×4 PC2–6400P–666–12–L0
HYS72T128020EP-2.5-B2 1GB 2R×8 PC2–6400P–666–12–G0
HYS72T128000EP-2.5-B2 1GB 1R×4 PC2–6400P–666–12–H0
2 Ranks, ECC
2 Ranks, ECC
1 Rank, ECC
1 Rank, ECC
512Mbit (×4)
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
HYS72T64000EP-2.5-B2
512MB 1R×8 PC2–6400P–666–12–F0
Rev. 1.02, 2008-06
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07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type1)
Compliance Code2)
Description
SDRAM Technology
PC2-5300 (4-4-4)
HYS72T256220EP-3-B2
HYS72T128020EP-3-B2
HYS72T128000EP-3-B2
HYS72T64000EP-3-B2
PC2-5300 (5-5-5)
2GB 2R×4 PC2–5300P–444–12–L0
1GB 2R×8 PC2–5300P–444–12–G0
1GB 1R×4 PC2–5300P–444–12–H0
512MB 1R×8 PC2–5300P–444–12–F0
2 Ranks, ECC
2 Ranks, ECC
1 Rank, ECC
1 Rank, ECC
512Mbit (×4)
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
HYS72T256220EP-3S-B2
HYS72T128020EP-3S-B2
HYS72T128000EP-3S-B2
HYS72T64000EP-3S-B2
PC2-4200 (4-4-4)
2GB 2R×4 PC2–5300P–555–12–L0
1GB 2R×8 PC2–5300P–555–12–G0
1GB 1R×4 PC2–5300P–555–12–H0
512MB 1R×8 PC2–5300P–555–12–F0
2 Ranks, ECC
2 Ranks, ECC
1 Rank, ECC
1 Rank, ECC
512Mbit (×4)
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
HYS72T256220EP-3.7-B2 2GB 2R×4 PC2–4200P–444–12–L0
HYS72T128020EP-3.7-B2 1GB 2R×8 PC2–4200P–444–12–G0
HYS72T128000EP-3.7-B2 1GB 1R×4 PC2–4200P–444–12–H0
2 Ranks, ECC
2 Ranks, ECC
1 Rank, ECC
1 Rank, ECC
512Mbit (×4)
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
HYS72T64000EP-3.7-B2
512MB 1R×8 PC2–4200P–444–12–F0
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400P–555–12–F0" where 6400P
means Registered DIMM with Parity bit modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS)
latency =5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the Industry Standard SPD Revision 1.2 and
produced on the Raw Card "F".
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
2GB
256M × 72
128M × 72
128M × 72
64M × 72
2
2
1
1
ECC
ECC
ECC
ECC
36
18
18
9
14/2/11
14/2/10
14/2/11
14/2/10
L
1GB
G
H
F
1GB
512MB
TABLE 4
Components on Modules
DRAM Organisation
Product Type1)2)
DRAM Components1)
DRAM Density
HYS72T256220EP
HYS72T128020EP
HYS72T128000EP
HYB18T512400B2F
HYB18T512800B2F
HYB18T512400B2F
HYB18T512800B2F
512Mbit
512Mbit
512Mbit
512Mbit
128M × 4
64M × 8
128M × 4
64M × 8
HYS72T64000EP
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.02, 2008-06
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07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
2
Pin Configurations and Block Diagrams
2.1
Pin Configurations
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in Table 5 (240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 6
and Table 7 respectively. The pin numbering is depicted in
Figure 1.
TABLE 5
Pin Configuration of RDIMM
Pin No.
Name
Pin
Buffer
Function
Type Type
Clock Signals
185
186
CK0
CK0
I
I
SSTL
SSTL
Clock Signal CK0, Complementary Clock Signal CK0
The system clock inputs. All address and command lines are sampled
on the cross point of the rising edge of CK and the falling edge of CK.
A Delay Locked Loop (DLL) circuit is driven from the clock inputs and
output timing for read operations is synchronized to the input clock.
52
CKE0
CKE1
I
I
SSTL
SSTL
Clock Enables 1:0
Activates the DDR2 SDRAM CK signal when HIGH and deactivates
the CK signal when LOW. By deactivating the clocks, CKE0 initiates
the Power Down Mode or the Self Refresh Mode.
171
Note: 2-Ranks module
Not Connected
NC
NC
—
Note: 1-Rank module
Control Signals
193
76
S0
S1
I
I
SSTL
SSTL
Chip Select
Enables the associated DDR2 SDRAM command decoder when LOW
and disables the command decoder when HIGH. When the command
decoder is disabled, new commands are ignored but previous
operations continue.
Rank 0 is selected by S0
Rank 1 is selected by S1
The input signals also disable all outputs (except CKE and ODT) of the
register(s) on the DIMM when both inputs are high. When S is HIGH,
all register outputs (except CK, ODT and Chip select) remain in the
previous state.
Note: 2-Ranks module
Not Connected
NC
NC
—
Note: 1-Rank module
Rev. 1.02, 2008-06
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07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Pin No.
Name
Pin
Buffer
Function
Type Type
220
S2
I
SSTL
—
Rank 2 is selected by S2
Not Connected
NC
NC
Note: 1-Rank, 2-Ranks module
221
S3
I
SSTL
—
Rank 3 is selected by S3
Not Connected
NC
NC
Note: 1-Rank, 2-Ranks module
192
74
RAS
CAS
WE
I
I
I
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
When sampled at the cross point of the rising edge of CK, and falling
edge of CK, RAS, CAS and WE define the operation to be executed by
the SDRAM.
73
18
RESET
I
CMOS
Register Reset
The RESET pin is connected to the RST pin on the register and to the
OE pin on the PLL. When LOW, all register outputs will be driven LOW
and the PLL clocks to the DRAMs and the register(s) will be set to low-
level. The PLL will remain synchronized with the input clock.
Address Signals
71
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Selects internal SDRAM memory bank
190
54
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
I
SSTL
Not Connected
Less than 1Gb DDR2 SDRAMS
188
183
63
A0
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Address Bus 12:0, Address Signal 10/AutoPrecharge
During a Bank Activate command cycle, defines the row address when
sampled at the crosspoint of the rising edge of CK and falling edge of
CK. During a Read or Write command cycle, defines the column
address when sampled at the cross point of the rising edge of CK and
falling edge of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is HIGH, autoprecharge is selected and BA[1:0] defines the
bank to be precharged. If AP is LOW, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with
BA[1:0] to control which bank(s) to precharge. If AP is HIGH, all banks
will be precharged regardless of the state of BA[1:0] inputs. If AP is
LOW, then BA[1:0] are used to define which bank to precharge.
A1
I
A2
I
182
61
A3
I
A4
I
60
A5
I
180
58
A6
I
A7
I
179
177
70
A8
I
A9
I
A10
AP
A11
A12
A13
NC
I
I
57
I
176
196
I
I
Address Signal 13
NC
Not Connected
Note: Non CA parity modules based on 256 Mbit component
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Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Pin No.
Name
A14
NC
Pin
Type Type
Buffer
Function
174
I
SSTL
—
Address Signal 14
Note: CA Parity module
NC
I
Not Connected
Note: Non CA parity module. Less than 1 GBit per DRAM die.
Address Signal 14
173
A15
NC
SSTL
—
Note: CA Parity module
NC
Not Connected
Note: Non CA parity module. Less than 1 GBit per DRAM die.
Data Signals
3
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Data Input/Output pins
4
DQ1
9
DQ2
10
DQ3
122
123
128
129
12
DQ4
DQ5
DQ6
DQ7
DQ8
13
DQ9
21
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
Rev. 1.02, 2008-06
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07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Pin No.
Name
Pin
Buffer
Function
Type Type
159
80
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Data Input/Output pins
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
Check Bits
42
CB0
CB1
CB2
CB3
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Check Bits 7:0
Check Bit Input / Output pins
43
Note: NC on Non-ECC module
48
49
Rev. 1.02, 2008-06
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07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Pin No.
Name
Pin
Buffer
Function
Type Type
161
CB4
CB5
CB6
CB7
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Check Bits 7:0
Check Bit Input / Output pins
162
Note: NC on Non-ECC module
167
168
Data Strobe Bus
7
DQS0
DQS0
DQS1
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
DQS8
DQS8
DQS9
DQS9
DQS10
DQS10
DQS11
DQS11
DQS12
DQS12
DQS13
DQS13
DQS14
DQS14
DQS15
DQS15
DQS16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Strobes Bus 17:0 and Complementary Data Strobe Bus 17:0
The data strobes, associated with one data byte, sourced with data
transfers. In Write mode, the data strobe is sourced by the controller
and is centered in the data window. In Read mode the data strobe is
sourced by the DDR2 SDRAM and is sent at the leading edge of the
data window. DQS signals are complements, and timing is relative to
the crosspoint of respective DQS and DQS. If the module is to be
operated in single ended strobe mode, all DQS signals must be tied on
the system board to VSS through a 20 Ω to 10 kΩ resistor and DDR2
SDRAM mode registers programmed appropriately.
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
Rev. 1.02, 2008-06
10
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Pin No.
Name
Pin
Buffer
Function
Type Type
233
DQS16
DQS17
DQS17
I/O
I/O
I/O
SSTL
SSTL
SSTL
Data Strobes Bus 17:0 and Complementary Data Strobe Bus 17:0
164
165
Data Mask
125
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Masks 8:0
The data write masks, associated with one data byte. In Write mode,
DM operates as a byte mask by allowing input data to be written if it is
LOW but blocks the write operation if it is HIGH. In Read mode, DM
lines have no effect.
134
146
155
202
Note: ×8 based module
211
223
232
164
EEPROM
120
SCL
SDA
I
CMOS
OD
Serial Bus Clock
This signal is used to clock data into and out of the SPD EEPROM.
119
I/O
Serial Bus Data
This is a bidirectional pin used to transfer data into or out of the SPD
EEPROM. A resistor must be connected from SDA to VDDSPD on the
motherboard to act as a pull-up.
239
240
101
Parity
55
SA0
SA1
SA2
I
I
I
CMOS
CMOS
CMOS
Serial Address Select Bus 2:0
These signals are tied at the system planar to either VSS or VDDSPD to
configure the serial SPD EEPROM address range
ERR_OUT
PAR_IN
O
I
CMOS
CMOS
Parity bits
Note: Only for modules with parity bit for address and control bus. Not
connected on non-parity registered modules.
68
Power Supplies
1
VREF
AI
—
—
I/O Reference Voltage
Reference voltage for the SSTL-18 inputs.
238
VDDSPD
PWR
EEPROM Power Supply
Serial EEPROM positive power supply, wired to a separated power pin
at the connector which supports from 1.7 Volt to 3.6 Volt.
51, 56, 62, 72, 75, VDDQ
78, 170, 175, 181,
191, 194
PWR
PWR
—
—
I/O Driver Power Supply
Power and ground for the DDR SDRAM
53, 59, 64, 67, 69, VDD
172, 178, 184, 187,
189, 197
Power Supply
Power and ground for the DDR SDRAM
Rev. 1.02, 2008-06
11
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Pin No.
Name
Pin
Buffer
Function
Type Type
2, 5, 8, 11, 14, 17, VSS
20, 23, 26, 29, 32,
35, 38, 41, 44, 47,
50, 65, 66, 79, 82,
85, 88, 91, 94, 97,
100, 103, 106, 109,
112, 115, 118, 121,
124, 127, 130, 133,
136, 139, 142, 145,
148, 151, 154, 157,
160, 163, 166, 169,
198, 201, 204, 207,
210, 213, 216, 219,
222, 225, 228, 231,
234, 237
GND —
Ground Plane
Power and ground for the DDR SDRAM
Other Pins
19, 102, 137, 138, NC
NC
—
Not connected
Pins not connected on Qimonda RDIMM’s
195
77
ODT0
I
I
SSTL
SSTL
On-Die Termination Control 1:0
Asserts on-die termination for DQ, DM, DQS, and DQS signals if
enabled via the DDR2 SDRAM mode register.
ODT1
Note: 2-Ranks module
NC
NC
—
Note: 1-Rank modules
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
CMOS
OD
Serial Stub Terminated Logic (SSTL_18)
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
Rev. 1.02, 2008-06
12
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
TABLE 7
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NU
NC
Ground
Not Usable
Not Connected
Rev. 1.02, 2008-06
13
07312007-HYD2-P177
ꢃ
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
FIGURE 1
Pin Configuration for RDIMM (240 pins)
95()
'4ꢀ
966
'46ꢀ
'4ꢈ
966
'4ꢇ
'46ꢁ
966
1&
'4ꢁꢀ
966
'4ꢁꢂ
'46ꢈ
966
'4ꢁꢇ
'4ꢈꢉ
966
'46ꢅ
'4ꢈꢊ
966
&%ꢁ
'46ꢋ
966
&%ꢅ
9''4
9''
1&ꢌ(35B287
ꢃ 3LQꢄꢀꢀꢁ
ꢃ 3LQꢄꢀꢀꢅ
ꢃ 3LQꢄꢀꢀꢆ
ꢃ 3LQꢄꢀꢀꢂ
ꢃ 3LQꢄꢀꢀꢇ
ꢃ 3LQꢄꢀꢁꢁ
ꢃ 3LQꢄꢀꢁꢅ
ꢃ 3LQꢄꢀꢁꢆ
ꢃ 3LQꢄꢀꢁꢂ
ꢃ 3LQꢄꢀꢁꢇ
3LQꢄꢁꢈꢁ ꢃ 966
3LQꢄꢁꢈꢈ ꢃ '4ꢉ
966
'4ꢁ
'46ꢀ ꢃ 3LQꢄꢀꢀꢊ
966
'4ꢅ
'4ꢋ
966
'46ꢁ ꢃ 3LQꢄꢀꢁꢊ
5(6(7 ꢃ 3LQꢄꢀꢁꢋ
ꢃ 3LQꢄꢀꢀꢈ
ꢃ 3LQꢄꢀꢀꢉ
3LQꢄꢁꢈꢅ ꢃ '4ꢆ
3LQꢄꢁꢈꢉ ꢃ 966
3LQꢄꢁꢈꢆ ꢃ '0ꢀꢌ'46ꢇ
3LQꢄꢁꢈꢊ ꢃ 1&ꢌ'46ꢇ
3LQꢄꢁꢈꢂ ꢃ 966
ꢃ 3LQꢄꢀꢀꢋ
ꢃ 3LQꢄꢀꢁꢀ
ꢃ 3LQꢄꢀꢁꢈ
ꢃ 3LQꢄꢀꢁꢉ
3LQꢄꢁꢈꢋ ꢃ '4ꢊ
3LQꢄꢁꢈꢇ ꢃ '4ꢂ
3LQꢄꢁꢅꢀ ꢃ 966
3LQꢄꢁꢅꢁ ꢃ '4ꢁꢈ
3LQꢄꢁꢅꢈ ꢃ '4ꢁꢅ
3LQꢄꢁꢅꢅ ꢃ 966
3LQꢄꢁꢅꢉ ꢃ '0ꢁꢌ'46ꢁꢀ
3LQꢄꢁꢅꢆ ꢃ 1&ꢌ'46ꢁꢀ
3LQꢄꢁꢅꢊ ꢃ 966
3LQꢄꢁꢅꢂ ꢃ 1&
3LQꢄꢁꢅꢇ ꢃ 966
3LQꢄꢁꢉꢁ ꢃ '4ꢁꢆ
3LQꢄꢁꢉꢅ ꢃ '4ꢈꢀ
3LQꢄꢁꢉꢆ ꢃ 966
3ꢄLQꢄꢁꢉꢂ ꢃ 1&ꢌ'46ꢁꢁ
3LQꢄꢁꢉꢇ ꢃ '4ꢈꢈ
3LQꢄꢁꢆꢁ ꢃ 966
3LQꢄꢁꢆꢅ ꢃ '4ꢈꢇ
3LQꢄꢁꢆꢆ ꢃ '0ꢅꢌ'46ꢁꢈ
3LQꢄꢁꢆꢂ ꢃ 966
3LQꢄꢁꢆꢇ ꢃ '4ꢅꢁ
3LQꢄꢁꢊꢁ ꢃ &%ꢉ
3LQꢄꢁꢊꢅ ꢃ 966
3LQꢄꢁꢊꢆ ꢃ 1&ꢌ'46ꢁꢂ
3LQꢄꢁꢊꢂ ꢃ &%ꢊ
3LQꢄꢁꢊꢇ ꢃ 966
3LQꢄꢁꢂꢁ ꢃ 1&ꢌ&.(ꢁ
3LQꢄꢁꢂꢅ ꢃ 1&ꢄꢌꢄ$ꢁꢆ
3LQꢄꢁꢂꢆ ꢃ 9''4
3LQꢄꢁꢂꢂ ꢃ $ꢇ
3LQꢄꢁꢂꢇ ꢃ $ꢋ
3LQꢄꢁꢋꢁ ꢃ 9''4
3LQꢄꢁꢋꢅ ꢃ $ꢁ
3LQꢄꢁꢅꢋ ꢃ 1&
3LQꢄꢁꢉꢀ ꢃ '4ꢁꢉ
ꢃ
3LQꢄꢁꢉꢈ 966
966
ꢃ 3LQꢄꢀꢈꢀ
ꢃ
ꢃ
3LQꢄꢀꢈꢁ
3LQꢄꢀꢈꢅ
ꢃ
ꢃ
'4ꢁꢁ
'4ꢁꢊ
966
'46ꢈ
'4ꢁꢋ
966
'4ꢈꢆ
'46ꢅ
966
'4ꢈꢂ
&%ꢀ
966
'46ꢋ
&%ꢈ
966
&.(ꢀ
3LQꢄꢀꢈꢈ
3LQꢄꢀꢈꢉ
ꢃ
3LQꢄꢁꢉꢉ '4ꢈꢁ
ꢃ 3LQꢄꢀꢈꢆ
3ꢄLQꢄꢀꢈꢂ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
3LQꢄꢁꢉꢊ '0ꢈꢌ'46ꢁꢁ
3LQꢄꢀꢈꢊ
3LQꢄꢀꢈꢋ
3LQꢄꢀꢅꢀ
3LQꢄꢀꢅꢈ
3LQꢄꢀꢅꢉ
3LQꢄꢀꢅꢊ
3LQꢄꢀꢅꢋ
3LQꢄꢀꢉꢀ
3LQꢄꢀꢉꢈ
3LQꢄꢀꢉꢉ
3LQꢄꢀꢉꢊ
3LQꢄꢀꢉꢋ
3LQꢄꢀꢆꢀ
3LQꢄꢀꢆꢈ
ꢃ
3LQꢄꢁꢉꢋ 966
ꢃ 3LQꢄꢀꢈꢇ
ꢃ 3LQꢄꢀꢅꢁ
ꢃ 3LQꢄꢀꢅꢅ
ꢃ 3LQꢄꢀꢅꢆ
ꢃ 3LQꢄꢀꢅꢂ
ꢃ 3LQꢄꢀꢅꢇ
ꢃ 3LQꢄꢀꢉꢁ
ꢃ 3LQꢄꢀꢉꢅ
ꢃ 3LQꢄꢀꢉꢆ
ꢃ 3LQꢄꢀꢉꢂ
ꢃ 3LQꢄꢀꢉꢇ
ꢃ 3LQꢄꢀꢆꢁ
ꢃ 3LQꢄꢀꢆꢅ
ꢃ 3LQꢄꢀꢆꢆ
ꢃ 3LQꢄꢀꢆꢂ
ꢃ 3LQꢄꢀꢆꢇ
ꢃ 3LQꢄꢀꢊꢁ
ꢃ 3LQꢄꢀꢊꢅ
ꢃ
3LQꢄꢁꢆꢀ '4ꢈꢅ
ꢃ
3LQꢄꢁꢆꢈ '4ꢈꢋ
ꢃ
3LQꢄꢁꢆꢉ 966
ꢃ
3LQꢄꢁꢆꢊ 1&ꢌ'46ꢁꢈ
ꢃ
3LQꢄꢁꢆꢋ '4ꢅꢀ
ꢃ
3LQꢄꢁꢊꢀ 966
ꢃ
3LQꢄꢁꢊꢈ &%ꢆ
ꢃ
3LQꢄꢁꢊꢉ '0ꢋꢌ'46ꢁꢂ
ꢃ
3LQꢄꢁꢊꢊ 966
ꢃ
3LQꢄꢁꢊꢋ &%ꢂ
ꢃ
3LQꢄꢁꢂꢀ 9''4
ꢃ
3LQꢄꢁꢂꢈ 9''
ꢃ
ꢃ
1&ꢌ%$ꢈ 3LQꢄꢀꢆꢉ
9''4
$ꢂ
$ꢆ
9''4
9''
3LQꢄꢁꢂꢉ 1&ꢌ$ꢁꢉ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
3LQꢄꢁꢂꢊ $ꢁꢈ
3LQꢄꢀꢆꢊ
3LQꢄꢀꢆꢋ
3LQꢄꢀꢊꢀ
3LQꢄꢀꢊꢈ
3LQꢄꢀꢊꢉ
$ꢁꢁ
9''
$ꢉ
ꢃ
3LQꢄꢁꢂꢋ 9''
ꢃ
3LQꢄꢁꢋꢀ $ꢊ
ꢃ
3LQꢄꢁꢋꢈ $ꢅ
$ꢈ
ꢃ
3LQꢄꢁꢋꢉ 9''
966
9''
9''
%$ꢀ
ꢃ 3LQꢄꢀꢊꢆ
ꢃ 3LQꢄꢀꢊꢂ
ꢃ 3LQꢄꢀꢊꢇ
ꢃ 3LQꢄꢀꢂꢁ
ꢃ 3LQꢄꢀꢂꢅ
ꢃ 3LQꢄꢀꢂꢆ
ꢃ 3LQꢄꢀꢂꢂ
ꢃ 3LQꢄꢀꢂꢇ
ꢃ 3LQꢄꢀꢋꢁ
ꢃ 3LQꢄꢀꢋꢅ
ꢃ 3LQꢄꢀꢋꢆ
ꢃ 3LQꢄꢀꢋꢂ
ꢃ 3LQꢄꢀꢋꢇ
ꢃ 3LQꢄꢀꢇꢁ
ꢃ 3LQꢄꢀꢇꢅ
ꢃ 3LQꢄꢀꢇꢆ
ꢃ 3LQꢄꢀꢇꢂ
ꢃ 3LQꢄꢀꢇꢇ
ꢃ 3LQꢄꢁꢀꢁ
ꢃ 3LQꢄꢁꢀꢅ
ꢃ 3LQꢄꢁꢀꢆ
ꢃ 3LQꢄꢁꢀꢂ
ꢃ 3LQꢄꢁꢀꢇ
ꢃ 3LQꢄꢁꢁꢁ
ꢃ 3LQꢄꢁꢁꢅ
ꢃ 3LQꢄꢁꢁꢆ
ꢃ 3LQꢄꢁꢁꢂ
ꢃ 3LQꢄꢁꢁꢇ
3LQꢄꢁꢋꢆ ꢃ &.ꢀ
3LQꢄꢁꢋꢂ ꢃ 9''
3LQꢄꢁꢋꢇ ꢃ 9''
3LQꢄꢁꢇꢁ ꢃ 9''4
3LQꢄꢁꢇꢅ ꢃ 6ꢀ
3LQꢄꢁꢇꢆ ꢃ 2'7ꢀ
3LQꢄꢁꢇꢂ ꢃ 9''
3LQꢄꢁꢇꢇ ꢃ '4ꢅꢊ
3LQꢄꢈꢀꢁ ꢃ 966
3LQꢄꢈꢀꢅ ꢃ 1&ꢌ'46ꢁꢅ
3LQꢄꢈꢀꢆ ꢃ '4ꢅꢋ
3LQꢄꢈꢀꢂ ꢃ 966
3LQꢄꢈꢀꢇ ꢃ '4ꢉꢆ
3LQꢄꢈꢁꢁ ꢃ '0ꢆꢌ'46ꢁꢉ
3LQꢄꢈꢁꢅ ꢃ 966
3LQꢄꢈꢁꢆ ꢃ '4ꢉꢂ
3LQꢄꢈꢁꢂ ꢃ '4ꢆꢈ
3LQꢄꢈꢁꢇ ꢃ 966
3LQꢄꢈꢈꢁ ꢃ 1&ꢌ6ꢅ
3LQꢄꢈꢈꢅ ꢃ '0ꢊꢌ'46ꢁꢆ
3LQꢄꢈꢈꢆ ꢃ 966
3LQꢄꢈꢈꢂ ꢃ '4ꢆꢆ
3LQꢄꢈꢈꢇ ꢃ '4ꢊꢀ
3LQꢄꢈꢅꢁ ꢃ 966
3LQꢄꢈꢅꢅ ꢃ 1&ꢌ'46ꢁꢊ
3LQꢄꢈꢅꢆ ꢃ '4ꢊꢈ
3LQꢄꢈꢅꢂ 966
3LQꢄꢈꢅꢇ 6$ꢀ
0337ꢀꢁꢂꢀ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
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ꢃ
ꢃ
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ꢃ
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ꢃ
ꢃ
ꢃ
3LQꢄꢁꢋꢊ &.ꢀ
966
3LQꢄꢀꢊꢊ
3LQꢄꢀꢊꢋ
3LQꢄꢀꢂꢀ
3LQꢄꢀꢂꢈ
3LQꢄꢀꢂꢉ
3LQꢄꢀꢂꢊ
3LQꢄꢀꢂꢋ
3LQꢄꢀꢋꢀ
3LQꢄꢀꢋꢈ
3LQꢄꢀꢋꢉ
3LQꢄꢀꢋꢊ
3LQꢄꢀꢋꢋ
3LQꢄꢀꢇꢀ
3LQꢄꢀꢇꢈ
3LQꢄꢀꢇꢉ
3LQꢄꢀꢇꢊ
3LQꢄꢀꢇꢋ
3LQꢄꢁꢀꢀ
3LQꢄꢁꢀꢈ
3LQꢄꢁꢀꢉ
3LQꢄꢁꢀꢊ
3LQꢄꢁꢀꢋ
3LQꢄꢁꢁꢀ
3LQꢄꢁꢁꢈ
3LQꢄꢁꢁꢉ
3LQꢄꢁꢁꢊ
3LQꢄꢁꢁꢋ
3LQꢄꢁꢈꢀ
1&ꢌ3$5B,1
ꢃ
3LQꢄꢁꢋꢋ $ꢀ
$ꢁꢀꢌ$3
9''4
&$6
1&ꢌ6ꢁ
9''4
'4ꢅꢈ
966
'46ꢉ
'4ꢅꢉ
966
'4ꢉꢁ
'46ꢆ
966
'4ꢉꢅ
'4ꢉꢋ
966
1&
'46ꢊ
966
'4ꢆꢁ
'4ꢆꢊ
966
'46ꢂ
'4ꢆꢋ
966
ꢃ
3LQꢄꢁꢇꢀ %$ꢁ
ꢃ
3LQꢄꢁꢇꢈ 5$6
:(
ꢃ
3LQꢄꢁꢇꢉ 9''4
9''4
1&ꢌ2'7ꢁ
966
'4ꢅꢅ
'46ꢉ
966
'4ꢅꢆ
'4ꢉꢀ
966
'46ꢆ
'4ꢉꢈ
966
'4ꢉꢇ
6$ꢈ
966
'46ꢊ
'4ꢆꢀ
966
'4ꢆꢂ
'46ꢂ
966
ꢃ
3LQꢄꢁꢇꢊ 1&ꢌ$ꢁꢅ
ꢃ
3LQꢄꢁꢇꢋ 966
ꢃ
3LQꢄꢈꢀꢀ '4ꢅꢂ
ꢃ
3LQꢄꢈꢀꢈ '0ꢉꢌ'46ꢁꢅ
ꢃ
3LQꢄꢈꢀꢉ 966
ꢃ
3LQꢄꢈꢀꢊ '4ꢅꢇ
ꢃ
3LQꢄꢈꢀꢋ '4ꢉꢉ
ꢃ
3LQꢄꢈꢁꢀ 966
ꢃ
3LQꢄꢈꢁꢈ 1&ꢌ'46ꢁꢉ
ꢃ
3LQꢄꢈꢁꢉ '4ꢉꢊ
ꢃ
3LQꢄꢈꢁꢊ 966
ꢃ
3LQꢄꢈꢁꢋ '4ꢆꢅ
ꢃ
3LQꢄꢈꢈꢀ 1&ꢌ6ꢈ
ꢃ
3LQꢄꢈꢈꢈ 966
ꢃ
3LQꢄꢈꢈꢉ 1&ꢌ'46ꢁꢆ
ꢃ
3LQꢄꢈꢈꢊ '4ꢆꢉ
ꢃ
3LQꢄꢈꢈꢋ 966
ꢃ
3LQꢄꢈꢅꢀ '4ꢊꢁ
ꢃ
3LQꢄꢈꢅꢈ '0ꢂꢌ'46ꢁꢊ
ꢃ
3LQꢄꢈꢅꢉ 966
ꢃ
3LQꢄꢈꢅꢊ '4ꢊꢅ
'4ꢆꢇ
6'$
3LQꢄꢈꢅꢋ 9''63'
3LQꢄꢈꢉꢀ 6$ꢁ
6&/
Rev. 1.02, 2008-06
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Registered DDR2 SDRAM Modules
3
Electrical Characteristics
This chapter contains speed grade definition, AC timing parameter and ODT tables.
3.1
Absolute Maximum Ratings
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 8
Absolute Maximum Ratings
Symbol
Parameter
Rating
Min.
Unit
Note
Max.
1)
VDD
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
–1.0
–0.5
–0.5
–0.5
+2.3
+2.3
+2.3
+2.3
V
V
V
V
VDDQ
VDDL
VIN, VOUT
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
TABLE 9
Environmental Requirements
Parameter
Symbol
Values
Min.
Unit
Note
Max.
1)
2)
3)
Operating temperature (ambient)
Storage Temperature
TOPR
TSTG
PBar
HOPR
HSTG
–
–
°C
°C
kPa
%
– 50
+69
10
5
+100
+105
90
Barometric Pressure (operating & storage)
Operating Humidity (relative)
Storage Humidity (without condensation)
95
%
1) The application designer must meet the case temperature specifications for individual module components.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
3) Up to 3000 m.
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TABLE 10
DRAM Component Operating Temperature Range
Symbol
Parameter
Rating
Unit
Note
Min.
Max.
1)2)3)4)
TCASE
Operating Temperature
0
95
°C
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 μs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
3.2
DC Operating Conditions
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Values
Min.
Unit
Note
Typ.
Max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
DC Input Logic High
DC Input Logic Low
VDD
1.7
1.8
1.9
V
V
V
V
V
V
V
V
μA
1)
2)
VDDQ
VREF
1.7
1.8
1.9
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
VDDSPD
VIH(DC)
VIL (DC
VIH(AC)
VIL (AC
IL
1.7
—
—
—
—
—
—
3.6
V
REF + 0.125
V
V
V
V
5
DDQ + 0.3
)
– 0.30
REF – 0.125
DDQ + VPEAK
REF –0.200
AC Input Logic High
AC Input Logic Low
V
V
REF + 0.200
SSQ – VPEAK
)
3)
In / Output Leakage Current
– 5
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
.
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3.3
Speed Grade Definitions
TABLE 12
Speed Grade Definition
Speed Grade
DDR2–800D
–25F
DDR2–800E
–2.5
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
Parameter
5–5–5
Min.
6–6–6
tCK
Symbol
Max.
Min.
Max.
—
1)2)3)4)
Clock Period
@ CL = 3
tCK
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
@ CL = 4
@ CL = 5
@ CL = 6
tCK
3.75
2.5
2.5
45
8
3.75
3
8
1)2)3)4)
tCK
8
8
1)2)3)4)
tCK
8
2.5
45
40
60
55
15
15
8
1)2)3)4)5)6)
1)2)3)4)5)7)
1)2)3)4)6)
1)2)3)4)7)
1)2)3)4)
Row Active Time
Row Active Time
Row Cycle Time
Row Cycle Time
RAS-CAS-Delay
tRAS
tRAS
tRC
tRC
tRCD
tRP
70k
70k
—
—
—
—
70k
70k
—
—
—
—
40
57.5
52.5
12.5
12.5
1)2)3)4)
Row Precharge Time
TABLE 13
Speed Grade Definition
Speed Grade
DDR2–667C
–3
DDR2–667D
–3S
DDR2–533C
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
Parameter
–3.7
4–4–4
5–5–5
4–4–4
tCK
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
—
1)2)3)4)
Clock Period
@ CL = 3
@ CL = 4
@ CL = 5
tCK
5
8
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
tCK
3
8
3.75
3
8
3.75
3.75
45
8
1)2)3)4)
tCK
3
8
8
8
1)2)3)4)5)6)
1)2)3)4)5)7)
1)2)3)4)6)
1)2)3)4)7)
1)2)3)4)
Row Active Time
Row Active Time
Row Cycle Time
Row Cycle Time
RAS-CAS-Delay
tRAS
tRAS
tRC
45
40
57
52
12
12
70k
70k
—
—
—
—
45
40
60
55
15
15
70k
70k
—
—
—
—
70k
70k
—
—
—
—
40
60
tRC
55
tRCD
tRP
15
1)2)3)4)
Row Precharge Time
15
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
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2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
6) Products released after 2007-08-01 can support tRAS.MIN = 40 ns for all DDR2 speed sort.
7) For products released after 2007-08-01.
.
3.4
Component AC Timing Parameters
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667
Parameter
Symbol DDR2–800
DDR2–667
Unit
Note1)2)3
)4)5)6)7)
Min.
Max.
Min.
Max.
CAS to CAS command delay
Average clock high pulse width
Average clock period
tCCD
2
—
2
—
nCK
tCK.AVG
ps
9)10)
11)
tCH.AVG
tCK.AVG
0.48
2500
3
0.52
8000
—
0.48
3000
3
0.52
8000
—
CKE minimum pulse width ( high and tCKE
nCK
low pulse width)
9)10)
Average clock low pulse width
tCL.AVG
tDAL
0.48
0.52
—
0.48
0.52
—
tCK.AVG
12)13)
Auto-Precharge write recovery +
precharge time
WR + tnRP
WR + tnRP
nCK
Minimum time clocks remain ON after tDELAY
CKE asynchronously drops LOW
tIS + tCK .AVG ––
+ tIH
tIS +
tCK .AVG + tIH
––
ns
14)18)19)
DQ and DM input hold time
tDH.BASE
125
––
—
175
––
—
ps
DQ and DM input pulse width for each tDIPW
0.35
0.35
tCK.AVG
input
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
0.35
0.35
—
—
0.35
0.35
—
—
tCK.AVG
tCK.AVG
ps
—
—
15)
16)
DQS-DQ skew for DQS & associated tDQSQ
200
240
DQ signals
DQS latching rising transition to
associated clock edges
tDQSS
– 0.25
+ 0.25
– 0.25
+ 0.25
tCK.AVG
17)18)19)
16)
DQ and DM input setup time
tDS.BASE
50
––
—
—
__
100
––
—
—
__
ps
DQS falling edge hold time from CK tDSH
0.2
0.2
tCK.AVG
tCK.AVG
ps
16)
DQS falling edge to CK setup time
CK half pulse width
tDSS
tHP
0.2
0.2
20)
Min(tCH.ABS
,
Min(tCH.ABS,
tCL.ABS
)
tCL.ABS)
8)21)
Data-out high-impedance time from tHZ
CK / CK
—
tAC.MAX
—
tAC.MAX
ps
22)24)
Address and control input hold time tIH.BASE
250
0.6
—
—
275
0.6
—
—
ps
Control & address input pulse width tIPW
tCK.AVG
for each input
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Registered DDR2 SDRAM Modules
Parameter
Symbol DDR2–800
Min.
DDR2–667
Min.
Unit
Note1)2)3
)4)5)6)7)
Max.
Max.
23)24)
8)21)
8)21)
Address and control input setup time tIS.BASE
DQ low impedance time from CK/CK tLZ.DQ
175
—
200
—
ps
ps
ps
2 x tAC.MIN
tAC.MIN
tAC.MAX
tAC.MAX
2 x tAC.MIN
tAC.MIN
tAC.MAX
tAC.MAX
DQS/DQS low-impedance time from tLZ.DQS
CK / CK
34)
MRS command to ODT update delay tMOD
0
2
12
—
0
2
12
—
ns
Mode register set command cycle
time
tMRD
nCK
34)
OCD drive mode output delay
tOIT
0
12
0
12
ns
ps
ps
μs
μs
ns
25)
DQ/DQS output hold time from DQS tQH
tHP – tQHS
—
t
HP – tQHS
—
26)
DQ hold skew factor
tQHS
tREFI
—
300
7.8
3.9
—
—
340
7.8
3.9
—
27)28)
27)29)
30)
Average periodic refresh Interval
—
—
—
—
Auto-Refresh to Active/Auto-Refresh tRFC
105
105
command period
31)32)
31)33)
34)
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
7.5
1.1
0.6
—
0.9
0.4
7.5
1.1
0.6
—
tCK.AVG
tCK.AVG
ns
Active to active command period for tRRD
1KB page size products
34)
Internal Read to Precharge command tRTP
7.5
—
7.5
—
ns
delay
Write preamble
tWPRE
tWPST
tWR
0.35
0.4
—
0.6
—
—
—
—
0.35
0.4
—
0.6
—
—
—
—
tCK.AVG
tCK.AVG
ns
Write postamble
Write recovery time
34)
15
15
34)35)
Internal write to read command delay tWTR
Exit power down to read command tXARD
7.5
7.5
ns
2
2
nCK
nCK
Exit active power-down mode to read tXARDS
8 – AL
7 – AL
command (slow exit, lower power)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
tXP
2
—
2
—
nCK
ns
34)
Exit self-refresh to a non-read
command
tXSNR
tRFC +10
—
—
t
RFC +10
—
—
Exit self-refresh to read command
tXSRD
200
200
nCK
nCK
Write command to DQS associated
clock edges
WL
RL – 1
RL–1
1) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
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6) The output timing reference voltage level is VTT.
7) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
t
DQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
9) Input clock jitter spec parameter. The jitter specified is a random jitter meeting a Gaussian distribution.
10) These parameters are specified per their average values.
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
12) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
13) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
14) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
V
IH.DC.MIN. See Figure 3.
15) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
17) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 3.
18) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
20) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
21) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
22) input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 4.
23) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 4.
24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
25) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
26) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
27) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
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Registered DDR2 SDRAM Modules
28) 0 °C≤ TCASE ≤ 85 °C.
29) 85 °C < TCASE ≤ 95 °C.
30) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between
any Refresh command and the next Refresh command is 9 x tREFI
.
31) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
t
nRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
35) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
36) This timing parameter is relaxed than Industry Standard
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Registered DDR2 SDRAM Modules
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Notes1)2)3)4)5)
6)
Min.
Max.
CAS A to CAS B command period
CK, CK high-level width
tCCD
tCH
2
—
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width tCKE
CK, CK low-level width
tCL
0.45
WR + tRP
0.55
—
7)
Auto-Precharge write recovery +
precharge time
tDAL
8)
Minimum time clocks remain ON after
CKE asynchronously drops LOW
tDELAY
tIS + tCK + tIH
225
––
––
—
—
ns
ps
ps
tCK
9)
DQ and DM input hold time (differential tDH.BASE
data strobe)
10)
DQ and DM input hold time (single ended tDH1.BASE
data strobe)
–25
DQ and DM input pulse width (each
input)
tDIPW
0.35
DQS input HIGH pulse width (write cycle) tDQSH
DQS input LOW pulse width (write cycle) tDQSL
0.35
0.35
—
—
tCK
tCK
ps
—
10)
DQS-DQ skew (for DQS & associated
DQ signals)
tDQSQ
300
Write command to 1st DQS latching
transition
tDQSS
– 0.25
100
–25
0.2
+ 0.25
—
tCK
ps
10)
10)
DQ and DM input setup time (differential tDS.BASE
data strobe)
DQ and DM input setup time (single
ended data strobe)
tDS1.BASE
tDSH
—
ps
DQS falling edge hold time from CK
(write cycle)
—
tCK
tCK
DQS falling edge to CK setup time (write tDSS
0.2
—
cycle)
11)
12)
Clock half period
tHP
MIN. (tCL, tCH)
Data-out high-impedance time from CK / tHZ
—
tAC.MAX
ps
CK
10)
Address and control input hold time
tIH.BASE
375
0.6
—
—
ps
Address and control input pulse width
(each input)
tIPW
tCK
10)
13)
13)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
tIS.BASE
tLZ(DQ)
tLZ(DQS)
tMOD
250
—
ps
ps
ps
ns
tCK
ns
2 × tAC.MIN
tAC.MAX
tAC.MAX
12
tAC.MIN
0
2
0
tMRD
—
tOIT
12
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–533
Min.
Unit
Notes1)2)3)4)5)
6)
Max.
Data output hold time from DQS
Data hold skew factor
tQH
t
HP –tQHS
—
tQHS
tREFI
tREFI
tRFC
—
400
7.8
3.9
—
ps
μs
μs
ns
13)14)
15)17)
16)
Average periodic refresh Interval
Average periodic refresh Interval
—
—
Auto-Refresh to Active/Auto-Refresh
command period
105
13)
Read preamble
Read postamble
tRPRE
tRPST
0.9
1.1
0.60
—
tCK
tCK
ns
13)
0.40
7.5
13)17)
Active bank A to Active bank B command tRRD
period for 1 KB page size
Internal Read to Precharge command
delay
tRTP
7.5
—
ns
Write preamble
Write postamble
tWPRE
tWPST
tWR
0.25
0.40
15
—
tCK
tCK
ns
18)
0.60
—
Write recovery time for write without
Auto-Precharge
19)
20)
Internal Write to Read command delay
tWTR
7.5
2
—
—
ns
Exit power down to any valid command tXARD
tCK
(other than NOP or Deselect)
20)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
6 – AL
2
—
—
tCK
tCK
Exit precharge power-down to any valid tXP
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command tXSNR
t
RFC +10
200
WR/tCK
—
—
ns
Exit Self-Refresh to Read command
tXSRD
tCK
tCK
21)
Write recovery time for write with Auto-
Precharge
WR
t
1) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
9) For timing definition, refer to the Component data sheet.
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
14) 0 °C≤ TCASE ≤ 85 °C.
15) 85 °C < TCASE ≤ 95 °C.
16) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between
any Refresh command and the next Refresh command is 9 x tREFI
.
17) The tRRD timing parameter depends on the page size of the DRAM organization.
18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
21) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
FIGURE 2
Method for Calculating Transitions and Endpoint
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Rev. 1.02, 2008-06
07312007-HYD2-P177
24
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
FIGURE 3
Differential Input Waveform Timing tDS and tDH
'46
'46
W'6
W'6
W'+
W'+
9''4
'4
9,+ꢍ$&ꢍ0,1
9,+ꢍ'&ꢍ0,1
95()
9,/ꢍ'&ꢍ0$;
9,/ꢍ$&ꢍ0$;
966
03(7ꢀꢅꢅꢁ
FIGURE 4
Differential Input Waveform Timing tlS and tlH
&.
&.
W,6
W,+
W,6
W,+
9''4
9,+ꢍ$&ꢍ0,1
&0'
$GGUHVV
9,+ꢍ'&ꢍ0,1
95()
9,/ꢍ'&ꢍ0$;
9,/ꢍ$&ꢍ0$;
966
03(7ꢀꢈꢈꢀ
Rev. 1.02, 2008-06
07312007-HYD2-P177
25
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
3.5
ODT AC Electrical Characteristics
This chapter describes the ODT AC electrical characteristics.
TABLE 16
ODT AC Characteristics and Operating Conditions for DDR2-667 , DDR2-800
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
1)
tAOND
tAON
ODT turn-on delay
2
2
nCK
ns
1)2)
1)
ODT turn-on
tAC.MIN
tAC.MAX + 0.7 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK + tAC.MAX + 1 ns
ns
1)
2.5
2.5
nCK
ns
1)3)
1)
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK + tAC.MAX + 1 ns ns
1)
3
8
—
—
nCK
nCK
1)
1) New units, “tCK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800 Unit “tCK.AVG” represents the actual tCK.AVG of the input clock
under operation. Unit “nCK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “tCK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800 tAOND is
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed,
t
AOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by
counting the actual input clock edges.
TABLE 17
ODT AC Characteristics and Operating Conditions for DDR2-533
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
tAOND
tAON
ODT turn-on delay
2
2
tCK
ns
ns
tCK
ns
ns
tCK
tCK
1)
2)
ODT turn-on
tAC.MIN
tAC.MAX + 1 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK + tAC.MAX + 1 ns
2.5
2.5
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK + tAC.MAX + 1 ns
3
8
—
—
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
3.6
IDD Specifications and Conditions
List of tables defining IDD Specifications and Conditions.
TABLE 18
DD Measurement Conditions
I
Parameter
Symbol Note1)2)
3)4)5)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
6)
Operating Current 1
IDD1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN
,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
IDD2Q
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Standby Current
IDD3N
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
IDD3P(0)
IDD3P(1)
IDD4R
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
6)
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX
;
t
RP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write
IDD4W
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
IDD5B
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Parameter
Symbol Note1)2)
3)4)5)
Distributed Refresh Current
IDD5D
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
6)
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
2)
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
I
DD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 19
4) For two rank modules: All active current measurements in the same IDD current mode. The other rank is in IDD2P Precharge Power-Down
Mode.
5) For details and notes see the relevant Qimonda component data sheet.
6)
I
DD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 19
Definitions for IDD
Parameter
LOW
Description
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
Inputs are stable at a HIGH or LOW level.
Inputs are VREF = VDDQ /2
STABLE
FLOATING
SWITCHING
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes.
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
TABLE 20
DD Specification for HYS72T[64/128/256]xx0EP–2.5–B2
I
Product Type
Unit
Note1)2)
Organization
512 MB
1 Rank
×72
1 GB
1 Rank
×72
1 GB
2 Ranks
×72
2 GB
2 Ranks
×72
-2.5
-2.5
-2.5
-2.5
Symbol
Max.
Max.
Max.
Max.
3)
IDD0
1060
1186
502
1940
2192
824
1382
1508
824
2084
2336
968
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)
IDD1
4)
IDD2P
4)
IDD2N
880
1580
1436
1220
896
1580
1436
1220
896
2480
2192
1760
1112
2660
3434
3434
3254
1004
252
4)
IDD2Q
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD3N
808
4)5)
4)6)
4)
700
538
925
1670
3290
3290
3110
842
1670
2057
2057
1967
842
3)
IDD4R
1735
1735
1645
511
3)
IDD4W
IDD5B
3)
4)7)
4)7)
3)
IDD5D
IDD6
63
126
126
IDD7
1807
3434
2129
3578
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
TABLE 21
DD Specification for HYS72T[64/128/256]xx0EP–25F–B2
I
Product Type
Unit
Note1)2)
Organization
512 MB
1 Rank
×72
1 GB
1 Rank
×72
1 GB
2 Ranks
×72
2 GB
2 Ranks
×72
-25F
-25F
-25F
-25F
Symbol
Max.
Max.
Max.
Max.
3)
IDD0
1132
1195
502
2084
2210
824
1454
1517
824
2228
2354
968
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)
IDD1
4)
IDD2P
4)
IDD2N
880
1580
1436
1220
896
1580
1436
1220
896
2480
2192
1760
1112
2660
3434
3434
3254
1004
252
4)
IDD2Q
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD3N
808
4)5)
4)6)
4)
700
538
925
1670
3290
3290
3110
842
1670
2057
2057
1967
842
3)
IDD4R
1735
1735
1645
511
3)
IDD4W
IDD5B
3)
4)7)
4)7)
3)
IDD5D
IDD6
63
126
126
IDD7
1825
3470
2147
3614
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
TABLE 22
DD Specification for HYS72T[64/128/256]xx0EP–3–B2
I
Product Type
Unit
Note1)2)
Organization
512 MB
1 Rank
×72
1 GB
1 Rank
×72
1 GB
2 Ranks
×72
2 GB
2 Ranks
×72
-3
-3
-3
-3
Symbol
Max.
Max.
Max.
Max.
3)
IDD0
1015
1078
457
1855
1981
739
1297
1360
739
1999
2125
883
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)
IDD1
4)
IDD2P
4)
IDD2N
745
1315
1279
1099
811
1315
1279
1099
811
2035
1963
1603
1027
2323
2989
2989
2989
919
4)
IDD2Q
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD3N
727
4)5)
4)6)
4)
637
493
817
1459
2845
2845
2845
757
1459
1792
1792
1792
757
3)
IDD4R
1510
1510
1510
466
3)
IDD4W
IDD5B
3)
4)7)
4)7)
3)
IDD5D
IDD6
63
126
126
252
IDD7
1735
3295
2017
3439
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
TABLE 23
DD Specification for HYS72T[64/128/256]xx0EP–3S–B2
I
Product Type
Unit
Note1)2)
Organization
512 MB
1 Rank
×72
1 GB
1 Rank
×72
1 GB
2 Ranks
×72
2 GB
2 Ranks
×72
-3S
-3S
-3S
-3S
Symbol
Max.
Max.
Max.
Max.
3)
IDD0
1006
1069
457
1837
1963
739
1288
1351
739
1981
2107
883
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)
IDD1
4)
IDD2P
4)
IDD2N
745
1315
1279
1099
811
1315
1279
1099
811
2035
1963
1603
1027
2323
2989
2989
2989
919
4)
IDD2Q
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD3N
727
4)5)
4)6)
4)
637
493
817
1459
2845
2845
2845
757
1459
1792
1792
1792
757
3)
IDD4R
1510
1510
1510
466
3)
IDD4W
IDD5B
3)
4)7)
4)7)
3)
IDD5D
IDD6
63
126
126
252
IDD7
1717
3259
1999
3403
Rev. 1.02, 2008-06
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
TABLE 24
DD Specification for HYS72T[64/128/256]xx0EP–3.7–B2
I
Product Type
Unit
Note1)2)
Organization
512 MB
1 Rank
×72
1 GB
1 Rank
×72
1 GB
2 Ranks
×72
2 GB
2 Ranks
×72
-3.7
-3.7
-3.7
-3.7
Symbol
Max.
Max.
Max.
Max.
3)
IDD0
915
1005
402
654
645
555
438
690
1275
1275
1410
411
63
1670
1850
644
1157
1247
644
1814
1994
788
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)
IDD1
4)
IDD2P
4)
IDD2N
1148
1130
950
1148
1130
950
1796
1760
1400
932
4)
IDD2Q
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD3N
4)5)
4)6)
4)
716
716
1220
2390
2390
2660
662
1220
1517
1517
1652
662
1940
2534
2534
2804
824
3)
IDD4R
3)
IDD4W
IDD5B
3)
4)7)
4)7)
3)
IDD5D
IDD6
126
126
252
IDD7
1590
3020
1832
3164
1) Module IDD is calculated on the basis of component IDD and includes currents of Registers and PLL. ODT disabled. IDD1,
I
DD4R, and IDD7,
are defined with the outputs disabled.
2) IDDX (rank) = Number of components x IDDX (component)
3) IDDX = IDDX (rank) + IDD2P (rank)
4) IDDX = 2 x IDDX (rank)
5) Fast: MRS(12)=0
6) Slow: MRS(12)=1
7) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.02, 2008-06
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Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
•
•
Table 25 “HYS72T[64/128/256]xx0EP-2.5-B2” on Page 34
Table 26 “HYS72T[64/128/256]xx0EP-25F-B2” on Page 39
Table 27 “HYS72T[64/128/256]xx0EP-3-B2” on Page 44
Table 28 “HYS72T[64/128/256]xx0EP-3S-B2” on Page 48
Table 29 “HYS72T[64/128/256]xx0EP-3.7-B2” on Page 52
TABLE 25
HYS72T[64/128/256]xx0EP-2.5-B2
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
6400P–666 6400P–666 6400P–666 6400P–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
1
2
3
4
5
6
7
8
9
10
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
60
48
00
05
25
40
80
08
08
0E
0B
60
48
00
05
25
40
80
08
08
0E
0A
61
48
00
05
25
40
80
08
08
0E
0B
61
48
00
05
25
40
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
Not used
Interface Voltage Level
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
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Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
6400P–666 6400P–666 6400P–666 6400P–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
06
82
08
08
00
0C
04
70
01
01
04
07
30
45
3D
50
3C
1E
3C
2D
80
17
25
05
12
06
82
04
04
00
0C
04
70
01
01
05
07
30
45
3D
50
3C
1E
3C
2D
01
17
25
05
12
06
82
08
08
00
0C
04
70
01
01
05
07
30
45
3D
50
3C
1E
3C
2D
80
17
25
05
12
06
82
04
04
00
0C
04
70
01
01
05
07
30
45
3D
50
3C
1E
3C
2D
01
17
25
05
12
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
Rev. 1.02, 2008-06
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Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
6400P–666 6400P–666 6400P–666 6400P–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
t
t
t
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
3C
1E
1E
00
00
3C
69
80
14
1E
0F
50
7A
5B
34
36
2E
5A
2A
5A
22
25
C4
8C
70
3C
1E
1E
00
00
3C
69
80
14
1E
0F
50
7A
5B
34
36
2E
5A
2A
5A
22
25
C4
8C
70
3C
1E
1E
00
00
3C
69
80
14
1E
0F
50
7A
5B
34
36
2E
5A
2A
5A
22
25
C4
8C
70
3C
1E
1E
00
00
3C
69
80
14
1E
0F
50
7A
5B
34
36
2E
5A
2A
5A
22
25
C4
8C
70
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ΔT4R4W Delta
T
Psi(T-A) DRAM
ΔT0 (DT0)
ΔT2N (DT2N, UDIMM) or ΔT2Q (DT2Q, RDIMM)
ΔT2P (DT2P)
ΔT3N (DT3N)
ΔT3P.fast (DT3P fast)
ΔT3P.slow (DT3P slow)
ΔT4R (DT4R) / ΔT4R4W Sign (DT4R4W)
ΔT5B (DT5B)
ΔT7 (DT7)
Psi(ca) PLL
Psi(ca) REG
ΔTPLL (DTPLL)
Rev. 1.02, 2008-06
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07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
6400P–666 6400P–666 6400P–666 6400P–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
ΔTREG (DTREG) / Toggle Rate
SPD Revision
B0
12
B9
7F
7F
7F
7F
7F
51
00
00
xx
B0
12
34
7F
7F
7F
7F
7F
51
00
00
xx
B0
12
BB
7F
7F
7F
7F
7F
51
00
00
xx
B0
12
35
7F
7F
7F
7F
7F
51
00
00
xx
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
37
32
54
36
34
30
30
30
45
50
32
2E
35
37
32
54
31
32
38
30
30
30
45
50
32
2E
37
32
54
31
32
38
30
32
30
45
50
32
2E
37
32
54
32
35
36
32
32
30
45
50
32
2E
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Rev. 1.02, 2008-06
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Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
6400P–666 6400P–666 6400P–666 6400P–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
86
87
88
89
90
91
92
93
94
Product Type, Char 14
42
32
20
20
20
3x
xx
xx
xx
xx
00
FF
35
42
32
20
20
3x
xx
xx
xx
xx
00
FF
35
42
32
20
20
3x
xx
xx
xx
xx
00
FF
35
42
32
20
20
4x
xx
xx
xx
xx
00
FF
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
Rev. 1.02, 2008-06
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
TABLE 26
HYS72T[64/128/256]xx0EP-25F-B2
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
6400P–555 6400P–555 6400P–555 6400P–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
60
48
00
05
25
40
06
82
08
08
00
0C
04
70
01
01
04
80
08
08
0E
0B
60
48
00
05
25
40
06
82
04
04
00
0C
04
70
01
01
05
80
08
08
0E
0A
61
48
00
05
25
40
06
82
08
08
00
0C
04
70
01
01
05
80
08
08
0E
0B
61
48
00
05
25
40
06
82
04
04
00
0C
04
70
01
01
05
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
tCK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Rev. 1.02, 2008-06
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07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
6400P–555 6400P–555 6400P–555 6400P–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Component Attributes
07
25
40
3D
50
32
1E
32
2D
80
17
25
05
12
3C
1E
1E
00
30
39
69
80
14
1E
0F
07
25
40
3D
50
32
1E
32
2D
01
17
25
05
12
3C
1E
1E
00
30
39
69
80
14
1E
0F
07
25
40
3D
50
32
1E
32
2D
80
17
25
05
12
3C
1E
1E
00
30
39
69
80
14
1E
0F
07
25
40
3D
50
32
1E
32
2D
01
17
25
05
12
3C
1E
1E
00
30
39
69
80
14
1E
0F
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
Rev. 1.02, 2008-06
40
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
6400P–555 6400P–555 6400P–555 6400P–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
CASE.MAX Delta / ΔT4R4W Delta
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
T
50
7A
5F
34
36
2E
5A
2A
5A
22
27
C4
8C
70
B0
12
C8
7F
7F
7F
7F
7F
51
00
00
50
7A
5F
34
36
2E
5A
2A
5A
22
27
C4
8C
70
B0
12
43
7F
7F
7F
7F
7F
51
00
00
50
7A
5F
34
36
2E
5A
2A
5A
22
27
C4
8C
70
B0
12
CA
7F
7F
7F
7F
7F
51
00
00
50
7A
5F
34
36
2E
5A
2A
5A
22
27
C4
8C
70
B0
12
44
7F
7F
7F
7F
7F
51
00
00
Psi(T-A) DRAM
ΔT0 (DT0)
ΔT2N (DT2N, UDIMM) or ΔT2Q (DT2Q, RDIMM)
ΔT2P (DT2P)
ΔT3N (DT3N)
ΔT3P.fast (DT3P fast)
ΔT3P.slow (DT3P slow)
ΔT4R (DT4R) / ΔT4R4W Sign (DT4R4W)
ΔT5B (DT5B)
ΔT7 (DT7)
Psi(ca) PLL
Psi(ca) REG
ΔTPLL (DTPLL)
ΔTREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Rev. 1.02, 2008-06
41
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
6400P–555 6400P–555 6400P–555 6400P–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Module Manufacturer Location
Product Type, Char 1
xx
37
32
54
36
34
30
30
30
45
50
32
35
46
42
32
20
20
20
3x
xx
xx
xx
xx
xx
37
32
54
31
32
38
30
30
30
45
50
32
35
46
42
32
20
20
3x
xx
xx
xx
xx
xx
37
32
54
31
32
38
30
32
30
45
50
32
35
46
42
32
20
20
3x
xx
xx
xx
xx
xx
37
32
54
32
35
36
32
32
30
45
50
32
35
46
42
32
20
20
4x
xx
xx
xx
xx
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
Rev. 1.02, 2008-06
42
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
6400P–555 6400P–555 6400P–555 6400P–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
99 - 127 Not used
00
FF
00
FF
00
FF
00
FF
128 -
255
Blank for customer use
Rev. 1.02, 2008-06
43
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
TABLE 27
HYS72T[64/128/256]xx0EP-3-B2
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
5300P–444 5300P–444 5300P–444 5300P–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
60
48
00
05
30
45
06
82
08
08
00
0C
04
38
01
01
04
07
80
08
08
0E
0B
60
48
00
05
30
45
06
82
04
04
00
0C
04
38
01
01
05
07
80
08
08
0E
0A
61
48
00
05
30
45
06
82
08
08
00
0C
04
38
01
01
05
07
80
08
08
0E
0B
61
48
00
05
30
45
06
82
04
04
00
0C
04
38
01
01
05
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
tCK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 1.02, 2008-06
44
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
5300P–444 5300P–444 5300P–444 5300P–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
30
45
50
60
30
1E
30
2D
80
20
27
10
17
3C
1E
1E
00
00
39
69
80
18
22
0F
50
7A
30
45
50
60
30
1E
30
2D
01
20
27
10
17
3C
1E
1E
00
00
39
69
80
18
22
0F
50
7A
30
45
50
60
30
1E
30
2D
80
20
27
10
17
3C
1E
1E
00
00
39
69
80
18
22
0F
50
7A
30
45
50
60
30
1E
30
2D
01
20
27
10
17
3C
1E
1E
00
00
39
69
80
18
22
0F
50
7A
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ΔT4R4W Delta
Psi(T-A) DRAM
T
Rev. 1.02, 2008-06
45
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
5300P–444 5300P–444 5300P–444 5300P–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
ΔT0 (DT0)
53
2E
36
27
4C
2A
4C
20
25
C4
8C
68
94
12
65
7F
7F
7F
7F
7F
51
00
00
xx
53
2E
36
27
4C
2A
4C
20
25
C4
8C
68
94
12
E0
7F
7F
7F
7F
7F
51
00
00
xx
53
2E
36
27
4C
2A
4C
20
25
C4
8C
68
94
12
67
7F
7F
7F
7F
7F
51
00
00
xx
53
2E
36
27
4C
2A
4C
20
25
C4
8C
68
94
12
E1
7F
7F
7F
7F
7F
51
00
00
xx
ΔT2N (DT2N, UDIMM) or ΔT2Q (DT2Q, RDIMM)
ΔT2P (DT2P)
ΔT3N (DT3N)
ΔT3P.fast (DT3P fast)
ΔT3P.slow (DT3P slow)
ΔT4R (DT4R) / ΔT4R4W Sign (DT4R4W)
ΔT5B (DT5B)
ΔT7 (DT7)
Psi(ca) PLL
Psi(ca) REG
ΔTPLL (DTPLL)
ΔTREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
37
32
37
32
37
32
37
32
Product Type, Char 2
Rev. 1.02, 2008-06
46
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
5300P–444 5300P–444 5300P–444 5300P–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 3
54
36
34
30
30
30
45
50
33
42
32
20
20
20
20
20
2x
xx
54
31
32
38
30
30
30
45
50
33
42
32
20
20
20
20
2x
xx
xx
xx
xx
00
FF
54
31
32
38
30
32
30
45
50
33
42
32
20
20
20
20
2x
xx
xx
xx
xx
00
FF
54
32
35
36
32
32
30
45
50
33
42
32
20
20
20
20
3x
xx
xx
xx
xx
00
FF
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
00
FF
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
Rev. 1.02, 2008-06
47
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
TABLE 28
HYS72T[64/128/256]xx0EP-3S-B2
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
5300P–555 5300P–555 5300P–555 5300P–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
60
48
00
05
30
45
06
82
08
08
00
0C
04
38
01
01
04
07
80
08
08
0E
0B
60
48
00
05
30
45
06
82
04
04
00
0C
04
38
01
01
05
07
80
08
08
0E
0A
61
48
00
05
30
45
06
82
08
08
00
0C
04
38
01
01
05
07
80
08
08
0E
0B
61
48
00
05
30
45
06
82
04
04
00
0C
04
38
01
01
05
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
tCK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 1.02, 2008-06
48
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
5300P–555 5300P–555 5300P–555 5300P–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
3D
50
50
60
3C
1E
3C
2D
80
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
0F
50
3D
50
50
60
3C
1E
3C
2D
01
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
0F
50
3D
50
50
60
3C
1E
3C
2D
80
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
0F
50
3D
50
50
60
3C
1E
3C
2D
01
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
0F
50
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ΔT4R4W Delta
T
Rev. 1.02, 2008-06
49
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
5300P–555 5300P–555 5300P–555 5300P–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Psi(T-A) DRAM
7A
4B
2E
36
27
4C
2A
4C
20
23
C4
8C
68
94
12
8E
7F
7F
7F
7F
7F
51
00
00
xx
7A
4B
2E
36
27
4C
2A
4C
20
23
C4
8C
68
94
12
09
7F
7F
7F
7F
7F
51
00
00
xx
7A
4B
2E
36
27
4C
2A
4C
20
23
C4
8C
68
94
12
90
7F
7F
7F
7F
7F
51
00
00
xx
7A
4B
2E
36
27
4C
2A
4C
20
23
C4
8C
68
94
12
0A
7F
7F
7F
7F
7F
51
00
00
xx
ΔT0 (DT0)
ΔT2N (DT2N, UDIMM) or ΔT2Q (DT2Q, RDIMM)
ΔT2P (DT2P)
ΔT3N (DT3N)
ΔT3P.fast (DT3P fast)
ΔT3P.slow (DT3P slow)
ΔT4R (DT4R) / ΔT4R4W Sign (DT4R4W)
ΔT5B (DT5B)
ΔT7 (DT7)
Psi(ca) PLL
Psi(ca) REG
ΔTPLL (DTPLL)
ΔTREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Rev. 1.02, 2008-06
50
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
5300P–555 5300P–555 5300P–555 5300P–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
37
32
54
36
34
30
30
30
45
50
33
53
42
32
20
20
20
20
2x
xx
37
32
54
31
32
38
30
30
30
45
50
33
53
42
32
20
20
20
2x
xx
xx
xx
xx
00
FF
37
32
54
31
32
38
30
32
30
45
50
33
53
42
32
20
20
20
2x
xx
xx
37
32
54
32
35
36
32
32
30
45
50
33
53
42
32
20
20
20
3x
xx
xx
xx
xx
00
FF
xx
xx
xx
00
FF
xx
95 - 98 Module Serial Number
99 - 127 Not used
xx
00
FF
128 -
255
Blank for customer use
Rev. 1.02, 2008-06
51
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
TABLE 29
HYS72T[64/128/256]xx0EP-3.7-B2
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
4200P–444 4200P–444 4200P–444 4200P–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
60
48
00
05
3D
50
06
82
08
08
00
0C
04
38
01
01
04
07
80
08
08
0E
0B
60
48
00
05
3D
50
06
82
04
04
00
0C
04
38
01
01
05
07
80
08
08
0E
0A
61
48
00
05
3D
50
06
82
08
08
00
0C
04
38
01
01
05
07
80
08
08
0E
0B
61
48
00
05
3D
50
06
82
04
04
00
0C
04
38
01
01
05
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
tCK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 1.02, 2008-06
52
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
4200P–444 4200P–444 4200P–444 4200P–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
3D
50
50
60
3C
1E
3C
2D
80
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
0F
50
3D
50
50
60
3C
1E
3C
2D
01
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
0F
50
3D
50
50
60
3C
1E
3C
2D
80
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
0F
50
3D
50
50
60
3C
1E
3C
2D
01
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
0F
50
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ΔT4R4W Delta
T
Rev. 1.02, 2008-06
53
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
4200P–444 4200P–444 4200P–444 4200P–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Psi(T-A) DRAM
7A
43
29
36
21
41
2A
40
1E
22
C4
8C
61
78
12
82
7F
7F
7F
7F
7F
51
00
00
xx
7A
43
29
36
21
41
2A
40
1E
22
C4
8C
61
78
12
FD
7F
7F
7F
7F
7F
51
00
00
xx
7A
43
29
36
21
41
2A
40
1E
22
C4
8C
61
78
12
84
7F
7F
7F
7F
7F
51
00
00
xx
7A
43
29
36
21
41
2A
40
1E
22
C4
8C
61
78
12
FE
7F
7F
7F
7F
7F
51
00
00
xx
ΔT0 (DT0)
ΔT2N (DT2N, UDIMM) or ΔT2Q (DT2Q, RDIMM)
ΔT2P (DT2P)
ΔT3N (DT3N)
ΔT3P.fast (DT3P fast)
ΔT3P.slow (DT3P slow)
ΔT4R (DT4R) / ΔT4R4W Sign (DT4R4W)
ΔT5B (DT5B)
ΔT7 (DT7)
Psi(ca) PLL
Psi(ca) REG
ΔTPLL (DTPLL)
ΔTREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Rev. 1.02, 2008-06
54
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
4200P–444 4200P–444 4200P–444 4200P–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
37
32
54
36
34
30
30
30
45
50
33
2E
37
42
32
20
20
20
2x
xx
37
32
54
31
32
38
30
30
30
45
50
33
2E
37
42
32
20
20
2x
xx
xx
xx
xx
37
32
54
31
32
38
30
32
30
45
50
33
2E
37
42
32
20
20
2x
xx
xx
xx
xx
37
32
54
32
35
36
32
32
30
45
50
33
2E
37
42
32
20
20
3x
xx
xx
xx
xx
xx
xx
xx
95 - 98 Module Serial Number
Rev. 1.02, 2008-06
55
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
Organization
512MB
1 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2– PC2– PC2– PC2–
4200P–444 4200P–444 4200P–444 4200P–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
99 - 127 Not used
00
FF
00
FF
00
FF
00
FF
128 -
255
Blank for customer use
Rev. 1.02, 2008-06
56
07312007-HYD2-P177
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
5
Package Outlines
This chapter contains the package outlines of the products.
FIGURE 5
Package Outline L-DIM-240-11 Raw Card F
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Rev. 1.02, 2008-06
57
07312007-HYD2-P177
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
FIGURE 6
Package Outline L-DIM-240-12 Raw Card G
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Rev. 1.02, 2008-06
58
07312007-HYD2-P177
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Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
FIGURE 7
Package Outline L-DIM-240-13 Raw Card H
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1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.02, 2008-06
59
07312007-HYD2-P177
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Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
FIGURE 8
Package Outline L-DIM-240-48 Raw Card L
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1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.02, 2008-06
60
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
6
Product Type Nomenclature
Qimonda’s nomenclature uses simple coding combined with
some proprietary coding. Table 30 provides examples for
module and component product type number as well as the
field number. The detailed field description together with
possible values and coding explanation is listed for modules
in Table 31 and for components in Table 32.
TABLE 30
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
DDR2 DRAM
HYS
HYB
64
18
T
T
64/128
0
2
0
0
K
A
M
C
–5
–5
–A
512/1G 16
TABLE 31
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
2
Qimonda Module Prefix
Module Data Width [bit]
HYS
64
Constant
Non-ECC
ECC
72
3
4
DRAM Technology
T
DDR2
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
512 MByte
1 GByte
2 GByte
4 GByte
64
128
256
512
0 .. 9
0, 2, 4
0 .. 9
A .. Z
D
5
6
7
8
9
Raw Card Generation
Number of Module Ranks
Product Variations
Look up table
1, 2, 4
Look up table
Look up table
SO-DIMM
Package, Lead-Free Status
Module Type
M
Micro-DIMM
Registered
Unbuffered
Fully Buffered
R
U
F
Rev. 1.02, 2008-06
61
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Field
Description
Values
Coding
10
Speed Grade
–19F
–1.9
–25F
–2.5
–3
PC2–8500 6–6–6
PC2–8500 7–7–7
PC2–6400 5–5–5
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
PC2–4200 4–4–4
PC2–3200 3–3–3
First
–3S
–3.7
–5
11
Die Revision
–A
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 32
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
2
3
4
Qimonda Component Prefix
Interface Voltage [V]
HYB
18
Constant
SSTL_18
DRAM Technology
T
DDR2
Component Density [Mbit]
256
512
1G
2G
40
256 Mbit
512 Mbit
1 Gbit
2 Gbit
5+6
Number of I/Os
×4
80
×8
16
×16
7
8
Product Variations
Die Revision
0 .. 9
A
Look up table
First
B
Second
9
Package, Lead-Free Status
Speed Grade
C
FBGA, lead-containing
FBGA, lead-free
PC2–8500 6–6–6
PC2–8500 7–7–7
PC2–6400 5–5–5
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
PC2–4200 4–4–4
PC2–3200 3–3–3
F
10
–19F
–1.9
–25F
–2.5
–3
–3S
–3.7
–5
Rev. 1.02, 2008-06
62
07312007-HYD2-P177
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configurations and Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
IDD Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1
3.2
3.3
3.4
3.5
3.6
4
5
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Rev. 1.02, 2008-06
63
07312007-HYD2-P177
Internet Data Sheet
Edition 2008-06
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2008.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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