HYS72T256000HR-3S-A [QIMONDA]
240-Pin Registered DDR SDRAM Modules; 240引脚注册的DDR SDRAM模块![HYS72T256000HR-3S-A](http://pdffile.icpdf.com/pdf1/p00107/img/icpdf/HYS72T256000HR_580569_icpdf.jpg)
型号: | HYS72T256000HR-3S-A |
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描述: | 240-Pin Registered DDR SDRAM Modules |
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February 2007
HYS72T128001HR–5–A
HYS72T256000HR–[3S/3.7/5]–A
240-Pin Registered DDR SDRAM Modules
RDIMM
DDR2 SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.4
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
HYS72T128001HR–5–A, HYS72T256000HR–[3S/3.7/5]–A
Revision History: 2007-02, Rev. 1.4
Page
Subjects (major changes since last revision)
All
All
Adapted internet edition
Added HYS72T256000HR-3S-A: Updated Ordering Information, Block Diagrams, IDD Currents, SPD Codes
Previous Revision: Rev. 1.31, 2006-09
All Qimonda Update
Previous Revision: Rev. 1.3, 2006-01
Added HYS72T128001HR-5-A: Updated Ordering Information, Block Diagrams, IDD Currents, SPD Codes and
Package Outlines accordingly
5
Added High Temperature Self refresh to Feature List, Operating Temperature and to SPD Codes
Changed footnote 1 (Table 9) into “Attention”
20
29
Added footnote 2 to IDD Currents (Table 18)
Previous Revision: Rev. 1.2, 2005-08
28, 32
35
SPD Codes updated
Package Outline figure updated
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
03062006-GD6J-14FP
2
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 240-Pin Registered DDR SDRAM Modules product family and describes its main
characteristics.
1.1
Features
•
240-Pin PC2–4200 and PC2–3200 DDR2 SDRAM
memory modules for PC, Workstation and Server main
memory applications.
One rank 128M ×72, 256M ×72 module organization and
128M x 8, 256M ×4 chip organization
Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
1 and 2 GByte module built with 1 Gbit DDR2 SDRAMs in
P-TFBGA-68 chipsize packages.
•
•
Auto Refresh (CBR) and Self Refresh
Average Refresh Period 7.8 µs at a TCASE lower than
85 °C, 3.9 µs between 85 °C and 95 °C
Programmable self refresh rate via EMRS2 setting
All inputs and outputs SSTL_18 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
•
•
•
•
•
•
•
Serial Presence Detect with E2PROM
RDIMM Dimensions (nominal):
•
•
•
30,00 mm high, 133.35 mm wide
All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications as well.
Programmable CAS Latencies (3, 4 & 5), Burst Length
(4 & 8) and Burst Type
•
•
Based on JEDEC standard reference card layouts Raw
Card “A-F” and “C-H”
RoHS compliant products1)
TABLE 1
Performance Table
Product Type Speed Code
Speed Grade
–3S
–3.7
–5
Unit
PC2–5300
5–5–5
PC2–4200
4–4–4
PC2–3200
4–4–4
—
Max. Clock Frequency
@CL5
@CL4
@CL3
fCK5
fCK4
fCK3
tRCD
tRP
333
266
200
15
266
266
200
15
200
200
200
15
MHz
MHz
MHz
ns
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
15
15
15
ns
tRAS
tRC
45
45
40
ns
60
60
55
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.4, 2007-02
3
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
1.2
Description
The Qimonda HYS72T[128/256]00xHR–[3S/3.7/5]–A module
family are Registered DIMM modules with 30,0 mm height
based on DDR2 technology. DIMMs are available as ECC
modules in 128M ×72 (1 GByte) and 256M ×72 (2 GByte)
organization and density, intended for mounting into 240-Pin
connector sockets.
signals are re-driven on the DIMM using register devices and
a PLL for the clock distribution. This reduces capacitive
loading to the system bus, but adds one cycle to the SDRAM
timing. Decoupling capacitors are mounted on the PCB
board. The DIMMs feature serial presence detect based on a
serial E2PROM device using the 2-pin I2C protocol. The first
128 bytes are programmed with configuration data and the
second 128 bytes are available to the customer.
The memory array is designed with 1-Gbit Double-Data-Rate-
Two (DDR2) Synchronous DRAMs. All control and address
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1)
Compliance Code2)
Description
SDRAM Technology
PC2–5300
HYS72T256000HR–3S–A
PC2–4200
2GB 1Rx4 PC2–5300R–444–11–H0
2GB 1Rx4 PC2–4200R–444–11–H0
1 Rank, ECC
1 Rank, ECC
1 Gbit (×4)
1 Gbit (×4)
HYS72T256000HR–3.7–A
PC2–3200
HYS72T128001HR–5–A
HYS72T256000HR–5–A
1GB 1Rx8 PC2–3200R–333–12–F0
2GB 1Rx4 PC2–3200R–333–11–H0
1 Rank, ECC
1 Rank, ECC
1 Gbit (×8)
1 Gbit (×4)
1) All Product Types end with a place code, designating the silicon die revision. Example: HYS72T256000HR–3.7–A, indicating Rev. “A” dies
are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–11–H0”, where
4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address Strobe (CAS)
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.1 and
produced on the Raw Card “F”
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
1 GB
2 GB
128M ×72
256M ×72
1
1
ECC
ECC
9
14/3/11
14/3/11
A-F
18
C-H
Rev. 1.4, 2007-02
4
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 4
Components on Modules
Product Type1)
DRAM Components1)
DRAM Density
DRAM Organisation
Note
2)
HYS72T128001HR
HYB18T1G800AF
HYB18T1G400AF
1 Gbit
1 Gbit
128M ×8
256M ×4
2)
HYS72T256000HR
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.4, 2007-02
5
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
2
Pin Configuration
2.1
Pin Configuration
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in Table 5 (240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 6
and Table 7 respectively. The pin numbering is depicted in
Figure 1.
TABLE 5
Pin Configuration of RDIMM
Ball No.
Name
Pin
Buffer
Function
Type Type
Clock Signals
185
186
52
CK0
CK0
CKE0
CKE1
NC
I
SSTL
SSTL
SSTL
SSTL
—
Clock Signal CK0, Complementary Clock Signal CK0
I
I
Clock Enables 1:0
Note: 2-Ranks module
171
I
NC
Not Connected
Note: 1-Rank module
Control Signals
193
76
S0
S1
NC
I
SSTL
SSTL
—
Chip Select Rank 1:0
Note: 2-Ranks module
I
NC
Not Connected
Note: 1-Rank module
192
RAS
I
I
I
I
SSTL
SSTL
SSTL
CMOS
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
74
CAS
73
WE
18
RESET
Register Reset
Address Signals
71
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 1:0
190
54
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
I
SSTL
Not Connected
Less than 1Gb DDR2 SDRAMS
Rev. 1.4, 2007-02
6
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
188
183
63
A0
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Address Bus 12:0, Address Signal 10/AutoPrecharge
A1
I
A2
I
182
61
A3
I
A4
I
60
A5
I
180
58
A6
I
A7
I
179
177
70
A8
I
A9
I
A10
AP
A11
A12
A13
NC
I
I
57
I
176
196
I
I
Address Signal 13
NC
Not Connected
Note: Non CA parity modules based on 256 Mbit component
Address Signal 14
174
173
A14
NC
I
SSTL
—
Note: CA Parity module
NC
I
Not Connected
Note: Non CA parity module. Less than 1 GBit per DRAM die.
Address Signal 14
A15
NC
SSTL
—
Note: CA Parity module
NC
Not Connected
Note: Non CA parity module. Less than 1 GBit per DRAM die.
Rev. 1.4, 2007-02
7
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
Data Signals
3
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
4
DQ1
9
DQ2
10
DQ3
122
123
128
129
12
DQ4
DQ5
DQ6
DQ7
DQ8
13
DQ9
21
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
Rev. 1.4, 2007-02
8
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
206
89
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
Check Bits
42
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Check Bits 7:0
Note: NC on Non-ECC module
43
48
49
161
162
167
168
Rev. 1.4, 2007-02
9
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
Data Strobe Bus
7
DQS0
DQS0
DQS1
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
DQS8
DQS8
DQS9
DQS9
DQS10
DQS10
DQS11
DQS11
DQS12
DQS12
DQS13
DQS13
DQS14
DQS14
DQS15
DQS15
DQS16
DQS16
DQS17
DQS17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Strobes 17:0
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165
Rev. 1.4, 2007-02
10
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
Data Mask
125
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Masks 8:0
Note: ×8 based module
134
146
155
202
211
223
232
164
EEPROM
120
SCL
SDA
SA0
SA1
SA2
I
CMOS
OD
Serial Bus Clock
Serial Bus Data
119
I/O
239
I
I
I
CMOS
CMOS
CMOS
Serial Address Select Bus 2:0
240
101
Parity
55
ERR_OUT
PAR_IN
O
I
CMOS
CMOS
Parity bits
Power Supplies
1
VREF
AI
—
—
—
I/O Reference Voltage
EEPROM Power Supply
I/O Driver Power Supply
238
VDDSPD
PWR
PWR
51, 56, 62, 72, 75, VDDQ
78, 170, 175, 181,
191, 194
53, 59, 64, 67, 69, VDD
172, 178, 184, 187,
189, 197
PWR
GND
—
—
Power Supply
Ground Plane
2, 5, 8, 11, 14, 17, VSS
20, 23, 26, 29, 32,
35, 38, 41, 44, 47,
50, 65, 66, 79, 82,
85, 88, 91, 94, 97,
100, 103, 106, 109,
112, 115, 118, 121,
124, 127, 130, 133,
136, 139, 142, 145,
148, 151, 154, 157,
160, 163, 166, 169,
198, 201, 204, 207,
210, 213, 216, 219,
222, 225, 228, 231,
234, 237
Rev. 1.4, 2007-02
11
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
Other Pins
19, 55, 68, 102,
137, 138, 173, 220,
221
NC
NC
—
Not connected
195
77
ODT0
ODT1
NC
I
SSTL
SSTL
—
On-Die Termination Control 1:0
Note: 2-Ranks module
I
NC
Note: 1-Rank modules
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
CMOS
OD
Serial Stub Terminated Logic (SSTL_18)
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
TABLE 7
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NU
NC
Ground
Not Usable
Not Connected
Rev. 1.4, 2007-02
12
03062006-GD6J-14FP
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ꢀꢈ
ꢀꢈ
ꢀꢈ
ꢀꢈ
ꢋ
ꢋ
ꢋ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
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ꢈ
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ꢈ
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ꢅ
ꢅ
ꢅ
ꢅ
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ꢆꢀꢄꢀ &.ꢁꢀ
9ꢀ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
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Qꢀ
Qꢀ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
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ꢁ
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ꢂ
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ꢋꢀ
ꢁꢀ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
ꢀ
ꢀ
ꢀ
ꢀ
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ꢁꢂꢃꢁꢀ
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
FIGURE 1
Pin Configuration for RDIMM (240 pins)
9
'
9ꢀ
'
'
9ꢀ
'
'
9ꢀ
1
'
9ꢀ
'
'
9ꢀ
'
'
9ꢀ
'
'
9ꢀ
&
'
5
4ꢁ
()
ꢀ
ꢀ
ꢄꢀ 3
ꢄꢀ 3
ꢄꢀ 3
ꢄꢀ 3
ꢄꢀ 3
ꢄꢀ 3
ꢄꢀ 3
ꢄꢀ 3
ꢄꢀ 3
ꢄꢀ 3
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
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Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
ꢁꢁ
ꢁꢁ
ꢁꢁ
ꢁꢁ
ꢁꢁ
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ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
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ꢁꢈ
ꢁꢈ
ꢁꢈ
ꢁꢈ
ꢁꢅ
ꢁꢅ
ꢁꢅ
ꢁꢅ
ꢁꢅ
ꢁꢉ
ꢁꢉ
ꢁꢉ
ꢁꢉ
ꢁꢉ
ꢁꢆ
ꢁꢆ
ꢁꢆ
ꢁꢆ
ꢁꢆ
ꢁꢊ
ꢁꢊ
ꢂꢀ
ꢅꢀ
ꢆꢀ
ꢃꢀ
ꢇꢀ
ꢂꢀ
ꢅꢀ
ꢆꢀ
ꢃꢀ
ꢇꢀ
ꢂꢀ
ꢅꢀ
ꢆꢀ
ꢃꢀ
ꢇꢀ
ꢂꢀ
ꢅꢀ
ꢆꢀ
ꢃꢀ
ꢇꢀ
ꢂꢀ
ꢅꢀ
ꢆꢀ
ꢃꢀ
ꢇꢀ
ꢂꢀ
ꢅꢀ
ꢆꢀ
ꢃꢀ
ꢇꢀ
ꢂꢀ
ꢅꢀ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
ꢀꢂ
ꢀꢂ
ꢀꢂ
ꢀꢂ
ꢀꢂ
ꢀꢂ
ꢀꢂ
ꢀꢂ
ꢀꢂ
ꢀꢂ
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ꢀꢂ
ꢀꢂ
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ꢀꢂ
ꢀꢂ
ꢀꢂ
ꢀꢂ
ꢀꢂ
ꢀꢂ
ꢀꢂ
ꢀꢂ
ꢈ
ꢈ
ꢈ
ꢈ
ꢈ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢉ
ꢉ
ꢉ
ꢉ
ꢉ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢊ
ꢊ
ꢊ
ꢊ
ꢊ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢋ
ꢋ
ꢂꢀꢄꢀ 9ꢀ 6ꢀ
6
9ꢀ
66ꢀ
ꢄꢀ 3
ꢄꢀ 3
ꢁꢀ ꢄꢀ 3
ꢄꢀ 3
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
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Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢈ
ꢈ
ꢈ
ꢈ
ꢈ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢉ
ꢉ
ꢉ
ꢉ
ꢉ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
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ꢊ
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ꢋꢀ
ꢁꢀ
ꢈꢀ
ꢉꢀ
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ꢁꢀ
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ꢉꢀ
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ꢋꢀ
ꢁꢀ
ꢈꢀ
ꢉꢀ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
ꢀ
ꢀ
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4
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Rev. 1.4, 2007-02
03062006-GD6J-14FP
13
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3
Electrical Characteristics
3.1
Absolute Maximum Ratings
TABLE 8
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit
Note/Test
Condition
Min.
Max.
Voltage on any pins relative to VSS
Voltage on VDD relative to VSS
VIN, VOUT
VDD
–0.5
–1.0
–0.5
5
2.3
2.3
2.3
95
V
V
V
%
Voltage on VDDQ relative to VSS
Storage Humidity (without condensation)
VDDQ
HSTG
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
Rev. 1.4, 2007-02
14
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.2
DC Operating Conditions
TABLE 9
Operating Conditions
Parameter
Symbol
Values
Min.
Unit
Note
Max.
1)
DIMM Module Operating Temperature Range (ambient)
DRAM Component Case Temperature Range
Storage Temperature
TOPR
TCASE
TSTG
PBar
0
+55
+95
+100
+105
90
°C
°C
°C
kPa
%
2)3)4)5)
0
–55
+69
10
6)
Barometric Pressure (operating & storage)
Operating Humidity (relative)
HOPR
1) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 %
2) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.
3) Within the DRAM Component Case Temperature range all DRAM specification will be supported.
4) Above 85 °C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
5) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 °C case
temperature before initiating self-refresh operation.
6) Up to 3000 m
TABLE 10
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Values
Min.
Unit
Note
Typ.
Max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
VDD
1.7
1.8
1.9
V
1)
2)
VDDQ
VREF
1.7
1.8
1.9
V
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
VDDSPD
VIH(DC)
VIL (DC
IL
1.7
—
—
—
—
3.6
V
DC Input Logic High
VREF + 0.125
V
V
5
DDQ + 0.3
V
DC Input Logic Low
)
– 0.30
– 5
REF – 0.125
V
3)
In / Output Leakage Current
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
.
Rev. 1.4, 2007-02
15
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.3
AC Characteristics
3.3.1
Speed Grades Definitions
TABLE 11
Speed Grade Definition
Speed Grade
DDR2–667
–3S
DDR2–533C
DDR2–400B
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
Parameter
–3.7
–5
5–5–5
4–4–4
Min.
3–3–3
tCK
Symbol
@ CL = 3 tCK
@ CL = 4 tCK
@ CL = 5 tCK
tRAS
Min.
Max.
Max.
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
5
8
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
3.75
3
8
3.75
3.75
45
8
5
8
8
8
5
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
45
60
15
15
70000
—
70000
—
40
55
15
15
70000
—
tRC
60
tRCD
tRP
—
15
—
—
—
15
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
3.3.2
AC Timing Parameters
TABLE 12
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)7)
8)
Min.
Max.
9)
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
tAC
–450
2
+450
—
ps
tCCD
nCK
tCK.AVG
ps
10)11)
tCH.AVG
tCK.AVG
0.48
3000
0.52
8000
Rev. 1.4, 2007-02
16
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)7)
8)
Min.
Max.
12)
CKE minimum pulse width ( high and low pulse tCKE
3
—
nCK
width)
1)1)
Average clock low pulse width
tCL.AVG
0.48
0.52
—
tCK.AVG
nCK
ns
13)14)
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK .AVG
tIH
+
—
19)20)15)
9)
DQ and DM input hold time
tDH.BASE
tDIPW
tDQSCK
tDQSH
175
—
ps
DQ and DM input pulse width for each input
DQS output access time from CK / CK
DQS input high pulse width
0.35
–400
0.35
0.35
—
—
tCK.AVG
ps
+400
—
tCK.AVG
tCK.AVG
ps
DQS input low pulse width
tDQSL
—
16)
17)
DQS-DQ skew for DQS & associated DQ signals tDQSQ
240
+0.25
DQS latching rising transition to associated clock tDQSS
–0.25
tCK.AVG
edges
18)19)20)
17)
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
tDS.BASE
100
0.2
0.2
––
—
—
__
ps
tDSH
tDSS
tHP
tCK.AVG
tCK.AVG
ps
17)
21)
Min(tCH.ABS
,
tCL.ABS
)
9)22)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
25)23)
tIH.BASE
275
0.6
ps
Control & address input pulse width for each input tIPW
—
tCK.AVG
ps
24)25)
9)22)
9)22)
1)
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
tIS.BASE
200
—
tLZ.DQ
tLZ.DQS
tMOD
tMRD
tOIT
2 × tAC.MIN
tAC.MAX
tAC.MAX
12
ps
tAC.MIN
ps
0
2
0
ns
—
nCK
ns
1)
12
26)
tQH
t
HP – tQHS
—
ps
27)
tQHS
—
340
1.1
0.6
—
ps
28)29)
28)30)
31)
Read preamble
tRPRE
tRPST
tRTP
0.9
0.4
7.5
0.35
0.4
15
tCK.AVG
tCK.AVG
ns
Read postamble
Internal Read to Precharge command delay
Write preamble
tWPRE
tWPST
tWR
—
tCK.AVG
tCK.AVG
ns
Write postamble
0.6
—
31)
Write recovery time
31)32)
Internal write to read command delay
Exit power down to read command
tWTR
tXARD
7.5
2
—
ns
—
nCK
nCK
Exit active power-down mode to read command tXARDS
7 – AL
—
(slow exit, lower power)
Rev. 1.4, 2007-02
17
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)7)
8)
Min.
Max.
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
nCK
31)
Exit self-refresh to a non-read command
Exit self-refresh to read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
200
nCK
nCK
Write command to DQS associated clock edges WL
RL–1
1) For details and notes see the relevant Qimonda component data sheet
2)
V
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 1)6)1)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations).
12) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
13) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
14) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 3.
16) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
18) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN
See Figure 3.
.
19) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
Rev. 1.4, 2007-02
18
03062006-GD6J-14FP
5(ꢀꢀEHJLꢀQꢀSRLQWꢀ
7
ꢀ
Hꢀ
ꢀSRLꢀQW
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Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
21) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
22) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
23) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 4.
24) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 4.
25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
26) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the
max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
27) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
28) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
30) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
31) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
32) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
FIGURE 2
Method for calculating transitions and endpoint
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W/=ꢀ
W53
W+=ꢀ
W536 QG
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Rev. 1.4, 2007-02
19
03062006-GD6J-14FP
W'+ꢀ
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Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
FIGURE 3
Differential input waveform timing - tDS and tDS
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Differential input waveform timing - tlS and tlH
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Rev. 1.4, 2007-02
20
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 13
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Note1)2)3)4)5)
6)7)
Min.
Max.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
–500
2
+500
—
ps
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
8)18)
9)
Auto-Precharge write recovery + precharge
time
tDAL
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
225
––
––
—
ns
ps
ps
10)
11)
DQ and DM input hold time (differential data
strobe)
t
t
DH(base)
DQ and DM input hold time (single ended data
strobe)
DH1(base)
–25
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
tDIPW
0.35
–450
0.35
—
—
tCK
ps
tCK
ps
tDQSCK
+450
—
DQS input low (high) pulse width (write cycle) tDQSL,H
11)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
300
Write command to 1st DQS latching transition tDQSS
– 0.25
100
+ 0.25
—
tCK
11)
11)
DQ and DM input setup time (differential data
strobe)
t
DS(base)
ps
DQ and DM input setup time (single ended data tDS1(base)
strobe)
–25
0.2
—
—
—
ps
DQS falling edge hold time from CK (write
cycle)
tDSH
tCK
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
12)
13)
11)
Clock half period
tHP
MIN. (tCL, tCH)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
ps
tCK
tIH(base)
tIPW
375
0.6
Address and control input pulse width
(each input)
—
11)
14)
14)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
250
—
ps
ps
ps
tCK
ns
—
ps
µs
2 × tAC.MIN
tAC.MAX
tAC.MAX
—
tAC.MIN
2
0
tOIT
12
Data output hold time from DQS
Data hold skew factor
tQH
t
HP –tQHS
—
tQHS
—
—
400
7.8
14)15)
Average periodic refresh Interval
tREFI
Rev. 1.4, 2007-02
21
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–533
Min.
Unit
Note1)2)3)4)5)
6)7)
Max.
16)18)
17)
Average periodic refresh Interval
tREFI
tRFC
—
—
3.9
—
µs
Auto-Refresh to Active/Auto-Refresh
command period
ns
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
tRP
t
RP + 1tCK
—
ns
ns
tCK
tCK
ns
tRP
15 + 1tCK
0.9
—
14)
tRPRE
tRPST
tRRD
1.1
0.60
—
14)
Read postamble
0.40
14)18)
Active bank A to Active bank B command
period
7.5
16)22)
Active bank A to Active bank B command
period
tRRD
10
—
ns
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
ns
tCK
tCK
ns
tWPRE
tWPST
tWR
0.25
0.40
15
—
19)
Write postamble
0.60
—
Write recovery time for write without Auto-
Precharge
20)
21)
Internal Write to Read command delay
tWTR
7.5
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
tXP
6 – AL
2
—
—
tCK
tCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
tXSNR
tXSRD
WR
t
RFC +10
200
WR/tCK
—
—
—
ns
tCK
tCK
22)
Write recovery time for write with Auto-
Precharge
t
1) For details and notes see the relevant Qimonda component data sheet.
2)
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 1)6)1)8)
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
Rev. 1.4, 2007-02
22
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS Compliant
Products” on Page 4.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2 - 400
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)7)
Min.
Max.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
–600
2
+600
—
ps
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
8)21)
9)
Auto-Precharge write recovery + precharge
time
tDAL
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
275
—
—
—
ns
ps
ps
10)
11)
DQ and DM input hold time (differential data
strobe)
t
t
DH(base)
DH1(base)
DQ and DM input hold time (single ended data
strobe)
–25
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
tDIPW
0.35
–500
0.35
—
—
tCK
ps
tCK
ps
tDQSCK
+500
—
DQS input low (high) pulse width (write cycle) tDQSL,H
11)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
350
Write command to 1st DQS latching transition tDQSS
– 0.25
150
+ 0.25
—
tCK
11)
11)
DQ and DM input setup time (differential data
strobe)
t
DS(base)
ps
DQ and DM input setup time (single ended
data strobe)
t
DS1(base)
–25
—
ps
Rev. 1.4, 2007-02
23
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)7)
Min.
Max.
DQS falling edge hold time from CK (write
cycle)
tDSH
0.2
—
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
tCK
—
12)
13)
11)
Clock half period
tHP
MIN. (tCL, tCH)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
ps
tCK
tIH(base)
tIPW
475
0.6
Address and control input pulse width
(each input)
—
11)
14)
14)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
350
—
ps
ps
ps
tCK
ns
—
ps
µs
µs
ns
2 × tAC.MIN
tAC.MAX
tAC.MAX
—
tAC.MIN
2
0
tOIT
12
Data output hold time from DQS
Data hold skew factor
tQH
t
HP –tQHS
—
tQHS
—
—
—
—
450
7.8
14)15)
16)18)
17)
Average periodic refresh Interval
Average periodic refresh Interval
tREFI
tREFI
3.9
Auto-Refresh to Active/Auto-Refresh
command period
—
—
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
tRP
t
RP + 1tCK
—
ns
ns
tCK
tCK
ns
tRP
15 + 1tCK
0.9
—
14)
tRPRE
tRPST
tRRD
1.1
0.60
—
14)
Read postamble
0.40
14)18)
Active bank A to Active bank B command
period
7.5
16)22)
Active bank A to Active bank B command
period
tRRD
10
—
ns
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
ns
tCK
tCK
ns
tWPRE
tWPST
tWR
0.25
0.40
15
—
19)
Write postamble
0.60
—
Write recovery time for write without Auto-
Precharge
20)
21)
Internal Write to Read command delay
tWTR
10
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
tXP
6 – AL
2
—
—
—
tCK
tCK
ns
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
tXSNR
tRFC +10
Rev. 1.4, 2007-02
24
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)7)
Min.
Max.
Exit Self-Refresh to Read command
tXSRD
200
—
—
tCK
tCK
22)
Write recovery time for write with Auto-
Precharge
WR
tWR/tCK
1) For details and notes see the relevant Qimonda component data sheet.
2)
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 1)6)1)8)
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS
Compliant Products” on Page 4.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
Rev. 1.4, 2007-02
25
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.3.3
ODT AC Electrical Characteristics
TABLE 15
ODT AC Characteristics and Operating Conditions for DDR2-667
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
1)
tAOND
tAON
ODT turn-on delay
2
2
nCK
ns
1)2)
1)
ODT turn-on
tAC.MIN
tAC.MAX + 0.7 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK +
t
AC.MAX + 1 ns
ns
1)
2.5
2.5
nCK
ns
1)3)
1)
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK +
t
AC.MAX + 1 ns
ns
1)
3
8
—
—
nCK
nCK
1)
1) New units, “tCK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800. Unit “tCK.AVG” represents the actual tCK.AVG of the input clock
under operation. Unit “nCK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “tCK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns
(= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual
input clock edges.
Rev. 1.4, 2007-02
26
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 16
ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
tAOND
tAON
ODT turn-on delay
2
2
tCK
ns
ns
tCK
ns
ns
tCK
tCK
1)
2)
ODT turn-on
tAC.MIN
tAC.MAX + 1 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK + tAC.MAX + 1 ns
2.5
2.5
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK + tAC.MAX + 1 ns
3
8
—
—
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
3.4
Currents Specifications and Conditions
TABLE 17
DD Measurement Conditions
I
Parameter
Symbol Note
1)2)3)4)5)6)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
IDD1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN
,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,
Data bus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
IDD2Q
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Rev. 1.4, 2007-02
27
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol Note
1)2)3)4)5)6)
Active Standby Current
IDD3N
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
IDD3P(0)
IDD3P(1)
IDD4W
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
IDD5B
IDD5D
IDD6
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
2)
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 18
4) DD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
I
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
6) For details and notes see the relevant Qimonda component data sheet
TABLE 18
Definitions for IDD
Parameter
Description
LOW
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
inputs are stable at a HIGH or LOW level
inputs are VREF = VDDQ /2
STABLE
FLOATING
SWITCHING
inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
Rev. 1.4, 2007-02
28
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 19
IDD Specification for HYS72T[128/256]00xHR–[3S/3.7/5]–A
Product Type
Unit Note1)
Organization
2 GByte
1 Rank
×72
2 GByte
1 Rank
×72
1 GByte
1 Rank
×72
2 GByte
1 Rank
×72
–3S
–3.7
–5
–5
Symbol
Max.
Max.
Max.
Max.
2)
IDD0
2130
2490
1680
720
1850
2030
1330
630
910
1000
590
340
530
640
440
360
1310
1270
1900
370
72
1670
1850
1040
530
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
3)
IDD2N
IDD2P
3)
3)
IDD2Q
IDD3N
IDD3P.MRS=0
IDD3P.MRS=1
IDD4R
IDD4W
IDD5B
1320
1770
470
910
910
3)
1400
860
1130
910
3)4)
3)5)
2)
720
660
730
4200
4200
4200
720
3100
3020
3830
680
2480
2390
3650
590
2)
2)
3)6)
3)6)
3)
IDD5D
IDD6
108
144
144
IDD7
5190
4640
2120
4100
1) Module IDD is calculated on the basis of component IDD and includes currents of Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are
defined with the outputs disabled.
2) The other rank is in IDD2P Percharge Power-Down mode
3) Both ranks are in the same IDD current mode
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6) Values for 0 °C ≤ TCASE ≤ 85 °C
Rev. 1.4, 2007-02
29
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
Table 20 “HYS72T[128/256]00xHR-[3S/3.7/5]-A” on Page 30
TABLE 20
HYS72T[128/256]00xHR-[3S/3.7/5]-A
Product Type
Organization
2 GByte
2 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×8) 1 Rank (×4)
Label Code
PC2– PC2– PC2– PC2–
5300R–555 4200R–444 3200R–333 3200R–333
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.1
HEX
Rev. 1.2
HEX
Rev. 1.1
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0B
60
48
00
05
30
45
02
82
04
80
08
08
0E
0B
60
48
00
05
3D
50
02
82
04
80
08
08
0E
0A
60
48
00
05
50
60
02
82
08
80
08
08
0E
0B
60
48
00
05
50
60
02
82
04
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Rev. 1.4, 2007-02
30
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
2 GByte
2 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×8) 1 Rank (×4)
Label Code
PC2– PC2– PC2– PC2–
5300R–555 4200R–444 3200R–333 3200R–333
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.1
HEX
Rev. 1.2
HEX
Rev. 1.1
HEX
Byte#
Description
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Error Checking SDRAM Width
Not used
04
00
0C
08
38
01
01
05
03
3D
50
50
60
3C
1E
3C
2D
02
20
27
10
17
3C
1E
1E
00
04
00
0C
08
38
00
01
05
01
3D
50
50
60
3C
1E
3C
2D
02
25
37
10
22
3C
1E
1E
00
08
00
0C
08
38
00
01
04
01
50
60
50
60
3C
1E
3C
28
01
35
47
15
27
3C
28
1E
00
04
00
0C
08
38
00
01
05
01
50
60
50
60
3C
1E
3C
28
02
35
47
15
27
3C
28
1E
00
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
Rev. 1.4, 2007-02
31
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
2 GByte
2 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×8) 1 Rank (×4)
Label Code
PC2– PC2– PC2– PC2–
5300R–555 4200R–444 3200R–333 3200R–333
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.1
HEX
Rev. 1.2
HEX
Rev. 1.1
HEX
Byte#
Description
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
06
3C
7F
80
18
22
0F
50
58
37
21
21
24
23
17
4A
21
28
C4
8C
68
94
12
8F
7F
7F
06
3C
7F
80
1E
28
0F
51
60
37
1D
23
1E
1F
16
43
22
2A
C4
8C
61
78
11
A4
7F
7F
06
37
7F
80
23
2D
0F
51
60
33
1A
23
18
18
16
35
21
25
C4
8C
59
5C
12
D8
7F
7F
06
37
7F
80
23
2D
0F
51
60
33
1A
23
18
18
16
35
21
25
C4
8C
59
5C
11
D2
7F
7F
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Rev. 1.4, 2007-02
32
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
2 GByte
2 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×8) 1 Rank (×4)
Label Code
PC2– PC2– PC2– PC2–
5300R–555 4200R–444 3200R–333 3200R–333
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.1
HEX
Rev. 1.2
HEX
Rev. 1.1
HEX
Byte#
Description
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
37
32
54
32
35
36
30
30
30
48
52
33
53
41
20
20
20
20
5x
37
32
54
32
35
36
30
30
30
48
52
33
2E
37
41
20
20
20
5x
37
32
54
31
32
38
30
30
31
48
52
35
41
20
20
20
20
20
3x
37
32
54
32
35
36
30
30
30
48
52
35
41
20
20
20
20
20
5x
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Rev. 1.4, 2007-02
33
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
2 GByte
2 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×8) 1 Rank (×4)
Label Code
PC2– PC2– PC2– PC2–
5300R–555 4200R–444 3200R–333 3200R–333
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.1
HEX
Rev. 1.2
HEX
Rev. 1.1
HEX
Byte#
Description
92
93
94
Test Program Revision Code
xx
xx
xx
xx
00
FF
xx
xx
xx
xx
00
FF
xx
xx
xx
xx
00
FF
xx
xx
xx
xx
00
FF
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
Rev. 1.4, 2007-02
34
03062006-GD6J-14FP
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Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
5
Package Outlines
FIGURE 5
Package Outline Raw Card A L-DIM-240-11
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03062006-GD6J-14FP
35
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Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
FIGURE 6
Package Outline Raw Card C L-DIM-240-13
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Rev. 1.4, 2007-02
03062006-GD6J-14FP
36
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
6
Product Type Nomenclature
(DDR2 DRAMs and DIMMs)
Qimonda’s nomenclature uses simple coding combined with
some propriatory coding. Table 21 provides examples for
module and component product type number as well as the
field number. The detailed field description together with
possible values and coding explanation is listed for modules
in Table 22 and for components in Table 23.
TABLE 21
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
DDR2 DRAM
HYS
HYB
64
18
T
T
64/128
0
2
0
0
K
A
M
C
–5
–5
–A
—
512/1G 16
TABLE 22
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
2
Qimonda Module Prefix
Module Data Width [bit]
HYS
64
Constant
Non-ECC
ECC
72
3
4
DRAM Technology
T
DDR2
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
512 MByte
1 GByte
2 GByte
4 GByte
64
128
256
512
0 .. 9
0, 2, 4
0 .. 9
A .. Z
D
5
6
7
8
9
Raw Card Generation
Number of Module Ranks
Product Variations
Look up table
1, 2, 4
Look up table
Look up table
SO-DIMM
Package, Lead-Free Status
Module Type
M
Micro-DIMM
Registered
Unbuffered
Fully Buffered
R
U
F
Rev. 1.4, 2007-02
37
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Field
Description
Values
Coding
10
Speed Grade
–2.5F
–2.5
–3
PC2–6400 5–5–5
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
PC2–4200 4–4–4
PC2–3200 3–3–3
First
–3S
–3.7
–5
11
Die Revision
–A
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 23
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
2
3
4
Qimonda Component Prefix
Interface Voltage [V]
HYB
18
Constant
SSTL_18
DRAM Technology
T
DDR2
Component Density [Mbit]
256
512
1G
2G
40
256 Mbit
512 Mbit
1 Gbit
2 Gbit
5+6
Number of I/Os
×4
80
×8
16
×16
7
8
Product Variations
Die Revision
0 .. 9
A
Look up table
First
B
Second
9
Package, Lead-Free Status
Speed Grade
C
FBGA, lead-containing
FBGA, lead-free
DDR2-800 5-5-5
DDR2-800 6-6-6
DDR2-667 4-4-4
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
F
10
–25F
–2.5
–3
–3S
–3.7
–5
Rev. 1.4, 2007-02
38
03062006-GD6J-14FP
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Currents Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4
5
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Rev. 1.4, 2007-02
39
03062006-GD6J-14FP
Internet Data Sheet
Edition 2007-02
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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