IDGV51-05A1F1C-40X [QIMONDA]
Synchronous Graphics RAM, 16MX32, CMOS, PBGA170, GREEN, PLASTIC, TFBGA-170;
| 型号： | IDGV51-05A1F1C-40X |
| 厂家： | 
QIMONDA AG |
| 描述： | Synchronous Graphics RAM, 16MX32, CMOS, PBGA170, GREEN, PLASTIC, TFBGA-170 动态存储器 内存集成电路 |
| 文件： | 总21页 (文件大小：911K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2008
IDGV51-05A1F1C-[40X/50X/55X]
512Mbit x32/x16 GDDR5 SGRAM
EU RoHS compliant
Internet Data Sheet
Rev. 1.20
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
IDGV51-05A1F1C-[40X/50X/55X]
Revision History: 2008-12, Rev. 1.20
Page
Subjects (major changes since last revision)
Speed bin -55X added, speed bin -45X removed
All
Previous Revision: Rev. 1.11, 2007-10
All Typos corrected
Previous Revision: Rev. 1.10, 2008-09
Figure1 - Maximum data rate for RDQS mode increased to 3.0 Gbps; PLL-off mode restricted to 4.0 Gbps
Previous Revision: Rev. 1.00, 2008-06
All 36X speed bin removed
5
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Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_A4, 4.22, 2008-07-22
11092007-TJ6A-WC0N
2
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
General Use Restriction
This document as well as any and all information, products,
trademarks, logos, graphics, and images provided in this
document (collectively "Materials") are copyrighted or
trademarked and are the property of Qimonda AG and it's
subsidiaries (collectively "Qimonda"). Any unauthorized use
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your company / legal entity. You agree to keep the Material
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that, you have no right to modify, edit, alter or enhance any of
the Materials in any manner. This limited license terminates
automatically, without notice to you, if you breach any of
these terms. Upon termination you agree to immediately
destroy any Materials.
Qimonda grants you the limited right to use the Materials for
the sole purpose of evaluating the products of Qimonda
("Products") to the extent this evaluation is related to your
(potential) purchase of such Products. You agree not to use
the Materials for any other purpose without the prior written
consent of Qimonda. Without limitation, you agree not to
reproduce, re-distribute, sell, publish, broadcast or circulate
any information contained in the materials to anyone outside
THE MATERIALS ARE PROVIDED BY QIMONDA ON AN
AS IS BASIS, AND QIMONDA EXPRESSLY DISCLAIMS
ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING WITHOUT LIMITATION WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE, WITH RESPECT TO ANY MATERIALS.
Rev. 1.20, 2008-12
3
11092007-TJ6A-WC0N
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
1
Overview
1.1
Features
•
Monolithic 512Mbit GDDR5 SGRAM (2Mbit x 32 I/O x 8
banks and 4Mbit x 16 I/O x 8 banks)
x32/x16 mode configuration set at power-up with EDC pin
Quarter data-rate differential clock inputs CK/CK for
address and commands
Two half data-rate differential clock inputs WCK/WCK,
each associated with two data bytes (DQ, DBI, EDC)
Single ended interface for data, address and command
Double Data Rate (DDR) data (WCK)
Single Data Rate (SDR) command (CK)
Double Data Rate (DDR) addressing (CK)
Write data mask function (single/double byte mask) via
address bus
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Auto Precharge option for each burst access
Programmable CAS latency: 6 to 20 tCK
Programmable Write latency: 3 to 7 tCK
Programmable CRC READ latency: 0 to 2 tCK
Programmable CRC WRITE latency: 8 to 11 tCK
Digital tRAS lockout
RDQS mode on EDC pin
Data output mode for Vendor ID, density and FIFO depth
Low Power modes
On-chip temperature sensor with read-out
Auto refresh and self refresh modes
32ms data retention (8k cycles)
Automatic temperature sensor controlled self refresh rate
On-die termination (ODT): nom. values of 60 Ω or 120 Ω
Pseudo open drain (POD–15) compatible outputs (40 Ω
pulldown, 60 Ω pullup)
•
•
•
•
•
•
•
•
•
•
•
8 internal banks
4 bank groups for tCCD = 3 tCK
8n prefetch architecture: 256 bit per array Read or Write
access
•
ODT and output driver strength auto-calibration with
•
•
•
•
•
•
Burst Length: 8 only
Data bus inversion (DBI) and address bus inversion (ABI)
Input/output PLL on/off mode
external resistor ZQ pin (120 Ω)
•
•
Programmable termination and driver strength offsets
Selectable external or internal VREF for data inputs;
programmable offsets for internal VREF
Separate external VREF for address / command inputs
Boundary Scan function with SEN pin
Mirror function with MF pin
Address training: address input monitoring via DQ pins
WCK2CK clock training: phase information via EDC pins
Data read and write training via Read FIFO
(FIFO depth = 5)
Read FIFO pattern preload by LDFF command
Direct write data load to Read FIFO by WRTR command
Consecutive read of Read FIFO by RDTR command
Programmable EDC hold pattern for CDR
Read/Write data transmission integrity secured by cyclic
redundancy check (CRC–8)
•
•
•
•
•
•
•
•
•
•
•
•
V
V
DD 1.5V +/- 3%
DDQ 1.5V +/- 3%
PG-TFBGA 170
RoHS Compliant Product1)
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.20, 2008-12
4
11092007-TJ6A-WC0N
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
TABLE 1
Ordering Information
Part Number1)
Organization
Max. Data Rate
(Gbps/pin)
Package
IDGV51-05A1F1C – 40X
IDGV51-05A1F1C – 50X
IDGV51-05A1F1C – 55X
×32 / x16
4.0
5.0
5.5
PG-TFBGA 170
1) I: Qimonda Identifier, D: DRAM, GV: GDDR5, 51: 512Mbit, 0: 1 x CS, 5: x32, A1: 1st node, F1: FBGA, C: Commercial 0° - 85/95°C
1.2
Description
The Qimonda GDDR5 SGRAM is a high speed dynamic random-access memory designed for applications requiring high
bandwidth. It contains 536,870,912 bits and is internally configured as a 8-bank DRAM.
The GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high-speed operation. It can be configured
to operate in x32 mode or x16 (clamshell) mode. The mode is detected during device initialization. The GDDR5 interface
transfers two 32 bit wide data words per WCK clock cycle to/from the I/O pins. Corresponding to the 8n prefetch a single write
or read access consists of a 256 bit wide, two CK clock cycle data transfer at the internal memory core and eight corresponding
32 bit wide one-half WCK clock cycle data transfers at the I/O pins.
The GDDR5 SGRAM operates from a differential clock CK and CK. Commands are registered at every rising edge of CK.
Addresses are registered at every rising edge of CK and every rising edge of CK.
GDDR5 replaces the pulsed strobes (WDQS & RDQS) used in previous DRAMs such as GDDR4 with a free running differential
forwarded clock (WCK/WCK) with both input and output data registered and driven respectively at both edges of the forwarded
WCK.
Read and write accesses to the GDDR5 SGRAM are burst oriented; accesses start at a selected location and continue for a
total of eight data words. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident with the ACTIVE command and the next rising CK edge are used to
select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command and
the next rising CK edge are used to select the bank and the column location for the burst access.
Rev. 1.20, 2008-12
5
11092007-TJ6A-WC0N
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
1.3
Operating Frequency Ranges
Figure 1 provides an overview of the operating frequency ranges for PLL-on and PLL-off operation in normal and RDQS
modes.
FIGURE 1
Operating Modes and Frequency Ranges
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Rev. 1.20, 2008-12
6
11092007-TJ6A-WC0N
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
2
Configuration
2.1
Signal Description
TABLE 2
Signal Description
Signal
Type Detailed Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. Command inputs are latched on the rising edge of
CK. Address inputs are latched on the rising edge of CK and the rising edge of CK. All latencies
are referenced to CK. CK and CK are externally terminated.
WCK01,
WCK01,
WCK23,
WCK23
Input
Data Clocks: WCK and WCK are differential clocks used for WRITE data capture and READ data
output. WCK01/WCK01 is associated with DQ0-DQ15, DBI0, DBI1, EDC0 and EDC1.
WCK23/WCK23 is associated with DQ16-DQ31, DBI2, DBI3, EDC2 and EDC3. WCK clocks
operate at nominally twice the CK clock frequency.
CKE
Input
Clock Enable: CKE LOW activates and CKE HIGH deactivates internal clock, device input buffers
and output drivers. Taking CKE HIGH provides Precharge Power-Down and Self Refresh
operations (all banks idle), or Active Power-Down (row active in any bank). CKE is synchronous for
Power-Down entry and exit and for Self Refresh entry and exit. CKE must be maintained LOW
throughout READ and WRITE accesses.
Input buffers excluding CK, CK, CKE, WCK01, WCK01, WCK23, WCK23 are disabled during
Power-Down. Input buffers excluding CKE are disabled during Self Refresh.
The value of CKE latched at power-up with RESET going HIGH determines the termination value
of the address and command inputs.
CS
Input
Chip Select: CS LOW enables, and CS HIGH disables the command decoder. All commands are
masked when CS is registered HIGH, but internal command execution continues. CS provides for
individual device selection on memory channels with multiple memory devices. CS is considered
part of the command code.
RAS, CAS, WE Input
Command inputs: RAS, CAS, and WE (along with CS) define the command to be entered.
BA0 - BA3
Input
Bank Address inputs: BA0-BA3 select to which internal bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied. BA0-BA3 also determine which Mode Register is
accessed with a MODE REGISTER SET command. BA0-BA3 are sampled with the rising edge of
CK.
A0 - A11
Input
Address inputs: A0-A11 provide the row address for ACTIVE commands. A0-A5(A6) provide the
column address and A8 defines the auto precharge function for READ and WRITE commands, to
select one location out of the memory array in the respective bank. The address inputs also provide
the op-code during a MODE REGISTER SET command, and the data bits during LDFF commands.
A8-A11 are sampled with the rising edge of CK and A0-A7 are sampled with the rising edge of CK.
DQ0 - DQ31
DBI0 - DBI3
I/O
I/O
Data Input/Output: 32 bit data bus
Data bus inversion: DBI0 is associated with DQ0-DQ7, DBI1 with DQ8-DQ15, DBI2 with DQ16-
DQ23, and DBI3 with DQ24-DQ31.
Rev. 1.20, 2008-12
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11092007-TJ6A-WC0N
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
Signal
Type Detailed Function
EDC0 - EDC3 Output Error Detection Code: The calculated CRC data is transmitted on these pins. Used also for x16
mode detection, EDC hold pattern and RDQS function. EDC0 is associated with DQ0-DQ7, EDC1
with DQ8-DQ15, EDC2 with DQ16-DQ23, and EDC3 with DQ24-DQ31.
ABI
Input
-
Address bus inversion
ZQ
Impedance Reference: external reference pin for auto-calibration
RESET
Input
Reset: RESET is a VDDQ CMOS input. RESET LOW asynchronously initiates a full chip reset. With
RESET LOW all ODTs are disabled.
MF
Input
Input
Mirror Function: MF is a VDDQ CMOS input. Must be tied to Power or Ground.
Scan Enable: SEN is a VDDQ CMOS input. Must be tied to Ground when not in use.
SEN
VREFC
VREFD
Supply Reference voltage for command and address inputs.
Supply Reference voltage for DQ and DBI inputs.
V
V
DD, VSS
Supply Power and Ground for the internal logic.
DDQ, VSSQ
Supply Isolated power and ground for the input and output buffers.
NC
-
Not Connected.
2.2
Ballout and Mirror Function Mode
The GDDR5 SGRAM provides a mirror function (MF) pin to change the physical location of command, address, data and WCK
pins and assist in routing devices back to back. The pins affected by this Mirror Function mode are listed in Table 3. Figure 2
and Figure 3 show the ballouts for non-mirrored (MF=0) and mirrored (MF=1) modes.
TABLE 3
Ball Assignment with Mirror Function
Ball Signal
MF=0
Ball Signal
MF=0
Ball Signal
MF=0
Ball Signal
Ball Signal
MF=1
MF=1
MF=1
MF=0
MF=1
MF=0 MF=1
A2
B2
C2
D2
E2
F2
DQ1
DQ3
DQ25 G3 RAS
CAS
T4
U4
D5
H5
DQ26
DQ24
DQ2
DQ0
H11 BA0 A2 BA2 A4 E13 DQ13 DQ21
K11 BA2 A4 BA0 A2 F13 DQ15 DQ23
DQ27 L3
CAS
DQ0
DQ2
RAS
EDC0 EDC3 A4
DQ24
DQ26
WCK01 WCK23 M11 DQ22
A9 A1 A11 A6 N11 DQ20
A11 A6 A9 A1 T11 DQ18
WCK23 WCK01 U11 DQ16
DQ14
DQ12
DQ10
DQ8
M13 DQ23 DQ15
N13 DQ21 DQ13
P13 DBI2 DBI1
R13 EDC2 EDC1
T13 DQ19 DQ11
U13 DQ17 DQ9
DBI0
DQ5
DQ7
DBI3
B4
DQ29 D4
DQ31 E4
WCK01 WCK23 K5
DQ4
DQ6
DQ28
DQ30
P5
M2 DQ31 DQ7
F4
H4
K4
H10 BA3 A3 BA1 A5 G12 CS
K10 BA1 A5 BA3 A3 L12 WE
WE
N2
P2
R2
T2
U2
DQ29 DQ5
DBI3 DBI0
A10 A0 A8 A7
A8 A7
CS
A10 A0 A11 DQ8
DQ16
DQ18
DQ20
DQ22
A13 DQ9
B13 DQ11
C13 EDC1
D13 DBI1
DQ17
DQ19
EDC2
DBI2
EDC3 EDC0 M4 DQ30
DQ6
DQ4
B11 DQ10
E11 DQ12
DQ27 DQ3
DQ25 DQ1
N4
P4
DQ28
WCK23 WCK01 F11 DQ14
Functions within the GDDR5 SGRAM that refer to external signals are transparent with respect to Mirror Function mode,
meaning that the signal names shown in the respective functional description apply both to mirrored (MF=1) and non-mirrored
(MF=0) modes. The referenced package pin is determined by the Mirror Function mode the devices is configured to.
Rev. 1.20, 2008-12
8
11092007-TJ6A-WC0N
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
FIGURE 2
Ballout, MF = 0 (Top View)
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Rev. 1.20, 2008-12
11092007-TJ6A-WC0N
9
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
FIGURE 3
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Rev. 1.20, 2008-12
11092007-TJ6A-WC0N
10
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
2.3
Addressing
The GDDR5 SGRAM uses a DDR address scheme to reduce pins required on the GDDR5 SGRAM as shown in Table 4. The
address should be provided to the GDDR5 SGRAM in two parts; the first half is latched on the rising edge of CK along with the
command pins such as RAS, CAS and WE; the second half is latched on the rising edge of CK.
The use of DDR addressing allows all address values to be latched in at the same rate as the SDR commands. All addresses
related to command access have been positioned for latching on the initial rising edge for faster decoding.
TABLE 4
Address Pairs
Clock Edge
Address Inputs
Rising CK
Rising CK
A8
A7
A11
A6
BA1
A5
BA2
A4
BA3
A3
BA0
A2
A9
A1
A10
A0
Two addressing schemes are supported for x32 mode and x16 mode, which differ only in the number of valid column
addresses, as shown in Table 5.
TABLE 5
Addressing Scheme
16Mx32
32Mx16
Row Address
Column addresses
Number of Banks
Bank address
Autoprecharge
Refresh
A0-A11
A0-A5
8
A0-A11
A0-A6
8
BA0-BA2
A8
BA0-BA2
A8
8K/32 ms
3.9 μs
2 KB
8K/32 ms
3.9 μs
2 KB
Refresh period
Page size
Bank Groups
4
4
Rev. 1.20, 2008-12
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11092007-TJ6A-WC0N
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
2.4
Commands
TABLE 6
Command Truth Table
Operation
Code
CKE CKE CS RAS CAS WE BA3- A11 A10 A8 A6-A7, A0-A5 Note
n-1
n
BA0
A9
(A6)
1)2)8)
1)2)8)
1)2)3)
1)2)4)
1)2)5)9)
1)2)5)
1)2)7)
1)2)
Device Deselect
No Operation
DESEL
NOP
MRS
ACT
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
L
H
L
L
L
L
L
L
L
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
Mode Register Set
Bank Activate
Read
MRA OPCODE
L
H
H
H
H
H
L
BA
BA
BA
BST
X
Row Address
RD
H
H
H
H
H
H
H
H
L
L
H
H
L
L
L
L
L
L
L
H
L
X
CA
CA
Read with Autoprecharge
Load FIFO
RDA
LDFF
RDTR
WR
X
L
DATA
Read Training
Write
H
L
L
X
X
X
X
X
X
1)2)5)
1)2)5)
1)2)5)
1)2)5)
BA
BA
BA
BA
L
CA
CA
CA
CA
Write with Autoprecharge
WRA
L
L
H
L
Write with Single Byte Mask WSM
L
H
H
Write with Autoprecharge,
Single Byte Mask
WSMA
L
H
1)2)5)
1)2)5)
Write with Double Byte Mask WDM
L
L
L
L
L
L
H
H
L
L
L
L
BA
BA
H
H
L
L
L
X
X
CA
CA
Write with Autoprecharge,
Double Byte Mask
WDMA
H
1)2)
1)2)
1)2)
1)6)
1)
Write Training
Precharge
WRTR
PRE
L
L
L
L
L
L
H
L
L
L
L
H
L
H
L
L
H
L
H
L
L
L
X
H
X
X
X
X
H
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
H
H
L
L
BA
X
L
Precharge All
Refresh
PREALL L
L
L
H
X
X
REF
PDE
L
L
L
H
X
H
X
H
H
X
H
X
Power Down Mode Entry
X
H
X
H
L
X
H
X
H
L
X
1)
Power Down Mode Exit
PDX
H
L
X
X
X
X
X
X
1)6)
1)
Self Refresh Entry
Self Refresh Exit
SRE
SRX
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
H
X
H
X
H
1) H = logic H level; L = logic L level; X = Don’t Care. Signal may be H or L, but not floating
2) Addresses shown are logical addresses; physical addresses are inverted when address bus inversion (ABI) is activated and ABI=L
3) BA0-BA3 provide the Mode Register address (MRA), A0-A11 the opcode to be loaded
4) BA0-BA3 provide the bank address (BA), A0-A11 provide the row address (RA)
5) BA0-BA3 provide the bank address, A0-A5 (A6) provide the column address (CA); no sub-word addressing within a burst of 8
6) This command is REFRESH when CKE(n) = L, and Self Refresh Entry when CKE(n) is H
7) BA0-BA3 and CA are used to select burst location (BST) and data respectively
8) DESELECT and NO OPERATION are functionally interchangeable
9) In address training mode READ is decoded from the command pins only with RAS = H, CAS = L, WE = H
Rev. 1.20, 2008-12
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11092007-TJ6A-WC0N
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
3
Mode Registers
The Mode Registers define the specific mode of operation. MR0 to MR6 and MR15 are defined as shown in the overview in
Figure 4. MR7 to MR14 are not used.
All Mode Registers are programmed via the MODE REGISTER SET (MRS) command and will retain the stored information
until they are reprogrammed or a subsequent reset. Mode Registers must be loaded when all banks are idle and no bursts are
in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of
these requirements will result in unspecified operation.
All Mode Registers are initialized upon reset with all 0’s (exception: MR4, bits A0-A3: ’1111’). However, the user shall program
all Mode Registers to the desired values e.g upon device initialization.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. RFU bits are
reserved for future use and must be programmed to 0.
FIGURE 4
Mode Registers Overview
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Rev. 1.20, 2008-12
11092007-TJ6A-WC0N
13
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
4
Electrical Characteristics
4.1
Absolute Maximum Ratings
TABLE 7
Absolute Maximum Ratings
Parameter
Symbol Ratings
Unit
Min.
Max.
Device supply voltage
Output buffer supply voltage
Input Voltage
VDD
VDDQ
VIN
-0.5
-0.5
-0.5
-0.5
-55
—
2.0
V
2.0
V
2.0
V
Output Voltage
VOUT
TSTG
TJ
2.0
V
Storage Temperature
Junction Temperature
Short Circuit Output Current
+150
+125
50
°C
°C
mA
IOUT
—
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage of
the device. This is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of these specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 1.20, 2008-12
14
11092007-TJ6A-WC0N
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
4.2
Operation Conditions
TABLE 8
DC Operating Conditions
Parameter 1)
Symbol
POD-15
Unit Notes
Min.
Typ.
Max.
2)
Device supply voltage
VDD
1.455
1.5
1.5
1.545
V
2)
Output supply voltage
VDDQ
1.455
1.545
V
3)4)
Reference voltage for DQ/DBI inputs
VREFD
0.69 * VDDQ
0.69 * VDDQ
0.71 * VDDQ
0.71 * VDDQ
—
V
5)
Reference voltage for command and address inputs VREFC
Input logic high voltage for address/command inputs VIHA(DC)
Input logic low voltage for address/command inputs VILA(DC)
Input logic high voltage for DQ/DBI inputs with VREFD VIHD(DC)
Input logic low voltage for DQ/DBI inputs with VREFD VILD(DC)
Input logic high voltage for RESET, SEN + MF inputs VIHR
Input logic low voltage for RESET, SEN + MF inputs VILR
V
VREFC + 0.15
V
V
V
V
V
V
V
—
VREFC - 0.15
VREFD + 0.1
—
—
VREFD - 0.1
1.05
—
—
0.3
—
Input logic high voltage in scan mode for all input
except RESET, SEN + MF inputs
VIHS
VDDQ - 0.3
Input logic low voltage in scan mode for all inputs
VILS
—
0.3
—
V
6)
Input logic high voltage for EDC1/2 (x16 mode detect) VIHX
Input logic low voltage for EDC1/2 (x16 mode detect) VILX
VDDQ - 0.3
V
6)
—
0.3
V
CK, CK, WCK and WCK single ended input voltage
Clock input mid-point voltage
VINCK
- 0.3
V
DDQ + 0.3
REFC + 0.1
V
7)8)9)10)
VMP(DC)
VREFC - 0.1
V
V
8)11)
CK/CK DC input differential voltage
WCK/WCK DC input differential voltage
VIDCK(DC) 0.22
VIDWCK(DC) 0.2
—
—
+5
V
9)12)13)
V
14)
Input leakage current (any input 0 V ≤ VIN ≤ VDDQ; all IIL
-5
µA
other pins not under test = 0 V)
14)
Output leakage current (DQs are disabled; 0 V ≤ VOUT IOZ
-5
+5
µA
≤ VDDQ
)
Output logic low voltage
External resistor value
VOL(DC)
—
0.62
125
V
ZQ
115
120
Ω
1) 0°C ≤ Tc ≤ 95°C. All voltages are measured at the package pins.
2) GDDR5 SGRAMs are designed to tolerate PCB designs with separate VDDQ and VDD power regulators.
3) AC noise in the system is estimated at 50mV peak-to-peak for the purpose of DRAM design.
4) Source of reference voltage and control of Reference voltage for DQ and DBI pins is determined by VREFD and VREFD Offset Mode
Registers.
5) External VREFC is to be provided by the controller as there is no alternative supply.
6)
VIHX and VILX define the input voltage levels for the receiver that detects x32 mode or x16 mode with RESET going HIGH..
7) This provides a minimum of 0.95V and a maximum of 1.15V, and is always 70% of VDDQ with POD-15. DRAM timings relative to CK cannot
be guaranteed if these limits are exceeded. .
8) For AC operations, all DC clock requirements must be satisfied as well.
9) The value of VIXCK and VIXWCK is expected to equal 70% of VDDQ for the transmitting device and must track variations of the DC level of the
same.
Rev. 1.20, 2008-12
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11092007-TJ6A-WC0N
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
10) The CK and CK input reference level (for timing referenced to CK and CK) is the point at which CK and CK cross.
11) VIDCK is the magnitude of the difference between the input level on CK and the input level on CK.
12) The WCK and WCK input reference level (for timing referenced to WCK and WCK) is the point at which WCK and WCK cross.
13) VIDWCK is the magnitude of the difference between the input level on WCK and the input level on WCK.
14) IIL and IOL are measured with ODT off.
TABLE 9
AC Operating Conditions
Parameter 1)2)
Symbol
POD-15
typ.
Unit Notes
min.
max.
Input logic high voltage for address/command inputs VIHA(AC)
Input logic low voltage for address/command inputs VILA(AC)
Input logic high voltage for DQ/DBI inputs with VREFD VIHD(AC)
Input logic low voltage for DQ/DBI inputs with VREFD VILD(AC)
V
REFC + 0.2
—
V
V
V
V
V
V
—
VREFC - 0.2
VREFD + 0.15
—
—
VREFD - 0.15
3)4)
5)6)
3)7)
5)7)
CK/CK input differential voltage
VIDCK(AC) 0.4
VIDWCK(AC) 0.3
—
—
WCK/WCK input differential voltage
CK/CK input crossing point voltage
WCK/WCK input crossing point voltage
VIXCK(AC)
V
REFC - 0.12
REFD - 0.1
V
REFC + 0.12 V
REFD + 0.1
VIXWCK(AC)
V
V
V
1) 0°C ≤ Tc ≤ 95°C. All voltages are measured at the package pins.
2) For optimum performance it is recommended that signal swings are larger than shown in the table.
3) The CK and CK input reference level (for timing referenced to CK and CK) is the point at which CK and CK cross.
4) IDCK is the magnitude of the difference between the input level on CK and the input level on CK.
5) The WCK and WCK input reference level (for timing referenced to WCK and WCK) is the point at which WCK and WCK cross..
6) IDWCK is the magnitude of the difference between the input level on WCK and the input level on WCK.
V
V
7) The value of VIXCK and VIXWCK is expected to equal 70% of VDDQ for the transmitting device and must track variations of the DC level of the
same.
Rev. 1.20, 2008-12
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11092007-TJ6A-WC0N
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
5
Package
5.1
Package Outline
FIGURE 5
Package Outline
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Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
List of Illustrations
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Operating Modes and Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ballout, MF = 0 (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ballout, MF = 1 (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Mode Registers Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Rev. 1.20, 2008-12
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11092007-TJ6A-WC0N
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ball Assignment with Mirror Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Rev. 1.20, 2008-12
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11092007-TJ6A-WC0N
Internet Data Sheet
IDGV51-05A1F1C
512MBit GDDR5 Graphics RAM
Contents
General Use Restriction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
1.3
2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ballout and Mirror Function Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
2.2
2.3
2.4
3
Mode Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
4.1
4.2
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Rev. 1.20, 2008-12
20
11092007-TJ6A-WC0N
Internet Data Sheet
Edition 2008-12
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2008.
All Rights Reserved.
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THE INFORMATION GIVEN IN THIS INTERNET DATA SHEET SHALL IN NO EVENT BE REGARDED AS A GUARANTEE
OF CONDITIONS OR CHARACTERISTICS. WITH RESPECT TO ANY EXAMPLES OR HINTS GIVEN HEREIN, ANY
TYPICAL VALUES STATED HEREIN AND/OR ANY INFORMATION REGARDING THE APPLICATION OF THE DEVICE,
QIMONDA HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND, INCLUDING WITHOUT
LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.
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For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
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Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Under no circumstances may the Qimonda product as referred to in this Internet Data Sheet be used in
1. Any applications that are intended for military usage (including but not limited to weaponry), or
2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining
or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if
a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly -
(i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or
(ii) Cause the failure of such Critical Systems; or
b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly -
(i) Endanger the health or the life of the user of such Critical Systems or any other person; or
(ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to
property, whether tangible or intangible).
www.qimonda.com
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