IDSH1G-04A1F1C-16J_技术文档

December 2008

IDSH1G–02A1F1C

IDSH1G–03A1F1C

IDSH1G–04A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

DDR3 SDRAM

EU RoHS Compliant Products

Advance

Internet Data Sheet

Rev. 0.65

Advance Internet Data Sheet

IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

Revision History: Rev. 0.65, 2008-12

45-47 IDD Values added

Previous Revision: Rev. 0.64, 2008-11

Page 20

Page 18

Page 9

Added the explanation for RTT_WR -00B - in Chapter 2.4, Mode Register 2 (MR2)

Changed the explanation for RTT_NOM -000B - in Chapter 2.3, Mode Register 1 (MR1)

Added explanation for ODT in Table 3 “Input / Output Signal Functional Description” on Page 9

Previous Revision: Rev. 0.63, 2008-06

Added more products

Page 43

Page 28

Added new table Table 35 “DDR3-DLL_off Speed Bins and Operating Conditions” on Page 43

Added values in Table 16 “DC and AC Input Levels for Single-Ended Command, Address and Control

Signals” on Page 28

Page 34

Changed CIO for DDR3-1066 to 2.7 pF in chapter 3.8

Previous Revision: Rev. 0.62, 2008-03

Added errata data sheet

Added output drive impedance of 40 Ohm

Updated output slew rates

Updated IDD tables

Previous Revision: Rev. 0.61, 2008-02

Editorial changes

Previous Revision: Rev. 0.60, 2007-12

Added new product IDSH1G-03A1F1C-16H, IDSH1G-03A1F1C-16J, IDSH1G-03A1F1C-16K, IDSH1G-

03A1F1C-16G

Previous Revision: Rev. 0.51, 2007-12

Page 9

Page 7

Added “termination data strobe “ in table 3

Corrected figure, Ballout for 1Gb × 8 Components

Editorial changes

Previous Revision: Rev. 0.50, 2007-11

Inital document

Added more products

Page 43

Page 28

Added new table Table 35 “DDR3-DLL_off Speed Bins and Operating Conditions” on Page 43

Added values in Table 16 “DC and AC Input Levels for Single-Ended Command, Address and Control

Signals” on Page 28

Page 34

Changed CIO for DDR3-1066 to 2.7 pF in chapter 3.8

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

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qag_techdoc_A4, 4.22, 2008-07-22

12192007-S9AR-ZT6N

2

Advance Internet Data Sheet

IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

1

Overview

This chapter gives an overview of the 1-Gbit Double-Data-Rate-Three (DDR3) SDRAM component product family and

describes its main characteristics.

1.1

Features

The 1-Gbit DDR3 SDRAM offers the following key features:

•

1.5 V ± 0.075 V supply voltage for V_DDand V_DDQ

SDRAM configurations with ×4, ×8 and ×16 data in/outputs

Eight internal banks for concurrent operation

8-Bit prefetch architecture

Page Size:1 kByte page size for ×4 and ×8,

2 kByte page size for ×16 components

•

Programmable read burst ordering: interleaved or nibble

sequential

Multi-purpose register (MPR) for readout of non-memory

related information

System level timing calibration support via write leveling

and MPR read pattern

•

Asynchronous RESET

•

Differential clock inputs (CK/CK)

Auto-Precharge operation for read and write commands

Refresh, Self-Refresh and power saving Power-down

modes; Auto Self-refresh (ASR) and Partial array self

refresh (PASR)

Average Refresh Period 7.8 µs at a T_OPERup to 85 °C,

3.9 µs up to 95 °C

Bi-directional, differential data strobe pair (DQS/DQS) is

transmitted / received with data. Edge aligned with read

data and center-aligned with write data

DLL aligns transmitted read data and strobe pair transition

with clock

Push-pull output driver with nominal R_ONof 34 Ω and 40 Ω

at V_OUT= V_DDQ/2

Programmable on-die termination (ODT) for data, data

•

Operating temperature range 0 - 85 °C and 85 - 95 °C

Data mask function for write operation

Commands can be entered on each positive clock edge

Data and data mask are referenced to both edges of a

differential data strobe pair (double data rate)

CAS latency (CL): 5, 6, 7, 8, 9, 10 and 11

Posted CAS with programmable additive latency (AL = 0,

CL–1 and CL–2) for improved command, address and

data bus efficiency

Read Latency RL = AL + CL

Programmable CAS Write Latency (CWL) per operating

frequency

mask and differential strobe pairs

Dynamic ODT mode for improved signal integrity and pre-

selectable termination impedances during writes

Terminate DQS (TDQS) Feature for Mix of ×4 and ×8

based Memory Modules within a Memory Channel

ZQ Calibration for output driver and on-die termination

using external reference resistor to ground

Two reference voltage inputs V_REFDQ, V_REFCA

Lead and halogen free packages: 78 ball (P(G)-TFBGA-

60) for ×4 and ×8 components

•

Write Latency WL = AL + CWL

Burst length 8 (BL8) and burst chop 4(BC4) modes: fixed

via mode register (MRS) or selectable On-The-Fly (OTF)

•

Lead and halogen free packages: 96 ball (P(G)-TFBGA-

84) for ×16 components, 0.8 × 0.8 mm ball pitch

Rev. 0.65, 2008-12

3

12192007-S9AR-ZT6N

Advance Internet Data Sheet

IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

1.2

Product List

The product list shows all possible products within the 1-Gbit DDR3 SDRAM first component generation. Availability depends

on application needs. For Qimonda product type nomenclature see Chapter 7.

TABLE 1

Ordering Information

QAG Part Number

Max. Clock

frequency

CAS-RCD-RP

latencies

Speed Sort Name Package

DDR3 SDRAM Components in ×4 Organization (256M × 4)

IDSH1G-02A1F1C-10F

IDSH1G-02A1F1C-13G

IDSH1G-02A1F1C-13H

533

667

7-7-7

8-8-8

9-9-9

DDR3-1066F

DDR3-1333G

DDR3-1333H

PG-TFBGA-78

DDR3 SDRAM Components in ×8 Organization (128M × 8)

IDSH1G-03A1F1C-08D

IDSH1G-03A1F1C-08E

IDSH1G-03A1F1C-10F

IDSH1G-03A1F1C-10G

IDSH1G-03A1F1C-13G

IDSH1G-03A1F1C-13H

IDSH1G-03A1F1C-16G

IDSH1G-03A1F1C-16H

IDSH1G-03A1F1C-16J

IDSH1G-03A1F1C-16K

400

533

667

800

5-5-5

DDR3-800D

DDR3-800E

DDR3-1066F

DDR3-1066G

DDR3-1333G

DDR3-1333H

DDR3-1600G

DDR3-1600H

DDR3-1600J

DDR3-1600K

PG-TFBGA-78

6-6-6

7-7-7

8-8-8

9-9-9

8-8-8

9-9-9

10-10-10

11-11-11

DDR3 SDRAM Components in ×16 Organization (64M × 16)

IDSH1G-04A1F1C-10F

IDSH1G-04A1F1C-10G

IDSH1G-04A1F1C-13G

IDSH1G-04A1F1C-13H

IDSH1G-04A1F1C-16G

IDSH1G-04A1F1C-16H

IDSH1G-04A1F1C-16J

IDSH1G-04A1F1C-16K

533

667

800

7-7-7

DDR3-1066F

DDR3-1066G

DDR3-1333G

DDR3-1333H

DDR3-1600G

DDR3-1600H

DDR3-1600J

DDR3-1600K

PG-TFBGA-96

8-8-8

9-9-9

8-8-8

9-9-9

10-10-10

11-11-11

Rev. 0.65, 2008-12

4

12192007-S9AR-ZT6N

Advance Internet Data Sheet

IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

1.3

DDR3 SDRAM Addressing

TABLE 2

1-Gbit DDR3 SDRAM Addressing

Configuration

256Mbit × 4

128Mbit × 8

64Mbit × 16

Note

Internal Organization

Number of Banks

Bank Address

8 banks × 32 Mbits × 4

8 banks × 16 Mbits × 8 8 banks × 8 Mbits × 16

8

BA[2:0]

A[13:0]

8K

BA[2:0]

A[13:0]

8K

BA[2:0]

A[12:0]

4K

Row Address

Number of addressable Rows

Column Address

A[9:0], A11

A[9:0]

1024

A[9:0]

1024

1)

2)

Number of addressable Columns 2048

(page length)

Page Size

1 KB

2 KB

Auto-Precharge

Burst length on-the-fly bit

A10 / AP

A12/BC

A10 / AP

A12/BC

1) Page length is the number of addressable columns and is defined as 2^COLBITS, where COLBITS is the number of column address bits,

excluding A10/AP and A12/BC

2) Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered.

Page size is per memory bank and calculated as follows: Page Size = 2^COLBITS× ORG/8, where COLBITS is the number of column address

bits and ORG is the number of DQ bits for a given SDRAM configuration (×4, ×8 or ×16).

Rev. 0.65, 2008-12

5

12192007-S9AR-ZT6N

Advance Internet Data Sheet

IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

1.4

Package Ballout

Figure 1, Figure 2 and Figure 3 show the ballouts for DDR3 SDRAM components. See Chapter 6 for package outlines.

FIGURE 1

Ballout for 1Gb ×4 Components (PG-TFBGA-78)

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

G

H

J

K

L

M

N

VSS

VDDQ

VSSQ

VREFDQ

NC

ODT

NC

VSS

VDD

VSS

VDD

VSS

VDD

VSSQ

DQ2

NF

VDDQ

VSS

VDD

CS

BA0

A3

A5

A7

RESET

NC

DQ0

DQS

NF

RAS

CAS

WE

BA2

A0

NF

DM

DQ1

VDD

NF

VSS

VSSQ

DQ3

VSS

NF

VSS

VDD

ZQ

VDD

VDDQ

VSSQ

VDDQ

NC

CKE

NC

VSS

VDD

VSS

VDD

VSS

A

B

C

D

E

F

G

H

J

K

L

M

N

CK

A10/AP

NC

A12 / BC BA1

V

REFCA

A2

A9

A13

A1

A11

NC

A4

A6

A8

Top View

DRAM

MPPH0260

Rev. 0.65, 2008-12

6

12192007-S9AR-ZT6N

Advance Internet Data Sheet

IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

FIGURE 2

Ballout for 1Gb × 8 Components (PG-TFBGA-78)

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

G

H

J

VSS

VDDQ

VSSQ

VREFDQ

NC

ODT

NC

VSS

VDD

VSSQ

DQ2

DQ6

VDDQ

VSS

VDD

CS

NC

DQ0

DQS

DQ4

RAS

CAS

WE

NU/TDQS VSS

DM/TDQS VSSQ

VDD

VDDQ

VSSQ

VDDQ

NC

CKE

NC

VSS

A

B

C

D

E

F

G

H

J

DQ1

VDD

DQ7

CK

A10/AP

NC

DQ3

VSS

DQ5

VSS

VDD

ZQ

REFCA

BA1

A4

BA0

A3

A5

BA2

A0

A2

V

K

L

VDD

VSS

A12 / BC

A1

VDD

VSS

K

L

M

N

VDD

VSS

A7

RESET

A9

A13

A11

NC

A6

A8

VDD

VSS

M

N

Top View

DRAM

MPPH0270

Rev. 0.65, 2008-12

7

12192007-S9AR-ZT6N

Advance Internet Data Sheet

IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

FIGURE 3

Ballout for 1Gb × 16 Components (PG-TFBGA-96)

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

G

H

J

VDDQ

VSSQ

VDDQ

VSSQ

VSS

VDDQ

VSSQ

VREFDQ

NC

ODT

NC

VSS

VDD

DQU5

VDD

DQU3

VDDQ

VSSQ

DQL2

DQL6

VDDQ

VSS

VDD

CS

BA0

A3

A5

DQU7

VSS

DQU1

DMU

DQL0

DQSL

DQL4

RAS

CAS

WE

BA2

A0

A2

A9

NC

DQU4

DQSU

DQU0

DML

DQL1

VDD

DQL7

CK

VDDQ

DQU6

DQU2

VSSQ

DQL3

VSS

DQL5

VSS

VDD

VSS

VSSQ

VDDQ

VDD

VDDQ

VSSQ

VDDQ

NC

CKE

NC

VSS

VDD

VSS

A

B

C

D

E

F

G

H

J

K

L

CK

A10/AP

NC

K

L

ZQ

VREFCA

M

N

P

R

T

M

N

P

R

T

A12 / BC BA1

VSS

VDD

VSS

A1

A11

NC

A4

A6

A8

A7

RESET

VDD

VSS

Top View

DRAM

MPPH0280

Rev. 0.65, 2008-12

8

12192007-S9AR-ZT6N

Advance Internet Data Sheet

IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

1.5

Input / Output Signal Functional Description

TABLE 3

Input / Output Signal Functional Description

Symbol

EDA Signal Name¹⁾Type

Function

CK, CK

ck_t, ck_c

Input

Clock: CK and CK are differential clock inputs. All address and control

input signals are sampled on the crossing of the positive edge of CK and

negative edge of CK.

CKE

cke

Input

Clock Enable: CKE High activates, and CKE Low deactivates internal

clock signals and device input buffers and output drivers. Taking CKE

Low provides Precharge Power-Down and Self-Refresh operation (all

banks idle), or Active Power-Down ( active row in any bank). CKE is

asynchronous for Self-Refresh exit. After V_REFCAand V_REFDQhave

become stable during the power on and initialization sequence, they

must be maintained during all operations (including Self-Refresh).

CKE must be maintained High throughout read and write accesses.

Input buffers, excluding CK, CK, ODT, CKE and RESET are disabled

during Power-down. Input buffers, excluding CKE and RESET are

disabled during self refresh.

CS

cs_n

Input

Chip Select: All command are masked when CS is registered High.

CS provides for external Rank selection on systems with multiple ranks.

CS is considered part of the command code.

RAS, CAS, WE

ODT

ras_n, cas_n, we_n Input

odt Input

Command Inputs: RAS, CAS and WE (along with CS) define the

command being entered.

On-Die Termination: ODT (registered High) enables termination

resistance internal to the DDR3 SDRAM. When enabled, ODT is only

applied to each DQ, DQS, DQS and DM signal for ×4/×8 configurations.

For ×16 configuration ODT is applied to each DQ, DQSU, DQSU,

DQSL, DQSL, DMU and DML signal.

The ODT signal will be ignored if Mode Registers MR1 and MR2 are

programmed to disable ODT and during Self Refresh.

DM (×4, ×8); DMU, dm (×4); dm_tdqs_t Input

Input Data Mask: DM is an input mask signal for write data. Input data

is masked when DM is sampled High coincident with that input data

during a Write access. DM is sampled on both edges of DQS. DMU and

DML are the input mask signals for ×16 components and control the

lower or upper bytes.

DML (×16)

(×8); dmu, dml (×16)

TDQS/TDQS

dm_tdqs_t,

nu_tdqs_c

Termin Termination Data Strobe: TDQS/TDQS is applicable for ×8 DRAMs

ation

Input

only. When enabled via Mode Register A11 = 1 in MR1, the DRAM will

enable the same termination resistance function on TDQS/TDQS that is

applied to DQS/DQS. When disabled via mode register A11 = 0 in MR1,

DM/TDQS will provide the data mask function and TDQS is not used.

×4/×16 DRAMs must disable the TDQS function via mode register A11

= 0 in MR1.

BA0 - BA2

ba0 - ba2

Bank Address Inputs: Define to which bank an Active, Read, Write or

Precharge command is being applied. Bank address also determines

which mode register is to be accessed during a mode register set cycle.

Rev. 0.65, 2008-12

9

12192007-S9AR-ZT6N

Advance Internet Data Sheet

IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

Symbol

EDA Signal Name¹⁾Type

Function

A0 - A13(×4, ×8); a0 - a13(×4, ×8); a0- Input

Address Inputs: Provides the row address for Active commands and

the column address for Read/Write commands to select one location

out of the memory array in the respective bank. (A10/AP and A12/BC

have additional functions, see below). The address inputs also provide

the op-code during Mode Register Set commands. For numbers of

addresses used on this assembly see Table 2.

A0-A12(×16)

a12(×16)

A10 / AP

a10

Input

Auto-Precharge: A10/AP is sampled during Read/Write commands to

determine whether Auto-Precharge should be performed to the

accessed bank after the Read/Write operation. (High: Auto-Precharge,

Low: no Auto-Precharge). A10/AP is sampled during Precharge

command to determine whether the Precharge applies to one bank

(A10 Low) or all banks (A10 High). If only one bank is to be precharged,

the bank is selected by bank addresses.

A12 / BC

a12

Burst Chop: A12/BC is sampled during Read and Write commands to

determine if burst chop (on-the-fly) will be performed. (High: no burst

chop, Low: burst chopped). See “Command Truth Table” on Page 11

for details.

DQ (×4, ×8);

dq (×4, ×8)

Input/

Data Input/Output: Bi-directional data bus.

DQL/DQU (×16)

dql/dqu (×16)

Output

DQS / DQS (×4,

×8);

DQSL, DQSL,

DQSU,

DQSU(×16)

dqs_t / dqs_c (×4,

×8);

dqsl_t, dqsl_c,

Input/

Data Strobe: output with read data, input with write data. Edge-aligned

Output with read data, centered in write data. For the ×16, DQSL corresponds

to the data on DQL0 - DQL7; DQSU corresponds to the data on DQU0-

DQU7.The data strobes DQS, DQSL and DQSU are paired with

differential signals DQS, DQSL and DQSU, respectively, to provide

differential pair signaling to the system during both reads and writes.

DDR3 SDRAM supports differential data strobe only and does not

support single-ended.

dqsu_t, dqsu_c (×16)

RESET

reset_n

CMOS Active Low Asynchronous Reset: Reset is active when RESET is

Input

Low, and inactive when RESET is High. RESET must be High during

normal operation. RESET is a CMOS rail to rail signal with DC High and

Low are 80% and 20% of V_DD, RESET active is destructive to data

contents.

NC

—

No Connect: no internal electrical connection is present

NF

—

No Function

V_DDQ

V_SSQ

V_DD

vddq

vssq

vdd

vss

Supply DQ Power Supply: 1.5 V ± 0.075 V

Supply DQ Ground

Supply Power Supply: 1.5 V ± 0.075 V

Supply Ground

V_SS

V_REFDQ

V_REFCA

ZQ

vrefdq

vrefca

zq

Supply Reference Voltage for DQ

Supply Reference Voltage for Command and Address inputs

Supply Reference ball for ZQ calibration

1) The EDA Signal Name is used in Qimonda's Simulation Models such as IBIS, Verilog, etc.

Note: Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, and RESET) do not supply termination.

Rev. 0.65, 2008-12

10

12192007-S9AR-ZT6N

Advance Internet Data Sheet

IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

2

Functional Description

The DDR3 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank SDRAM.

2.1

Truth Tables

The truth tables list the input signal values at a given clock

edge which represent a command or state transition expected

to be executed by the DDR3 SDRAM . Table 4 lists all valid

commands to the DDR3 SDRAM. For a detailed description

of the various power mode entries and exits please refer to

Table 5. In addition, the DM functionality is described in

Table 6.

TABLE 4

Command Truth Table

Function

Abbr.

CKE

CS RAS CAS WE BA2 A15 A12/ A10/ A11, Note

BC AP A9-A0

-

Prev. Curr.

Cycle Cycle

BA0 A13

1)2)3)4)5)

Mode Register Set

Refresh

MRS

REF

SRE

SRX

H

L

H

L

H

L

V

H

L

H

L

BA OP Code

1)2)3)4)5)

L

H

V

H

L

V

1)2)3)4)5)6)7)8)

1)2)3)4)5)6)7)8)9)

Self-Refresh Entry

Self-Refresh Exit

L

H

V

H

L

1)2)3)4)5)

1)2)3)4)5)10)

Single Bank Precharge

Precharge all Banks

Active

PRE

PREA

ACT

WR

H

BA

V

L

V

L

H

L

BA RA (Row Address)

Write (BL8MRS or

BC4MRS)

BA RFU V

L

CA

1)2)3)4)5)10)

Write (BC4OTF)

Write (BL8OTF)

WRS4

WRS8

H

L

H

L

BA RFU L

BA RFU H

BA RFU V

L

CA

Write w/AP (BL8MRS or WRA

BC4MRS)

H

1)2)3)4)5)10)

Write w/AP (BC4OTF)

Write w/AP (BL8OTF)

WRAS4 H

WRAS8 H

H

L

H

L

BA RFU L

BA RFU H

BA RFU V

H

L

CA

Read (BL8MRS or

BC4MRS)

RD

H

1)2)3)4)5)10)

Read (BC4OTF)

Read (BL8OTF)

RDS4

RDS8

H

L

H

L

H

BA RFU L

BA RFU H

BA RFU V

L

H

CA

Read w/AP (BL8MRS or RDA

BC4MRS)

1)2)3)4)5)10)

1)2)3)4)5)11)

Read w/AP (BC4OTF)

Read w/AP (BL8OTF)

No Operation

RDAS4

H

L

H

L

H

BA RFU L

BA RFU H

H

V

CA

V

RDAS8

NOP

H

V

Rev. 0.65, 2008-12

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Advance Internet Data Sheet

IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

Function

Abbr.

CKE

CS RAS CAS WE BA2 A15 A12/ A10/ A11, Note

-

BC AP A9-A0

Prev. Curr.

Cycle Cycle

BA0 A13

1)2)3)4)5)12)

Device Deselect

DES

PDE

H

L

H

L

X

H

V

H

V

H

X

H

V

H

V

H

X

H

V

H

V

L

X

V

X

V

X

V

X

V

X

V

1)2)3)4)5)8)13)

Power Down Entry

H

1)2)3)4)5)8)13)

Power Down Exit

PDX

L

H

L

V

H

1)2)3)4)5)

ZQ Calibration Short

ZQ Calibration Long

ZQCS

ZQCL

H

L

X

L

X

L

H

1) BA = Bank Address, RA = Row Address, CA = Column Address, BC = Burst Chop, AP = Auto Precharge, X = Don’t care, V = valid

2) All DDR3 SDRAM commands are defined by states of CS, RAS, CAS, WE and CKE at the rising edge of the clock. The higher order

address bits of BA, RA and CA are device density and IO configuration (×4, ×8, ×16) dependent.

3) RESET is a low active signal which will be used only for asynchronous reset. It must be maintained High during any function.

4) Bank addresses (BA) determine which bank is to be operated upon. For MRS, BA selects a Mode Register.

5) V means H or L (but a defined logic level) and X means either “defined or undefined (like floating) logic level”.

6) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh

7)

V_REF(both V_REFCAand V_REFDQ) must be maintained during Self Refresh operation.

8) Refer to “Clock Enable (CKE) Truth Table for Synchronous Transitions” on Page 13 for more detail with CKE transition.

9) Self refresh exit is asynchronous.

10) Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS.

11) The No Operation (NOP) command should be used in cases when the DDR3 SDRAM is in an idle or a wait state. The purpose of the NOP

command is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A NOP command will not

terminate a previous operation that is still executing, such as a read or write burst.

12) The Deselect command (DES) performs the same function as a No Operation command.

13) The Power Down Mode does not perform any refresh operation.

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1-Gbit Double-Data-Rate-Three SDRAM

TABLE 5

Clock Enable (CKE) Truth Table for Synchronous Transitions

Current State ¹⁾CKE(N-1)²⁾CKE(N)²⁾

Command (N)³⁾RAS, Action (N)³⁾

CAS, WE, CS

Note

Current

Cycle

4)5)6)7)8)9)

Power Down

Self Refresh

L

H

L

H

L

X

Maintain Power Down

4)5)6)7)8)10)

L

DES or NOP

X

Power Down Exit

4)5)6)7)9)11)

L

Maintain Self Refresh

Self Refresh Exit

4)5)6)7)11)12)13)

4)5)6)7)8)10)14)

4)5)6)7)8)10)14)15)

4)5)6)7)10)

L

DES or NOP

REF

Bank(s) Active

Reading

H

Active Power Down Entry

Power Down Entry

Writing

Power Down Entry

Precharging

Refreshing

All Banks Idle

Power Down Entry

Precharge Power Down Entry

Self Refresh Entry

4)5)6)7)10)8)14)16)

4)5)6)7)14)16)17)

4)5)6)7)18)

Any other state

Refer to “Command Truth Table” on Page 11 for more detail with all command signals

1) Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N.

2) CKE(N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.

3) COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N),ODT is not included here.

4) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

5) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

6) CKE must be registered with the same value on t_CKE.MINconsecutive positive clock edges. CKE must remain at the valid input level the

entire time it takes to achieve the t_CKE.MINclocks of registeration. Thus, after any CKE transition, CKE may not transition from its valid level

during the time period of t_IS+ t_CKE.MIN+ t_IH.

7) DES and NOP are defined in “Command Truth Table” on Page 11.

8) The Power Down does not perform any refresh operations

9) X means Don’t care (including floating around V_REFCA) in Self Refresh and Power Down. It also applies to address pins.

10) Valid commands for Power Down Entry and Exit are NOP and DES only

11) V_REF(both V_REFCAand V_REFDQ) must be maintained during Self Refresh operation.

12) On Self Refresh Exit DES or NOP commands must be issued on every clock edge occurring during the t_XSperiod. Read, or ODT

commands may be issued only after t_XSDLLis satisfied.

13) Valid commands for Self Refresh Exit are NOP and DES only.

14) Self Refresh can not be entered while Read or Write operations are in progress.

15) If all banks are closed at the conclusion of a read, write or precharge command then Precharge Power-down is entered, otherwise Active

Power-down is entered.

16) ‘Idle state’ is defined as all banks are closed (t_RP, t_DAL, etc. satisfied), no data bursts are in progress, CKE is High, and all timings from

previous operations are satisfied (t_MRD, t_MOD, t_RFC, t_ZQ.INIT, t_ZQ.OPER, t_ZQCS, etc.) as well as all Self-Refresh exit and Power-Down Exit

parameters are satisfied (t_XS, t_XP, t_XPDLL, etc.).

17) Self Refresh mode can only be entered from the All Banks Idle state.

18) Must be a legal command as defined in “Command Truth Table” on Page 11.

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TABLE 6

Data Mask (DM) Truth Table

Name (Function)

DM

DQs

Write Enable

Write Inhibit

L

Valid

X

H

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2.2

Mode Register 0 (MR0)

The mode register MR0 stores the data for controlling various

operating modes of DDR3 SDRAM. It controls burst length,

read burst type, CAS latency, test mode, DLL reset, WR

(write recovery time for auto-precharge) and DLL control for

precharge Power-Down, which includes various vendor

specific options to make DDR3 SDRAM useful for various

applications. The mode register is written by asserting Low on

CS, RAS, CAS, WE, BA0, BA1, and BA2, while controlling the

states of address pins according to Table 7.

BA2 BA1 BA0 A13 A12 A11 A10

A9

A8

A7

A6

A5

CL

A4

A3

A2

CL

A1

A0

DLL

res

0

0¹⁾PPD

WR

TM

RBT

BL

MPBH0470

TABLE 7

MR0 Mode register Definition, BA[2:0]=000_B

Field

Bits¹⁾

Description

Burst Length (BL) and Control Method

BL

A[1:0]

Number of sequential bits per DQ related to one Read/Write command.

00_BBL8MRS mode with fixed burst length of 8. A12/BC at Read or Write command time is Don’t care

at read or write command time.

01_BBLOTF on-the-fly (OTF) enabled using A12/BC at Read or Write command time. When A12/BC is

High during Read or Write command time a burst length of 8 is selected (BL8OTF mode). When

A12/BC is Low, a burst chop of 4 is selected (BC4OTF mode). Auto-Precharge can be enabled or

disabled.

10_BBC4MRS mode with fixed burst chop of 4 with t_CCD= 4 × n_CK. A12/BC is Don’t care at Read or

Write command time.

11_BTBD Reserved

RBT

A3

Read Burst Type

0_B

1_B

Nibble Sequential

Interleaved

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Field

Bits¹⁾

Description

CL

A[6:4,2] CAS Latency (CL)

CAS Latency is the delay, in clock cycles, between the internal Read command and the availability of the

first bit of output data.

Note: For more information on the supported CL and AL settings based on the operating clock frequency,

refer to “Speed Bins” on Page 37.

Notes

1. All other bit combinations are reserved.

2. The table only shows the encodings for a given CAS Latency. For actual supported CAS Latency,

please refer to speed bin tables for each frequency

0000_BRESERVED

0010_B

0100_B

0110_B

1000_B

1010_B

5

6

7

8

9

1100_B10

1110_B11

0001_B12

0011_B13

0101_B14

0111_B15

1001_B16

1011_BRESERVED

1101_BRESERVED

1111_BRESERVED

TM

A7

Test Mode

The normal operating mode is selected by MR0(bit A7 = 0) and all other bits set to the desired values

shown in this table. Programming bit A7 to a 1 places the DDR3 SDRAM into a test mode that is only

used by the SDRAM manufacturer and should NOT be used. No operations or functionality is guaranteed

if A7 = 1.

0_B

1_B

Normal Mode

Vendor specific test mode

DLLres A8

DLL Reset

The internal DLL Reset bit is self-clearing, meaning it returns back to the value of 0 after the DLL reset

function has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any

time the DLL reset function is used, t_DLLKmust be met before any functions that require the DLL can be

used (i.e. Read commands or synchronous ODT operations).

0_B

1_B

No DLL Reset

DLL Reset triggered

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Field

Bits¹⁾

Description

WR

A[11:9] Write Recovery for Auto-Precharge

Number of clock cycles for write recovery during Auto-Precharge. WR_MINin clock cycles is calculated by

dividing t_WR.MIN(in ns) by the actual t_CK.AVG(in ns) and rounding up to the next integer: WR.MIN [n_CK] =

Roundup(t_WR.MIN[ns] / t_CK.AVG[ns]). The WR value in the mode register must be programmed to be equal

or larger than WR.MIN. The resulting WR value is also used with t_RPto determine t_DAL. Since WR of 9

and 11 is not implemented in DDR3 and the above formula results in these values, higher values have

to be programmed.

Note: The table only shows the encodings for Write Recovery. For actual Write recovery timing, please

refer to AC timing table.

000_B16

001_B

010_B

011_B

100_B

5

6

7

8

101_B10

110_B12

111_B14

PPD

A12

Precharge Power-Down DLL Control

Active Power-Down will always be with DLL-on. Bit A12 will have no effect in this case. For Precharge

Power-Down, bit A12 in MR0 is used to select the DLL usage as shown below.

0_B

Slow Exit. DLL is frozen during precharge Power-down.Read and synchronous ODT commands

are only allowed after t_XPDLL

.

1_B

Fast Exit. DLL remains on during precharge Power-down.Any command can be applied after t_XP,

provided that other timing parameters are satisfied.

1) A13, A14 and A15 - even if not available on a specific device - must be programmed to 0_B.

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2.3

Mode Register 1 (MR1)

The Mode Register MR1 stores the data for enabling or on CS, RAS, CAS, WE, High on BA0 and Low on BA1and

disabling the DLL, output driver strength, R_{TT_NOM}impedance, BA2, while controlling the states of address pins according to

additive latency (AL), Write leveling enable and Qoff (output Table 8.

disable). The Mode Register MR1 is written by asserting Low

BA2 BA1 BA0 A13 A12 A11 A10 A9

A8

0

A7

A6

A5

A4

A3

A2

A1

A0

RTT_

nom

RTT_

nom

RTT_

nom

DLL

dis

0

0¹⁾Qoff TDQS

0

Level

DIC

AL

DIC

MPBH0480

TABLE 8

MR1 Mode Register Definition, BA[2:0]=001_B

Field

Bits¹⁾

Description

DLL Disable

DLLdis

A0

The DLL must be enabled for normal operation. DLL enable is required during power up initialization,

after reset and upon returning to normal operation after having the DLL disabled. During normal

operation (DLL-on) with MR1(A0 = 0), the DLL is automatically disabled when entering Self-Refresh

operation and is automatically re-enabled and reset upon exit of Self-Refresh operation. Any time the

DLL is enabled, a DLL reset must be issued afterwards. Any time the DLL is reset, t_DLLKclock cycles

must occur before a Read or synchronous ODT command can be issued to allow time for the internal

clock to be synchronized with the external clock. Failing to wait for synchronization to occur may

result in a violation of the t_DQSCK, t_AON, t_AOFor t_ADCparameters. During t_DLLK, CKE must continuously

be registered high. DDR3 SDRAM does not require DLL for any Write operation.

0_B

1_B

DLL is enabled

DLL is disabled

DIC

A[5, 1]

Output Driver Impedance Control

Note: All other bit combinations are reserved.

00_BNominal Drive Strength RON40 = RZQ/6 (nominal 40.0 Ω, with nominal RZQ = 240 Ω)

01_BNominal Drive Strength RON34 = RZQ/7 (nominal 34.3 Ω, with nominal RZQ = 240 Ω)

R_{TT_NOM}

A[9, 6, 2] Nominal Termination Resistance of ODT

Notes

1. If R_{TT_NOM}is used during Writes, only the values R_ZQ/2, R_ZQ/4 and R_ZQ/6 are allowed.

2. In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 1, all R_TT_Nom settings are allowed; in

Write Leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 0, only R_{TT_NOM}settings of R_ZQ/2, R_ZQ/4

and R_ZQ/6 are allowed.

3. All other bit combinations are reserved.

000_B

R_{TT_NOM}disabled, R_{TT_WR}is controlled independently via MR2

001_BRTT60 = RZQ / 4 (nominal 60 Ω with nominal RZQ = 240 Ω)

010_BRTT120 = RZQ / 2 (nominal 120 Ω with nominal RZQ = 240 Ω

011_BRTT40 = RZQ / 6 (nominal 40 Ω with nominal RZQ = 240 Ω)

100_BRTT20 = RZQ / 12 (nominal 20 Ω with nominal RZQ = 240 Ω)

101_BRTT30 = RZQ / 8 (nominal 30 Ω with nominal RZQ = 240 Ω)

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Field

Bits¹⁾

Description

AL

A[4, 3]

Additive Latency (AL)

Any read or write command is held for the time of Additive Latency (AL) before it is issued as internal

read or write command.

Notes

1. AL has a value of CL - 1 or CL - 2 as per the CL value programmed in the MR0 register.

00_B

01_B

10_B

11_B

AL = 0 (AL disabled)

AL = CL - 1

AL = CL - 2

Reserved

Level

TDQS

Qoff

A7

Write Leveling Mode

0_B

1_B

Write Leveling Mode Disabled, Normal operation mode

Write Leveling Mode Enabled

A11

A12

TDQS enable

0_B

1_B

Disable

Enable

Output Disable

Under normal operation, the SDRAM outputs are enabled during read operation and write leveling

for driving data (Qoff bit in the MR1 is set to 0_B). When the Qoff bit is set to 1_B, the SDRAM outputs

(DQ, DQS, DQS, also on upper byte lane in case of ×16) will be disabled - also during write leveling.

Disabling the SDRAM outputs allows users to run write leveling on multiple ranks and to measure I_DD

currents during Read operations, without including the output.

0_B

1_B

Output buffer enabled

Output buffer disabled

1) A13, A14, A15 - even if not available on a specific device - must be programmed to 0_B.

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2.4

Mode Register 2 (MR2)

The Mode Register MR2 stores the data for controlling

refresh related features, R_{TT_WR}impedance, and CAS write

latency. The Mode Register MR2 is written by asserting Low

on CS, RAS, CAS, WE, High on BA1 and Low on BA0 and

BA2, while controlling the states of address signals according

to Table 9.

BA2 BA1 BA0

A13 A12 A11 A10

A9

A8

0

A7

A6

A5

A4

A3

A2

A1

A0

CWL

0

1

0

RTT_WR

SRT ASR

PASR

reg. addr

MPBH0100

TABLE 9

MR2 Mode Register Definition, BA[2:0]=010_B

Field

PASR

Bits¹⁾

A[2:0]

Description

Partial Array Self Refresh (PASR)

If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the

specified self refresh location may get lost if self refresh is entered. During non-self-refresh operation,

data integrity will be maintained if t_REFIconditions are met.

000_BFull array (Banks 000_B- 111_B)

001_BHalf Array(Banks 000_B- 011_B)

010_BQuarter Array(Banks 000_B- 001_B)

011_B1/8th array (Banks 000_B)

100_B3/4 array(Banks 010_B- 111_B)

101_BHalf array(Banks 100_B- 111_B)

110_BQuarter array(Banks 110_B- 111_B)

111_B1/8th array(Banks 111_B)

CWL

A[5:3]

CAS Write Latency (CWL)

Number of clock cycles from internal write command to first write data in.

000_B5 (3.3 ns ≥ t_CK.AVG≥ 2.5 ns)

001_B6 (2.5 ns > t_CK.AVG≥ 1.875 ns)

010_B7 (1.875 ns > t_CK.AVG≥ 1.5 ns)

011_B8 (1.5 ns > t_CK.AVG≥ 1.25 ns)

100_B9 (1.25 ns > t_CK.AVG≥ 1.07 ns)

101_B10 (1.07 ns > t_CK.AVG≥ 0.935 ns)

110_B11 (0.935 ns > t_CK.AVG≥ 0.833 ns)

111_B12 (0.833 ns > t_CK.AVG≥ 0.75 ns)

Note: Besides CWL limitations on t_CK.AVG, there are also t_AA.MIN/MAXrestrictions that need to be

observed. For details, please refer to “Speed Bins” on Page 37.

ASR

A6

Auto Self Refresh (ASR)

When enabled, DDR3 SDRAM will automatically provide appropriate self refresh entry all supported

operating temperature values. If not enabled, the SRT bit must be programmed to indicate T_OPER

during subsequent self refresh operation.

0_B

1_B

Disabled, manual Self-Refresh Reference (SRT)

Auto Self Refresh enabled

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Field

Bits¹⁾

Description

SRT

A7

Self-Refresh Temperature Range (SRT)

If ASR = 0, the SRT bit must be programmed to indicate T_OPERduring subsequent self refresh

operation. If ASR = 1, SRT bit must be set to 0_b.

0_B

1_B

Normal operating temperature range

Extended operating temperature range

R_{TT_WR}

A[10:9]

Dynamic ODT mode and R_{TT_WR}Pre-selection

Notes

1. The R_{TT_WR}value can be applied during writes even when R_{TT_NOM}is disabled. During write

leveling, Dynamic ODT is not available.

00_B

01_B

10_B

Dynamic ODT mode disabled, write does not affect the R_TTvalue

Dynamic ODT mode enabled with R_{TT_WR}= RZQ/4 = 60 Ω

Dynamic ODT mode enabled with R_{TT_WR}= RZQ/2 = 120Ω

1) A13, A14, A15 - even if not available on a specific device - must be programmed to 0_B.

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2.5

Mode Register 3 (MR3)

The Mode Register MR3 controls Multi purpose registers and

optional On-die thermal sensor (ODTS) feature. The Mode

Register MR3 is written by asserting Low on CS, RAS, CAS,

WE, High on BA1 and BA0, and Low on BA2 while controlling

the states of address signals according to Table 10.

BA2 BA1 BA0 A13 A12 A11 A10

A9

0

A8

0

A7

0

A6

0

A5

0

A4

0

A3

0

A2

A1

A0

0

1

0

MPR

MPR loc

MPBH0490

TABLE 10

MR3 Mode Register Definition, BA[2:0]=011_B

Field

Bits¹⁾

Description

Multi Purpose Register Location

MPR loc

A[1:0]

00_B

01_B

10_B

11_B

Pre-defined data pattern for read synchronization

RFU

MPR

A2

Multi Purpose Register Enable

0_B

1_B

MPR disabled, normal memory operation

Dataflow from the Multi Purpose register MPR

1) A13, A14 and A15 - even if not available on a specific device - must be programmed to 0_B.

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2.6

Read / Write Operations and Access Modes

After a bank has been activated, a read or write access can

be executed. This is accomplished by setting RAS High, CS

and CAS Low at the clock’s rising edge. WE must also be

defined at this time to determine whether the access cycle is

a read operation (WE High) or a write operation (WE Low).

The DDR3 SDRAM provides a burst column access

operation. A single Read or Write Command will initiate a

serial read or write operation on successive clock edges.

2.6.1

Burst Order

Accesses within a given burst may be interleaved or nibble

sequential depending on the programmed bit A3 in the mode

register MR0.

column address bits CA[2:0] are ignored during the write

command. For writes with a burst being chopped to 4, the

input on column address 2 (CA[2]) determines if the lower or

upper four burst bits are selected. In this case, the inputs on

the lower 2 column address bits CA[1:0] are ignored during

the write command.The following table shows burst order

versus burst start address for reads and writes of bursts of 8

as well as of bursts of 4 operation (burst chop).

Regarding read commands, the lower 3 column address bits

CA[2:0] at read command time determine the start address

for the read burst.

Regarding write commands, the burst order is always fixed.

For writes with a burst length of 8, the inputs on the lower 3

TABLE 11

Bit Order during Burst

Burst Command Column Address Interleaved Burst Sequence

Nibble Sequential Burst

Sequence

Note

Length

2:0

Bit Order within Burst

CA2 CA1 CA0 1. 2. 3. 4. 5. 6. 7. 8. 1. 2. 3. 4. 5. 6. 7. 8.

1)

8

READ

0

1

V

0

1

0

1

0

1

0

1

V

0

1

0

1

V

0

1

0

1

0

1

0

1

V

0

1

0

1

0

1

0

1

V

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

4

1

0

3

2

5

4

7

6

1

0

3

2

5

4

7

6

1

5

2

3

0

1

6

7

4

5

2

3

0

1

6

7

4

5

2

6

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

7

4

5

6

7

0

1

2

3

4

T

X

5

4

7

6

1

0

3

2

5

T

X

6

7

4

5

2

3

0

1

6

T

X

7

6

5

4

3

2

1

0

7

T

X

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

4

1

2

3

0

5

6

7

4

1

2

3

0

5

6

7

4

1

5

2

3

0

1

6

7

4

5

2

3

0

1

6

7

4

5

2

6

3

0

1

2

7

4

5

6

3

0

1

2

7

4

5

6

3

7

4

5

6

7

0

1

2

3

4

T

X

5

6

7

4

1

2

3

0

5

T

X

6

7

4

5

2

3

0

1

6

T

X

7

4

5

6

3

0

1

2

7

T

X

1)

1)2)

WRITE

READ

1)3)4)

1)2)4)5)

4

(Burst

Chop

Mode)

WRITE

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1) 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.

2) V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.

3) T: output drivers for data and strobe are in high impedance.

4) In case of BC4MRS (burst length being fixed to 4 by MR0 setting), the internal write operation starts two clock cycles earlier than for the

BL8 modes. This means that the starting point for t_WRand t_WTRwill be pulled in by two clocks. In case of BC4OTF mode (burst length being

selected on-the-fly via A12/BC), the internal write operation starts at the same point in time as a burst of 8 write operation. This means that

during on-the-fly control, the starting point for t_WRand t_WTRwill not be pulled in by two clocks.

5) X: Don’t Care

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3

Operating Conditions and

Interface Specification

3.1

Absolute Maximum Ratings

TABLE 12

Absolute Maximum Ratings

Parameter

Symbol

Rating

Min.

Unit

Note

Max.

1)2)

1)

Voltage on V_DDball relative to V_SS

Voltage on V_DDQball relative to V_SS

Voltage on any ball relative to V_SS

Storage Temperature

V_DD

–0.4

–55

+1.975

+100

V

V_DDQ

V

V_IN, V_OUT

T_STG

V

1)3)

°C

1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2)

V

_DDand V_DDQmust be within 300mV of each other at all times. V_REFDQand V_REFCAmust not be greater than 0.6 × V_DDQ. When V_DDand

_DDQare less than 500 mV, V_REFDQand V_REFCAmay be equal or less than 300 mV.

3) Storage Temperature is the case surface temperature on the center/top side of the SDRAM. For the measurement conditions, please refer

to JESD51-2 standard.

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3.2

Operating Conditions

TABLE 13

SDRAM Component Operating Temperature Range

Parameter

Symbol

Rating

Unit

Note

Min.

Max.

1)2)3)

1)3)4)

Normal Operating Temperature Range

Extended Temperature Range

T_OPER

0

85

95

°C

85

1) Operating Temperature T_OPERis the case surface temperature on the center / top side of the SDRAM. For measurement conditions, please

refer to the JEDEC document JESD51-2.

2) The Normal Temperature Range specifies the temperatures where all SDRAM specification will be supported.

3) During operation, the SDRAM operating temperature must be maintained above 0 °C under all operating conditions. Either the device

operating temperature rating may be used to set an appropriate refresh rate and/or to monitor the maximum operating temperature.

4) Some application require operation of the DRAM in the Extended Temperature Range between 85 °C and 95 °C operating temperature.

Full specifications are provided in this range, but the following additional conditions apply:

a) Refresh commands have to be doubled in frequency, therefore reducing the Refresh interval t_REFIto 3.9 µs.

b) If Self-Refresh operation is required in the Extended Temperature Range, than it is mandatory to either use the Manual Self-Refresh

mode with Extended Temperature Range capability (MR2 A6 = 0_Band MR2 A7 = 1_B) or enable the Auto Self-Refresh mode (ASR) (MR2

A6 = 1_Band MR2 A7= 0_B). For SDRAM operations on DIMM module refer to DIMM module data sheets and SPD bytes for Extended

Temperature and Auto Self-Refresh option availability.

TABLE 14

DC Operating Conditions

Supply Voltage

Mode (SVM),

Parameter

Symbol

Min.

Typ.

Max.

Unit Note

V_DD.TYP/ V_DDQ.TYP

1)2)

1.5 V

All

Supply Voltage

V_DD

1.425

1.5

1.575

V

1)2)

Supply Voltage for Output

V_DDQ

V

3)4)

Reference Voltage for DQ, DM inputs V_REFDQ.DC0.49 × V_DD0.5 × V_DD0.51 × V_DD

V

3)4)

Reference Voltage for ADD, CMD

inputs

V_REFCA.DC0.49 × V_DD0.5 × V_DD0.51 × V_DD

V

5)

External Calibration Resistor

R_ZQ237.6 240.0 242.4

Ω

connected from ZQ ball to ground

1) V_DDQtracks with V_DD. AC parameters are measured with V_DDand V_DDQtied together.

2) Under all conditions V_DDQmust be less than or equal to V_DD

.

3) The AC peak noise on V_REFmay not allow V_REFto deviate from V_REF.DCby more than ±1% V_DD(for reference: approx. ± 15 mV).

4) For reference: approx. V_DD/2 ± 15 mV.

5) The external calibration resistor R_ZQcan be time-shared among DRAMs in multi-rank DIMMs.

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TABLE 15

Input and Output Leakage Currents

Parameter

Symbol

Condition

Rating

Unit

Note

Min.

Max.

1)2)

2)3)

Input Leakage Current

Output Leakage Current

I_IL

Any input 0 V < V_IN< V_DD

0V < V_OUT< V_DDQ

–2

–5

+2

+5

µA

I_OL

1) All other balls not under test = 0 V.

2) Values are shown per ball.

3) DQ’s, DQS, DQS and ODT are disabled.

3.3

Interface Test Conditions

Figure 4 represents the effective reference load of 25 Ω used

in defining the relevant timing parameters of the device as

well as for output slew rate measurements. It is not intended

as either a precise representation of the typical system

environment nor a depiction of the actual load presented by a

production tester. System designers should use IBIS or other

simulation tools to correlate the timing reference load to a

system environment. Qimonda correlates to its production

test conditions, generally one or more coaxial transmission

lines terminated at the tester electronics.

FIGURE 4

Reference Load for AC Timings and Output Slew Rates

V_DDQ

DQ

CK, CK

DQS

V

_TT= V_{DDQ / 2}

DUT

DQS

25 ohm

Timing Reference Points

MPBH0370

The Timing Reference Points are the idealized input and

output nodes / terminals on the outside of the packaged

SDRAM device as they would appear in a schematic or an

IBIS model. The output timing reference voltage level for

single ended signals is the cross point with V_TT.The output

timing reference voltage level for differential signals is the

cross point of the true (e.g. DQS) and the complement (e.g.

DQS) signal.

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3.4

Voltage Levels

3.4.1

DC and AC Logic Input Levels

Table 16 shows the input levels for single-ended input signals for Address and Control Signals.

Table 17 shows the input levels for single-ended input signals for DQ and DM Signals.

TABLE 16

DC and AC Input Levels for Single-Ended Command, Address and Control Signals

SVM Parameter

Symbol

DDR3-800, DDR3-1066

DDR3-1333, DDR3-1600

Unit Note

Min.

_REF+ 0.100 V_DD

V_{SS REF}- 0.100 V_SS

_REF+ 0.175 See ²⁾_REF+ 0.175 See ²⁾

_REF- 0.175 See ²⁾

_REF- 0.175

_REF+ 0.150 See ²⁾_REF+ 0.150 See ²⁾

Reduced AC input logic low V_IL.CA.AC150See ²⁾_REF- 0.150 See ²⁾

_REF- 0.150

Max.

Min.

_REF+ 0.100 V_DD

_REF- 0.100

Max.

1)

1.5V DC input logic high

DC input logic low

V_IH.CA.DC

V_IL.CA.DC

V

1)

V

1)

AC input logic high

AC input logic low

V_IH.CA.AC175

V_IL.CA.AC175See ²⁾

V

1)

V

1)

Reduced AC input logic high V_IH.CA.AC150

V

1)

V

1) For input only pins except RESET: V_REF= V_REF.CA

.

2) See Chapter 3.9, Overshoot and Undershoot Specification.

TABLE 17

DC and AC Input Levels for Single-Ended DQ and DM Signals

SVM

Parameter

Symbol

DDR3-800, DDR3-1066

DDR3-1333, DDR3-1600

Unit

Note

Min.

_REF+ 0.100 V_DD

V_{SS REF}- 0.100 V_SS

Max.

Min.

_REF+ 0.100 V_DD

_REF- 0.100

Max.

1)

1.5V

DC input logic high

DC input logic low

AC input logic high

V_IH.DQ.DC

V

1)

V_IL.DQ.DC

V

1)3)

V_IH.DQ.AC175

V_IH.DQ.AC150

V_IL.DQ.AC175

V_IL.DQ.AC150

V

_REF+ 0.175 See ²⁾

_REF+ 0.150 See ²⁾

—

V

_REF+ 0.150 See ²⁾

1)3)

AC input logic low

See ²⁾

V

_REF- 0.175

_REF- 0.150 See ²⁾

—

V

_REF- 0.150

1) For DQ and DM: V_REF= V_REFDQ, for input only signals except RESET: V_REF= V_REFCA

2) See Chapter 3.9, Overshoot and Undershoot Specification.

.

3) Single ended swing requirement for DQS, DQS is 350 mV (peak to peak). Differential swing requirement for DQS, DQS is 700 mV (peak

to peak).

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Differential Swing Requirement for Differential Signals

Table 18 shows the input levels for differential input signals.

TABLE 18

Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

SVM

Parameter

Symbol

DDR3–800, DDR3–1066, DDR3–1333, DDR3–1600 Unit

Note

Min.

Max.

2)

4)

1.5 V

Differential input high

Differential input low

V_IH.DIFF

V_IL.DIFF

+0.200

See ¹⁾

V

–0.200

See ¹⁾

3)

Differential input high AC V_IH.DIFF.AC

Differential input low AC V_IL.DIFF.AC

2 × (V_IH.AC- V_REF

See ¹⁾

)

5)

2 × (V_REF- V_IL.AC

)

1) These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the

respective limits ( V_IH.DC.MAX, V_IL.DC.MIN) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to

Chapter 3.9.

2) Used to define a differential signal slew-rate.

3) Clock: use V_IH.CA.ACfor V_IH.AC. Strobe: use V_IH.DQ.ACfor V_IH.AC

.

4) For CK - CK use V_IH/V_IL.CA.ACof ADD/CMD and V_REFCA; for DQS - DQS (×4, ×8); or DQSL - DQSL, DQSU - DQSU (×16) use V_IH/V_IL.DQ.AC

of DQs and V_REFDQ; if a reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here.

5) Clock: use V_IL.CA.ACfor V_IL.AC. Strobe: use V_IL.DQ.ACfor V_IL.AC

.

TABLE 19

Allowed Time Before Ringback (t_DVAC) for CLK - CLK and DQS - DQS

Slew Rate [V/ns]

SVM: 1.5 V

_DVAC[ps]

t

t_DVAC[ps]

@ |V_{IH/IL.DIFF.AC}| = 350mV

@ |V_{IH/IL.DIFF.AC}| = 300mV

Min.

Max.

Min.

Max.

> 4.0

4.0

75

57

50

38

34

29

22

13

0

—

175

170

167

163

162

161

159

155

150

—

3.0

2.0

1.8

1.6

1.4

1.2

1.0

<1.0

0

Single-Ended Requirements for Differential Signals

Each individual component of a differential signal (for ×4, ×8:

CK, DQS, CK, DQS, for ×16: CK, DQSL, DQSU, CK, DQSL,

DQSU) has also to comply with certain requirements for

single-ended signals. CK and CK have to approximately

reach V_SEH.MIN/ V_SEL.MAX(approximately equal to the AC-

levels (V_IH.CA.AC/ V_IL.CA.AC) for ADD/CMD signals) in every

half-cycle. DQS, DQS (×4, ×8) and DQSL, DQSL, DQSU,

DQSU (×16), respectively, have to reach V_SEH.MIN/ V_SEL.MAX

(approximately the AC-levels (V_IH.DQ.AC/ V_IL.DQ.AC) for DQ

signals) in every half-cycle preceeding and following a valid

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transition. Note that the applicable AC-levels for ADD/CMD

and DQs might be different per speed-bin etc. E.g. if

differential signals have a requirement with respect to V_DD/2;

this is nominally the same. The transition of single-ended

signals through the AC-levels is used to measure setup time.

For single-ended components of differential signals the

requirement to reach V_SEL.MAX, V_SEH.MINhas no bearing on

timing, but adds a restriction on the common mode

charateristics of these signals.

V

_IH.CA.AC150/ V_IL.CA.AC150is used for ADD/CMD signals, then

these AC-levels apply also for the single-ended signals CK

and CK.

Note that while ADD/CMD and DQ signal requirements are

with respect to V_REF, the single-ended components of

TABLE 20

Each Single-Ended Levels for CK, CK, DQS, DQS, DQSL, DQSL, DQSU or DQSU

SVM

Parameter

Symbol

DDR3–800, DDR3–1066, DDR3–1333, DDR3–1600 Unit Note

Min.

Max.

2)3)

Single-ended high-level for strobes V_SEH

Single-ended high-level for CK, CK V_SEH

Single-ended low-level for strobes V_SEL

Single-ended low-level for CK, CK V_SEL

(V_DD/2) + 0.175

See ¹⁾

V

1.5 V

(V_DD/2) - 0.175

See ¹⁾

1) These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the

respective limits ( V_IH.DC.MAX, V_IL.DC.MIN) for single-ended signals as well as the limitations for overshoot and undershoot.

2) For CK, CK use V_IH.CA.AC/V_IL.CA.ACof ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use V_IH.DQ.AC/V_IL.DQ.ACof DQs.

3) V_IH.DQ.AC/V_IL.DQ.ACfor DQs is based on V_REFDQ; V_IH.CA.AC/V_IL.CA.ACfor ADD/CMD is based on V_REFCA; if a reduced AC-high or ac-low level

is used for a signal group, then the reduced level applies also here.

TABLE 21

Cross Point Voltage for Differential Input Signals (CK, DQS)

SVM

Symbol Parameter

DDR3–800, DDR3–1066, DDR3–1333, Unit Note

DDR3–1600

Min.

Max.

1.5 V

V_IX

Differential Input Cross Point Voltage relative –150

150

175

mV

1)

to V_DD/2 for CK - CK

–175

Differential Input Cross Point Voltage relative –150

150

mV

to V_DD/2 for DQS -DQS

1) Extended range for V_IXis only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended

swing V_SEL/V_SEH(see Single-Ended Requirements for Differential Signals) of at least V_DD/2 +/-250 mV and if the differential slew rate

of CK - CK is larger than 3 V/ns.

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3.4.2

DC and AC Output Measurements Levels

TABLE 22

DC and AC Output Levels for Single-Ended Signals

Parameter

Symbol Value

Unit Note

DC output high measurement level (for output impedance measurement)

DC output mid measurement level (for output impedance measurement)

DC output low measurement level (for output impedance measurement)

AC output high measurement level (for output slew rate)

V_OH.DC

V_OM.DC

V_OL.DC

V_OH.AC

V_OL.AC

0.8 × V_DDQ

V

0.5 × V_DDQ

0.2 × V_DDQ

1)

V

_TT+ 0.1 × V_DDQ

_TT- 0.1 × V_DDQ

V

1)

AC output low measurement level (for output slew rate)

V

1) Background: the swing of ± 0.1 × V_DDQis based on approximately 50% of the static differential output high or low swing with a driver

impedance of 40 Ω and an effective test load of 25 Ω to V_TT= V_DDQ/ 2.

TABLE 23

AC Output Levels for Differential Signals

SVM

Parameter

Symbol

Value

Unit Note

Min.

Max.

1)

All

AC differential output high measurement level (for output V_OH.DIFF.AC+0.2 × V_DDQ

V

slew rate)

AC differential output low measurement level (for output V_OL.DIFF.AC–0.2 × V_DDQ

V

slew rate)

2)

1.5 V

Deviation of the output cross pointvoltage from the

termination voltage

V_OX

-100

100

mV

1) Background: the swing of ± 0.2 × V_DDQis based on approximately 50% of the static differential output high or low swing with a driver

impedance of 40 Ω and an effective test load of 25 Ω to V_TT=V_DDQ/ 2 at each of the differential outputs.

2) With an effective test load of 25 Ω to V_TT= V_DDQ/2 at each of the differential outputs (see chapter Chapter 3.3, Interface Test Conditions).

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3.5

ODT DC Impedance and Mid-Level Characteristics

Table 24 provides the ODT DC impedance and mid-level characteristics.

TABLE 24

ODT DC Impedance and Mid-Level Characteristics

Symbol

Description

V_OUTCondition

Min. Nom. Max. Unit

Note

1)2)3)4)

1)2)3)4)5)

R_TT120

R_TT60

R_TT40

R_TT30

R_TT20

ΔV_M

R

_TTeffective = 120 Ω

_TTeffective = 60 Ω

_TTeffective = 40 Ω

_TTeffective = 30 Ω

_TTeffective = 20 Ω

V

_IL.ACand V_IH.AC

0.9

–5

1.0

—

1.6

+5

R

_ZQ/2

_ZQ/4

_ZQ/6

_ZQ/8

_ZQ/12

Deviation of V_Mwith respect to V_DDQ/ 2

floating

%

1) With R_ZQ= 240 Ω.

2) Measurement definition for R_TT: Apply V_IH.ACand V_IL.ACto test ball separately, then measure current I (V_IH.AC) and I (V_IL.AC) respectively.

_TT= [V_IH.AC- V_IL.AC] / [I (V_IH.AC) - I (V_IL.AC)]

R

3) The tolerance limits are specified after calibration with stable voltage and temperature. For the behaviour of the tolerance limits if

temperature or voltage changes after calibration, see the ODT DC Impedance Sensitivity on Temperature and Voltage Drifts.

4) The tolerance limits are specified under the condition that V_DDQ= V_DDand that V_SSQ= V_SS

.

5) Measurement Definition for ΔV_M: Measure voltage (V_M) at test ball (midpoint) with no load: ΔV_M= (2 × V_M/ V_DDQ- 1) × 100%

3.6

ODT DC Impedance Sensitivity on Temperature and

Voltage Drifts

If temperature and/or voltage change after calibration, the tolerance limits widen for R_TTaccording to the following tables. The

following definitions are used:

ΔT = T - T (at calibration)

ΔV = V_DDQ- V_DDQ(at calibration)

V

_DD= V_DDQ

TABLE 25

ODT DC Impedance after proper IO Calibration and Voltage/Temperature Drift

Symbol Value

Min.

Unit

Note

Max.

1)

R_TT

0.9 - dR_TTdT × |ΔT| - dR_TTdV × |ΔV|

1.6 + dR_TTdT × |ΔT| + dR_TTdV × |ΔV|

R_ZQ/ TISF_RTT

1) TISF_RTT: Termination Impedance Scaling Factor for R_TT

TISF_RTT= 12 for R_TT020

:

TISF_RTT= 8 for R_TT030

TISF_RTT= 6 for R_TT040

TISF_RTT= 4 for R_TT060

TISF_RTT= 2 for R_TT120

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TABLE 26

OTD DC Impedance Sensitivity Parameters

Symbol

Value

Min.

Unit

Note

Max.

1)

dR_TTdT

dR_TTdV

0

1.5

%/°C

0.15

%/mV

1) These parameters may not be subject to production test. They are verified by design and characterization.

3.7

Output Slew Rate Definition and Requirements

The slew rate definition depends if the signal is single-ended or differential. For the relevant AC output reference levels see

Chapter 3.4.2.

3.7.1

Output Slew Rates

TABLE 27

Output Slew Rates

SVM

Parameter

Symbol

DDR3–800, DDR3–1066, DDR3–1333,

DDR3–1600

Unit

Note

Min.

Max.

2)3)

1.5 V

Single-ended Output Slew SRQse

Rate

2.5

5 ¹⁾

V / ns

Differential Output Slew

Rate

SRQdiff

5

12

1) In two cases, a maximum slew rate of 6 V/ns applies for a single DQ signal within a byte lane.

- Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to

high) while all remaining DQ signals in the same byte lane are static (i.e they stay at either high or low).

- Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to

high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low

respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.

2) For R_ON= R_ZQ/7 settings only.

3) Background for Symbol Nomenclature: SR: Slew Rate; Q: Query Output; se: single-ended; diff: differential

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3.8

Interface Capacitance

Definition and values for interface capacitances are provided in the following table.

TABLE 28

Interface Capacitance Values

Parameter

Signals

Symbol

DDR3–800 DDR3–1066 DDR3–1333 DDR3–1600 Unit Note

Min. Max. Min. Max. Min. Max. Min. Max.

1)2)3)

Input/Output

Capacitance

DQ, DM, DQS,

DQS, NF

C_IO

1.5 3.0

1.5

2.7

1.5

2.5

1.5

2.3

pF

2)3)

Input Capacitance CK, CK

C_CK

0.8 1.6

0.8

0

1.6

0.8

0

1.4

0.8

0

1.4

2)3)4)

Delta of Input

Capacitance

CK, CK

C_DCK

0

0.15

0.2

0.15

0.15 pF

2)3)5)

Delta of

DQS, DQS

C_DDQS

0

0.2

0

0.15

0

0.15 pF

Input/Output

Capacitance of

DQS balls

2)3)6)

Input Capacitance All other input-only C_I

0.75 1.4

–0.5 0.3

0.75 1.35 0.75 1.3

0.75 1.3

–0.4 0.2

–0.4 0.4

–0.5 0.3

pF

pins

2)3)7)8)

Delta of Input

Capacitance

All CTRL input-only C_DI.CTRL

pins

–0.5 0.3

–0.5 0.5

–0.5 0.3

–0.4 0.2

–0.4 0.4

–0.5 0.3

2)3)9)

10)

Delta of Input

Capacitance

All ADD and CMD C_{DI.ADD_CMD}–0.5 0.5

input-only pins

2)3)11)

Delta of

Input/Output

Capacitance

DQ, DM, DQS,

DQS

C_DIO

–0.5 0.3

12)

ZQ Capacitance

ZQ

C_ZQ

–

3

–

3

–

3

–

3

pF

1) Although the DM signal has different function, the loading matches DQ and DQS

2) This parameter is not subject to production test. It is verified by design and characterization. Capacitance is measured according to JEP147

(Procedure for measuring input capacitance using a vector network analyzer (VNA) with V_DD, V_DDQ, V_SS, V_SSQapplied and all other balls

floating (except the ball under test, CKE, RESET and ODT as necessary). V_DD= V_DDQ= 1.5 V, V_BIAS= V_DD/2 and on-die termination off

3) This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4) Absolute value of C_CK- C_CK#

5) Absolute value of C_IO.DQS- C_IO.DQS#

6) C_Iapplies to ODT, CS, CKE, A[A13:0] (×4, ×8) or A[A12:0] (×16), BA[2:0], RAS, CAS, WE

7)

8)

9)

C

_{DI_CTRL}applies to ODT, CS and CKE

_{DI_CTRL}= C_I.CTRL- 0.5 × (C_CK+ C_CK#

_{DI_ADD_CMD}applies to A[A13:0] (×4, ×8) or A[A12:0] (×16), BA[2:0], BA[2:0], RAS, CAS and WE

)

10) C_{DI_ADD_CMD}= C_I.ADD,CMD- 0.5 × (C_I.CK+ C_I.CK#

)

11) C_DIO= C_IO.DQ,DM- 0.5 × (C_IO.DQS+ C_IO.DQS#

)

12) Maximum external load capacitance on ZQ signal: 5 pF

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3.9

Overshoot and Undershoot Specification

TABLE 29

AC Overshoot / Undershoot Specification for Address and Control Signals

Parameter

DDR3–800 DDR3–1066 DDR3–1333 DDR3–1600 Unit

Note

1)

Maximum peak amplitude allowed for overshoot area 0.4

0.4

V

1)

Maximum peak amplitude allowed for undershoot

area

0.4

1)

Maximum overshoot area above V_DD

Maximum undershoot area below V_SS

0.67

0.5

0.4

0.33

V × ns

1) Applies for the following signals: A[15:0], BA[3:0], CS, RAS, CAS, WE, CKE and ODT

FIGURE 5

AC Overshoot / Undershoot Definitions for Address and Control Signals

Maximum Amplitude

Volts (V)

Overshoot Area

V_DD

V_SS

Undershoot Area

Maximum Amplitude

Time (ns)

MPEH0090

TABLE 30

AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Signals

Parameter

DDR3–80 DDR3–106 DDR3–133 DDR3–160 Unit

Note

0

6

3

0

1)

Maximum peak amplitude allowed for overshoot area 0.4

0.4

V

Maximum peak amplitude allowed for undershoot

area

0.4

1)

Maximum overshoot area above V_DDQ

0.25

0.19

0.15

0.13

V × ns

Maximum undershoot area below V_SSQ

1) Applies for CK, CK, DQ, DQS, DQS & DM

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FIGURE 6

AC Overshoot / Undershoot Definitions for Clock, Data, Strobe and Mask Signals

Maximum Amplitude

Volts (V)

Overshoot Area

V_DDQ

V_SSQ

Undershoot Area

Maximum Amplitude

Time (ns)

MPEH0100

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4

Speed Bins and Timing Parameters

AC timings are provided with CK/CK and DQS/DQS

differential slew rate of 2.0 V/ns. Timings are further provided

for calibrated OCD drive strength. The CK/CK input reference

level (for timing referenced to CK / CK) is the point at which

CK and CK cross. The DQS/DQS reference level (for timing

referenced to DQS/DQS) is the point at which DQS and DQS

cross. Inputs are not recognized as valid until V_REFstabilizes.

During the period before V_REF.CAand V_REFDQstabilizes, CKE

= 0.2 x V_DDQis recognized as low. The output timing reference

voltage level is V_TT.

4.1

Speed Bins

The following tables show DDR3 speed bins and relevant

timing parameters. Other timing parameters are provided in

the following chapter.

The absolute specification for all speed bins is T_OPERand

V_DD= V_DDQ= 1.5 V +/-0.075 V. In addition the following

general notes apply.

General Notes for Speed Bins:

•

The CL setting and CWL setting result in t_CK.AVG.MINand

in module application, t_AA/t_RCD/t_RPshould be programmed

with minimum supported values. For example, DDR3-

1333H supporting down-shift to DDR3-1066F should

program SPD as 13.125 ns for t_AA.MIN(Byte16) / t_{RCD. MIN}

(Byte18) / t_RP(Byte20). DDR3-1600K supporting down-

shift to DDR3-1333H and to DDR3-1066F should program

SPD as 13.125 ns for t_AA.MIN(Byte16) / t_{RCD. MIN}(Byte18) /

t

_CK.AVG.MAXrequirements. When making a selection of

_CK.AVG, both need to be fulfiled: Requirements from CL

setting as well as requirements from CWL setting

•

t

_CK.AVG.MINlimits: Since CAS Latency is not purely analog -

data and strobe output are synchronized by the DLL - all

possible intermediate frequencies may not be provided. An

application should use the next smaller standard t_CK.AVG

value (2.5, 1.875, 1.5, 1.25, 1.07, or 0.935 ns) when

calculating CL [nCK] = t_AA[ns] / t_CK.AVG[ns], rounding up to

the next ‘Supported CL’

t

_RP(Byte20).

•

Any DDR3-1066 speed bin also supports functional

operation at lower frequencies as shown in the tables

which are not subject to Production Tests but verified by

Design/Characterization

Any DDR3-1333 speed bin also supports functional

operation at lower frequencies as shown in the tables

which are not subject to Production Tests but verified by

Design/Characterization

Any DDR3-1600 speed bin also supports functional

operation at lower frequencies as shown in the tables

which are not subject to Production Tests but verified by

Design/Characterization

•

t_CK.AVG.MAXlimits: Calculate t_CK.AVG= t_AA.MAX/

CLSELECTED and round the resulting t_CK.AVGdown to the

next valid speed bin limit (i.e. 3.3 ns or 2.5 ns or 1.875 ns

or 1.5 ns or 1.25 ns or 1.07 ns or 0.935 ns). This result is

t

_CK.AVG.MAXcorresponding to CLSELECTED

•

‘Reserved’ settings are not allowed. User must program a

different value

Downbinning support for DDR3-1333H and DDR3-1600K

parts: The minimum t_AA/t_RCD/t_RPsupported by DDR3-

1333H and DDR3-1600K devices is 13.125 ns. Therefore,

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TABLE 31

DDR3-800 Speed Bins and Operating Conditions

Speed Bin

DDR3-800D

DDR3-800E

Unit Note

CL-nRCD-nRP

QAG Partnumber Extension

Parameter

5-5-5

6-6-6

-08D

-08E

Symbol

Min.

Max.

Min.

Max.

1)

Internal read command to first data

ACT to internal read or write delay time

PRE command period

t_AA

12.5

50.0

5, 6

5

20.0

—

15.0

52.5

6

20.0

—

ns

1)

t_RCD

ns

1)

t_RP

—

ns

1)

ACT to ACT or REF command period

Supported CL Settings

t_RC

—

ns

1)

Sup_CL

Sup_CWL

t_{CK.AVG.CL05.CWL05}

t_{CK.AVG.CL06.CWL05}

n_CK

1)

Supported CWL Settings

5

n_CK

1)2)

Average Clock Period with CL = 5; CWL = 5

Average Clock Period with CL = 6; CWL = 5

2.5

3.3

RESERVED

2.5 3.3

ns

1)2)

2.5

ns

1) Please refer to "General Notes for Speed Bins" at beginning of this chapter.

2) Max. limits are exclusive. E.g. if t_CK.AVG.MAXvalue is 2.5 ns, t_CK.AVGneeds to be < 2.5 ns.

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TABLE 32

DDR3-1066 Speed Bins and Operating Conditions

Speed Bin

DDR3-1066E

DDR3-1066F

DDR3-1066G

Unit Note

CL-nRCD-nRP

QAG Partnumber Extension

Parameter

6-6-6

7-7-7

8-8-8

-10E

-10F

-10G

Symbol

Min.

Max.

Min.

Max.

Min.

Max.

1)

Internal read command to first data t_AA

11.25 20.0

13.125 20.0

15.0

20.0

—

ns

1)

ACT to internal read or write delay

time

t_RCD

11.25

—

13.125

—

ns

1)

PRE command period

t_RP

t_RC

11.25

48.75

—

13.125

50.625

—

15.0

52.5

—

ns

1)

ACT to ACT or REF command

period

ns

1)

Supported CL Settings

Supported CWL Settings

Sup_CL

5, 6, 7, 8

5, 6

6, 7, 8

5, 6

6, 8

5, 6

n_CK

1)

Sup_CWL

n_CK

1)2)

Average Clock Period with CL = 5; t_{CK.AVG.CL05.CWL05}2.5

3.3

RESERVED

ns

CWL = 5

1)2)

Average Clock Period with CL = 5; t_{CK.AVG.CL05.CWL06}RESERVED

RESERVED

ns

CWL = 6

1)2)

Average Clock Period with CL = 6; t_{CK.AVG.CL06.CWL05}2.5

3.3

2.5

3.3

2.5

3.3

ns

CWL = 5

1)2)

Average Clock Period with CL = 6; t_{CK.AVG.CL06.CWL06}1.875 2.5

CWL = 6

RESERVED

1.875 2.5

RESERVED

1.875 2.5

RESERVED

1.875 2.5

ns

1)2)

Average Clock Period with CL = 7; t_{CK.AVG.CL07.CWL05}RESERVED

CWL = 5

ns

1)2)

Average Clock Period with CL = 7; t_{CK.AVG.CL07.CWL06}1.875 2.5

CWL = 6

ns

1)2)

Average Clock Period with CL = 8; t_{CK.AVG.CL08.CWL05}RESERVED

CWL = 5

ns

1)2)

Average Clock Period with CL = 8; t_{CK.AVG.CL08.CWL06}1.875 2.5

ns

CWL = 6

1) Please refer to "General Notes for Speed Bins" at beginning of this chapter.

2) Max. limits are exclusive. E.g. if t_CK.AVG.MAXvalue is 2.5 ns, t_CK.AVGneeds to be < 2.5 ns.

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TABLE 33

DDR3-1333 Speed Bins and Operating Conditions

Speed Bin

DDR3-1333G

DDR3-1333H

Unit Note

CL-nRCD-nRP

QAG Partnumber Extension

Parameter

8-8-8

9-9-9

-13G

-13H

Symbol

Min.

Max.

Min.

Max.

1)

Internal read command to first data

t_AA

12.0

48.0

20.0

—

13.125 20.0

13.125 —

49.125 —

ns

1)

ACT to internal read or write delay time

PRE command period

t_RCD

ns

1)

t_RP

—

ns

1)

ACT to ACT or REF command period

Supported CL Settings

t_RC

—

ns

1)

Sup_CL

5, 6, 7, 8, 9, 10 6,7,8, 9, 10

n_CK

1)

Supported CWL Settings

Sup_CWL

5, 6, 7

2.5

5, 6, 7

n_CK

1)2)

Average Clock Period with CL = 5; CWL = 5

Average Clock Period with CL = 5; CWL = 6

Average Clock Period with CL = 5; CWL = 7

Average Clock Period with CL = 6; CWL = 5

Average Clock Period with CL = 6; CWL = 6

Average Clock Period with CL = 6; CWL = 7

Average Clock Period with CL = 7; CWL = 5

Average Clock Period with CL = 7; CWL = 6

Average Clock Period with CL = 7; CWL = 7

Average Clock Period with CL = 8; CWL = 5

Average Clock Period with CL = 8; CWL = 6

Average Clock Period with CL = 8; CWL = 7

Average Clock Period with CL = 9; CWL = 5

Average Clock Period with CL = 9; CWL = 6

Average Clock Period with CL = 9; CWL = 7

Average Clock Period with CL = 10; CWL = 5

Average Clock Period with CL = 10; CWL = 6

Average Clock Period with CL = 10; CWL = 7

t_{CK.AVG.CL05.CWL05}

t_{CK.AVG.CL05.CWL06}

t_{CK.AVG.CL05.CWL07}

t_{CK.AVG.CL06.CWL05}

t_{CK.AVG.CL06.CWL06}

t_{CK.AVG.CL06.CWL07}

t_{CK.AVG.CL07.CWL05}

t_{CK.AVG.CL07.CWL06}

t_{CK.AVG.CL07.CWL07}

t_{CK.AVG.CL08.CWL05}

t_{CK.AVG.CL08.CWL06}

t_{CK.AVG.CL08.CWL07}

t_{CK.AVG.CL09.CWL05}

t_{CK.AVG.CL09.CWL06}

t_{CK.AVG.CL09.CWL07}

t_{CK.AVG.CL10.CWL05}

t_{CK.AVG.CL10.CWL06}

t_{CK.AVG.CL10.CWL07}

3.3

RESERVED

ns

1)2)

RESERVED

ns

1)2)

ns

1)2)

2.5

3.3

2.5

3.3

ns

1)2)

RESERVED

1.875 2.5

RESERVED

1.875 2.5

RESERVED

1.875 2.5

RESERVED

1.875 2.5

ns

1)2)

ns

1)2)

ns

1)2)

ns

1)2)

ns

1)2)

ns

1)2)

ns

1)2)

1.5

1.875 RESERVED

ns

1)2)

RESERVED

ns

1)2)

ns

1)2)

1.5

1.875 1.5

1.875 ns

1)2)

RESERVED

ns

1.5

1.875 1.5

1.875 ns

1) Please refer to "General Notes for Speed Bins" at beginning of this chapter.

2) Max. limits are exclusive. E.g. if t_CK.AVG.MAXvalue is 2.5 ns, t_CK.AVGneeds to be < 2.5 ns.

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TABLE 34

DDR3-1600 Speed Bins and Operating Conditions

Speed Bin

DDR3-1600G

8-8-8

DDR3-1600H

DDR3-1600J

10-10-10

-16J

DDR3-1600K Unit Note

CL-nRCD-nRP

9-9-9

11-11-11

-16K

QAG Partnumber Extension

-16G

-16H

Parameter

Symbol

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

1)

Internal read command t_AA

to first data

10.0

20.0

11.25 20.0

12.5

20.0

13.12 20.0

5

ns

1)

ACT to internal read or t_RCD

write delay time

10.0

45.0

—

11.25

46.25

—

12.5

47.5

—

13.12

5

—

1)

PRE command period t_RP

13.12

5

1)

ACT to ACT or REF

command period

t_RC

48.12

5

1)

Supported CL Settings Sup_CL

5, 6, 7, 8, 9, 10, 5, 6, 7, 8, 9, 10, 5, 6, 7, 8, 9, 10, 6, 7, 8, 9, 10, n_CK

11

1)

Supported CWL

Settings

Sup_CWL

5, 6, 7, 8

n_CK

ns

1)2)

Average Clock Period t_{CK.AVG.CL05.CWL05}2.5

with CL = 5; CWL = 5

3.3

2.5

3.3

2.5

3.3

RESERVED

Average Clock Period t_{CK.AVG.CL05.CWL06}RESERVED

with CL = 5; CWL = 6

RESERVED

Average Clock Period t_{CK.AVG.CL05.CWL07}RESERVED

with CL = 5; CWL = 7

Average Clock Period t_{CK.AVG.CL05.CWL08}RESERVED

with CL = 5; CWL = 8

Average Clock Period t_{CK.AVG.CL06.CWL05}2.5

with CL = 6; CWL = 5

3.3

2.5

3.3

2.5

3.3

2.5

3.3

Average Clock Period t_{CK.AVG.CL06.CWL06}1.875 2.5

with CL = 6; CWL = 6

1.875 2.5

RESERVED

1.875 2.5

RESERVED

1.875 2.5

RESERVED

1.875 2.5

RESERVED

Average Clock Period t_{CK.AVG.CL06.CWL07}RESERVED

with CL = 6; CWL = 7

Average Clock Period t_{CK.AVG.CL06.CWL08}RESERVED

with CL = 6; CWL = 8

Average Clock Period t_{CK.AVG.CL07.CWL05}RESERVED

with CL = 7; CWL = 5

Average Clock Period t_{CK.AVG.CL07.CWL06}1.875 2.5

with CL = 7; CWL = 6

Average Clock Period t_{CK.AVG.CL07.CWL07}1.5

with CL = 7; CWL = 7

1.875 RESERVED

Average Clock Period t_{CK.AVG.CL07.CWL08}RESERVED

with CL = 7; CWL = 8

RESERVED

Average Clock Period t_{CK.AVG.CL08.CWL05}RESERVED

with CL = 8; CWL = 5

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Speed Bin

DDR3-1600G

8-8-8

DDR3-1600H

9-9-9

DDR3-1600J

10-10-10

-16J

DDR3-1600K Unit Note

CL-nRCD-nRP

11-11-11

-16K

QAG Partnumber Extension

-16G

-16H

Parameter

Symbol

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

1)2)

Average Clock Period t_{CK.AVG.CL08.CWL06}1.875 2.5

with CL = 8; CWL = 6

1.875 2.5

RESERVED

ns

Average Clock Period t_{CK.AVG.CL08.CWL07}1.5

1.875 1.5

1.875 RESERVED

with CL = 8; CWL = 7

Average Clock Period t_{CK.AVG.CL08.CWL08}1.25

1.5 RESERVED

RESERVED

with CL = 8; CWL = 8

Average Clock Period t_{CK.AVG.CL09.CWL05}RESERVED

with CL = 9; CWL = 5

RESERVED

Average Clock Period t_{CK.AVG.CL09.CWL06}RESERVED

with CL = 9; CWL = 6

Average Clock Period t_{CK.AVG.CL09.CWL07}1.5

with CL = 9; CWL = 7

1.875 1.5

1.5 1.25

1.875 1.5

1.5

1.875 1.5

1.875 ns

Average Clock Period t_{CK.AVG.CL09.CWL08}1.25

RESERVED

ns

with CL = 9; CWL = 8

Average Clock Period t_{CK.AVG.CL10.CWL05}RESERVED

with CL = 10; CWL = 5

RESERVED

Average Clock Period t_{CK.AVG.CL10.CWL06}RESERVED

with CL = 10; CWL = 6

Average Clock Period t_{CK.AVG.CL10.CWL07}1.5

with CL = 10; CWL = 7

1.875 1.5

1.5 1.25

1.875 1.5

1.5 1.25

1.875 1.5

1.875 ns

Average Clock Period t_{CK.AVG.CL10.CWL08}1.25

1.5 RESERVED

ns

with CL = 10; CWL = 8

Average Clock Period t_{CK.AVG.CL11.CWL05}RESERVED

with CL = 11; CWL = 5

RESERVED

Average Clock Period t_{CK.AVG.CL11.CWL06}RESERVED

with CL = 11; CWL = 6

Average Clock Period t_{CK.AVG.CL11.CWL07}RESERVED

with CL = 11; CWL = 7

Average Clock Period t_{CK.AVG.CL11.CWL08}1.25

1.5

1.25

1.5

1.25

1.5

1.25

1.5

with CL = 11; CWL = 8

1) Please refer to "General Notes for Speed Bins" at beginning of this chapter.

2) Max. limits are exclusive. E.g. if t_CK.AVG.MAXvalue is 2.5 ns, t_CK.AVGneeds to be < 2.5 ns.

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TABLE 35

DDR3-DLL_off Speed Bins and Operating Conditions

Speed Bin

DDR3-DLL_off

Unit

Note

CL-nRCD-nRP

6-x-x

QAG Partnumber Extension

Parameter

DLL_off

Min.

Symbol

Max.

1)

Internal read command to first data

ACT to internal read or write delay time

PRE command period

t_AA

48.0

15.0

52.5

6

—

ns

1)

t_RCD

ns

1)

t_RP

ns

1)

ACT to ACT or REF command period

Supported CL Settings

t_RC

ns

1)

Sup_CL

Sup_CWL

n_CK

ns

1)

Supported CWL Settings

6

1)2)

Average Clock Period with CL = 6; CWL = 6 t_{CK.AVG.CL06.CWL06}

8.0

—

1) Please refer to "General Notes for Speed Bins" at beginning of this chapter.

2) Max. limits are exclusive. E.g. if t_CK.AVG.MAXvalue is 2.5 ns, t_CK.AVGneeds to be < 2.5 ns.

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5

I_DDCurrent Specifications

5.1

According to DDR3 Industry Standard defined 2008

TABLE 36

_DDSpecification for 1G

I

Speed Bin

Config. DDR3–800 DDR3–1066 DDR3–1333 DDR3–1600 Unit

Symbol Definition

Max.

I_DD0

Operating Current -

Active - Precharge

×4

62

80

82

84

109

15

68

73

92

91

93

120

16

81

mA

×8

68

81

×16

×4

86

101

100

102

128

16.5

I_DD1

Operating Current -

Active - Read - Precharge

86

×8

88

×16

All

116

15.5

I_DD2P0

I_DD2P1

I_DD2N

Precharge Power-down Current (slow

exit)

Precharge Power-down Current (fast

exit)

All

27

31

34

37

mA

Precharge Standby current

×4

43

48

49

52

57

77

152

43

31

47

50

54

56

60

57

77

152

49

35

54

56

61

62

67

57

77

152

54

38

60

63

67

69

75

57

77

152

60

42

67

mA

×8

×16

×4

I_DD2NT

Precharge Standby ODT current

×8

×16

×4

I_DDQ2NTPrecharge Standby ODT I_DDQcurrent

×8

×16

×4

I_DD2Q

Precharge Quiet Standby current

×8

×16

All

I_DD3P

I_DD3N

Active Power-down current

Active Standby current

×4

×8

×16

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Speed Bin

Config. DDR3–800 DDR3–1066 DDR3–1333 DDR3–1600 Unit

Symbol Definition

Max.

I_DD4R

Operating Current -

Read burst

×4

116

140

205

56

142

170

248

57

168

197

287

59

190

225

330

63

mA

×8

×16

×4

I_DDQ4R

Precharge I_DDQcurrent

Read burst

×8

74

77

81

85

×16

×4

128

106

125

165

177

12

131

130

149

198

185

12

135

152

173

230

190

12

139

180

200

265

197

12

I_DD4W

Operating Current -

Write Burst

×8

×16

All

I_DD5B

I_DD6

I_DD6ET

I_DD7

Burst Refresh Current

Self-Refresh Current, T_OPER= 0 - 85°C All

Self-Refresh Current, T_OPER= 0 - 95 °C All

14

Operating Bank Interleave Current

×4

186

204

285

15.5

202

221

303

15.5

240

261

330

15.5

252

274

366

15.5

×8

×16

All

I_DD8

Reset-Low Current

Notes

1. Max. value for I_DDcurrents consider worst case conditions of process, temperature and voltage.

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IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

5.2

According to DDR3 Industry Standard defined 2004

TABLE 37

_DDSpecification for 1G

I

Speed Bin

Config. DDR3–800 DDR3–1066 DDR3–1333 DDR3–1600 Unit

Symbol Definition

Max.

I_DD0

Operating Current -

Active - Precharge

×4

66

84

85

110

14

72

90

89

114

15

75

95

90

115

16

85

mA

×8

85

×16

×4

104

103

104

129

16

I_DD1

Operating Current -

Active - Read - Precharge

×8

×16

All

I_DD2P(0)Precharge Power-down Current (slow

exit)

I_DD2P(1)Precharge Power-down Current (fast exit) All

26

30

33

37

mA

I_DD2N

Precharge Standby current

×4

43

50

56

63

×8

43

50

56

63

×16

×4

43

50

56

63

I_DD2Q

Precharge Quiet Standby current

43

49

54

60

×8

43

49

54

60

×16

All

43

49

54

60

I_DD3P

I_DD3N

Active Power-down current

Active Standby current

31

35

38

42

×4

47

54

60

67

×8

47

54

60

67

×16

×4

47

54

60

67

I_DD4R

Operating Current -

Read burst

114

129

179

110

123

159

177

12

140

158

220

135

150

195

185

12

165

186

259

159

177

230

190

12

190

214

299

184

204

266

197

12

×8

×16

×4

I_DD4W

Operating Current -

Write Burst

×8

×16

All

I_DD5B

I_DD6

I_DD6ET

I_DD7

Burst Refresh Current

Self-Refresh Current, T_OPER= 0 - 85°C

Self-Refresh Current, T_OPER= 0 - 95 °C

Operating Bank Interleave Current

All

14

×4

164

178

251

180

195

270

216

234

313

228

247

327

×8

×16

Notes

1. Max. value for I_DDcurrents consider worst case conditions of process, temperature and voltage.

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Advance Internet Data Sheet

IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

6

Package Outline

This chapter contains the package dimension figures.

Notes

1. Drawing according to ISO 8015

2. Dimensions in mm

FIGURE 7

Package Outline PG-TFBGA-78

12.5

12 x 0.8 = 9.6

0.8

0.18 MAX.

0.2

4)

B

4)

3)

1)

2)

A

0.1

C

0.1

C

78x

ø0.15

ø0.08

0.05

ø0.45

M

A B

SEATING PLANE

C

Lead free solder balls (green solder balls)

1) Bad unit marking (light = good)

2) Package orientation mark A1

3) Solder ball attach fiducial

4) Middle of packages edges

FPO_PG-TFBGA__-078-051

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IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

FIGURE 8

Package Outline PG-TFBGA-96

13.5

15 x 0.8 = 12

0.8

0.18 MAX.

0.2

4)

B

4)

3)

1)

2)

A

0.1

C

0.1

C

96x

ø0.15

ø0.08

5)

0.05

ø0.45

M

A B

SEATING PLANE

C

Lead free solder balls (green solder balls)

1) Bad unit mark (light = good)

2) Package orientation mark A1

3) Solder ball attach fiducial

4) Middle of packages edges

5) Solder ball diameter refers to post reflow conduction

pre-flow diameter 0.45 mm

FPO_PG-TFBGA__-096-051

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Advance Internet Data Sheet

IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

7

Product Type Nomenclature

For reference the applicable Qimonda DDR3 component nomenclature is listed in this chapter.

TABLE 38

Example for Nomenclature Fields

Example for

Field Number

1

2

3

4

5

6

7

8

9

10

11

12

DDR3 SDRAM Component

ID

SH

1G

—

0

2

A1

F1

C

—

08

E

TABLE 39

DDR3 SDRAM Nomenclature

Field Description

Value

Coding

1

Qimonda SDRAM Component Prefix ID

Qimonda Device

IS

SH

512

1G

2G

4G

—

0

Qimonda Dual-Die Device

Standard DDR3

512 Mbit

2

3

SDRAM Technology

Component Density

1 GBit

2 GBit

4 GBit

4

5

Module Type / ECC Support

Number of Chip Select

No ECC support on SDRAM level

1 Chip Select (2⁰)

2 Chip Select (2¹)

4 DQ lines (2²)

1

6

Number of DQs

2

3

8 DQ lines (2³)

4

16 DQ lines (2⁴)

32 DQ lines (2⁵)

First Die

5

7

8

Die Revision

Package

A1

F1

F2

C

Planar FBGA, lead- and halogen-free

Dual-Die FBGA, lead- and halogen-free

Commercial (0 °C - 95 °C)

9

Temperature Range

Supply Voltage

10

—

L

Standard DDR3 supply voltage support, 1.5V

Low voltage and standard DDR3 supply voltage support,

1.35 and 1.5V

11

Band Width Per DQ

08

10

13

16

DDR3–800 = 800 Mbit per ball per second, t_CK= 2.5 ns

DDR3–1066 = 1066 Mbit per ball per second, t_CK= 1.875 ns

DDR3–1333 = 1333 Mbit per ball per second, t_CK= 1.5 ns

DDR3–1600 = 1600 Mbit per ball per second, t_CK= 1.25 ns

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IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

Field Description

12 Latencies

Value

Coding

D

E

F

G

H

J

CL–RCD–RP = 5–5–5

CL–RCD–RP = 6–6–6

CL–RCD–RP = 7–7–7

CL–RCD–RP = 8–8–8

CL–RCD–RP = 9–9–9

CL–RCD–RP = 10–10–10

CL–RCD–RP = 11–11–11

K

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IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

List of Illustrations

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Ballout for 1Gb ×4 Components (PG-TFBGA-78). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ballout for 1Gb × 8 Components (PG-TFBGA-78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ballout for 1Gb × 16 Components (PG-TFBGA-96) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Reference Load for AC Timings and Output Slew Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

AC Overshoot / Undershoot Definitions for Address and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

AC Overshoot / Undershoot Definitions for Clock, Data, Strobe and Mask Signals . . . . . . . . . . . . . . . . . . . . . 36

Package Outline PG-TFBGA-78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Package Outline PG-TFBGA-96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

List of Tables

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1-Gbit DDR3 SDRAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Input / Output Signal Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Clock Enable (CKE) Truth Table for Synchronous Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

MR0 Mode register Definition, BA[2:0]=000_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

MR1 Mode Register Definition, BA[2:0]=001_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MR2 Mode Register Definition, BA[2:0]=010_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MR3 Mode Register Definition, BA[2:0]=011_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Bit Order during Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

SDRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

DC and AC Input Levels for Single-Ended Command, Address and Control Signals . . . . . . . . . . . . . . . . . . . 28

DC and AC Input Levels for Single-Ended DQ and DM Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) . . . . . . . . . . . . . . . . . . . . . . . . 29

Allowed Time Before Ringback (t_DVAC) for CLK - CLK and DQS - DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Each Single-Ended Levels for CK, CK, DQS, DQS, DQSL, DQSL, DQSU or DQSU . . . . . . . . . . . . . . . . . . . 30

Cross Point Voltage for Differential Input Signals (CK, DQS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

DC and AC Output Levels for Single-Ended Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

AC Output Levels for Differential Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

ODT DC Impedance and Mid-Level Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

ODT DC Impedance after proper IO Calibration and Voltage/Temperature Drift . . . . . . . . . . . . . . . . . . . . . . . 32

OTD DC Impedance Sensitivity Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Output Slew Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Interface Capacitance Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

AC Overshoot / Undershoot Specification for Address and Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . 35

AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Signals . . . . . . . . . . . . . . . . . . . 35

DDR3-800 Speed Bins and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DDR3-1066 Speed Bins and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DDR3-1333 Speed Bins and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DDR3-1600 Speed Bins and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DDR3-DLL_off Speed Bins and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

I_DDSpecification for 1G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

I_DDSpecification for 1G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Example for Nomenclature Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

DDR3 SDRAM Nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 9

Table 10

Table 11

Table 12

Table 13

Table 14

Table 15

Table 16

Table 17

Table 18

Table 19

Table 20

Table 21

Table 22

Table 23

Table 24

Table 25

Table 26

Table 27

Table 28

Table 29

Table 30

Table 31

Table 32

Table 33

Table 34

Table 35

Table 36

Table 37

Table 38

Table 39

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IDSH1G–0[2/3/4]A1F1C

1-Gbit Double-Data-Rate-Three SDRAM

Contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Product List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

DDR3 SDRAM Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Package Ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Input / Output Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1

1.2

1.3

1.4

1.5

2

Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Mode Register 0 (MR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Mode Register 1 (MR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Mode Register 2 (MR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Mode Register 3 (MR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read / Write Operations and Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Burst Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1

2.2

2.3

2.4

2.5

2.6

2.6.1

3

Operating Conditions and Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Interface Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DC and AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DC and AC Output Measurements Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

ODT DC Impedance and Mid-Level Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

ODT DC Impedance Sensitivity on Temperature and Voltage Drifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Output Slew Rate Definition and Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Output Slew Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Interface Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Overshoot and Undershoot Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.1

3.2

3.3

3.4

3.4.1

3.4.2

3.5

3.6

3.7

3.7.1

3.8

3.9

4

Speed Bins and Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.1

Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5

5.1

5.2

I_DDCurrent Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

According to DDR3 Industry Standard defined 2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

According to DDR3 Industry Standard defined 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6

7

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Rev. 0.65, 2008-12

53

12192007-S9AR-ZT6N

Advance Internet Data Sheet

Edition 2008-12

Published by Qimonda AG

Gustav-Heinemann-Ring 212

D-81739 München, Germany

Legal Disclaimer

THE INFORMATION GIVEN IN THIS INTERNET DATA SHEET SHALL IN NO EVENT BE REGARDED AS A GUARANTEE

OF CONDITIONS OR CHARACTERISTICS. WITH RESPECT TO ANY EXAMPLES OR HINTS GIVEN HEREIN, ANY

TYPICAL VALUES STATED HEREIN AND/OR ANY INFORMATION REGARDING THE APPLICATION OF THE DEVICE,

QIMONDA HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND, INCLUDING WITHOUT

LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please

contact your nearest Qimonda Office.

Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a

failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect

the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human

body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health

of the user or other persons may be endangered.

www.qimonda.com


型号：	IDSH1G-04A1F1C-16J
厂家：	QIMONDA AG
描述：	DDR DRAM, 64MX16, CMOS, PBGA96, 0.80 MM PITCH, GREEN, PLASTIC, TFBGA-96 动态存储器双倍数据速率内存集成电路
文件：	总54页 (文件大小：1308K)
中文：	中文翻译
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IDSH1G-04A1F1C-16J [QIMONDA]

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