首页 |元器件品牌

IMHH2GP13A1F1C-08E [QIMONDA]

DDR DRAM Module, 256MX72, CMOS, GREEN, DIMM-240;
IMHH2GP13A1F1C-08E
型号： IMHH2GP13A1F1C-08E
厂家： QIMONDA AG    QIMONDA AG
描述：

DDR DRAM Module, 256MX72, CMOS, GREEN, DIMM-240

动态存储器 双倍数据速率 内存集成电路
文件： 总95页 (文件大小：4844K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
January 2008  
IM[S/H]H1GP03A1F1C  
IM[S/H]H2GP[13/02]A1F1C  
IM[S/H]H4GP[23/12]A1F1C  
240-Pin DDR3 Registered Modules with Parity bit  
1GByte, 2GByte and 4GByte  
RoHS compliant  
Advance  
Internet Data Sheet  
Rev. 0.51  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
IM[S/H]H1GP03A1F1C, IM[S/H]H2GP[13/02]A1F1C, IM[S/H]H4GP[23/12]A1F1C  
Revision History: 2008-01, Rev. 0.51  
Page  
Subjects (major changes since last revision)  
Added Product Types and related information for modules with Heat Spreader.  
All  
Previous Revision: 2007-12, Rev. 0.5  
All Data sheet for 1GB, 2GB and 4GB Registered Memory Modules with Parity bit Product Family.  
We Listen to Your Comments  
Any information within this document that you feel is wrong, unclear or missing at all?  
Your feedback will help us to continuously improve the quality of this document.  
Please send your proposal (including a reference to this document) to:  
techdoc@qimonda.com  
qag_techdoc_A4, 4.20, 2008-01-25  
12122007-WJ2L-RGDP  
2
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
1
Overview  
This chapter gives an overview of the 240–pin Registered DDR3 Dual-In-Line Memory Modules product family with parity bit  
for address and control bus and describes its main characteristics.  
1.1  
Features  
•
•
240-pin 8-Byte DDR3 SDRAM Registered Dual-In-Line  
Memory Modules with parity bit for address and control  
bus.  
Module organization: One rank – 128M × 72, 256M × 72,  
two rank – 256M × 72, 512M × 72 , four rank – 512M × 72  
Chip organization: 128M × 8, 256M × 4  
PC3-10600, PC3-8500 and PC3-6400 module speed  
grades.  
4GB, 2GB, 1GB modules built with 1Gb DDR3 SDRAMs in  
packages PG-TFBGA-78  
DDR3 SDRAMs with a single 1.5 V (± 0.075 V) power  
supply.  
•
•
Programmable CAS Latency, CAS Write Latency, Additive  
Latency, Burst Length and Burst Type.  
On-Die-Termination (ODT) and Dynamic ODT for  
improved signal integrity.  
Refresh. Self Refresh and Power Down Modes.  
ZQ Calibration for output driver and ODT.  
System Level Timing Calibration Support via Write  
Leveling and Multi Purpose Register (MPR) Read Pattern.  
Serial Presence Detect with EEPROM.  
On-DIMM Thermal Sensor.  
•
•
•
•
•
•
•
•
•
•
•
RDIMM dimensions: 133.35 mm x 30 mm.  
Based on standard reference raw cards: 'A', 'B', 'C', 'E' and  
'H'  
Asynchronous Reset.  
•
RoHS compliant products1).  
TABLE 1  
Performance Table for DDR3–1600 and DDR3–1333  
Qimonda Speed Code  
Module Speed Bin  
Device Speed Bin  
CL-nRCD-nRP  
–13G  
–13H  
Unit  
Note  
1)  
PC3  
–10600G  
–1333G  
8-8-8  
–10600H  
–1333H  
9-9-9  
DDR3  
CL and CWL settings for maximum clock  
frequency  
CL = 8  
CWL = 7  
CL = 9  
CWL = 7  
MHz  
Maximum Clock Frequency  
and Data Rate  
667  
1333  
667  
1333  
MHz  
Mb/s  
with above CL and CWL settings  
Minimum Clock Frequency  
and Data Rate  
533  
1066  
533  
1066  
MHz  
Mb/s  
with above CL and CWL settings  
1) The available CL and CWL settings depend on the SDRAM device speed bin. The CL setting and CWL setting result in maximum but also  
minimum clock frequency requirements. When making a selection of operating clock frequency, both need to be fulfilled: Requirements  
from CL setting as well as requirements from CWL setting. For details, refer to Chapter 4.1 Speed Bins.  
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined  
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,  
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.  
Rev. 0.51, 2008-01  
3
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 2  
Performance Table for DDR3–1066 and DDR3–800  
Qimonda Speed Code  
Module Speed Bin  
Device Speed Bin  
CL-nRCD-nRP  
–10F  
–10G  
–08D  
–08E  
Unit  
Note  
1)  
PC3  
–8500F  
–1066F  
7-7-7  
–8500G  
–1066G  
8-8-8  
–6400D  
–800D  
5-5-5  
–6400E  
–800E  
6-6-6  
DDR3  
CL and CWL settings for maximum  
clock frequency  
CL = 7  
CWL = 6  
CL = 8  
CWL = 6  
CL = 5  
CWL = 5  
CL = 6  
CWL = 5  
MHz  
Maximum Clock Frequency  
and Data Rate  
533  
1066  
533  
1066  
400  
800  
400  
800  
MHz  
Mb/s  
with above CL and CWL settings  
Minimum Clock Frequency  
and Data Rate  
400  
800  
400  
800  
300  
600  
300  
600  
MHz  
Mb/s  
with above CL and CWL settings  
1) The available CL and CWL settings depend on the SDRAM device speed bin. The CL setting and CWL setting result in maximum but also  
minimum clock frequency requirements. When making a selection of operating clock frequency, both need to be fulfilled: Requirements  
from CL setting as well as requirements from CWL setting. For details, refer to Chapter 4.1 Speed Bins.  
Rev. 0.51, 2008-01  
4
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
1.2  
Description  
The  
Qimonda  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
are  
loading to the system bus, but adds one cycle to the SDRAM  
timing. De-coupling capacitors, stub resistors, calibration  
resistors and termination resistors are mounted on the PCB  
board. The DIMMs feature serial presence detect based on a  
256 byte serial EEPROM device using the 2-pin I2C protocol.  
The first 176 bytes are programmed with module specific  
SPD data.  
Registered DIMM (PDIMM) family with parity bit for address  
and control bus and 30 mm height based on DDR3 SDRAM  
technology. DIMMs are available in 128M × 72 (1GB),  
256M × 72 (2GB), 512M × 72 (4GB) organization and  
density, intended for mounting into 240 pin connector  
sockets.  
The memory array is designed with 1Gb Double Data Rate  
(DDR3) Synchronous DRAMs. All control and address  
signals are re-driven on the DIMM using register devices and  
a PLL for the clock distribution. This reduces capacitive  
TABLE 3  
Product Information for Modules without Heat Spreader  
Qimonda Part Number  
Compliance Code  
Description  
1024 MByte Registered DIMM IMSH1GP03A1F1C  
IMSH1GP03A1F1C–08D  
1GB 1R×8 PC3–6400P–5-XX–A0  
1GB 1R×8 PC3–6400P–6-XX–A0  
240-pin 1024 MByte DDR3 registered DIMM with  
one rank and on-DIMM thermal sensor. The  
memory rank consists of nine DDR3 components in  
x8 organization. Standard reference card A is used  
on this assembly  
Used DDR3 SDRAM Component  
Part Number: IDSH1G-03A1F1C  
Density: 1 Gbit  
IMSH1GP03A1F1C–08E  
IMSH1GP03A1F1C–10F  
IMSH1GP03A1F1C–10G  
IMSH1GP03A1F1C–13G  
IMSH1GP03A1F1C–13H  
1GB 1R×8 PC3–8500P–7-XX–A0  
1GB 1R×8 PC3–8500P–8-XX–A0  
1GB 1R×8 PC3–10600P–8-XX–A0  
1GB 1R×8 PC3–10600P–9-XX–A0  
Organization: 128Mbit × 8  
Address Bits (Row/Column/Bank): 14/10/3  
2048 MByte Registered DIMM IMSH2GP13A1F1C  
IMSH2GP13A1F1C–08D  
IMSH2GP13A1F1C–08E  
IMSH2GP13A1F1C–10F  
IMSH2GP13A1F1C–10G  
IMSH2GP13A1F1C–13G  
IMSH2GP13A1F1C–13H  
2GB 2R×8 PC3–6400P–5-XX–B0  
240-pin 2048 MByte DDR3 registered DIMM with  
two ranks and on-DIMM thermal sensor. Each  
memory rank consists of nine DDR3 components in  
x8 organization. Standard reference card B is used  
on this assembly  
Used DDR3 SDRAM Component  
Part Number: IDSH1G-03A1F1C  
Density: 1 Gbit  
2GB 2R×8 PC3–6400P–6-XX–B0  
2GB 2R×8 PC3–8500P–7-XX–B0  
2GB 2R×8 PC3–8500P–8-XX–B0  
2GB 2R×8 PC3–10600P–8-XX–B0  
2GB 2R×8 PC3–10600P–9-XX–B0  
Organization: 128Mbit × 8  
Address Bits (Row/Column/Bank): 14/10/3  
2048 MByte Registered DIMM IMSH2GP02A1F1C  
IMSH2GP02A1F1C–08D  
IMSH2GP02A1F1C–08E  
IMSH2GP02A1F1C–10F  
IMSH2GP02A1F1C–10G  
IMSH2GP02A1F1C–13G  
IMSH2GP02A1F1C–13H  
2GB 1R×4 PC3–6400P–5-XX–C0  
240-pin 2048 MByte DDR3 registered DIMM with  
one rank and on-DIMM thermal sensor. The  
memory rank consists of eighteen DDR3  
components in x4 organization. Standard reference  
card C is used on this assembly  
Used DDR3 SDRAM Component  
Part Number: IDSH1G-02A1F1C  
Density: 1 Gbit  
2GB 1R×4 PC3–6400P–6-XX–C0  
2GB 1R×4 PC3–8500P–7-XX–C0  
2GB 1R×4 PC3–8500P–8-XX–C0  
2GB 1R×4 PC3–10600P–8-XX–C0  
2GB 1R×4 PC3–10600P–9-XX–C0  
Organization: 256Mbit × 4  
Address Bits (Row/Column/Bank): 14/11/3  
Rev. 0.51, 2008-01  
5
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Qimonda Part Number  
Compliance Code  
Description  
4096 MByte Registered DIMM IMSH4GP23A1F1C  
IMSH4GP23A1F1C–08D  
IMSH4GP23A1F1C–08E  
IMSH4GP23A1F1C–10F  
IMSH4GP23A1F1C–10G  
IMSH4GP23A1F1C–13G  
IMSH4GP23A1F1C–13H  
4GB 4R×8 PC3–6400P–5-XX–H0  
240-pin 4096 MByte DDR3 registered DIMM with  
four ranks and on-DIMM thermal sensor. Each  
memory rank consists of nine DDR3 components in  
x4 organization. Standard reference card H is used  
on this assembly  
Used DDR3 SDRAM Component  
Part Number: IDSH1G-03A1F1C  
Density: 1 Gbit  
4GB 4R×8 PC3–6400P–6-XX–H0  
4GB 4R×8 PC3–8500P–7-XX–H0  
4GB 4R×8 PC3–8500P–8-XX–H0  
4GB 4R×8 PC3–10600P–8-XX–H0  
4GB 4R×8 PC3–10600P–9-XX–H0  
Organization: 128Mbit × 8  
Address Bits (Row/Column/Bank): 14/10/3  
4096 MByte Registered DIMM IMSH4GP12A1F1C  
IMSH4GP12A1F1C–08D  
IMSH4GP12A1F1C–08E  
IMSH4GP12A1F1C–10F  
IMSH4GP12A1F1C–10G  
IMSH4GP12A1F1C–13G  
IMSH4GP12A1F1C–13H  
4GB 2R×4 PC3–6400P–5-XX–E0  
240-pin 4096 MByte DDR3 registered DIMM with  
two ranks and on-DIMM thermal sensor. Each  
memory rank consists of eighteen DDR3  
components in x4 organization. Standard reference  
card E is used on this assembly  
Used DDR3 SDRAM Component  
Part Number: IDSH1G-02A1F1C  
Density: 1 Gbit  
4GB 2R×4 PC3–6400P–6-XX–E0  
4GB 2R×4 PC3–8500P–7-XX–E0  
4GB 2R×4 PC3–8500P–8-XX–E0  
4GB 2R×4 PC3–10600P–8-XX–E0  
4GB 2R×4 PC3–10600P–9-XX–E0  
Organization: 256Mbit × 4  
Address Bits (Row/Column/Bank): 14/11/3  
TABLE 4  
Product Information for Modules with Heat Spreader  
Description  
Qimonda Part Number  
Compliance Code  
1024 MByte Registered DIMM IMHH1GP03A1F1C  
IMHH1GP03A1F1C–08D  
1GB 1R×8 PC3–6400P–5-XX–A0  
1GB 1R×8 PC3–6400P–6-XX–A0  
240-pin 1024 MByte DDR3 registered DIMM with  
one rank and on-DIMM thermal sensor. The  
memory rank consists of nine DDR3 components in  
x8 organization. Standard reference card A is used  
on this assembly  
Used DDR3 SDRAM Component  
Part Number: IDSH1G-03A1F1C  
Density: 1 Gbit  
IMHH1GP03A1F1C–08E  
IMHH1GP03A1F1C–10F  
IMHH1GP03A1F1C–10G  
IMHH1GP03A1F1C–13G  
IMHH1GP03A1F1C–13H  
1GB 1R×8 PC3–8500P–7-XX–A0  
1GB 1R×8 PC3–8500P–8-XX–A0  
1GB 1R×8 PC3–10600P–8-XX–A0  
1GB 1R×8 PC3–10600P–9-XX–A0  
Organization: 128Mbit × 8  
Address Bits (Row/Column/Bank): 14/10/3  
2048 MByte Registered DIMM IMHH2GP13A1F1C  
IMHH2GP13A1F1C–08D  
IMHH2GP13A1F1C–08E  
IMHH2GP13A1F1C–10F  
IMHH2GP13A1F1C–10G  
IMHH2GP13A1F1C–13G  
IMHH2GP13A1F1C–13H  
2GB 2R×8 PC3–6400P–5-XX–B0  
240-pin 2048 MByte DDR3 registered DIMM with  
two ranks and on-DIMM thermal sensor. Each  
memory rank consists of nine DDR3 components in  
x8 organization. Standard reference card B is used  
on this assembly  
Used DDR3 SDRAM Component  
Part Number: IDSH1G-03A1F1C  
Density: 1 Gbit  
2GB 2R×8 PC3–6400P–6-XX–B0  
2GB 2R×8 PC3–8500P–7-XX–B0  
2GB 2R×8 PC3–8500P–8-XX–B0  
2GB 2R×8 PC3–10600P–8-XX–B0  
2GB 2R×8 PC3–10600P–9-XX–B0  
Organization: 128Mbit × 8  
Address Bits (Row/Column/Bank): 14/10/3  
Rev. 0.51, 2008-01  
6
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Qimonda Part Number  
Compliance Code  
Description  
2048 MByte Registered DIMM IMHH2GP02A1F1C  
IMHH2GP02A1F1C–08D  
IMHH2GP02A1F1C–08E  
IMHH2GP02A1F1C–10F  
IMHH2GP02A1F1C–10G  
IMHH2GP02A1F1C–13G  
IMHH2GP02A1F1C–13H  
2GB 1R×4 PC3–6400P–5-XX–C0  
240-pin 2048 MByte DDR3 registered DIMM with  
one rank and on-DIMM thermal sensor. The  
memory rank consists of eighteen DDR3  
components in x4 organization. Standard reference  
card C is used on this assembly  
Used DDR3 SDRAM Component  
Part Number: IDSH1G-02A1F1C  
Density: 1 Gbit  
2GB 1R×4 PC3–6400P–6-XX–C0  
2GB 1R×4 PC3–8500P–7-XX–C0  
2GB 1R×4 PC3–8500P–8-XX–C0  
2GB 1R×4 PC3–10600P–8-XX–C0  
2GB 1R×4 PC3–10600P–9-XX–C0  
Organization: 256Mbit × 4  
Address Bits (Row/Column/Bank): 14/11/3  
4096 MByte Registered DIMM IMHH4GP23A1F1C  
IMHH4GP23A1F1C–08D  
IMHH4GP23A1F1C–08E  
IMHH4GP23A1F1C–10F  
IMHH4GP23A1F1C–10G  
IMHH4GP23A1F1C–13G  
IMHH4GP23A1F1C–13H  
4GB 4R×8 PC3–6400P–5-XX–H0  
240-pin 4096 MByte DDR3 registered DIMM with  
four ranks and on-DIMM thermal sensor. Each  
memory rank consists of nine DDR3 components in  
x4 organization. Standard reference card H is used  
on this assembly  
Used DDR3 SDRAM Component  
Part Number: IDSH1G-03A1F1C  
Density: 1 Gbit  
4GB 4R×8 PC3–6400P–6-XX–H0  
4GB 4R×8 PC3–8500P–7-XX–H0  
4GB 4R×8 PC3–8500P–8-XX–H0  
4GB 4R×8 PC3–10600P–8-XX–H0  
4GB 4R×8 PC3–10600P–9-XX–H0  
Organization: 128Mbit × 8  
Address Bits (Row/Column/Bank): 14/10/3  
4096 MByte Registered DIMM IMHH4GP12A1F1C  
IMHH4GP12A1F1C–08D  
IMHH4GP12A1F1C–08E  
IMHH4GP12A1F1C–10F  
IMHH4GP12A1F1C–10G  
IMHH4GP12A1F1C–13G  
IMHH4GP12A1F1C–13H  
4GB 2R×4 PC3–6400P–5-XX–E0  
240-pin 4096 MByte DDR3 registered DIMM with  
two ranks and on-DIMM thermal sensor. Each  
memory rank consists of eighteen DDR3  
components in x4 organization. Standard reference  
card E is used on this assembly  
Used DDR3 SDRAM Component  
Part Number: IDSH1G-02A1F1C  
Density: 1 Gbit  
4GB 2R×4 PC3–6400P–6-XX–E0  
4GB 2R×4 PC3–8500P–7-XX–E0  
4GB 2R×4 PC3–8500P–8-XX–E0  
4GB 2R×4 PC3–10600P–8-XX–E0  
4GB 2R×4 PC3–10600P–9-XX–E0  
Organization: 256Mbit × 4  
Address Bits (Row/Column/Bank): 14/11/3  
Rev. 0.51, 2008-01  
7
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
2
Configuration  
2.1  
Pin Configuration  
TABLE 5  
Pin Configuration of DDR3 RDIMM - 240 Pins  
Pin Name  
EDA Signal  
Name1)  
Pin No.  
Pin  
Type Type  
Buffer Function  
Clock Signals  
CK0  
ck0_t  
ck0_c  
ck1_t  
ck1_c  
184  
185  
63  
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
Differnetial Clock Inputs [1:0]  
CK0  
CK1  
CK1  
64  
Control Signals  
CKE0  
CKE1/NC  
ODT0  
ODT1/NC  
S0  
cke0  
50  
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
Clock Enable [1:0]  
On-Die Termination [1:0]  
Chip Select [3:0]  
cke1  
odt0  
odt1  
s0_n  
s1_n  
s2_n  
s3_n  
169  
195  
77  
193  
76  
SSTL  
SSTL  
SSTL  
SSTL  
S1  
S2  
79  
S3  
198  
Command Signals  
RAS  
CAS  
WE  
ras_n  
cas_n  
we_n  
192  
74  
I
I
I
SSTL  
SSTL  
SSTL  
Row Address Strobe  
Column Address Strobe  
Write Enable  
73  
Bank Address Signals  
BA0  
BA1  
BA2  
ba0  
ba1  
ba2  
71  
I
I
I
SSTL  
SSTL  
SSTL  
Bank Address Bus[2:0]  
190  
52  
Address Signals  
A0  
A1  
A2  
A3  
A4  
a0  
a1  
a2  
a3  
a4  
188  
181  
61  
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Address Bus [15:0]  
180  
59  
Rev. 0.51, 2008-01  
8
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Pin Name  
EDA Signal  
Name1)  
Pin No.  
Pin  
Type Type  
Buffer Function  
A5  
a5  
58  
I
I
I
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Address Bus [15:0]  
A6  
a6  
178  
56  
A7  
a7  
A8  
a8  
177  
175  
70  
A9  
a9  
A10/AP  
A11  
a10  
a11  
a12  
a13  
a14  
a15  
55  
A12/BC  
A13  
174  
196  
172  
171  
A14  
A15  
Data Signals  
DQ0  
dq0  
3
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus [63:0]  
DQ1  
dq1  
4
DQ2  
dq2  
9
DQ3  
dq3  
10  
DQ4  
dq4  
122  
123  
128  
129  
12  
DQ5  
dq5  
DQ6  
dq6  
DQ7  
dq7  
DQ8  
dq8  
DQ9  
dq9  
13  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ24  
DQ25  
DQ26  
DQ27  
dq10  
dq11  
dq12  
dq13  
dq14  
dq15  
dq16  
dq17  
dq18  
dq19  
dq20  
dq21  
dq22  
dq23  
dq24  
dq25  
dq26  
dq27  
18  
19  
131  
132  
137  
138  
21  
22  
27  
28  
140  
141  
146  
147  
30  
31  
36  
37  
Rev. 0.51, 2008-01  
9
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Pin Name  
EDA Signal  
Name1)  
Pin No.  
Pin  
Type Type  
Buffer Function  
DQ28  
DQ29  
DQ30  
DQ31  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
dq28  
dq29  
dq30  
dq31  
dq32  
dq33  
dq34  
dq35  
dq36  
dq37  
dq38  
dq39  
dq40  
dq41  
dq42  
dq43  
dq44  
dq45  
dq46  
dq47  
dq48  
dq49  
dq50  
dq51  
dq52  
dq53  
dq54  
dq55  
dq56  
dq57  
dq58  
dq59  
dq60  
dq61  
dq62  
dq63  
149  
150  
155  
156  
81  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus [63:0]  
82  
87  
88  
200  
201  
206  
207  
90  
91  
96  
97  
209  
210  
215  
216  
99  
100  
105  
106  
218  
219  
224  
225  
108  
109  
114  
115  
227  
228  
233  
234  
Rev. 0.51, 2008-01  
10  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Pin Name  
EDA Signal  
Name1)  
Pin No.  
Pin  
Type Type  
Buffer Function  
CB0  
cb0  
39  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Check Bit [7:0]  
Check Bit input/output Pin  
CB1  
cb1  
40  
CB2  
cb2  
45  
CB3  
cb3  
46  
CB4  
cb4  
158  
159  
164  
165  
7
CB5  
cb5  
CB6  
cb6  
CB7  
cb7  
DQS0  
dqs0_t  
dqs0_c  
dqs1_t  
dqs1_c  
dqs2_t  
dqs2_c  
dqs3_t  
dqs3_c  
dqs4_t  
dqs4_c  
dqs5_t  
dqs5_c  
dqs6_t  
dqs6_c  
dqs7_t  
dqs7_c  
dqs8_t  
dqs8_c  
dqs9_t  
dqs9_c  
dqs10_t  
dqs10_c  
dqs11_t  
dqs11_c  
dqs12_t  
dqs12_c  
dqs13_t  
dqs13_c  
dqs14_t  
dqs14_c  
dqs15_t  
dqs15_c  
Data Strobe Signals [8:0]  
Differential Data strobe input/output pins.  
DQS0  
6
DQS1  
16  
DQS1  
15  
DQS2  
25  
DQS2  
24  
DQS3  
34  
DQS3  
33  
Data Strobe Signals [8:0]  
Differential Data strobe input/output pins.  
DQS4  
85  
DQS4  
84  
DQS5  
94  
DQS5  
93  
DQS6  
103  
102  
112  
111  
43  
DQS6  
DQS7  
DQS7  
DQS8  
DQS8  
42  
(T)DQS9  
(T)DQS9  
(T)DQS10  
(T)DQS10  
(T)DQS11  
(T)DQS11  
(T)DQS12  
(T)DQS12  
(T)DQS13  
(T)DQS13  
(T)DQS14  
(T)DQS14  
(T)DQS15  
(T)DQS15  
125  
126  
134  
135  
143  
144  
152  
153  
203  
204  
212  
213  
221  
222  
Data Strobe Signals [17:9]  
Rev. 0.51, 2008-01  
11  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Pin Name  
EDA Signal  
Name1)  
Pin No.  
Pin  
Type Type  
Buffer Function  
(T)DQS16  
(T)DQS16  
(T)DQS17  
(T)DQS17  
dqs16_t  
dqs16_c  
dqs17_t  
dqs17_c  
230  
231  
161  
162  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
Data Strobe Signals [17:9]  
EEPROM and Thermal Sensor  
SCL  
SDA  
SA0  
SA1  
SA2  
scl  
118  
238  
117  
237  
119  
I
CMOS Serial Bus Clock  
OD Serial Data Bus  
sda  
sa0  
sa1  
sa2  
I/O  
I
I
I
CMOS Serial Address Select Bus [2:0]  
CMOS  
CMOS  
Power Supply  
VDD vdd  
51, 54, 57, 60, 62, 65, PWR  
66, 69, 72, 75, 78,  
170, 173, 176, 179,  
182, 183, 186, 189,  
191, 194, 197  
-
-
Power Supply  
Ground  
VSS  
vss  
2, 5, 8, 11, 14, 17, 20, GND  
23, 26, 29, 32, 35, 38,  
41, 44, 47, 80, 83, 86,  
89,92, 95, 98, 101,  
104, 107, 110, 113,  
116, 121, 124,  
127, 130, 133, 136,  
139, 142, 145, 148,  
151, 154, 157, 160,  
163, 166, 199, 202,  
205, 208, 211, 214,  
217, 220, 223, 226,  
229, 232, 235, 239  
VREF.DQ  
VREF.CA  
VTT  
vrefdq  
vrefca  
vtt  
1
AI  
-
-
-
-
Reference Voltage  
67  
AI  
Reference Voltage  
48, 49, 120 , 240  
236  
PWR  
Termination Voltage  
VDDSPD  
Other Pins  
RESET  
Err_Out  
vddspd  
EEPROM and Thermal Sensor Power Supply  
reset_n  
168  
53  
I
Asynchronous Reset  
Err_Out  
err_out_n  
O
OD  
Par_In  
EVENT  
NC  
par_in  
event_n  
nc  
68  
I
Par_In  
187  
O
-
OD  
-
EVENT  
79, 126, 135, 144,  
153, 162, 167, 198,  
204, 213, 222, 231,  
Not Connected  
1) The EDA (Electronic Design Automation) Signal Name is used in Qimonda Simulation Models such as EBD (Electronic Board Description).  
Rev. 0.51, 2008-01  
12  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 6  
Abbreviations for Pin Type  
Abbreviation  
Description  
I
Standard Input pin only. Digital levels.  
Standard Output pin only - Digital levels.  
I/O is a bidirectional input/output signal.  
Input - Analog levels.  
O
I/O  
AI  
PWR  
GND  
NC  
Power  
Ground  
Not Connected  
TABLE 7  
Abbreviations for Buffer Type  
Abbreviation  
Description  
SSTL  
CMOS  
OD  
Serial Stub Terminated Logic  
CMOS Levels  
Open Drain. The corresponding pin has 2 operational states, active low and tri-state,  
and allows multiple devices to share as a wire-OR.  
Rev. 0.51, 2008-01  
13  
12122007-WJ2L-RGDP  
ꢇ
                                               
                                                
                                                 
                                                                                                                      
                                                                                                                      
                                                                                                                       
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
FIGURE 1  
Pin Configuration RDIMM - 240 Pin  
95()ꢌ'4 ꢇ 3LQꢀꢁꢁꢂ  
3LQꢀꢂꢈꢂ ꢇ 966  
966  
ꢇ 3LQꢀꢁꢁꢈ  
ꢇ 3LQꢀꢁꢁꢉ  
ꢇ 3LQꢀꢁꢁꢊ  
ꢇ 3LQꢀꢁꢁꢋ  
ꢇ 3LQꢀꢁꢂꢁ  
ꢇ 3LQꢀꢁꢂꢈ  
ꢇ 3LQꢀꢁꢂꢉ  
ꢇ 3LQꢀꢁꢂꢊ  
ꢇ 3LQꢀꢁꢂꢋ  
ꢇ 3LQꢀꢁꢈꢁ  
3LQꢀꢂꢈꢈ ꢇ'4ꢉ  
3LQꢀꢂꢈꢉ ꢇ966  
'4ꢁ  
966  
'46ꢁ  
'4ꢈ  
966  
'4ꢆ  
'46ꢂ  
966  
'4ꢂꢂ  
'4ꢂꢊ  
966  
ꢇ 3LQꢀꢁꢁꢃ  
ꢇ 3LQꢀꢁꢁꢄ  
ꢇ 3LQꢀꢁꢁꢅ  
ꢇ 3LQꢀꢁꢁꢆ  
ꢇ 3LQꢀꢁꢂꢂ  
ꢇ 3LQꢀꢁꢂꢃ  
ꢇ 3LQꢀꢁꢂꢄ  
ꢇ 3LQꢀꢁꢂꢅ  
ꢇ 3LQꢀꢁꢂꢆ  
3LQꢀꢂꢈꢃ ꢇ '4ꢄ  
3LQꢀꢂꢈꢄ ꢇ ꢎ7ꢏ'46ꢆ  
3LQꢀꢂꢈꢅ ꢇ 966  
3LQꢀꢂꢈꢆ ꢇ '4ꢅ  
3LQꢀꢂꢃꢂ ꢇ '4ꢂꢈ  
3LQꢀꢂꢃꢃ ꢇ 966  
3LQꢀꢂꢃꢄ ꢇ ꢎ7ꢏ'46ꢂꢁ  
3LQꢀꢂꢃꢅ ꢇ '4ꢂꢉ  
3LQꢀꢂꢃꢆ ꢇ 966  
3LQꢀꢂꢉꢂ ꢇ '4ꢈꢂ  
3LQꢀꢂꢉꢃ ꢇ ꢎ7ꢏ'46ꢂꢂ  
3LQꢀꢂꢉꢄ ꢇ 966  
3ꢀLQꢀꢂꢉꢅ ꢇ '4ꢈꢃ  
3LQꢀꢂꢉꢆ ꢇ '4ꢈꢋ  
3LQꢀꢂꢄꢂ ꢇ 966  
3LQꢀꢂꢄꢃ ꢇ ꢎ7ꢏ'46ꢂꢈ  
3LQꢀꢂꢄꢄ ꢇ '4ꢃꢁ  
3LQꢀꢂꢄꢅ ꢇ 966  
3LQꢀꢂꢄꢆ ꢇ &%ꢄ  
3LQꢀꢂꢊꢂ ꢇ ꢎ7ꢏ'46ꢂꢅ  
3LQꢀꢂꢊꢃ ꢇ 966  
'4ꢂ  
'46ꢁ  
966  
'4ꢃ  
'4ꢋ  
966  
'46ꢂ  
'4ꢂꢁ  
966  
'4ꢂꢅ  
'46ꢈ  
966  
'4ꢂꢆ  
'4ꢈꢉ  
966  
'46ꢃ  
'4ꢈꢊ  
966  
&%ꢂ  
'46ꢋ  
966  
&%ꢃ  
977  
3LQꢀꢂꢈꢊ ꢇꢎ7ꢏ'46ꢆ  
3LQꢀꢂꢈꢋ ꢇ'4ꢊ  
3LQꢀꢂꢃꢁ ꢇ966  
3LQꢀꢂꢃꢈ ꢇ'4ꢂꢃ  
3LQꢀꢂꢃꢉ ꢇꢎ7ꢏ'46ꢂꢁ  
3LQꢀꢂꢃꢊ ꢇ966  
3LQꢀꢂꢃꢋ ꢇ'4ꢂꢄ  
3LQꢀꢂꢉꢁ ꢇ'4ꢈꢁ  
ꢇ
ꢇ
3LQꢀꢁꢈꢂ  
3LQꢀꢁꢈꢃ  
ꢇ
ꢇ
3LQꢀꢁꢈꢈ  
3LQꢀꢁꢈꢉ  
3LQꢀꢂꢉꢈ  
3LQꢀꢂꢉꢉ  
3LQꢀꢂꢉꢊ  
3LQꢀꢂꢉꢋ  
3LQꢀꢂꢄꢁ  
3LQꢀꢂꢄꢈ  
3LQꢀꢂꢄꢉ  
3LQꢀꢂꢄꢊ  
3LQꢀꢂꢄꢋ  
3LQꢀꢂꢊꢁ  
3LQꢀꢂꢊꢈ  
3LQꢀꢂꢊꢉ  
3LQꢀꢂꢊꢊ  
3LQꢀꢂꢊꢋ  
966  
ꢇ
ꢇ
ꢎ7ꢏ'46ꢂꢂ  
'46ꢈ  
'4ꢂꢋ  
966  
'4ꢈꢄ  
'46ꢃ  
966  
'4ꢈꢅ  
&%ꢁ  
966  
'46ꢋ  
&%ꢈ  
966  
ꢇ 3LQꢀꢁꢈꢄ  
3ꢀLQꢀꢁꢈꢅ  
)
5
2
1
7
6
,
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
3LQꢀꢁꢈꢊ  
3LQꢀꢁꢈꢋ  
3LQꢀꢁꢃꢁ  
3LQꢀꢁꢃꢈ  
3LQꢀꢁꢃꢉ  
3LQꢀꢁꢃꢊ  
3LQꢀꢁꢃꢋ  
3LQꢀꢁꢉꢁ  
3LQꢀꢁꢉꢈ  
3LQꢀꢁꢉꢉ  
3LQꢀꢁꢉꢊ  
3LQꢀꢁꢉꢋ  
'4ꢈꢈ  
%
$
&
.
6
,
ꢇ
966  
ꢇ 3LQꢀꢁꢈꢆ  
ꢇ 3LQꢀꢁꢃꢂ  
ꢇ 3LQꢀꢁꢃꢃ  
ꢇ 3LQꢀꢁꢃꢄ  
ꢇ 3LQꢀꢁꢃꢅ  
ꢇ 3LQꢀꢁꢃꢆ  
ꢇ 3LQꢀꢁꢉꢂ  
ꢇ 3LQꢀꢁꢉꢃ  
ꢇ 3LQꢀꢁꢉꢄ  
ꢇ 3LQꢀꢁꢉꢅ  
ꢇ
'4ꢈꢆ  
ꢇ
ꢎ7ꢏ'46ꢂꢈ  
ꢇ
966  
ꢇ
'4ꢃꢂ  
'
(
ꢇ
&%ꢉ  
'
(
ꢇ
966  
ꢇ
ꢎ7ꢏ'46ꢂꢅ  
ꢇ
&%ꢊ  
3LQꢀꢂꢊꢄ ꢇ &%ꢅ  
3LQꢀꢂꢊꢅ ꢇ 1&  
ꢇ
966  
ꢇ
5(6(7  
977  
9''  
ꢇ 3LQꢀꢁꢉꢆ  
ꢇ 3LQꢀꢁꢄꢂ  
3LQꢀꢂꢊꢆ ꢇ &.(ꢂ  
3LQꢀꢂꢅꢂ ꢇ $ꢂꢄ  
3LQꢀꢂꢅꢃ ꢇ 9''  
3LQꢀꢂꢅꢄ ꢇ $ꢆ  
3LQꢀꢂꢅꢅ ꢇ $ꢋ  
3LQꢀꢂꢅꢆ ꢇ 9''  
3LQꢀꢂꢋꢂ ꢇ $ꢂ  
3LQꢀꢂꢋꢃ ꢇ 9''  
3LQꢀꢂꢋꢄ ꢇ &.ꢁ  
3LQꢀꢂꢋꢅ ꢇ (9(17  
3LQꢀꢂꢋꢆ ꢇ 9''  
3LQꢀꢂꢆꢂ ꢇ 9''  
3LQꢀꢂꢆꢃ ꢇ 6ꢁ  
3LQꢀꢂꢆꢄ ꢇ 2'7ꢁ  
3LQꢀꢂꢆꢅ ꢇ 9''  
3LQꢀꢂꢆꢆ ꢇ 966  
3LQꢀꢈꢁꢂ ꢇ '4ꢃꢅ  
3LQꢀꢈꢁꢃ ꢇ ꢎ7ꢏ'46ꢂꢃ  
3LQꢀꢈꢁꢄ ꢇ 966  
3LQꢀꢈꢁꢅ ꢇ '4ꢃꢆ  
3LQꢀꢈꢁꢆ ꢇ '4ꢉꢉ  
3LQꢀꢈꢂꢂ ꢇ 966  
3LQꢀꢈꢂꢃ ꢇ ꢎ7ꢏ'46ꢂꢉ  
3LQꢀꢈꢂꢄ ꢇ '4ꢉꢊ  
3LQꢀꢈꢂꢅ ꢇ 966  
3LQꢀꢈꢂꢆ ꢇ '4ꢄꢃ  
3LQꢀꢈꢈꢂ ꢇ ꢎ7ꢏ'46ꢂꢄ  
3LQꢀꢈꢈꢃ ꢇ 966  
3LQꢀꢈꢈꢄ ꢇ '4ꢄꢄ  
3LQꢀꢈꢈꢅ ꢇ '4ꢊꢁ  
3LQꢀꢈꢈꢆ ꢇ 966  
3LQꢀꢈꢃꢂ ꢇ ꢎ7ꢏ'46ꢂꢊ  
3LQꢀꢈꢃꢃ ꢇ '4ꢊꢈ  
3LQꢀꢈꢃꢄ ꢇ 966  
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
9''  
&.(ꢁ  
%$ꢈ  
9''  
$ꢅ  
$ꢄ  
3LQꢀꢁꢄꢁ  
3LQꢀꢁꢄꢈ  
3LQꢀꢁꢄꢉ  
3LQꢀꢁꢄꢊ  
3LQꢀꢁꢄꢋ  
3LQꢀꢁꢊꢁ  
3LQꢀꢁꢊꢈ  
3LQꢀꢁꢊꢉ  
3LQꢀꢁꢊꢊ  
3LQꢀꢁꢊꢋ  
3LQꢀꢁꢅꢁ  
3LQꢀꢁꢅꢈ  
3LQꢀꢁꢅꢉ  
3LQꢀꢁꢅꢊ  
3LQꢀꢁꢅꢋ  
3LQꢀꢁꢋꢁ  
3LQꢀꢁꢋꢈ  
3LQꢀꢁꢋꢉ  
3LQꢀꢁꢋꢊ  
3LQꢀꢁꢋꢋ  
3LQꢀꢁꢆꢁ  
3LQꢀꢁꢆꢈ  
3LQꢀꢁꢆꢉ  
3LQꢀꢁꢆꢊ  
3LQꢀꢁꢆꢋ  
3LQꢀꢂꢁꢁ  
3LQꢀꢂꢁꢈ  
3LQꢀꢂꢁꢉ  
3LQꢀꢂꢁꢊ  
3LQꢀꢂꢁꢋ  
3LQꢀꢂꢂꢁ  
3LQꢀꢂꢂꢈ  
3LQꢀꢂꢂꢉ  
3LQꢀꢂꢂꢊ  
3LQꢀꢂꢂꢋ  
3LQꢀꢂꢈꢁ  
3LQꢀꢂꢅꢁ  
3LQꢀꢂꢅꢈ  
3LQꢀꢂꢅꢉ  
3LQꢀꢂꢅꢊ  
3LQꢀꢂꢅꢋ  
3LQꢀꢂꢋꢁ  
3LQꢀꢂꢋꢈ  
3LQꢀꢂꢋꢉ  
3LQꢀꢂꢋꢊ  
3LQꢀꢂꢋꢋ  
3LQꢀꢂꢆꢁ  
3LQꢀꢂꢆꢈ  
3LQꢀꢂꢆꢉ  
3LQꢀꢂꢆꢊ  
3LQꢀꢂꢆꢋ  
3LQꢀꢈꢁꢁ  
3LQꢀꢈꢁꢈ  
3LQꢀꢈꢁꢉ  
3LQꢀꢈꢁꢊ  
3LQꢀꢈꢁꢋ  
3LQꢀꢈꢂꢁ  
3LQꢀꢈꢂꢈ  
3LQꢀꢈꢂꢉ  
3LQꢀꢈꢂꢊ  
3LQꢀꢈꢂꢋ  
3LQꢀꢈꢈꢁ  
3LQꢀꢈꢈꢈ  
3LQꢀꢈꢈꢉ  
3LQꢀꢈꢈꢊ  
3LQꢀꢈꢈꢋ  
3LQꢀꢈꢃꢁ  
3LQꢀꢈꢃꢈ  
3LQꢀꢈꢃꢉ  
3LQꢀꢈꢃꢊ  
3LQꢀꢈꢃꢋ  
3LQꢀꢈꢉꢁ  
ꢇ
$ꢂꢉ  
(UUB2XW ꢇ 3LQꢀꢁꢄꢃ  
ꢇ
$ꢂꢈꢍ%&  
$ꢂꢂ  
9''  
$ꢉ  
$ꢈ  
&.ꢂ  
9''  
ꢇ 3LQꢀꢁꢄꢄ  
ꢇ 3LQꢀꢁꢄꢅ  
ꢇ 3LQꢀꢁꢄꢆ  
ꢇ 3LQꢀꢁꢊꢂ  
ꢇ 3LQꢀꢁꢊꢃ  
ꢇ 3LQꢀꢁꢊꢄ  
ꢇ
9''  
ꢇ
$ꢊ  
ꢇ
$ꢃ  
9''  
9''  
ꢇ
9''  
ꢂꢏ  
ꢇ
&.ꢂ  
9''  
3DUB,Q  
$ꢂꢁꢍ$3  
9''  
&$6  
6ꢂ  
9''  
&.ꢁ  
ꢇ
9''  
95()ꢌ&$ ꢇ 3LQꢀꢁꢊꢅ  
ꢇ
$ꢁ  
9''  
%$ꢁ  
:(  
9''  
ꢇ 3LQꢀꢁꢊꢆ  
ꢇ 3LQꢀꢁꢅꢂ  
ꢇ 3LQꢀꢁꢅꢃ  
ꢇ 3LQꢀꢁꢅꢄ  
ꢇ
%$ꢂ  
ꢇ
5$6  
ꢇ
9''4  
ꢇ
$ꢂꢃ  
2'7ꢂꢍ1&ꢇ 3LQꢀꢁꢅꢅ  
ꢇ
6ꢃꢍ1&  
6ꢈꢍ1&  
'4ꢃꢈ  
966  
'46ꢉ  
'4ꢃꢉ  
966  
'4ꢉꢂ  
'46ꢄ  
966  
'4ꢉꢃ  
'4ꢉꢋ  
966  
'46ꢊ  
'4ꢄꢁ  
966  
'4ꢄꢅ  
'46ꢅ  
966  
'4ꢄꢆ  
6$ꢁ  
6$ꢈꢍ966 ꢇ 3LQꢀꢂꢂꢆ  
ꢇ 3LQꢀꢁꢅꢆ  
ꢇ 3LQꢀꢁꢋꢂ  
ꢇ 3LQꢀꢁꢋꢃ  
ꢇ 3LQꢀꢁꢋꢄ  
ꢇ 3LQꢀꢁꢋꢅ  
ꢇ 3LQꢀꢁꢋꢆ  
ꢇ 3LQꢀꢁꢆꢂ  
ꢇ 3LQꢀꢁꢆꢃ  
ꢇ 3LQꢀꢁꢆꢄ  
ꢇ 3LQꢀꢁꢆꢅ  
ꢇ 3LQꢀꢁꢆꢆ  
ꢇ 3LQꢀꢂꢁꢂ  
ꢇ 3LQꢀꢂꢁꢃ  
ꢇ 3LQꢀꢂꢁꢄ  
ꢇ 3LQꢀꢂꢁꢅ  
ꢇ 3LQꢀꢂꢁꢆ  
ꢇ 3LQꢀꢂꢂꢂ  
ꢇ 3LQꢀꢂꢂꢃ  
ꢇ 3LQꢀꢂꢂꢄ  
ꢇ 3LQꢀꢂꢂꢅ  
ꢇ
966  
'4ꢃꢊ  
ꢇ
'4ꢃꢃ  
'46ꢉ  
966  
'4ꢃꢄ  
'4ꢉꢁ  
966  
'46ꢄ  
'4ꢉꢈ  
966  
'4ꢉꢆ  
'46ꢊ  
966  
'4ꢄꢂ  
'4ꢄꢊ  
966  
'46ꢅ  
'4ꢄꢋ  
966  
966  
ꢇ
ꢎ7ꢏ'46ꢂꢃ  
ꢇ
'4ꢃꢋ  
ꢇ
966  
ꢇ
'4ꢉꢄ  
ꢇ
ꢎ7ꢏ'46ꢂꢉ  
ꢇ
966  
ꢇ
'4ꢉꢅ  
ꢇ
'4ꢄꢈ  
ꢇ
966  
ꢇ
ꢎ7ꢏ'46ꢂꢄ  
ꢇ
'4ꢄꢉ  
ꢇ
966  
ꢇ
'4ꢊꢂ  
ꢇ
ꢎ7ꢏ'46ꢂꢊ  
ꢇ
966  
ꢇ
'4ꢊꢃ  
ꢇ
9''63'  
3LQꢀꢈꢃꢅ 6$ꢂ  
3LQꢀꢈꢃꢆ 966  
6&/  
977  
6'$  
977  
ꢂꢏꢀ3LQꢀꢊꢃꢀDQGꢀ3LQꢀꢊꢉꢀWHUPLQDWHGꢀZLWKꢀꢂꢈꢁꢀŸ  
ꢎ7ꢏꢀꢐꢀ)RUꢀ[ꢋꢀ'5$0ꢀRQO\  
033+ꢁꢈꢄꢁ  
Rev. 0.51, 2008-01  
12122007-WJ2L-RGDP  
14  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
3
Operating Conditions  
3.1  
Absolute Maximum Ratings  
TABLE 8  
Absolute Maximum Ratings  
Parameter  
Symbol  
Rating  
Unit  
Note  
Min.  
Max.  
1)  
Voltage on VDD pin relative to VSS  
Voltage on VDDQ pin relative to VSS  
Voltage on any pin relative to VSS  
VDD  
–0.4  
–0.4  
–0.4  
+1.975  
+1.975  
+1.975  
V
V
V
VDDQ  
VIN, VOUT  
1)  
V
DD and VDDQ must be within 300mV of each other at all times. VREFDQ and VREFCA must not be greater than 0.6 x VDDQ. When VDD and V  
DDQ are less than 500 mV, VREFDQ and VREFCA may be equal or less than 300 mV.  
TABLE 9  
Environmental Parameters  
Parameter  
Symbol  
Rating  
Min.  
Unit  
Note  
Max.  
1)  
2)  
3)  
Operating Temperature  
TOPR  
HOPR  
TSTG  
HSTG  
–
–
°C  
Operating Humidity (relative)  
Storage Temperature  
10  
–50  
5
90  
%
+100  
95  
°C  
Storage Humidity (without condensation)  
%
Barometric Pressure (Operating and Storage) PBar  
69  
105  
KPascal  
1) Device designer must meet the case temperature specification for individual module components.  
2) Storage Temperature is the case surface temperature on the center/top side of the SDRAM mentioned in Qimonda component datasheet.  
3) Up to 9850 ft.  
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to  
the device. This is a stress rating only and functional operation of the device at these or any other  
conditions above those indicated in the operational sections of this specification is not implied. Exposure  
to absolute maximum rating conditions for extended periods may affect reliability.  
Rev. 0.51, 2008-01  
15  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 10  
DRAM Component Operating Temperature Range  
Parameter  
Symbol  
Rating  
Unit  
Note  
Min.  
Max.  
1)2)  
1)3)  
Normal Operating Temperature Range  
Extended Temperature Range  
TOPER  
0
85  
95  
°C  
°C  
85  
1) Operating Temperature TOPER is the case surface temperature on the center / top side of the SDRAM mentioned..  
2) The Normal Temperature Range specifies the temperatures where all SDRAM specification will be supported.  
3) Some application require operation of the DRAM in the Extended Temperature Range between 85 °C and 95 °C operating temperature.  
For more details please refer to Qimonda Component datasheet.  
3.2  
Recommended DC Operating Conditions  
TABLE 11  
DC Operating Conditions  
Parameter  
Symbol  
Min.  
Typ.  
Max.  
Unit Note  
1)2)  
Supply Voltage  
VDD  
1.425  
3.0  
1.5  
3.3  
1.5  
1.575  
3.6  
V
1)2)  
Supply Voltage for EEPROM and Thermal Sensor  
Supply Voltage for Output  
VDD.SPD  
VDDQ  
V
1)2)  
1.425  
1.575  
V
3)4)  
Reference Voltage for DQ, DM inputs  
Reference Voltage for ADD, CMD inputs  
Terminal Voltage  
VREFDQ.DC 0.49 x VDD 0.5 x VDD 0.51 x VDD  
VREFCA.DC 0.49 x VDD 0.5 x VDD 0.51 x VDD  
V
3)4)  
V
VTT  
0.49 x VDD 0.5 x VDD 0.51 x VDD  
237.6 240.0 242.4  
DDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together  
2) Under all conditions VDDQ must be less than or equal to VDD  
V
5)  
External Calibration Resistor connected from ZQ pin to ground RZQ  
Ω
1)  
V
.
3) The ac peak noise on VREF may not allow VREF to deviate from VREF.DC by more than ±1% VDD (for reference: approx. ± 15 mV).  
4) For reference: approx. VDD/2 ± 15 mV.  
5) The external calibration resistor RZQ can be time-shared among DRAMs in multi-rank DIMMs.  
Rev. 0.51, 2008-01  
16  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
4
Speed Bins and Timing Parameters  
AC timings are provided with CK/CK and DQS/DQS  
differential slew rate of 2.0 V/ns. Timings are further provided  
for calibrated OCD drive strength. The CK/CK input reference  
level (for timing referenced to CK / CK) is the point at which  
CK and CK cross.The DQS/DQS reference level (for timing  
referenced to DQS/DQS) is the point at which DQS and DQS  
cross.Inputs are not recognized as valid until VREF stabilizes.  
During the period before VREF.CA and VREFDQ stabilizes, CKE  
= 0.2 x VDDQ is recognized as low. The output timing reference  
voltage level is VTT.For details of all relevant AC timing  
parameters see the QIMONDA DDR3 component datasheet.  
4.1  
Speed Bins  
The following tables show DDR3 speed bins and relevant  
timing parameters. Other timing parameters are provided in  
the following chapter.  
The absolute specification for all speed bins is TOPER and  
VDD = VDDQ = 1.5 V +/-0.075 V. In addition the following  
general notes apply.  
General Notes for Speed Bins:  
•
The CL setting and CWL setting result in tCK.AVG.MIN and  
•
•
‘Reserved’ settings are not allowed. User must program a  
different value  
Any DDR3-1066 speed bin also supports functional  
operation at lower frequencies as shown in the tables  
which are not subject to Production Tests but verified by  
Design/Characterization  
Any DDR3-1333 speed bin also supports functional  
operation at lower frequencies as shown in the tables  
which are not subject to Production Tests but verified by  
Design/Characterization  
Any DDR3-1600 speed bin also supports functional  
operation at lower frequencies as shown in the tables  
which are not subject to Production Tests but verified by  
Design/Characterization  
t
t
CK.AVG.MAX requirements. When making a selection of  
CK.AVG, both need to be fulfiled: Requirements from CL  
setting as well as requirements from CWL setting  
• tCK.AVG.MIN limits: Since CAS Latency is not purely analog -  
data and strobe output are synchronized by the DLL - all  
possible intermediate frequencies may not be provided. An  
application should use the next smaller standard tCK.AVG  
value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL  
[nCK] = tAA [ns] / tCK.AVG [ns], rounding up to the next  
‘Supported CL’  
•
•
• tCK.AVG.MAX limits: Calculate tCK.AVG = tAA.MAX  
/
CLSELECTED and round the resulting tCK.AVG down to the  
next valid speed bin limit (i.e. 3.3 ns or 2.5 ns or 1.875 ns  
or 1.25 ns). This result is tCK.AVG.MAX corresponding to  
CLSELECTED  
TABLE 12  
DDR3–800 Speed Bins  
Speed Bin  
DDR3-800D  
5-5-5  
DDR3-800E  
Unit Note  
CL-nRCD-nRP  
6-6-6  
Qimonda Partnumber Extension  
-08D  
-08E  
Parameter  
Symbol  
Min.  
Max.  
Min.  
Max.  
1)  
Internal read command to first data  
ACT to internal read or write delay time  
PRE command period  
tAA  
12.5  
12.5  
12.5  
50.0  
5, 6  
5
20.0  
—
15.0  
15.0  
15.0  
52.5  
6
20.0  
—
ns  
1)  
tRCD  
tRP  
ns  
1)  
—
—
ns  
1)  
ACT to ACT or REF command period  
Supported CL Settings  
tRC  
—
—
ns  
1)  
Sup_CL  
nCK  
1)  
Supported CWL Settings  
Sup_CWL  
17  
5
nCK  
Rev. 0.51, 2008-01  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Speed Bin  
DDR3-800D  
5-5-5  
DDR3-800E  
6-6-6  
Unit Note  
CL-nRCD-nRP  
Qimonda Partnumber Extension  
Parameter  
-08D  
-08E  
Symbol  
Min.  
Max.  
Min.  
Max.  
1)2)  
Average Clock Period with CL = 5; CWL = 5  
Average Clock Period with CL = 6; CWL = 5  
tCK.AVG.CL05.CWL05  
tCK.AVG.CL06.CWL05  
2.5  
2.5  
3.3  
3.3  
RESERVED  
ns  
1)2)  
2.5  
3.3  
ns  
1) Please refer to "General Notes for Speed Bins" at beginning of this chapter.  
2) Max. limits are exclusive. E.g. if tCK.AVG.MAX value is 2.5 ns, tCK.AVG needs to be < 2.5 ns.  
TABLE 13  
DDR3–1066 Speed Bins  
Speed Bin  
DDR3-1066E  
6-6-6  
DDR3-1066F  
7-7-7  
DDR3-1066G  
Unit Note  
CL-nRCD-nRP  
8-8-8  
Qimonda Partnumber Extension  
Parameter  
-10E  
-10F  
-10G  
Symbol  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
1)  
Internal read command to first data tAA  
11.25 20.0  
13.125 20.0  
15.0  
15.0  
20.0  
—
ns  
1)  
ACT to internal read or write delay  
time  
tRCD  
11.25  
—
13.125  
—
ns  
1)  
PRE command period  
tRP  
tRC  
11.25  
48.75  
—
—
13.125  
50.625  
—
—
15.0  
52.5  
—
—
ns  
1)  
ACT to ACT or REF command  
period  
ns  
1)  
Supported CL Settings  
Supported CWL Settings  
Sup_CL  
5, 6, 7, 8  
5, 6  
6, 7, 8  
5, 6  
6, 8  
5, 6  
nCK  
1)  
Sup_CWL  
nCK  
1)2)  
Average Clock Period with CL = 5; tCK.AVG.CL05.CWL05 2.5  
3.3  
RESERVED  
RESERVED  
ns  
CWL = 5  
1)2)  
Average Clock Period with CL = 5; tCK.AVG.CL05.CWL06 RESERVED  
RESERVED  
RESERVED  
ns  
CWL = 6  
1)2)  
Average Clock Period with CL = 6; tCK.AVG.CL06.CWL05 2.5  
3.3  
2.5  
3.3  
2.5  
3.3  
ns  
CWL = 5  
1)2)  
Average Clock Period with CL = 6; tCK.AVG.CL06.CWL06 1.875 2.5  
CWL = 6  
RESERVED  
RESERVED  
1.875 2.5  
RESERVED  
1.875 2.5  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
1.875 2.5  
ns  
1)2)  
Average Clock Period with CL = 7; tCK.AVG.CL07.CWL05 RESERVED  
CWL = 5  
ns  
1)2)  
Average Clock Period with CL = 7; tCK.AVG.CL07.CWL06 1.875 2.5  
CWL = 6  
ns  
1)2)  
Average Clock Period with CL = 8; tCK.AVG.CL08.CWL05 RESERVED  
CWL = 5  
ns  
1)2)  
Average Clock Period with CL = 8; tCK.AVG.CL08.CWL06 1.875 2.5  
ns  
CWL = 6  
1) Please refer to "General Notes for Speed Bins" at beginning of this chapter.  
2) Max. limits are exclusive. E.g. if tCK.AVG.MAX value is 2.5 ns, tCK.AVG needs to be < 2.5 ns.  
Rev. 0.51, 2008-01  
18  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 14  
DDR3–1333 Speed Bins  
Speed Bin  
DDR3-  
1333G  
DDR3-  
1333H  
DDR3-1333J Unit Note  
CL-nRCD-nRP  
8-8-8  
-13G  
9-9-9  
-13H  
10-10-10  
-13J  
Qimonda Partnumber Extension  
Parameter  
Symbol  
Min. Max. Min. Max. Min. Max.  
1)  
1)  
1)  
1)  
1)  
Internal read command to first data  
ACT to internal read or write delay time  
PRE command period  
tAA  
12.0 20.0 13.5 20.0 15.0 20.0 ns  
tRCD  
tRP  
12.0  
12.0  
48.0  
—
—
—
13.5  
13.5  
49.5  
—
—
—
15.0  
15.0  
51.0  
—
—
—
ns  
ns  
ACT to ACT or REF command period  
Supported CL Settings  
tRC  
ns  
Sup_CL  
5, 6, 7, 8, 9, 6, 8, 9, 10  
10  
6, 8, 10  
nCK  
1)  
Supported CWL Settings  
Sup_CWL  
5, 6, 7  
5, 6, 7  
5, 6, 7  
nCK  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
Average Clock Period with CL = 5; CWL = 5 tCK.AVG.CL05.CWL05 2.5  
3.3  
RESERVED RESERVED ns  
Average Clock Period with CL = 5; CWL = 6 tCK.AVG.CL05.CWL06 RESERVED RESERVED RESERVED ns  
Average Clock Period with CL = 5; CWL = 7 tCK.AVG.CL05.CWL07 RESERVED RESERVED RESERVED ns  
Average Clock Period with CL = 6; CWL = 5 tCK.AVG.CL06.CWL05 2.5  
3.3  
2.5  
3.3  
2.5  
3.3  
ns  
Average Clock Period with CL = 6; CWL = 6 tCK.AVG.CL06.CWL06 RESERVED RESERVED RESERVED ns  
Average Clock Period with CL = 6; CWL = 7 tCK.AVG.CL06.CWL07 RESERVED RESERVED RESERVED ns  
Average Clock Period with CL = 7; CWL = 5 tCK.AVG.CL07.CWL05 RESERVED RESERVED RESERVED ns  
Average Clock Period with CL = 7; CWL = 6 tCK.AVG.CL07.CWL06 1.875 2.5  
RESERVED RESERVED ns  
Average Clock Period with CL = 7; CWL = 7 tCK.AVG.CL07.CWL07 RESERVED RESERVED RESERVED ns  
Average Clock Period with CL = 8; CWL = 5 tCK.AVG.CL08.CWL05 RESERVED RESERVED RESERVED ns  
Average Clock Period with CL = 8; CWL = 6 tCK.AVG.CL08.CWL06 1.875 2.5  
1.875 2.5  
1.875 2.5  
ns  
Average Clock Period with CL = 8; CWL = 7 tCK.AVG.CL08.CWL07 1.5 1.875 RESERVED RESERVED ns  
Average Clock Period with CL = 9; CWL = 5 tCK.AVG.CL09.CWL05 RESERVED RESERVED RESERVED ns  
Average Clock Period with CL = 9; CWL = 6 tCK.AVG.CL09.CWL06 RESERVED RESERVED RESERVED ns  
Average Clock Period with CL = 9; CWL = 7 tCK.AVG.CL09.CWL07 1.5  
1.875 1.5  
1.875 RESERVED ns  
Average Clock Period with CL = 10; CWL = 5 tCK.AVG.CL10.CWL05 RESERVED RESERVED RESERVED ns  
Average Clock Period with CL = 10; CWL = 6 tCK.AVG.CL10.CWL06 RESERVED RESERVED RESERVED ns  
Average Clock Period with CL = 10; CWL = 7 tCK.AVG.CL10.CWL07 1.5  
1.875 1.5  
1.875 1.5  
1.875 ns  
1) Please refer to "General Notes for Speed Bins" at beginning of this chapter.  
2) Max. limits are exclusive. E.g. if tCK.AVG.MAX value is 2.5 ns, tCK.AVG needs to be < 2.5 ns.  
Rev. 0.51, 2008-01  
19  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
5
SPD Codes  
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands  
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.  
List of SPD Code Tables  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Table 15 “IMSH1GP03A1F1C-[08D/08E/10F/10G]” on Page 21  
Table 16 “IMSH1GP03A1F1C-[13G/13H]” on Page 24  
Table 17 “IMSH2GP02A1F1C-[08D/08E/10F/10G]” on Page 2797  
Table 18 “IMSH2GP02A1F1C-[13G/13H]” on Page 30  
Table 19 “IMSH2GP13A1F1C-[08D/08E/10F/10G]” on Page 33  
Table 20 “IMSH2GP13A1F1C-[13G/13H]” on Page 37  
Table 21 “IMSH4GP12A1F1C-[08D/08E/10F/10G]” on Page 40  
Table 22 “IMSH4GP12A1F1C-[13G/13H]” on Page 44  
Table 23 “IMSH4GP23A1F1C-[08D/08E/10F/10G]” on Page 47  
Table 24 “IMSH4GP23A1F1C-[13G/13H]” on Page 51  
Table 15 “IMSH1GP03A1F1C-[08D/08E/10F/10G]” on Page 21  
Table 16 “IMSH1GP03A1F1C-[13G/13H]” on Page 24  
Table 17 “IMSH2GP02A1F1C-[08D/08E/10F/10G]” on Page 27  
Table 18 “IMSH2GP02A1F1C-[13G/13H]” on Page 30  
Table 19 “IMSH2GP13A1F1C-[08D/08E/10F/10G]” on Page 33  
Table 20 “IMSH2GP13A1F1C-[13G/13H]” on Page 37  
Table 21 “IMSH4GP12A1F1C-[08D/08E/10F/10G]” on Page 40  
Table 22 “IMSH4GP12A1F1C-[13G/13H]” on Page 44  
Table 23 “IMSH4GP23A1F1C-[08D/08E/10F/10G]” on Page 47  
Table 24 “IMSH4GP23A1F1C-[13G/13H]” on Page 51  
Rev. 0.51, 2008-01  
20  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 15  
IMSH1GP03A1F1C-[08D/08E/10F/10G]  
Product Type  
Organization  
1 GByte  
1 GByte  
1 GByte  
1 GByte  
×72  
×72  
×72  
×72  
1 Rank (×x8) 1 Rank (×x8) 1 Rank (×x8) 1 Rank (×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
11  
00  
01  
0B  
52  
01  
08  
14  
00  
06  
00  
64  
78  
64  
50  
92  
05  
0B  
01  
02  
11  
00  
01  
0B  
52  
01  
08  
14  
00  
04  
00  
78  
78  
78  
50  
92  
05  
0B  
01  
02  
11  
00  
01  
0B  
52  
01  
08  
0F  
00  
1C  
00  
69  
78  
69  
3C  
92  
05  
0B  
01  
02  
11  
00  
01  
0B  
52  
01  
08  
0F  
00  
14  
00  
78  
78  
78  
3C  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
64  
11  
78  
11  
69  
11  
78  
11  
Rev. 0.51, 2008-01  
21  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
1 GByte  
1 GByte  
1 GByte  
1 GByte  
×72  
×72  
×72  
×72  
1 Rank (×x8) 1 Rank (×x8) 1 Rank (×x8) 1 Rank (×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
HEX  
22  
23  
24  
25  
26  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
2C  
2C  
A4  
70  
03  
3C  
2C  
95  
70  
03  
3C  
2C  
A4  
70  
03  
3C  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 90  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
3C  
3C  
Time (tRTP.MIN), MSB  
28  
29  
30  
31  
Upper Nibble for tFAW  
01  
40  
02  
81  
00  
10  
11  
00  
00  
00  
85  
51  
xx  
01  
40  
02  
81  
00  
10  
11  
00  
00  
00  
85  
51  
xx  
xx  
01  
2C  
02  
81  
00  
10  
11  
00  
00  
00  
85  
51  
xx  
01  
2C  
02  
81  
00  
10  
11  
00  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
xx  
xx  
126  
127  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
9C  
A3  
93  
52  
0B  
0B  
68  
FE  
Rev. 0.51, 2008-01  
22  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
1 GByte  
1 GByte  
1 GByte  
1 GByte  
×72  
×72  
×72  
×72  
1 Rank (×x8) 1 Rank (×x8) 1 Rank (×x8) 1 Rank (×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 1  
49  
4D  
53  
48  
31  
47  
50  
30  
33  
41  
31  
46  
31  
43  
2D  
30  
38  
44  
0x  
xx  
49  
4D  
53  
48  
31  
47  
50  
30  
33  
41  
31  
46  
31  
43  
2D  
30  
38  
45  
1x  
xx  
49  
4D  
53  
48  
31  
47  
50  
30  
33  
41  
31  
46  
31  
43  
2D  
31  
30  
46  
0x  
xx  
49  
4D  
53  
48  
31  
47  
50  
30  
33  
41  
31  
46  
31  
43  
2D  
31  
30  
47  
2x  
xx  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
00  
00  
Rev. 0.51, 2008-01  
23  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 16  
IMSH1GP03A1F1C-[13G/13H]  
Product Type  
Organization  
IMSH1GP03A1F1C–13G  
IMSH1GP03A1F1C–13H  
1 GByte  
×72  
1 GByte  
×72  
1 Rank (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
1 Rank (×x8)  
PC3–10600R–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
11  
00  
01  
0B  
52  
01  
08  
0C  
00  
7E  
00  
60  
78  
60  
30  
92  
05  
0B  
01  
02  
11  
00  
01  
0B  
52  
01  
08  
0C  
00  
74  
00  
6C  
78  
6C  
30  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
22  
23  
24  
25  
26  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
60  
11  
20  
6C  
11  
20  
8C  
70  
03  
3C  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 80  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
Time (tRTP.MIN), MSB  
Rev. 0.51, 2008-01  
24  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMSH1GP03A1F1C–13G  
IMSH1GP03A1F1C–13H  
1 GByte  
1 GByte  
×72  
×72  
1 Rank (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
1 Rank (×x8)  
PC3–10600R–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte# Description  
HEX  
28  
29  
30  
31  
Upper Nibble for tFAW  
00  
F0  
02  
81  
00  
10  
11  
00  
00  
00  
85  
51  
xx  
00  
F0  
02  
81  
00  
10  
11  
00  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
CF  
84  
49  
4D  
53  
48  
31  
47  
50  
30  
33  
41  
31  
46  
31  
43  
D9  
2D  
49  
4D  
53  
48  
31  
47  
50  
30  
33  
41  
31  
46  
31  
43  
Rev. 0.51, 2008-01  
25  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMSH1GP03A1F1C–13G  
IMSH1GP03A1F1C–13H  
1 GByte  
1 GByte  
×72  
×72  
1 Rank (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
1 Rank (×x8)  
PC3–10600R–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 15  
2D  
31  
33  
47  
1x  
xx  
2D  
31  
33  
48  
2x  
xx  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
Rev. 0.51, 2008-01  
26  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 17  
IMSH2GP02A1F1C-[08D/08E/10F/10G]  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
1 Rank (×x4) 1 Rank (×x4) 1 Rank (×x4) 1 Rank (×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
12  
00  
00  
0B  
52  
01  
08  
14  
00  
06  
00  
64  
78  
64  
50  
92  
05  
0B  
01  
02  
12  
00  
00  
0B  
52  
01  
08  
14  
00  
04  
00  
78  
78  
78  
50  
92  
05  
0B  
01  
02  
12  
00  
00  
0B  
52  
01  
08  
0F  
00  
1C  
00  
69  
78  
69  
3C  
92  
05  
0B  
01  
02  
12  
00  
00  
0B  
52  
01  
08  
0F  
00  
14  
00  
78  
78  
78  
3C  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
64  
11  
78  
11  
69  
11  
78  
11  
Rev. 0.51, 2008-01  
27  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
1 Rank (×x4) 1 Rank (×x4) 1 Rank (×x4) 1 Rank (×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
HEX  
22  
23  
24  
25  
26  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
2C  
2C  
A4  
70  
03  
3C  
2C  
95  
70  
03  
3C  
2C  
A4  
70  
03  
3C  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 90  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
3C  
3C  
Time (tRTP.MIN), MSB  
28  
29  
30  
31  
Upper Nibble for tFAW  
01  
40  
02  
81  
00  
10  
11  
02  
00  
00  
85  
51  
xx  
01  
40  
02  
81  
00  
10  
11  
02  
00  
00  
85  
51  
xx  
xx  
01  
2C  
02  
81  
00  
10  
11  
02  
00  
00  
85  
51  
xx  
01  
2C  
02  
81  
00  
10  
11  
02  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
xx  
xx  
126  
127  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
29  
26  
BE  
C5  
DD  
30  
6D  
9C  
Rev. 0.51, 2008-01  
28  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
1 Rank (×x4) 1 Rank (×x4) 1 Rank (×x4) 1 Rank (×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 1  
49  
4D  
53  
48  
32  
47  
50  
30  
32  
41  
31  
46  
31  
43  
2D  
30  
38  
44  
0x  
xx  
49  
4D  
53  
48  
32  
47  
50  
30  
32  
41  
31  
46  
31  
43  
2D  
30  
38  
45  
1x  
xx  
49  
4D  
53  
48  
32  
47  
50  
30  
32  
41  
31  
46  
31  
43  
2D  
31  
30  
46  
0x  
xx  
49  
4D  
53  
48  
32  
47  
50  
30  
32  
41  
31  
46  
31  
43  
2D  
31  
30  
47  
1x  
xx  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
00  
00  
Rev. 0.51, 2008-01  
29  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 18  
IMSH2GP02A1F1C-[13G/13H]  
Product Type  
Organization  
IMSH2GP02A1F1C–13G  
IMSH2GP02A1F1C–13H  
2 GByte  
×72  
2 GByte  
×72  
1 Rank (×x4)  
PC3–10600P–8  
Rev. 0.5  
HEX  
1 Rank (×x4)  
PC3–10600R–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
12  
00  
00  
0B  
52  
01  
08  
0C  
00  
7E  
00  
60  
78  
60  
30  
92  
05  
0B  
01  
02  
12  
00  
00  
0B  
52  
01  
08  
0C  
00  
74  
00  
6C  
78  
6C  
30  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
22  
23  
24  
25  
26  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
60  
11  
20  
6C  
11  
20  
8C  
70  
03  
3C  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 80  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
Time (tRTP.MIN), MSB  
Rev. 0.51, 2008-01  
30  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMSH2GP02A1F1C–13G  
IMSH2GP02A1F1C–13H  
2 GByte  
2 GByte  
×72  
×72  
1 Rank (×x4)  
PC3–10600P–8  
Rev. 0.5  
HEX  
1 Rank (×x4)  
PC3–10600R–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte# Description  
HEX  
28  
29  
30  
31  
Upper Nibble for tFAW  
00  
F0  
02  
81  
00  
10  
11  
02  
00  
00  
85  
51  
xx  
00  
F0  
02  
81  
00  
10  
11  
02  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
7A  
4A  
49  
4D  
53  
48  
32  
47  
50  
30  
32  
41  
31  
46  
31  
43  
6C  
E3  
49  
4D  
53  
48  
32  
47  
50  
30  
32  
41  
31  
46  
31  
43  
Rev. 0.51, 2008-01  
31  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMSH2GP02A1F1C–13G  
IMSH2GP02A1F1C–13H  
2 GByte  
2 GByte  
×72  
×72  
1 Rank (×x4)  
PC3–10600P–8  
Rev. 0.5  
HEX  
1 Rank (×x4)  
PC3–10600R–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 15  
2D  
31  
33  
47  
1x  
xx  
2D  
31  
33  
48  
2x  
xx  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
Rev. 0.51, 2008-01  
32  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 19  
IMSH2GP13A1F1C-[08D/08E/10F/10G]  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
11  
00  
09  
0B  
52  
01  
08  
14  
00  
06  
00  
64  
78  
64  
50  
92  
05  
0B  
01  
02  
11  
00  
09  
0B  
52  
01  
08  
14  
00  
04  
00  
78  
78  
78  
50  
92  
05  
0B  
01  
02  
11  
00  
09  
0B  
52  
01  
08  
0F  
00  
1C  
00  
69  
78  
69  
3C  
92  
05  
0B  
01  
02  
11  
00  
09  
0B  
52  
01  
08  
0F  
00  
14  
00  
78  
78  
78  
3C  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
64  
11  
78  
11  
69  
11  
78  
11  
Rev. 0.51, 2008-01  
33  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
HEX  
22  
23  
24  
25  
26  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
2C  
2C  
A4  
70  
03  
3C  
2C  
95  
70  
03  
3C  
2C  
A4  
70  
03  
3C  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 90  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
3C  
3C  
Time (tRTP.MIN), MSB  
28  
29  
30  
31  
Upper Nibble for tFAW  
01  
40  
02  
81  
00  
10  
11  
01  
00  
00  
85  
51  
xx  
01  
40  
02  
81  
00  
10  
11  
01  
00  
00  
85  
51  
xx  
xx  
01  
2C  
02  
81  
00  
10  
11  
01  
00  
00  
85  
51  
xx  
01  
2C  
02  
81  
00  
10  
11  
01  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
xx  
xx  
126  
Cyclical Redundancy Code LSB  
72  
7D  
E5  
86  
Rev. 0.51, 2008-01  
34  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
AA  
49  
4D  
53  
48  
32  
47  
50  
31  
33  
41  
31  
46  
31  
43  
2D  
30  
38  
44  
0x  
xx  
5B  
49  
4D  
53  
48  
32  
47  
50  
31  
33  
41  
31  
46  
31  
43  
2D  
30  
38  
45  
1x  
xx  
02  
49  
4D  
53  
48  
32  
47  
50  
31  
33  
41  
31  
46  
31  
43  
2D  
31  
30  
46  
0x  
xx  
F7  
49  
4D  
53  
48  
32  
47  
50  
31  
33  
41  
31  
46  
31  
43  
2D  
31  
30  
47  
1x  
xx  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
85  
51  
85  
51  
85  
51  
85  
51  
Rev. 0.51, 2008-01  
35  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
Rev. 0.5  
Rev. 0.5  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
150 -  
175  
Manufactures’s Specific Data  
00  
00  
00  
00  
176 -  
255  
Blank for Customer Use  
00  
00  
00  
00  
Rev. 0.51, 2008-01  
36  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 20  
IMSH2GP13A1F1C-[13G/13H]  
Product Type  
Organization  
IMSH2GP13A1F1C–13G  
IMSH2GP13A1F1C–13H  
2 GByte  
×72  
2 GByte  
×72  
2 Ranks (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
2 Ranks (×x8)  
PC3–10600R–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
11  
00  
09  
0B  
52  
01  
08  
0C  
00  
7E  
00  
60  
78  
60  
30  
92  
05  
0B  
01  
02  
11  
00  
09  
0B  
52  
01  
08  
0C  
00  
74  
00  
6C  
78  
6C  
30  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
22  
23  
24  
25  
26  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
60  
11  
20  
6C  
11  
20  
8C  
70  
03  
3C  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 80  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
Time (tRTP.MIN), MSB  
Rev. 0.51, 2008-01  
37  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMSH2GP13A1F1C–13G  
IMSH2GP13A1F1C–13H  
2 GByte  
2 GByte  
×72  
×72  
2 Ranks (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
2 Ranks (×x8)  
PC3–10600R–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte# Description  
HEX  
28  
29  
30  
31  
Upper Nibble for tFAW  
00  
F0  
02  
81  
00  
10  
11  
01  
00  
00  
85  
51  
xx  
00  
F0  
02  
81  
00  
10  
11  
01  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
21  
8D  
49  
4D  
53  
48  
32  
47  
50  
31  
33  
41  
31  
46  
31  
43  
37  
24  
49  
4D  
53  
48  
32  
47  
50  
31  
33  
41  
31  
46  
31  
43  
Rev. 0.51, 2008-01  
38  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMSH2GP13A1F1C–13G  
IMSH2GP13A1F1C–13H  
2 GByte  
2 GByte  
×72  
×72  
2 Ranks (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
2 Ranks (×x8)  
PC3–10600R–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 15  
2D  
31  
33  
47  
1x  
xx  
2D  
31  
33  
48  
2x  
xx  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
Rev. 0.51, 2008-01  
39  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 21  
IMSH4GP12A1F1C-[08D/08E/10F/10G]  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x4)  
(×x4)  
(×x4)  
(×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
12  
00  
08  
0B  
52  
01  
08  
14  
00  
06  
00  
64  
78  
64  
50  
92  
05  
0B  
01  
02  
12  
00  
08  
0B  
52  
01  
08  
14  
00  
04  
00  
78  
78  
78  
50  
92  
05  
0B  
01  
02  
12  
00  
08  
0B  
52  
01  
08  
0F  
00  
1C  
00  
69  
78  
69  
3C  
92  
05  
0B  
01  
02  
12  
00  
08  
0B  
52  
01  
08  
0F  
00  
14  
00  
78  
78  
78  
3C  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
64  
11  
78  
11  
69  
11  
78  
11  
Rev. 0.51, 2008-01  
40  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x4)  
(×x4)  
(×x4)  
(×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
HEX  
22  
23  
24  
25  
26  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
2C  
2C  
A4  
70  
03  
3C  
2C  
95  
70  
03  
3C  
2C  
A4  
70  
03  
3C  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 90  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
3C  
3C  
Time (tRTP.MIN), MSB  
28  
29  
30  
31  
Upper Nibble for tFAW  
01  
40  
02  
81  
00  
10  
11  
04  
00  
00  
85  
51  
xx  
01  
40  
02  
81  
00  
10  
11  
04  
00  
00  
85  
51  
xx  
xx  
01  
2C  
02  
81  
00  
10  
11  
04  
00  
00  
85  
51  
xx  
01  
2C  
02  
81  
00  
10  
11  
04  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
xx  
xx  
126  
Cyclical Redundancy Code LSB  
4C  
43  
DB  
B8  
Rev. 0.51, 2008-01  
41  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x4)  
(×x4)  
(×x4)  
(×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
9F  
49  
4D  
53  
48  
34  
47  
50  
31  
32  
41  
31  
46  
31  
43  
2D  
30  
38  
44  
0x  
xx  
6E  
49  
4D  
53  
48  
34  
47  
50  
31  
32  
41  
31  
46  
31  
43  
2D  
30  
38  
45  
1x  
xx  
37  
49  
4D  
53  
48  
34  
47  
50  
31  
32  
41  
31  
46  
31  
43  
2D  
31  
30  
46  
0x  
xx  
C2  
49  
4D  
53  
48  
34  
47  
50  
31  
32  
41  
31  
46  
31  
43  
2D  
31  
30  
47  
1x  
xx  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
85  
51  
85  
51  
85  
51  
85  
51  
Rev. 0.51, 2008-01  
42  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x4)  
(×x4)  
(×x4)  
(×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400R–6  
8500P–7  
8500R–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
Rev. 0.5  
Rev. 0.5  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
150 -  
175  
Manufactures’s Specific Data  
00  
00  
00  
00  
176 -  
255  
Blank for Customer Use  
00  
00  
00  
00  
Rev. 0.51, 2008-01  
43  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 22  
IMSH4GP12A1F1C-[13G/13H]  
Product Type  
Organization  
IMSH4GP12A1F1C–13G  
IMSH4GP12A1F1C–13H  
4 GByte  
×72  
4 GByte  
×72  
2 Ranks (×x4)  
PC3–10600P–8  
Rev. 0.5  
HEX  
2 Ranks (×x4)  
PC3–10600R–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
12  
00  
08  
0B  
52  
01  
08  
0C  
00  
7E  
00  
60  
78  
60  
30  
92  
05  
0B  
01  
02  
12  
00  
08  
0B  
52  
01  
08  
0C  
00  
74  
00  
6C  
78  
6C  
30  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
22  
23  
24  
25  
26  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
60  
11  
20  
6C  
11  
20  
8C  
70  
03  
3C  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 80  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
Time (tRTP.MIN), MSB  
Rev. 0.51, 2008-01  
44  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMSH4GP12A1F1C–13G  
IMSH4GP12A1F1C–13H  
4 GByte  
4 GByte  
×72  
×72  
2 Ranks (×x4)  
PC3–10600P–8  
Rev. 0.5  
HEX  
2 Ranks (×x4)  
PC3–10600R–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte# Description  
HEX  
28  
29  
30  
31  
Upper Nibble for tFAW  
00  
F0  
02  
81  
00  
10  
11  
04  
00  
00  
85  
51  
xx  
00  
F0  
02  
81  
00  
10  
11  
04  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
1F  
B8  
49  
4D  
53  
48  
34  
47  
50  
31  
32  
41  
31  
46  
31  
43  
09  
11  
49  
4D  
53  
48  
34  
47  
50  
31  
32  
41  
31  
46  
31  
43  
Rev. 0.51, 2008-01  
45  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMSH4GP12A1F1C–13G  
IMSH4GP12A1F1C–13H  
4 GByte  
4 GByte  
×72  
×72  
2 Ranks (×x4)  
PC3–10600P–8  
Rev. 0.5  
HEX  
2 Ranks (×x4)  
PC3–10600R–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 15  
2D  
31  
33  
47  
1x  
xx  
2D  
31  
33  
48  
2x  
xx  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
Rev. 0.51, 2008-01  
46  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 23  
IMSH4GP23A1F1C-[08D/08E/10F/10G]  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
4 Ranks  
4 Ranks  
4 Ranks  
4 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
11  
00  
19  
0B  
52  
01  
08  
14  
00  
06  
00  
64  
78  
64  
50  
92  
05  
0B  
01  
02  
11  
00  
19  
0B  
52  
01  
08  
14  
00  
04  
00  
78  
78  
78  
50  
92  
05  
0B  
01  
02  
11  
00  
19  
0B  
52  
01  
08  
0F  
00  
1C  
00  
69  
78  
69  
3C  
92  
05  
0B  
01  
02  
11  
00  
19  
0B  
52  
01  
08  
0F  
00  
14  
00  
78  
78  
78  
3C  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
64  
11  
78  
11  
69  
11  
78  
11  
Rev. 0.51, 2008-01  
47  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
4 Ranks  
4 Ranks  
4 Ranks  
4 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
HEX  
22  
23  
24  
25  
26  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
2C  
2C  
A4  
70  
03  
3C  
2C  
95  
70  
03  
3C  
2C  
A4  
70  
03  
3C  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 90  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
3C  
3C  
Time (tRTP.MIN), MSB  
28  
29  
30  
31  
Upper Nibble for tFAW  
01  
40  
02  
81  
00  
10  
11  
07  
00  
00  
85  
51  
xx  
01  
40  
02  
81  
00  
10  
11  
07  
00  
00  
85  
51  
xx  
xx  
01  
2C  
02  
81  
00  
10  
11  
07  
00  
00  
85  
51  
xx  
01  
2C  
02  
81  
00  
10  
11  
07  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
xx  
xx  
126  
Cyclical Redundancy Code LSB  
7A  
75  
ED  
8E  
Rev. 0.51, 2008-01  
48  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
4 Ranks  
4 Ranks  
4 Ranks  
4 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
2D  
49  
4D  
53  
48  
34  
47  
50  
32  
33  
41  
31  
46  
31  
43  
2D  
30  
38  
44  
0x  
xx  
DC  
49  
4D  
53  
48  
34  
47  
50  
32  
33  
41  
31  
46  
31  
43  
2D  
30  
38  
45  
0x  
xx  
85  
49  
4D  
53  
48  
34  
47  
50  
32  
33  
41  
31  
46  
31  
43  
2D  
31  
30  
46  
0x  
xx  
70  
49  
4D  
53  
48  
34  
47  
50  
32  
33  
41  
31  
46  
31  
43  
2D  
31  
30  
47  
0x  
xx  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
85  
51  
85  
51  
85  
51  
85  
51  
Rev. 0.51, 2008-01  
49  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
4 Ranks  
4 Ranks  
4 Ranks  
4 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
Rev. 0.5  
Rev. 0.5  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
150 -  
175  
Manufactures’s Specific Data  
00  
00  
00  
00  
176 -  
255  
Blank for Customer Use  
00  
00  
00  
00  
Rev. 0.51, 2008-01  
50  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 24  
IMSH4GP23A1F1C-[13G/13H]  
Product Type  
Organization  
IMSH4GP23A1F1C–13G  
IMSH4GP23A1F1C–13H  
4 GByte  
×72  
4 GByte  
×72  
4 Ranks (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
4 Ranks (×x8)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
11  
00  
19  
0B  
52  
01  
08  
0C  
00  
7E  
00  
60  
78  
60  
30  
92  
05  
0B  
01  
02  
11  
00  
19  
0B  
52  
01  
08  
0C  
00  
74  
00  
6C  
78  
6C  
30  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
22  
23  
24  
25  
26  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
60  
11  
20  
6C  
11  
20  
8C  
70  
03  
3C  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 80  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
Time (tRTP.MIN), MSB  
Rev. 0.51, 2008-01  
51  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMSH4GP23A1F1C–13G  
IMSH4GP23A1F1C–13H  
4 GByte  
4 GByte  
×72  
×72  
4 Ranks (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
4 Ranks (×x8)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte# Description  
HEX  
28  
29  
30  
31  
Upper Nibble for tFAW  
00  
F0  
02  
81  
00  
10  
11  
07  
00  
00  
85  
51  
xx  
00  
F0  
02  
81  
00  
10  
11  
07  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
29  
0A  
49  
4D  
53  
48  
34  
47  
50  
32  
33  
41  
31  
46  
31  
43  
3F  
A3  
49  
4D  
53  
48  
34  
47  
50  
32  
33  
41  
31  
46  
31  
43  
Rev. 0.51, 2008-01  
52  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMSH4GP23A1F1C–13G  
IMSH4GP23A1F1C–13H  
4 GByte  
4 GByte  
×72  
×72  
4 Ranks (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
4 Ranks (×x8)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 15  
2D  
31  
33  
47  
1x  
xx  
2D  
31  
33  
48  
1x  
xx  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
Rev. 0.51, 2008-01  
53  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 25  
IMHH1GP03A1F1C-[08D/08E/10F/10G]  
Product Type  
Organization  
1 GByte  
1 GByte  
1 GByte  
1 GByte  
×72  
×72  
×72  
×72  
1 Rank (×x8) 1 Rank (×x8) 1 Rank (×x8) 1 Rank (×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
11  
00  
01  
0B  
52  
01  
08  
14  
00  
06  
00  
64  
78  
64  
50  
92  
05  
0B  
01  
02  
11  
00  
01  
0B  
52  
01  
08  
14  
00  
04  
00  
78  
78  
78  
50  
92  
05  
0B  
01  
02  
11  
00  
01  
0B  
52  
01  
08  
0F  
00  
1C  
00  
69  
78  
69  
3C  
92  
05  
0B  
01  
02  
11  
00  
01  
0B  
52  
01  
08  
0F  
00  
14  
00  
78  
78  
78  
3C  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
64  
11  
78  
11  
69  
11  
78  
11  
Rev. 0.51, 2008-01  
54  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
1 GByte  
1 GByte  
1 GByte  
1 GByte  
×72  
×72  
×72  
×72  
1 Rank (×x8) 1 Rank (×x8) 1 Rank (×x8) 1 Rank (×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
HEX  
22  
23  
24  
25  
26  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
2C  
2C  
A4  
70  
03  
3C  
2C  
95  
70  
03  
3C  
2C  
A4  
70  
03  
3C  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 90  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
3C  
3C  
Time (tRTP.MIN), MSB  
28  
29  
30  
31  
Upper Nibble for tFAW  
01  
40  
02  
81  
00  
10  
11  
00  
00  
00  
85  
51  
xx  
01  
40  
02  
81  
00  
10  
11  
00  
00  
00  
85  
51  
xx  
xx  
01  
2C  
02  
81  
00  
10  
11  
00  
00  
00  
85  
51  
xx  
01  
2C  
02  
81  
00  
10  
11  
00  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
xx  
xx  
126  
127  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
13  
11  
1C  
E0  
84  
B9  
E7  
4C  
Rev. 0.51, 2008-01  
55  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
1 GByte  
1 GByte  
1 GByte  
1 GByte  
×72  
×72  
×72  
×72  
1 Rank (×x8) 1 Rank (×x8) 1 Rank (×x8) 1 Rank (×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 1  
49  
4D  
48  
48  
31  
47  
50  
30  
33  
41  
31  
46  
31  
43  
2D  
30  
38  
44  
1x  
xx  
49  
4D  
48  
48  
31  
47  
50  
30  
33  
41  
31  
46  
31  
43  
2D  
30  
38  
45  
1x  
xx  
49  
4D  
48  
48  
31  
47  
50  
30  
33  
41  
31  
46  
31  
43  
2D  
31  
30  
46  
1x  
xx  
49  
4D  
48  
48  
31  
47  
50  
30  
33  
41  
31  
46  
31  
43  
2D  
31  
30  
47  
1x  
xx  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
00  
00  
Rev. 0.51, 2008-01  
56  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 26  
IMHH1GP03A1F1C-[13G/13H]  
Product Type  
Organization  
IMHH1GP03A1F1C–13G  
IMHH1GP03A1F1C–13H  
1 GByte  
×72  
1 GByte  
×72  
1 Rank (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
1 Rank (×x8)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
11  
00  
01  
0B  
52  
01  
08  
0C  
00  
7E  
00  
60  
78  
60  
30  
92  
05  
0B  
01  
02  
11  
00  
01  
0B  
52  
01  
08  
0C  
00  
74  
00  
6C  
78  
6C  
30  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
22  
23  
24  
25  
26  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
60  
11  
20  
6C  
11  
20  
8C  
70  
03  
3C  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 80  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
Time (tRTP.MIN), MSB  
Rev. 0.51, 2008-01  
57  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMHH1GP03A1F1C–13G  
IMHH1GP03A1F1C–13H  
1 GByte  
1 GByte  
×72  
×72  
1 Rank (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
1 Rank (×x8)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte# Description  
HEX  
28  
29  
30  
31  
Upper Nibble for tFAW  
00  
F0  
02  
81  
00  
10  
11  
00  
00  
00  
85  
51  
xx  
00  
F0  
02  
81  
00  
10  
11  
00  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
40  
36  
49  
4D  
48  
48  
31  
47  
50  
30  
33  
41  
31  
46  
31  
43  
B7  
9E  
49  
4D  
48  
48  
31  
47  
50  
30  
33  
41  
31  
46  
31  
43  
Rev. 0.51, 2008-01  
58  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMHH1GP03A1F1C–13G  
IMHH1GP03A1F1C–13H  
1 GByte  
1 GByte  
×72  
×72  
1 Rank (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
1 Rank (×x8)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 15  
2D  
31  
33  
47  
2x  
xx  
2D  
31  
33  
48  
2x  
xx  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
Rev. 0.51, 2008-01  
59  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 27  
IMHH2GP02A1F1C-[08D/08E/10F/10G]  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
1 Rank (×x4) 1 Rank (×x4) 1 Rank (×x4) 1 Rank (×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
12  
00  
00  
0B  
52  
01  
08  
14  
00  
06  
00  
64  
78  
64  
50  
92  
05  
0B  
01  
02  
12  
00  
00  
0B  
52  
01  
08  
14  
00  
04  
00  
78  
78  
78  
50  
92  
05  
0B  
01  
02  
12  
00  
00  
0B  
52  
01  
08  
0F  
00  
1C  
00  
69  
78  
69  
3C  
92  
05  
0B  
01  
02  
12  
00  
00  
0B  
52  
01  
08  
0F  
00  
14  
00  
78  
78  
78  
3C  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
64  
11  
78  
11  
69  
11  
78  
11  
Rev. 0.51, 2008-01  
60  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
1 Rank (×x4) 1 Rank (×x4) 1 Rank (×x4) 1 Rank (×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
HEX  
22  
23  
24  
25  
26  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
2C  
2C  
A4  
70  
03  
3C  
2C  
95  
70  
03  
3C  
2C  
A4  
70  
03  
3C  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 90  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
3C  
3C  
Time (tRTP.MIN), MSB  
28  
29  
30  
31  
Upper Nibble for tFAW  
01  
40  
02  
81  
00  
10  
11  
02  
00  
00  
85  
51  
xx  
01  
40  
02  
81  
00  
10  
11  
02  
00  
00  
85  
51  
xx  
xx  
01  
2C  
02  
81  
00  
10  
11  
02  
00  
00  
85  
51  
xx  
01  
2C  
02  
81  
00  
10  
11  
02  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
xx  
xx  
126  
127  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
57  
00  
58  
F1  
C0  
A8  
A3  
5D  
Rev. 0.51, 2008-01  
61  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
1 Rank (×x4) 1 Rank (×x4) 1 Rank (×x4) 1 Rank (×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 1  
49  
4D  
48  
48  
32  
47  
50  
30  
32  
41  
31  
46  
31  
43  
2D  
30  
38  
44  
1x  
xx  
49  
4D  
48  
48  
32  
47  
50  
30  
32  
41  
31  
46  
31  
43  
2D  
30  
38  
45  
1x  
xx  
49  
4D  
48  
48  
32  
47  
50  
30  
32  
41  
31  
46  
31  
43  
2D  
31  
30  
46  
1x  
xx  
49  
4D  
48  
48  
32  
47  
50  
30  
32  
41  
31  
46  
31  
43  
2D  
31  
30  
47  
1x  
xx  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
00  
00  
Rev. 0.51, 2008-01  
62  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 28  
IMHH2GP02A1F1C-[13G/13H]  
Product Type  
Organization  
IMHH2GP02A1F1C–13G  
IMHH2GP02A1F1C–13H  
2 GByte  
×72  
2 GByte  
×72  
1 Rank (×x4)  
PC3–10600P–8  
Rev. 0.5  
HEX  
1 Rank (×x4)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
12  
00  
00  
0B  
52  
01  
08  
0C  
00  
7E  
00  
60  
78  
60  
30  
92  
05  
0B  
01  
02  
12  
00  
00  
0B  
52  
01  
08  
0C  
00  
74  
00  
6C  
78  
6C  
30  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
22  
23  
24  
25  
26  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
60  
11  
20  
6C  
11  
20  
8C  
70  
03  
3C  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 80  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
Time (tRTP.MIN), MSB  
Rev. 0.51, 2008-01  
63  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMHH2GP02A1F1C–13G  
IMHH2GP02A1F1C–13H  
2 GByte  
2 GByte  
×72  
×72  
1 Rank (×x4)  
PC3–10600P–8  
Rev. 0.5  
HEX  
1 Rank (×x4)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte# Description  
HEX  
28  
29  
30  
31  
Upper Nibble for tFAW  
00  
F0  
02  
81  
00  
10  
11  
02  
00  
00  
85  
51  
xx  
00  
F0  
02  
81  
00  
10  
11  
02  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
04  
27  
49  
4D  
48  
48  
32  
47  
50  
30  
32  
41  
31  
46  
31  
43  
F3  
8F  
49  
4D  
48  
48  
32  
47  
50  
30  
32  
41  
31  
46  
31  
43  
Rev. 0.51, 2008-01  
64  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMHH2GP02A1F1C–13G  
IMHH2GP02A1F1C–13H  
2 GByte  
2 GByte  
×72  
×72  
1 Rank (×x4)  
PC3–10600P–8  
Rev. 0.5  
HEX  
1 Rank (×x4)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 15  
2D  
31  
33  
47  
2x  
xx  
2D  
31  
33  
48  
2x  
xx  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
Rev. 0.51, 2008-01  
65  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 29  
IMHH2GP13A1F1C-[08D/08E/10F/10G]  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
11  
00  
09  
0B  
52  
01  
08  
14  
00  
06  
00  
64  
78  
64  
50  
92  
05  
0B  
01  
02  
11  
00  
09  
0B  
52  
01  
08  
14  
00  
04  
00  
78  
78  
78  
50  
92  
05  
0B  
01  
02  
11  
00  
09  
0B  
52  
01  
08  
0F  
00  
1C  
00  
69  
78  
69  
3C  
92  
05  
0B  
01  
02  
11  
00  
09  
0B  
52  
01  
08  
0F  
00  
14  
00  
78  
78  
78  
3C  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
64  
11  
78  
11  
69  
11  
78  
11  
Rev. 0.51, 2008-01  
66  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
HEX  
22  
23  
24  
25  
26  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
2C  
2C  
A4  
70  
03  
3C  
2C  
95  
70  
03  
3C  
2C  
A4  
70  
03  
3C  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 90  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
3C  
3C  
Time (tRTP.MIN), MSB  
28  
29  
30  
31  
Upper Nibble for tFAW  
01  
40  
02  
81  
00  
10  
11  
01  
00  
00  
85  
51  
xx  
01  
40  
02  
81  
00  
10  
11  
01  
00  
00  
85  
51  
xx  
xx  
01  
2C  
02  
81  
00  
10  
11  
01  
00  
00  
85  
51  
xx  
01  
2C  
02  
81  
00  
10  
11  
01  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
xx  
xx  
126  
Cyclical Redundancy Code LSB  
0A  
05  
9D  
FE  
Rev. 0.51, 2008-01  
67  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
08  
49  
4D  
48  
48  
32  
47  
50  
31  
33  
41  
31  
46  
31  
43  
2D  
30  
38  
44  
1x  
xx  
F9  
49  
4D  
48  
48  
32  
47  
50  
31  
33  
41  
31  
46  
31  
43  
2D  
30  
38  
45  
1x  
xx  
A0  
49  
4D  
48  
48  
32  
47  
50  
31  
33  
41  
31  
46  
31  
43  
2D  
31  
30  
46  
1x  
xx  
55  
49  
4D  
48  
48  
32  
47  
50  
31  
33  
41  
31  
46  
31  
43  
2D  
31  
30  
47  
1x  
xx  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
85  
51  
85  
51  
85  
51  
85  
51  
Rev. 0.51, 2008-01  
68  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
2 GByte  
2 GByte  
2 GByte  
2 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
Rev. 0.5  
Rev. 0.5  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
150 -  
175  
Manufactures’s Specific Data  
00  
00  
00  
00  
176 -  
255  
Blank for Customer Use  
00  
00  
00  
00  
Rev. 0.51, 2008-01  
69  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 30  
IMHH2GP13A1F1C-[13G/13H]  
Product Type  
Organization  
IMHH2GP13A1F1C–13G  
IMHH2GP13A1F1C–13H  
2 GByte  
×72  
2 GByte  
×72  
2 Ranks (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
2 Ranks (×x8)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
11  
00  
09  
0B  
52  
01  
08  
0C  
00  
7E  
00  
60  
78  
60  
30  
92  
05  
0B  
01  
02  
11  
00  
09  
0B  
52  
01  
08  
0C  
00  
74  
00  
6C  
78  
6C  
30  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
22  
23  
24  
25  
26  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
60  
11  
20  
6C  
11  
20  
8C  
70  
03  
3C  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 80  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
Time (tRTP.MIN), MSB  
Rev. 0.51, 2008-01  
70  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMHH2GP13A1F1C–13G  
IMHH2GP13A1F1C–13H  
2 GByte  
2 GByte  
×72  
×72  
2 Ranks (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
2 Ranks (×x8)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte# Description  
HEX  
28  
29  
30  
31  
Upper Nibble for tFAW  
00  
F0  
02  
81  
00  
10  
11  
01  
00  
00  
85  
51  
xx  
00  
F0  
02  
81  
00  
10  
11  
01  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
59  
2F  
49  
4D  
48  
48  
32  
47  
50  
31  
33  
41  
31  
46  
31  
43  
AE  
87  
49  
4D  
48  
48  
32  
47  
50  
31  
33  
41  
31  
46  
31  
43  
Rev. 0.51, 2008-01  
71  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMHH2GP13A1F1C–13G  
IMHH2GP13A1F1C–13H  
2 GByte  
2 GByte  
×72  
×72  
2 Ranks (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
2 Ranks (×x8)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 15  
2D  
31  
33  
47  
2x  
xx  
2D  
31  
33  
48  
2x  
xx  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
Rev. 0.51, 2008-01  
72  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 31  
IMHH4GP12A1F1C-[08D/08E/10F/10G]  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x4)  
(×x4)  
(×x4)  
(×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
12  
00  
08  
0B  
52  
01  
08  
14  
00  
06  
00  
64  
78  
64  
50  
92  
05  
0B  
01  
02  
12  
00  
08  
0B  
52  
01  
08  
14  
00  
04  
00  
78  
78  
78  
50  
92  
05  
0B  
01  
02  
12  
00  
08  
0B  
52  
01  
08  
0F  
00  
1C  
00  
69  
78  
69  
3C  
92  
05  
0B  
01  
02  
12  
00  
08  
0B  
52  
01  
08  
0F  
00  
14  
00  
78  
78  
78  
3C  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
64  
11  
78  
11  
69  
11  
78  
11  
Rev. 0.51, 2008-01  
73  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x4)  
(×x4)  
(×x4)  
(×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
HEX  
22  
23  
24  
25  
26  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
2C  
2C  
A4  
70  
03  
3C  
2C  
95  
70  
03  
3C  
2C  
A4  
70  
03  
3C  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 90  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
3C  
3C  
Time (tRTP.MIN), MSB  
28  
29  
30  
31  
Upper Nibble for tFAW  
01  
40  
02  
81  
00  
10  
11  
04  
00  
00  
85  
51  
xx  
01  
40  
02  
81  
00  
10  
11  
04  
00  
00  
85  
51  
xx  
xx  
01  
2C  
02  
81  
00  
10  
11  
04  
00  
00  
85  
51  
xx  
01  
2C  
02  
81  
00  
10  
11  
04  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
xx  
xx  
126  
Cyclical Redundancy Code LSB  
D9  
D6  
4E  
2D  
Rev. 0.51, 2008-01  
74  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x4)  
(×x4)  
(×x4)  
(×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
83  
49  
4D  
48  
48  
34  
47  
50  
31  
32  
41  
31  
46  
31  
43  
2D  
30  
38  
44  
1x  
xx  
72  
49  
4D  
48  
48  
34  
47  
50  
31  
32  
41  
31  
46  
31  
43  
2D  
30  
38  
45  
1x  
xx  
2B  
49  
4D  
48  
48  
34  
47  
50  
31  
32  
41  
31  
46  
31  
43  
2D  
31  
30  
46  
1x  
xx  
DE  
49  
4D  
48  
48  
34  
47  
50  
31  
32  
41  
31  
46  
31  
43  
2D  
31  
30  
47  
1x  
xx  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
85  
51  
85  
51  
85  
51  
85  
51  
Rev. 0.51, 2008-01  
75  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
2 Ranks  
2 Ranks  
2 Ranks  
2 Ranks  
(×x4)  
(×x4)  
(×x4)  
(×x4)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
Rev. 0.5  
Rev. 0.5  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
150 -  
175  
Manufactures’s Specific Data  
00  
00  
00  
00  
176 -  
255  
Blank for Customer Use  
00  
00  
00  
00  
Rev. 0.51, 2008-01  
76  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 32  
IMHH4GP12A1F1C-[13G/13H]  
Product Type  
Organization  
IMHH4GP12A1F1C–13G  
IMHH4GP12A1F1C–13H  
4 GByte  
×72  
4 GByte  
×72  
2 Ranks (×x4)  
PC3–10600P–8  
Rev. 0.5  
HEX  
2 Ranks (×x4)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
12  
00  
08  
0B  
52  
01  
08  
0C  
00  
7E  
00  
60  
78  
60  
30  
92  
05  
0B  
01  
02  
12  
00  
08  
0B  
52  
01  
08  
0C  
00  
74  
00  
6C  
78  
6C  
30  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
22  
23  
24  
25  
26  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
60  
11  
20  
6C  
11  
20  
8C  
70  
03  
3C  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 80  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
Time (tRTP.MIN), MSB  
Rev. 0.51, 2008-01  
77  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMHH4GP12A1F1C–13G  
IMHH4GP12A1F1C–13H  
4 GByte  
4 GByte  
×72  
×72  
2 Ranks (×x4)  
PC3–10600P–8  
Rev. 0.5  
HEX  
2 Ranks (×x4)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte# Description  
HEX  
28  
29  
30  
31  
Upper Nibble for tFAW  
00  
F0  
02  
81  
00  
10  
11  
04  
00  
00  
85  
51  
xx  
00  
F0  
02  
81  
00  
10  
11  
04  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
8A  
A4  
49  
4D  
48  
48  
34  
47  
50  
31  
32  
41  
31  
46  
31  
43  
7D  
0C  
49  
4D  
48  
48  
34  
47  
50  
31  
32  
41  
31  
46  
31  
43  
Rev. 0.51, 2008-01  
78  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMHH4GP12A1F1C–13G  
IMHH4GP12A1F1C–13H  
4 GByte  
4 GByte  
×72  
×72  
2 Ranks (×x4)  
PC3–10600P–8  
Rev. 0.5  
HEX  
2 Ranks (×x4)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 15  
2D  
31  
33  
47  
2x  
xx  
2D  
31  
33  
48  
2x  
xx  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
Rev. 0.51, 2008-01  
79  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 33  
IMHH4GP23A1F1C-[08D/08E/10F/10G]  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
4 Ranks  
4 Ranks  
4 Ranks  
4 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
11  
00  
19  
0B  
52  
01  
08  
14  
00  
06  
00  
64  
78  
64  
50  
92  
05  
0B  
01  
02  
11  
00  
19  
0B  
52  
01  
08  
14  
00  
04  
00  
78  
78  
78  
50  
92  
05  
0B  
01  
02  
11  
00  
19  
0B  
52  
01  
08  
0F  
00  
1C  
00  
69  
78  
69  
3C  
92  
05  
0B  
01  
02  
11  
00  
19  
0B  
52  
01  
08  
0F  
00  
14  
00  
78  
78  
78  
3C  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
64  
11  
78  
11  
69  
11  
78  
11  
Rev. 0.51, 2008-01  
80  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
4 Ranks  
4 Ranks  
4 Ranks  
4 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
HEX  
22  
23  
24  
25  
26  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
2C  
2C  
A4  
70  
03  
3C  
2C  
95  
70  
03  
3C  
2C  
A4  
70  
03  
3C  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 90  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
3C  
3C  
Time (tRTP.MIN), MSB  
28  
29  
30  
31  
Upper Nibble for tFAW  
01  
40  
02  
81  
00  
10  
11  
07  
00  
00  
85  
51  
xx  
01  
40  
02  
81  
00  
10  
11  
07  
00  
00  
85  
51  
xx  
xx  
01  
2C  
02  
81  
00  
10  
11  
07  
00  
00  
85  
51  
xx  
01  
2C  
02  
81  
00  
10  
11  
07  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
xx  
xx  
126  
Cyclical Redundancy Code LSB  
EF  
E0  
78  
1B  
Rev. 0.51, 2008-01  
81  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
4 Ranks  
4 Ranks  
4 Ranks  
4 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Rev. 0.5  
HEX  
Byte#  
Description  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
31  
49  
4D  
48  
48  
34  
47  
50  
32  
33  
41  
31  
46  
31  
43  
2D  
30  
38  
44  
1x  
xx  
C0  
49  
4D  
48  
48  
34  
47  
50  
32  
33  
41  
31  
46  
31  
43  
2D  
30  
38  
45  
1x  
xx  
99  
49  
4D  
48  
48  
34  
47  
50  
32  
33  
41  
31  
46  
31  
43  
2D  
31  
30  
46  
1x  
xx  
6C  
49  
4D  
48  
48  
34  
47  
50  
32  
33  
41  
31  
46  
31  
43  
2D  
31  
30  
47  
1x  
xx  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
85  
51  
85  
51  
85  
51  
85  
51  
Rev. 0.51, 2008-01  
82  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
4 GByte  
4 GByte  
4 GByte  
4 GByte  
×72  
×72  
×72  
×72  
4 Ranks  
4 Ranks  
4 Ranks  
4 Ranks  
(×x8)  
(×x8)  
(×x8)  
(×x8)  
Label Code  
PC3–  
PC3–  
PC3–  
PC3–  
6400P–5  
6400P–6  
8500P–7  
8500P–8  
Industry Standard SPD Revision  
Rev. 0.5  
Rev. 0.5  
Rev. 0.5  
Rev. 0.5  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
150 -  
175  
Manufactures’s Specific Data  
00  
00  
00  
00  
176 -  
255  
Blank for Customer Use  
00  
00  
00  
00  
Rev. 0.51, 2008-01  
83  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
TABLE 34  
IMHH4GP23A1F1C-[13G/13H]  
Product Type  
Organization  
IMHH4GP23A1F1C–13G  
IMHH4GP23A1F1C–13H  
4 GByte  
×72  
4 GByte  
×72  
4 Ranks (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
4 Ranks (×x8)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
0
# of SPD bytes utilized / # of bytes in SPD / CRC  
SPD Revision  
92  
05  
0B  
01  
02  
11  
00  
19  
0B  
52  
01  
08  
0C  
00  
7E  
00  
60  
78  
60  
30  
92  
05  
0B  
01  
02  
11  
00  
19  
0B  
52  
01  
08  
0C  
00  
74  
00  
6C  
78  
6C  
30  
1
2
SDRAM technology key byte  
DIMM module type  
3
4
SDRAM density and banks  
SDRAM addressing  
5
6
Module physical attributes  
Module organization  
7
8
Module memory bus width  
Fine time base (FTB) dividend and divisor  
Medium time base (MTB) dividend  
Medium time base (MTB) divisor  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Minimum SDRAM cycle time (tCK.MIN  
Reserved  
)
CAS Latencies Supported - LSB  
CAS Latencies Supported - MSB  
Minimum CAS Latency Time (tCK.MIN  
Minimum Write Recovery Time (tWR.MIN  
Minimum RAS# toCAS# Delay Time (tRCD.MIN  
Minimum Row Active to Row Active Delay Time  
(tRRD.MIN  
)
)
)
)
20  
21  
22  
23  
24  
25  
26  
Minimum Row PrechargeTime (tRP.MIN  
Upper Nibbles for tRAS and tRC  
)
60  
11  
20  
6C  
11  
20  
8C  
70  
03  
3C  
Minimum Active to Precharge Time (tRAS.MIN), LSB  
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 80  
Minimum Refresh Recovery Time (tRFC.MIN), LSB  
Minimum Refresh Recovery Time (tRFC.MIN), MSB  
70  
03  
Minimum Internal Write to Read Command Delay Time 3C  
(tWTR.MIN  
)
27  
Minimum Internal Read to Precharge Command Delay 3C  
3C  
Time (tRTP.MIN), MSB  
Rev. 0.51, 2008-01  
84  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMHH4GP23A1F1C–13G  
IMHH4GP23A1F1C–13H  
4 GByte  
4 GByte  
×72  
×72  
4 Ranks (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
4 Ranks (×x8)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte# Description  
HEX  
28  
29  
30  
31  
Upper Nibble for tFAW  
00  
F0  
02  
81  
00  
10  
11  
07  
00  
00  
85  
51  
xx  
00  
F0  
02  
81  
00  
10  
11  
07  
00  
00  
85  
51  
xx  
Minimum Four Activate Window Delay Time (tFAW.MIN  
SDRAM Output Drivers supported  
SDRAM Refresh Options  
)
32 - 59 Reserved  
60  
61  
62  
63  
Module Nominal Height  
Module Maximum Thickness  
Raw Card used  
Address Mapping from Edge Connector to DRAM  
64 - 116 Reserved  
117  
118  
119  
DIMM Manufacturer’s ID Code LSB  
DIMM Manufacturer’s ID Code MSB  
Module Manufacturing Location  
Module Manufacturing Date  
120 -  
121  
xx  
xx  
122 -  
125  
Module Serial Number  
xx  
xx  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
Cyclical Redundancy Code LSB  
Cyclical Redundancy Code MSB  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
BC  
16  
49  
4D  
48  
48  
34  
47  
50  
32  
33  
41  
31  
46  
31  
43  
4B  
BE  
49  
4D  
48  
48  
34  
47  
50  
32  
33  
41  
31  
46  
31  
43  
Rev. 0.51, 2008-01  
85  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Product Type  
Organization  
IMHH4GP23A1F1C–13G  
IMHH4GP23A1F1C–13H  
4 GByte  
4 GByte  
×72  
×72  
4 Ranks (×x8)  
PC3–10600P–8  
Rev. 0.5  
HEX  
4 Ranks (×x8)  
PC3–10600P–9  
Rev. 0.5  
Label Code  
Industry Standard SPD Revision  
Byte#  
Description  
HEX  
142  
143  
144  
145  
146  
147  
148  
149  
Product Type, Char 15  
2D  
31  
33  
47  
2x  
xx  
2D  
31  
33  
48  
2x  
xx  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code, LSB  
Module Revision Code, MSB  
DRAM Manufacturer’s ID Code, LSB  
DRAM Manufacturer’s ID Code, MSB  
Manufactures’s Specific Data  
85  
51  
00  
85  
51  
00  
150 -  
175  
176 -  
255  
Blank for Customer Use  
00  
00  
Rev. 0.51, 2008-01  
86  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
6
Package Outline Diagrams  
FIGURE 2  
Package Outline LG-DIM-240-091 R/C A  
ꢍꢎꢎꢏꢎꢐ  
'ꢋꢏꢍ  
ꢍꢉꢒꢏꢌꢐ  
ꢍ
ꢍꢉꢋ  
'ꢋꢏꢍ  
'ꢋꢏꢍ  
ꢍꢉ  
ꢉꢏꢐ  
'ꢋꢏꢍ  
ꢍꢏꢉꢑ  
'ꢋꢏꢍ  
ꢐ
'ꢋꢏꢍ  
'ꢋꢏꢍ  
ꢑꢍ  
ꢊꢑ  
'ꢋꢏꢍ  
ꢍꢏꢐ  
ꢍꢉꢍ  
ꢉꢊꢋ  
ꢉꢏꢍꢞꢋꢏꢉꢐ  
ꢆꢓ%ꢔꢕꢖꢗ"ꢘꢗꢙ"!%ꢔꢙ%$  
ꢆ#ꢔ&ꢕ!ꢚꢗꢔꢙꢙ"#ꢛꢕ!ꢚꢗ%"ꢗꢇꢜꢂꢗꢒꢋꢍꢐ  
ꢝꢓ!ꢓ#ꢔꢖꢗ%"ꢖꢓ#ꢔ!ꢙꢓ$ꢗ'ꢋꢏꢍꢐ  
ꢆꢕ ꢓ!$ꢕ"!$ꢗꢕ!ꢗ    
ꢍ
'ꢋꢏꢉ  
ꢋꢏꢒ  
ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢃꢃꢃꢃꢅꢉꢊꢋꢅꢋꢌꢍ  
Note: SDRAM component outlines are symbolic representation of the device placement. For actual SDRAM outline details  
please refer to SDRAM Component Data Sheet.  
Rev. 0.51, 2008-01  
87  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
FIGURE 3  
Package Outline LG-DIM-240-092 R/C B  
ꢏꢎꢎꢐꢎꢑ  
+ꢌꢐꢏ  
ꢏꢊꢓꢐꢍꢑ  
+ꢌꢐꢏ  
ꢏꢐꢊ  
+ꢌꢐꢏ  
ꢏꢌꢎꢐꢊꢑ  
ꢋꢗꢉꢚꢝꢐ  
+ꢌꢐꢏ  
+ꢌꢐꢏ  
ꢋꢋꢐꢋꢑ  
ꢎꢌꢐꢏ  
ꢏ
ꢏꢊꢌ  
ꢊꢋꢌ  
+ꢌꢐꢏ  
+ꢌꢐꢏ  
ꢏꢊ  
ꢊꢐꢑ  
ꢜ
ꢊꢐꢑ  
+ꢌꢐꢏ  
ꢑ
+ꢌꢐꢏ  
ꢏꢐꢊꢒ  
+ꢌꢐꢏ  
+ꢌꢐꢏ  
ꢒꢏ  
ꢋꢒ  
ꢚ
+ꢌꢐꢏ  
ꢏꢐꢑ  
ꢏꢊꢏ  
+ꢌꢐꢏ  
ꢊꢐꢏ  
ꢇꢔ(ꢕ!"ꢗ%ꢖꢗꢗ%$(ꢕꢗ('  
ꢇ&ꢕ)!$ ꢗꢕꢗꢗ%&ꢘ!$ ꢗ(%ꢗꢈꢙꢂꢗꢓꢌꢏꢑ  
ꢅꢔ$ꢔ&ꢕ"ꢗ(%"ꢔ&ꢕ$ꢗꢔ'ꢗ+ꢌꢐꢏꢑ  
ꢇ!#ꢔ$'!%$'ꢗ!$ꢗ##  
ꢏ
+ꢌꢐꢌꢑ  
ꢌꢐꢓ  
*ꢌꢐꢏ ꢚ ꢛ ꢜ  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢃꢃꢃꢃꢆꢊꢋꢌꢆꢌꢍꢊ  
Note: SDRAM component outlines are symbolic representation of the device placement. For actual SDRAM outline details  
please refer to SDRAM Component Data Sheet.  
Rev. 0.51, 2008-01  
88  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
FIGURE 4  
Package Outline LG-DIM-240-093 R/C C  
ꢍꢎꢎꢏꢎꢐ  
'ꢋꢏꢍ  
ꢍꢉꢒꢏꢌꢐ  
ꢍ
ꢍꢉꢋ  
'ꢋꢏꢍ  
'ꢋꢏꢍ  
ꢍꢉ  
ꢉꢏꢐ  
'ꢋꢏꢍ  
ꢍꢏꢉꢑ  
'ꢋꢏꢍ  
ꢐ
'ꢋꢏꢍ  
'ꢋꢏꢍ  
ꢑꢍ  
ꢊꢑ  
'ꢋꢏꢍ  
ꢍꢏꢐ  
ꢍꢉꢍ  
ꢉꢊꢋ  
ꢉꢏꢍꢞꢋꢏꢉꢐ  
ꢆꢓ%ꢔꢕꢖꢗ"ꢘꢗꢙ"!%ꢔꢙ%$  
ꢆ#ꢔ&ꢕ!ꢚꢗꢔꢙꢙ"#ꢛꢕ!ꢚꢗ%"ꢗꢇꢜꢂꢗꢒꢋꢍꢐ  
ꢝꢓ!ꢓ#ꢔꢖꢗ%"ꢖꢓ#ꢔ!ꢙꢓ$ꢗ'ꢋꢏꢍꢐ  
ꢆꢕ ꢓ!$ꢕ"!$ꢗꢕ!ꢗ    
ꢍ
'ꢋꢏꢉ  
ꢋꢏꢒ  
ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢃꢃꢃꢃꢅꢉꢊꢋꢅꢋꢌꢎ  
Note: SDRAM component outlines are symbolic representation of the device placement. For actual SDRAM outline details  
please refer to SDRAM Component Data Sheet.  
Rev. 0.51, 2008-01  
89  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
FIGURE 5  
Package Outline LG-DIM-240-097 R/C E  
ꢆꢇꢇꢈꢇꢉ  
›ꢃꢈꢆ  
ꢆꢁꢊꢈꢄꢉ  
ꢁX ꢋꢆꢈꢉꢌ  
ꢇꢈꢅ -!8ꢈ  
›ꢃꢈꢆ  
›ꢃꢈꢆ  
ꢇꢂ  
ꢇꢂ  
ꢆ
ꢆꢁꢃ  
ꢁꢂꢃ  
ꢁꢈꢉ  
#
ꢁꢈꢉ  
ꢉ
›ꢃꢈꢆ  
ꢂꢅ  
ꢅꢆ  
ꢆꢈꢁꢅ  
!
"
›ꢃꢈꢆ  
ꢆꢈꢉ  
,
ꢃꢈꢆ  
# " &  
ꢆꢁꢆ  
ꢂX ꢋꢁꢈꢆꢌ  
$ETAIL OF CONTACTS  
$RAWING ACCORDING TO )3/ ꢊꢃꢆꢉ  
'ENERAL TOLERANCES ›ꢃꢈꢆꢉ  
$IMENSIONS IN MM  
ꢆ
›ꢃꢈꢃꢉ  
ꢃꢈꢊ  
,
,
ꢃꢈꢆꢃ  
ꢃꢈꢃꢉ  
# " !  
#
&0/?,'ꢀ$)-????ꢀꢁꢂꢃꢀꢃꢄꢅ  
Note: SDRAM component outlines are symbolic representation of the device placement. For actual SDRAM outline details  
please refer to SDRAM Component Data Sheet.  
Rev. 0.51, 2008-01  
90  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
FIGURE 6  
Package Outline LG-DIM-240-098 R/C H  
7%'  
Rev. 0.51, 2008-01  
91  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
7
Product Type Nomenclature  
For reference the applicable Qimonda DDR3 DIMM module nomenclature is listed in this chapter.  
TABLE 35  
Example: DDR3 1GByte Registered Module  
Field Number  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
Qimonda Part Number  
I
M
S
H
1G  
P
0
3
A1  
F1  
C
–
08  
E
TABLE 36  
DDR3 DIMM Nomenclature  
Field Description  
Value  
Coding  
1
2
3
Qimonda Identifier  
I
Qimonda DIMM modules  
Module  
Product Group  
M
S
Power or Application  
Standard  
L
Low Power  
H
H
51  
1G  
2G  
4G  
U
E
Heat Spreader  
DDR3  
4
5
Product Family  
Density  
512 MBytes  
1024 MBytes  
2048 MBytes  
4096 MBytes  
6
Module Type / ECC Support  
240 pin unbuffered DIMMs - Non-ECC  
240 pin unbuffered DIMMs - ECC  
204 pin Small Outline DIMMs - Non-ECC  
240 pin Registered DIMMs - ECC  
240 pin Registered DIMMs with Parity Bit - ECC  
One Rank of SDRAMs  
S
R
P
7
8
Number of Ranks  
0
1
Two Ranks of SDRAMs  
2
Four Ranks of SDRAMs  
×4 components (22)  
DRAM Device Number of IOs  
2
3
×8 components (23)  
4
×16 components (24)  
9
Die Revision  
Package  
A1  
F1  
F2  
C
–
First  
10  
Planar FBGA, lead- and halogen-free  
Dual Die FBGA, lead- and halogen-free  
Commercial (0 °C - 95 °C)  
RFU  
9
Temperature Range  
10  
Reserved For Future Use  
Rev. 0.51, 2008-01  
92  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Field Description  
Value  
Coding  
11  
Band Width  
08  
10  
13  
16  
D
PC3–6400, 6.4 GB/s, tCK = 2.5 ns, fCK =400 MHz  
PC3–8500, 8.5 GB/s, tCK = 1.875 ns, fCK =533 MHz  
PC3–10600, 10,66 GB/s, tCK = 1.5 ns, fCK =667 MHz  
PC3–12800, 12,8 GB/s, tCK = 1.25 ns, fCK =800 MHz  
CL–RCD–RP = 5–5–5  
12  
Latencies  
E
CL–RCD–RP = 6–6–6  
F
CL–RCD–RP = 7–7–7  
G
H
CL–RCD–RP = 8–8–8  
CL–RCD–RP = 9–9–9  
J
CL–RCD–RP = 10–10–10  
Rev. 0.51, 2008-01  
93  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
DDR3 Registered DIMM  
IM[S/H]H[1G/2G/4G]PxxA1F1C  
Contents  
1
1.1  
1.2  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
2.1  
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3
3.1  
3.2  
Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
4
Speed Bins and Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
4.1  
Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
5
6
7
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Package Outline Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87  
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92  
Rev. 0.51, 2008-01  
94  
12122007-WJ2L-RGDP  
Advance Internet Data Sheet  
Edition 2008-01  
Published by Qimonda AG  
Gustav-Heinemann-Ring 212  
D-81739 München, Germany  
© Qimonda AG 2008.  
All Rights Reserved.  
Legal Disclaimer  
THE INFORMATION GIVEN IN THIS INTERNET DATA SHEET SHALL IN NO EVENT BE REGARDED AS A GUARANTEE  
OF CONDITIONS OR CHARACTERISTICS. WITH RESPECT TO ANY EXAMPLES OR HINTS GIVEN HEREIN, ANY  
TYPICAL VALUES STATED HEREIN AND/OR ANY INFORMATION REGARDING THE APPLICATION OF THE DEVICE,  
QIMONDA HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND, INCLUDING WITHOUT  
LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.  
Information  
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.  
Warnings  
Due to technical requirements components may contain dangerous substances. For information on the types in question please  
contact your nearest Qimonda Office.  
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a  
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect  
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human  
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health  
of the user or other persons may be endangered.  
www.qimonda.com  

相关型号：

IMHH2GP13A1F1C-10F

 DDR DRAM Module, 256MX72, CMOS, GREEN, DIMM-240
QIMONDA

IMHH2GP13A1F1C-10G

 DDR DRAM Module, 256MX72, CMOS, GREEN, DIMM-240
QIMONDA

IMHH2GP13A1F1C-13H

 DDR DRAM Module, 256MX72, CMOS, GREEN, DIMM-240
QIMONDA

IMHH4GP12A1F1C-08E

 DDR DRAM Module, 512MX72, CMOS, GREEN, DIMM-240
QIMONDA

IMHH4GP12A1F1C-10F

 DDR DRAM Module, 512MX72, CMOS, GREEN, DIMM-240
QIMONDA

IMHH4GP12A1F1C-10G

 DDR DRAM Module, 512MX72, CMOS, GREEN, DIMM-240
QIMONDA

IMHH4GP12A1F1C-13G

 DDR DRAM Module, 512MX72, CMOS, GREEN, DIMM-240
QIMONDA

IMHH4GP12A1F1C-13H

 DDR DRAM Module, 512MX72, CMOS, GREEN, DIMM-240
QIMONDA

IMHH4GP12A1F2C-10F

 DDR DRAM Module, 512MX72, CMOS, GREEN, RDIMM-240
QIMONDA

IMHH4GP12A1F2C-10G

 DDR DRAM Module, 512MX72, CMOS, GREEN, RDIMM-240
QIMONDA

IMHH4GP12A1F2C-13H

 DDR DRAM Module, 512MX72, CMOS, GREEN, RDIMM-240
QIMONDA

IMHH4GP23A1F1C-08D

 DDR DRAM Module, 512MX72, CMOS, GREEN, DIMM-240
QIMONDA
©2020 ICPDF网 联系我们和版权申明