DM2200T1-12 [RAMTRON]
Cache DRAM, 4MX1, 30ns, MOS, PDSO44, 0.300 INCH, PLASTIC, TSOP2-11;
| 型号： | DM2200T1-12 |
| 厂家： | 
RAMTRON INTERNATIONAL CORPORATION |
| 描述： | Cache DRAM, 4MX1, 30ns, MOS, PDSO44, 0.300 INCH, PLASTIC, TSOP2-11 动态存储器 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总18页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DM2200 EDRAM
4Mb x 1 Enhanced Dynamic RAM
Product Specification
Enhanced
Memory Systems Inc.
Features
■ 2Kbit SRAM Cache Memory for 12ns Random Reads Within a Page ■ Hidden Precharge and Refresh Cycles
■ Fast 4Mbit DRAM Array for 30ns Access to Any New Page
■ Write Posting Register for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
■ 256-byte Wide DRAM to SRAM Bus for 14.2 Gigabytes/Sec Cache
Fill
■ Extended 64ms Refresh Period for Low Standby Power
■ 300 Mil Plastic SOJ and TSOP-II Package Options
■ +5 and +3.3 Volt Power Supply Voltage Options
■ Low Power, Self Refresh Mode Option
■ Industrial Temperature Range Option
■ On-chip Cache Hit/Miss Comparators Maintain Cache Coherency
on Writes
Description
Architecture
The EDRAM architecture has a simple integrated SRAM cache
which allows it to operate much like a page mode or static column
DRAM.
The 4Mb Enhanced DRAM (EDRAM) combines raw speed with
innovative architecture to offer the optimum cost-performance solution
for high performance local or system main memory. In most high
speed applications, no-wait-state performance can be achieved without
secondary SRAM cache and without interleaving main memory banks at
system clock speeds through 50MHz. Two-way interleave will allow no-
wait-state operation at clock speeds greater than 100MHz without the
need of secondary SRAM cache. The EDRAM outperforms conventional
SRAM cache plus DRAM memory systems by minimizing processor wait
states for all possible bus events, not just cache hits. The combination
of data and address latching, 2K of fast on-chip SRAM cache, and
simplified on-chip cache control allows system level flexibility,
performance, and overall memory cost reduction not available with any
other high density memory component. Architectural similarity with
JEDEC DRAMs allows a single memory controller design to support
either slow JEDEC DRAMs or high speed EDRAMs. A system designed in
this manner can provide a simple upgrade path to higher system
performance.
The EDRAM’s SRAM cache is integrated into the DRAM array as
tightly coupled row registers. Memory reads always occur from the
cache row register. When the internal comparator detects a page hit,
only the SRAM is accessed and data is available in 12ns from column
address. When a page read miss is detected, the new DRAM row is
loaded into the cache and data is available at the output all within
30ns from row enable. Subsequent reads within the page (burst reads
or random reads) can continue at 12ns cycle time. Since reads occur
from the SRAM cache, the DRAM precharge can occur simultaneously
without degrading performance. The on-chip refresh counter with
independent refresh bus allows the EDRAM to be refreshed during
cache reads.
Memory writes are internally posted in 12ns and directed to the
DRAM array. During a write hit, the on-chip address comparator
activates a parallel write path to the SRAM cache to maintain
coherency. The EDRAM delivers 12ns cycle page mode memory
TSOP-II Pin
Configuration
SOJ Pin
Configuration
Functional Diagram
NC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS *
A
Column
Add
Latch
0-10
/CAL
A
0
2
V
SS
Column Decoder
NC
3
V
SS
Q
D
2048 X 1 Cache (Row Register)
A
1
4
Q
11 Bit
Comp
A
V
SS
1
2
3
4
5
6
7
28
27
26
25
0
NC
5
D
A
Q
A
3
6
NC
NC
NC
/G
V
1
Sense Amps
& Column Write Select
/G
A
4
7
A
3
D
I/O
Control
and
Data
Latches
NC
8
A
Last
Row
Read
Add
NC
NC
4
A
A
5
9
0-10
A
24
5
/RE
10
11
12
13
14
15
16
17
18
19
20
21
22
CC
/RE
23 /G
V
V
CC
Latch
CC
/S
V
V
CC
22
21
20
19
18
V
V
SS
CC
SS
Memory
Array
(2048 X 2048)
Row
Add
Latch
V
V
V
V
SS
8
SS
SS
SS
/WE
A
6
/WE
/S
A
6
9
/WE
/S
A
7
A
7
10
11
12
13
14
A
8
/F
A
8
/F
NC
NC
W/R
NC
/CAL
A
2
17 W/R
A
2
V
CC
A
9
A
NC
16
15
/CAL
0-9
V
SS
/F
W/R
/RE
Row Add
and
Refresh
Control
A
9
V
A
CC
10
Refresh
Counter
V
A
CC
10
V
NC
CC*
* Reserved for future use
© 1996 Enhanced Memory Systems Inc., 1850 Ramtron Drive, Colorado Springs, CO
Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced
80921
38-2108-001
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
writes. Memory writes do not affect the contents of the cache row clocked to latch the column address. In page mode, data valid
register except during a cache hit.
time is determined by either tAC or tCQV.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior performance over standard slow 4Mb DRAMs.
By eliminating the need for SRAMs and cache controllers, system
cost, board space, and power can all be reduced.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
and /F & /CAL high. The EDRAM compares the new row address to
the LRR address latch (an 11-bit latch loaded on each /RE active
read miss cycle). If the row address does not match the LRR, the
requested data is not in SRAM cache and a new row must be
fetched from the DRAM. The EDRAM will load the new row data
into the SRAM cache and update the LRR latch. The data at the
specified column address is available at the output pins at the
greater of times tRAC, tAC, and tGQV. It is possible to bring /RE high
after time tRE since the new row data is safely latched into SRAM
cache. This allows the EDRAM to precharge the DRAM array while
data is accessed from SRAM cache. It is possible to access additional
SRAM cache locations by providing new column addresses to the
multiplex address inputs. New data is available at the output at time
tAC after each column address change. During read cycles, it is
possible to operate in either static column mode with /CAL=high or
page mode with /CAL clocked to latch the column address. In page
Functional Description
The EDRAM is designed to provide optimum memory
performance with high speed microprocessors. As a result, it is
possible to perform simultaneous operations to the DRAM and SRAM
cache sections of the EDRAM. This feature allows the EDRAM to hide
precharge and refresh operation during SRAM cache reads and
maximize SRAM cache hit rate by maintaining valid cache contents
during write operations even if data is written to another memory
page. These new functions, in conjunction with the faster basic DRAM
and cache speeds of the EDRAM, minimize processor wait states.
EDRAM Basic Operating Modes
mode, data valid time is determined by either tAC or tCQV
DRAM Write Hit
If a DRAM write request is initiated by clocking /RE while W/R,
.
The EDRAM operating modes are specified in the table below.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to the page of data contained in the SRAM cache row register. This
is always equal to the contents of the last row that was read from
(as modified by any write hit data). Writing to a new page does not
cause the cache to be modified.
/CAL, /WE, and /F are high, the EDRAM will compare the new row
address to the LRR address latch (an 11-bit address latch loaded
on each /RE active read miss cycle). If the row address matches,
the EDRAM will write data to both the DRAM array and selected
SRAM cache simultaneously to maintain coherency. The write
address and data are posted to the DRAM as soon as the column
address is latched by bringing /CAL low and the write data is
latched by bringing /WE low. The write address and data can be
latched very quickly after the fall of /RE (tRAH + tASC for the column
address and tDS for the data). During a write burst sequence, the
second write data can be posted at time tRSW after /RE. Subsequent
writes within a page can occur with write cycle time tPC. With /G
enabled and /WE disabled, it is possible to perform cache read
operations while the /RE is activated in write hit mode. This allows
read-modify-write, write-verify, or random read-write sequences
within the page with 12ns cycle times (the first read cannot
complete until after time tRAC2). At the end of a write sequence
(after /CAL and /WE are brought high and tRE is satisfied), /RE can
be brought high to precharge the memory. It is possible to perform
DRAM Read Hit
A DRAM read request is initiated by clocking /RE with W/R low
and /F & /CAL high. The EDRAM compares the new row address to
the last row read address latch (LRR - an 11-bit latch loaded on
each /RE active read miss cycle). If the row address matches the
LRR, the requested data is already in the SRAM cache and no
DRAM memory reference is initiated. The data specified by the
column address is available at the output pins at the greater of
times tAC or tGQV. Since no DRAM activity is initiated, /RE can be
brought high after time tRE1, and a shorter precharge time, tRP1, is
allowed. It is possible to access additional SRAM cache locations by
providing new column addresses to the multiplex address inputs.
New data is available at the output at time tAC after each column
address change. During read cycles, it is possible to operate in
either static column mode with /CAL=high or page mode with /CAL
EDRAM Basic Operating Modes
Function
/S
L
L
L
L
X
/RE
↓
W/R
L
/F
H
H
H
H
L
/CAL /WE
A
Comment
0-10
Read Hit
H
H
H
H
X
X
X
H
H
X
Row = LRR
Row ≠ LRR
Row = LRR
Row ≠ LRR
X
No DRAM Reference, Data in Cache
DRAM Row to Cache
Read Miss
Write Hit
↓
L
↓
H
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
Cache Reads Enabled
Write Miss
Internal Refresh
↓
H
↓
X
Low Power Standby
Unallowed Mode
H
H
H
H
L
↓
X
X
H
X
H
H
H
X
L
H
X
H
X
X
X
1mA Standby Current
Unallowed Mode (Except -L Option)
Standby Current, Internal Refresh Clock (-L Option)
Low Power Self-Refresh
Option
H = High; L = Low; X = Don’t Care; ↓ = High-to-Low Transition; LRR = Last Row Read
1-2
cache reads concurrently with precharge. During write sequences, the output pin Q (as shown below). The specific databit selected to
a write operation is not performed unless both /CAL and /WE are the output is determined by column addresses A and A . System
9
10
low. As a result, the /CAL input can be used as a byte write select in operation is consistent with the standard “Functional Description”
multi-chip systems.
and timing diagrams shown in this specification. See the note in the
read timing diagrams and “Switching Characteristics” chart for the
faster access and data hold times.
DRAM Write Miss
If a DRAM write request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high, the EDRAM will compare the new row
address to the LRR address latch (an 11-bit latch loaded on each
/RE active read miss cycle). If the row address does not match, the
EDRAM will write data to the DRAM array only and contents of the
current cache are not modified. The write address and data are
posted to the DRAM as soon as the column address is latched by
bringing /CAL low and the write data is latched by bringing /WE
low. The write address and data can be latched very quickly after
the fall of /RE (tRAH + tASC for the column address and tDS for the
data). During a write burst sequence, the second write data can be
posted at time tRSW after /RE. Subsequent writes within a page can
occur with write cycle time tPC. During a write miss sequence,
cache reads are inhibited and the output buffers are disabled
(independently of /G) until time tWRR after /RE goes high. At the
end of a write sequence (after /CAL and /WE are brought high and
tRE is satisfied), /RE can be brought high to precharge the memory.
It is possible to perform cache reads concurrently with the
precharge. During write sequences, a write operation is not
performed unless both /CAL and /WE are low. As a result, /CAL can
be used as a byte write select in multi-chip systems.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle.
DM2200 Datapath Architecture
EDRAM
Row Address
4M DRAM Array
A
0-10
2,048 Bits
EDRAM
2K SRAM Cache
Column Address
A
2-10
128 Bits
Column Address
4 to 1
Output Selector
/RE Inactive Operation
A A
9, 10
It is possible to read data from the SRAM cache without
clocking /RE. This option is desirable when the external control
logic is capable of fast hit/miss comparison. In this case, the
controller can avoid the time required to perform row/column
multiplexing on hit cycles. This capability also allows the EDRAM to
perform cache read operations during precharge and refresh
cycles to minimize wait states and reduce power. It is only
necessary to select /S and /G and provide the appropriate column
address to read data as shown in the table below. The row address
of the SRAM cache accessed without clocking /RE will be specified
by the LRR address latch loaded during the last /RE active read
cycle. To perform a cache read in static column mode, /CAL is held
high, and the cache contents at the specified column address will
be valid at time tAC after address is stable. To perform a cache read
in page mode, /CAL is clocked to latch the column address. The
cache data is valid at time tAC after the column address is setup to
/CAL.
1 Bit
Q
Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
mode, the internal DRAM circuitry is powered down to reduce
standby current to 1mA.
Low Power, Self-Refresh Option
When the low power, self-refresh option is specified when
ordering the EDRAM, the EDRAM enters this mode when /RE is
clocked while /S, W/R, /F, and /WE are high; and /CAL is low. In this
mode, the power is turned off to all I/O pins except /RE to
minimize chip power, and an on-board refresh clock is enabled to
perform self-refresh cycles using the on-board refresh counter. The
EDRAM remains in this low power mode until /RE is brought high
again to terminate the mode. The EDRAM /RE input must remain
high for tRP2 following exit from self-refresh mode to allow any on-
going internal refresh to terminate prior to the next memory
operation.
On-Chip SRAM Interleave
The DM2200 has an on-chip interleave of its SRAM cache
which allows 8ns random accesses (tAC1) for up to three data
words (burst reads) following an initial read access (hit or miss).
The SRAM cache is integrated into the DRAM arrays in a 512 x 4
organization. It is converted into a 2K x 1 page organization by
using an on-chip address multiplexer to select one of four bits to
+3.3 Volt Power Supply Operation
If the +3.3 volt power supply option is specified, the EDRAM
will operate from a +3.3 volt ±0.3 volt power supply and all inputs
and outputs will have LVTTL/LVCMOS compatible signal levels. The
+3.3 volt EDRAM will not accept input levels which exceed the
power supply voltage. If mixed I/O levels are expected in your
system, please specify the +5 volt version of the EDRAM.
Function
/S
L
/G /CAL
A
0-8
Cache Read (Static Column)
Cache Read (Page Mode)
L
L
H
Column Address
Column Address
↓
/CAL Before /RE Refresh (“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
discussed in the “Reduced Pin Count Operation” section below.
L
H = High; L = Low; X = Don’t Care; ↓ = Transitioning
1-3
data from the EDRAM SRAM row registers. On read operations, /RE
can be brought high as soon as data is loaded into cache to allow
early precharge.
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAM refresh, it is possible to perform
an /RE only refresh using an externally supplied row address. /RE
refresh is performed by executing a write cycle (W/R and /F are
high) where /CAL is not clocked. This is necessary so that the
current cache contents and LRR are not modified by the refresh
/CAL — Column Address Latch
This input is used to latch the column address and in
combination with /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL is low,
the column address latch is closed and the output of the latch
contains the address present while /CAL was high.
operation. All combinations of addresses A must be sequenced
0-9
e
very 64ms refresh period. A does not need to be cycled. Read
10
refresh cycles are not allowed because a DRAM refresh cycle does not
W/R — Write/Read
occur when a read refresh address matches the LRR address latch.
This input along with /F specifies the type of DRAM operation
initiated on the low going edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
Initialization Cycles
A minimum of 10 initialization (start-up) cycles are required
before normal operation is guaranteed. At least eight /F refresh
cycles and two read cycles to different row addresses are necessary
to complete initialization. /RE must be high for at least 300ns prior
to initialization.
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when it is low on the
low going edge of /RE.
Unallowed Mode
Read, write, or /RE only refresh operations must not be performed
to unselected memory banks by clocking /RE when /S is high.
/WE — Write Enable
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are low.
Reduced Pin Count Operation
/G — Output Enable
This input controls the gating of read data to the output data
pins during read operations.
Although it is desirable to use all EDRAM control pins to
optimize system performance, it is possible to simplify the interface
to the EDRAM by either tying pins to ground or by tying one or
more control inputs together. The /S input can be tied to ground if
the low power standby modes are not required. The /CAL and /F
pins can be tied together if hidden refresh operation is not
required. In this case, a CBR refresh (/CAL before /RE) can be
performed by holding the combined input low prior to /RE. A CBR
refresh does not require that a row address be supplied when /RE
is asserted. The timing is identical to /F refresh cycle timing. The
/WE input can be tied to /CAL if independent posting of column
addresses and data are not required during write operations. In
this case, both column address and write data will be latched by
the combined input during writes. W/R and /G can be tied together
if reads are not performed during write hit cycles. If these
techniques are used, the EDRAM will require only three control
lines for operation (/RE, /CAS [combined /CAL, /F, and /WE], and
W/R [combined W/R and /G]). The simplified control interface still
allows the fast page read/write cycle times, fast random read/write
times, and hidden precharge functions available with the EDRAM.
/S — Chip Select
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in its low power mode. /S
must remain active throughout any read or write operation. With
the exception of /F refresh cycles, /RE should never be clocked
when /S is inactive.
D — Data Input
This input pin is used to write data to the EDRAM.
Q — Data Output
This output pin is used to read data from the EDRAM.
A
0-10 — Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The11-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles.
V Power Supply
CC These inputs are connected to the +5 or +3.3 volt power supply.
Pin Descriptions
/RE — Row Enable
This input is used to initiate DRAM read and write operations
and latch a row address. It is not necessary to clock /RE to read
V Ground
SS
These inputs are connected to the power supply ground
connection.
Pin Names
Pin Names
Function
Pin Names
Function
A
Address Inputs
Row Enable
Data In
V
Ground
0-10
SS
/WE
/G
Write Enable
Output Enable
Refresh Control
/RE
D
Q
Data Out
/F
/S
Chip Select - Active/Standby Control
No Connection
/CAL
W/R
Column Address Latch
Write/Read Control
NC
V
Power (+5V or +3.3V)
CC
1-4
AC Test Load and Waveforms
V Timing Reference Point at V and V
IN IL IH
Load Circuit
Input Waveforms
+ 5.0 (+3.3 Volt Option)
V
V
IH
IH
(5.0 volt)
R
= 828Ω
1
(3.3 Volt Option)
R
= 1178Ω
1
Output
V
V
IL
IL
C = 50pf
L
(5.0 volt)
R
= 295Ω
GND
2
R
= 868Ω
(3.3 Volt Option)
≤5ns
≤5ns
2
Absolute Maximum Ratings
(Beyond Which Permanent Damage Could Result)
Capacitance
Description
Max
6pf, 7pf(1)
Pins
3.3V Option
Rating
Description
Ratings
- 1 ~ 7v
- 1 ~ 7v
- 1 ~ 7v
A
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Output Capacitance
0-9
Input Voltage (V )
- .5 ~ 4.6v
- .5 ~ 4.6v
- .5 ~ 4.6v
IN
7pf, 10pf(1) A , /CAL, /RE, W/R, /WE, /F, /S
10
Output Voltage (VOUT
)
/G
D
2pf
6pf
6pf
Power Supply Voltage (V )
CC
Ambient Operating Temperature (TA)
Storage Temperature (TS)
-40 ~ 85°C -40 ~ 85°C
-55 ~ 150°C -55 ~ 150°C
Q
(1) +5 V, DM2200-15 only.
Static Discharge Voltage
(Per MIL-STD-883 Method 3015)
Class 1
20mA
Class 1
50mA
Short Circuit O/P Current (IOUT
)
Electrical Characteristics
T = 0 to 70°C (Commercial); -40 to 85°C (Industrial)
A
3.3V Option
Symbol
Parameters
Max
Min
Test Conditions
Max
Min
V
Supply Voltage
3.0V
3.6V
4.75V
5.25V
Vcc+0.5V
0.8V
All Voltages Referenced to V
SS
CC
V
Input High Voltage
Input Low Voltage
Output High Level
Output Low Level
2.0V
Vss-0.3V
2.4V
V +0.3V 2.4V
IH
CC
V
0.8V Vss-0.5V
2.4V
IL
VOH
VOL
Ii(L)
IOUT = - 5mA (-2ma For 3.3 Volt Option)
IOUT = 4.2mA (2ma For 3.3 Volt Option)
0.4V
0.4V
10µA
10µA
Input Leakage Current
Output Leakage Current
-5µA
-5µA
5µA
5µA
-10µA
-10µA
OV ≤ V ≤ Vcc + 0.5 Volts
IN
IO(L)
O ≤ VI/O ≤ Vcc
Symbol
Operating Current
Random Read
33MHz Typ (1)
-15 Max
-12 Max
Test Condition
Notes
ICC1
110mA
65mA
55mA
135mA
50mA
1mA
225mA
145mA
110mA
190mA
135mA
1mA
180mA /RE, /CAL, and Addresses Cycling: tC = tC Minimum
115mA /CAL and Addresses Cycling: tPC = tPC Minimum
2, 3, 5
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
Fast Page Mode Read
Static Column Read
Random Write
2, 4, 5
2, 4, 5
2, 3
90mA
Addresses Cycling: tSC = tSC Minimum
/RE, /CAL, /WE, and Addresses Cycling: tC = tC Minimum
150mA
Fast Page Mode Write
105mA /CAL, /WE, and Addresses Cycling: tPC = tPC Minimum
2, 4
Standby
1mA
All Control Inputs Stable ≥ VCC - 0.2V, Output Driven
Self-Refresh
Option (-L)
/S, /F, W/R, /WE, and A0-10 at ≥ VCC - 0.2V
/RE and /CAL at ≤ VSS + 0.2V, I/O Open
200 µA
30mA
200 µA
—
200 µA
—
ICCT
1
Average Typical
See “Estimating EDRAM Operating Power” Application Note
Operating Current
(1) “33MHz Typ” refers to worst case I expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested
CC
or guaranteed. (2) I is dependent on cycle rates and is measured with CMOS levels and the outputs open. (3) I is measured with a maximum of one address change while
CC
CC
/RE = V . (4) I is measured with a maximum of one address change while /CAL = V . (5) /G is high.
IL
CC
IH
1-5
Switching Characteristics
V = 5V ± 5% (+5 Volt Option), V = 3.3V ± 0.3V (+3.3 Volt Option), C = 50pf, T = 0 to 70°C (Commercial) ,T = -40 to 85°C (Industrial)
CC
CC
L
A
A
-12
-15
Symbol
Description
Units
Min
Max
12
8
Min
Max
15
8
(1)
AC
t
Column Address Access Time for Addresses A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0-8
(1)
t
Column Address Access Time for Addresses A and A
AC1
9
10
t
Column Address Valid to /CAL Inactive (Write Cycle)
12
5
15
5
ACH
AQX
AQX1
ASC
ASR
C
t
Column Address Change to Output Data Invalid for Addresses A
0-8
t
t
t
t
t
t
t
t
t
Column Address Change to Output Data Invalid for Addresses A and A
1
5
1
5
9
10
Column Address Setup Time
Row Address Setup Time
Row Enable Cycle Time
5
5
65
25
6
55
20
5
Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only
Column Address Latch Active Time
C1
CAE
CAH
CH
Column Address Hold Time
0
0
5
5
Column Address Latch High Time (Latch Transparent)
/CAL Inactive Lead Time to /RE Inactive (Write Cycles Only)
-2
-2
CHR
t
t
t
0
0
Column Address Latch High to Write Enable Low (Multiple Writes)
Column Address Latch High to Data Valid
ns
ns
ns
CHW
CQV
CQX
15
17
Column Address Latch Inactive to Data Invalid for Addresses A
0-8
5
5
t
t
t
t
Column Address Latch Inactive to Data Invalid for Addresses A and A
1
5
5
0
1
5
5
0
ns
ns
ns
ns
CQX1
CRP
CWL
DH
9
10
Column Address Latch Setup Time to Row Enable
/WE Low to /CAL Inactive
Data Input Hold Time
t
t
5
5
Data Input Setup Time
ns
ns
DS
(1)
Output Enable Access Time
5
5
5
5
5
5
GQV
(2,3)
t
t
t
t
t
t
t
t
t
Output Enable to Output Drive Time
0
0
0
0
ns
ns
GQX
(4,5)
Output Turn-Off Delay From Output Disabled (/G↑)
/F and W/R Mode Select Hold Time
GQZ
0
0
ns
ns
ns
ns
ns
MH
/F and W/R Mode Select Setup Time
5
5
MSU
NRH
NRS
PC
/CAL, /G, /WE, and W/R Hold Time For /RE-Only Refresh
/CAL, /G, /WE, and W/R Setup Time For /RE-Only Refresh,
0
0
5
5
Column Address Latch Cycle Time
12
15
(1)
Row Enable Access Time, On a Cache Miss
Row Enable Access Time, On a Cache Hit (Limit Becomes t
30
15
35
17
ns
ns
RAC
(1)
)
RAC1
AC
(1,6)
t
t
t
30
35
ns
ns
ns
Row Enable Access Time for a Cache Write Hit
Row Address Hold Time
RAC2
RAH
RE
1
1.5
35
Row Enable Active Time
30
100000
100000
1-6
Switching Characteristics (continued)
V = 5V ± 5% (+5 Volt Option), V = 3.3V ± 0.3V% (+3.3 Volt Option), C = 50pf, T = 0 to 70°C (Commercial) ,T = -40 to 85°C (Industrial)
CC
CC
L
A
A
-12
-15
Symbol
Description
Units
Min
Max
64
Min
Max
64
t
t
t
t
t
t
t
Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle
Refresh Period
8
10
ns
ms
ns
ns
ns
ns
ns
RE1
REF
RGX
Output Enable Don't Care From Row Enable (Write, Cache Miss), O/P Hi Z
Row Enable High to Output Turn-On After Write Miss
Row Precharge Time
9
0
10
0
(2,6)
12
15
RQX1
RP
20
8
25
10
Row Precharge Time, Cache Hit (Row=LRR) Read Cycle
Row Precharge Time, Self-Refresh Mode
RP1
RP2
100
100
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
0
12
35
12
12
0
0
15
40
15
15
0
Read Hold Time From Row Enable (Write Only)
Last Write Address Latch to End of Write
Row Enable to Column Address Latch Low For Second Write
Last Write Enable to End of Write
Column Address Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RRH
RSH
RSW
RWL
SC
Select Hold From Row Enable
SHR
(1)
SQV
Chip Select Access Time
12
12
8
15
15
10
(2,3)
SQX
0
0
Output Turn-On From Select Low
Output Turn-Off From Chip Select
Select Setup Time to Row Enable
Transition Time (Rise and Fall)
0
0
(4,5)
SQZ
SSR
T
5
5
1
10
1
10
12
5
Write Enable Cycle Time
15
5
WC
WCH
WHR
WI
Column Address Latch Low to Write Enable Inactive Time
Write Enable Hold After /RE
0
0
5
Write Enable Inactive Time
5
5
5
Write Enable Active Time
WP
(1)
WQV
12
12
12
15
15
15
Data Valid From Write Enable High
Data Output Turn-On From Write Enable High
Data Turn-Off From Write Enable Low
Write Enable Setup Time to Row Enable
Write to Read Recovery (Following Write Miss)
(2,5)
WQX
0
0
5
0
0
5
(3,4)
WQZ
WRP
WRR
16
18
(1) V Timing Reference Point at 1.5V
OUT
(2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to V or V
OH
OL
(3) Minimum Specification is Referenced from V and Maximum Specification is Referenced from V on Input Control Signal
IH
IL
(4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to V or V
OH
OL
(5) Minimum Specification is Referenced from V and Maximum Specification is Referenced from V on Input Control Signal
IL
IH
(6) Access Parameter Applies When /CAL Has Not Been Asserted Prior to t
RAC2
1-7
/RE Inactive Cache Read Hit (Static Column Mode)
/RE
/F
W/R
A
Column 1
tSC
Column 2
tSC
Column 3
tSC
Column 4
0-10
/CAL
/WE
tAC
tAC
tAC
tAC
tAQX
tAQX
tAQX
Open
tGQX
Data 1
Data 2
Data 3
Data 4
tGQZ
Q
tGQV
/G
/S
tSQX
tSQV
tSQZ
Don’t Care or Indeterminate
Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
NOTES: 1.
2. If column address 2, 3, or 4 modifies only address pin A or A , then t becomes t for data 2, 3, and 4,
AC1
9
10
AC
and t becomes t
for data 1, 2, and 3.
AQX
AQX1
1-8
/RE Inactive Cache Read Hit (Page Mode)
/RE
/F
W/R
tCAH
A
Column 1
tASC
Column 2
tASC
Row
0-10
tCAH
tCAE
tPC
tCH
/CAL
/WE
tCQV
tAC
tCQX
Open
Data 1
Data 2
Q
tAC
tGQX
tGQZ
tGQV
/G
/S
tSQX
tSQV
tSQZ
Don’t Care or Indeterminate
NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
2.
If column address 2 modifies only address pin A or A , then t becomes t
for data 2 and t
becomes t
for data 1.
9
10
AC
AC1
CQX
CQX1
1-9
/RE Active Cache Read Hit (Static Column Mode)
tC1
tRE1
tMSU
/RE
tRP1
tMH
/F
tMSU
tMH
W/R
tASR
tRAH
A
Row
Column 1
tSC
Column 2
tSC
Column 3
tSC
Column 4
0-10
tCRP
/CAL
/WE
tAC
tAC
tAC
tAC
tRAC1
tAQX
tAQX
tAQX
Open
tGQX
Data 1
Data 2
Data 3
Data 4
tGQZ
Q
tGQV
/G
/S
tSHR
tSQZ
tSSR
Don’t Care or Indeterminate
for data 2, 3, and 4, and t becomes
NOTES:
1. If column address 2, 3, or 4 modifies only address pin A or A , then t becomes t
9
10
AC
AC1
AQX
t
for data 1, 2, and 3.
AQX
1-10
/RE Active Cache Read Hit (Page Mode)
tC1
tRE1
tMSU
/RE
tRP1
tMH
/F
tMSU
tMH
W/R
tASR
tCAH
tRAH
A
Row
Column 1
tASC
Column 2
tASC
Row
0-10
tCRP
tCAH
tCAE
tPC
tCH
/CAL
/WE
tCQV
tAC
tCQX
tRAC1
Open
Data 1
Data 2
Q
tAC
tGQX
tGQZ
tGQV
/G
/S
tSHR
tSQZ
tSSR
Don’t Care or Indeterminate
for data 2 and t becomes
1.
NOTES:
If column address 2 modifies only address pin A or A , then t becomes t
CQX1
9
10
AC
AC1
CQX
t
for data 1.
1-11
/RE Active Cache Read Miss (Static Column Mode)
tC
tRE
/RE
tRP
tMSU
tMH
/F
tMSU
tMH
W/R
tASR
tRAH
tSC
Column 1
Row
Column 2
Row
A
0-10
tCRP
/CAL
tAQX
/WE
tAC
tAC
tRAC
tAQX
Open
Data 1
Data 2
Q
tGQX
tGQV
tGQZ
/G
/S
tSHR
tSSR
tSQZ
Don’t Care or Indeterminate
for data 2, and t becomes
NOTES:
1. If column address 2 modifies only address pin A or A , then t becomes t
9
10
AC
AC1
AQX
t
for data 1.
AQX1
1-12
/RE Active Cache Read Miss (Page Mode)
tC
tRE
/RE
tRP
tMSU
tMH
/F
tMSU
tMH
W/R
tASR
tRAH
tCAH
Row
Column 1
Column 2
tASC
Row
A
0-10
tASC
tCRP
tCAH
tCAE
tCH
/CAL
/WE
tPC
tCQV
tAC
tCQX
tRAC
Open
Data 1
Data 2
Q
tAC
tGQZ
/G
/S
tGQX
tSHR
tSSR
tGQV
tSQZ
Don’t Care or Indeterminate
for data 2, and t becomes
1.
NOTES: If column address 2 modifies only address pin A or A , then t becomes t
9
10
AC
AC1
CQX
t
for data 1.
CQX1
1-13
Burst Write (Hit or Miss) Followed By /RE Inactive Cache Reads
tRE
/RE
tMSU
tRP
tMH
tCHR
/F
tMSU
tMH
W/R
tASR
tRAH
Column 1
tCAH
tRSW
A
Row
Column 2
tACH
Column n
0-10
tACH
tCHR
tASC
tCAH
tRSH
tCRP
tCWL
tCWL
tCAE
tCAE
/CAL
/WE
tCH
tCHW
tWCH
tWP
tPC
tWCH
tWP
tWRP
tRRH
tWI
tWHR
tWC
tDS
tRWL
tDH
tDS
tDH
D
Q
Data 1
Data 2
tWRR
tRQX1
tAC
Open
Cache (Column n)
tGQV
tGQX
/G
/S
tSSR
Don’t Care or Indeterminate
NOTES: 1. /G becomes a don’t care after t during a write miss.
RGX
1-14
Read/Write During Write Hit Cycle (Can Include Read-Modify-Write)
tC
tRE
/RE
tRP
tMSU
tCHR
tMH
/F
tMSU
t MH
W/R
tASR
tAC
tCHR
tRAH
Column 1
tCAH
A
Row
Column 2
Column 3
0-10
tACH
tRSH
tCRP
tASC
tCAE
tWCH
/CAL
/WE
tCQV
tCWL
tWP
tWRP
tRRH
tWHR
tRAC2
tAQX
tRWL
tAC
tWQV
tCQX
D
Q
Read Data
Read Data
tDH
tWQX
tDS
Write Data
tGQX
tGQZ
tGQZ
tGQV
tGQV
/G
/S
tSSR
Don’t Care or Indeterminate
NOTES: 1.
If column address 2 modifies only address pin A or A , then t becomes t
.
9
10
AQX
AQX1
1-15
/F Refresh Cycle
tRE
/RE
/F
tMSU
tRP
tMH
Don’t Care or Indeterminate
NOTES: 1. During /F refresh cycles, the status of W/R, /WE, A0-10, /CAL, /S, and /G is a don’t care.
2. /RE inactive cache reads may be performed in parallel with /F refresh cycles.
/RE-Only Refresh
tC
tRE
/RE
tRP
tASR
tRAH
A
Row
0-10
tNRS
tNRH
/CAL, /WE, /G,
W/R
tMSU
tMH
/F
/S
tSSR
tSHR
Don’t Care or Indeterminate
NOTES: 1. All binary combinations of A must be refreshed every 64ms interval. A does not have to be cycled, but must remain valid
0-9
10
during row address setup and hold times.
2. /RE refresh is write cycle with no /CAL active cycle.
1-16
Low Power Self-Refresh Mode Option
/RE
tRP2
A
0-10
tMSU
tMH
/CAL
tMSU
tMH
/F, W/R,
/WE, /S
Don’t Care or Indeterminate
NOTES: 1. EDRAM self refreshes as long as /RE remains low. (Low Power Self-Refresh parts only).
2. When using the Low Power Self Refresh mode the following operations must be performed:
If row addresses are being refreshed in an evenly distributed manner over the refresh interval using /F refresh cycles, then at
least one /F refresh cycle must be performed immediately after exit from the Low Power Self Refresh Mode. If row addresses
are being refreshed in any other manner (/F burst or /RE distributed or burst), then all rows must be refresh immediately before
entry to and immediately after exit from the Low Power Self Refresh.
Part Numbering System
DM2200J 1 - 12I
Temperature Range
o
No Designator = 0 to 70 C (Commercial)
o
I = -40 to 85 C (Industrial)
o
L = 0 to 70 C, Low Power Self-Refresh
Access Time from Cache in Nanoseconds
12ns
15ns
Power Supply Voltage
No Designator = +5 Volts
1 = +3.3 Volts
Packaging System
J = 300 Mil, Plastic SOJ
T = 300 Mil, Plastic TSOP-II
I/O Width
i.e., Power to Which 2 is Raised for I/O Width (x1)
Capacity in Bits
i.e., Power to Which 2 is Raised for Total Capacity (4Mbit)
Dynamic Memory
1-17
Mechanical Data
28 Pin 300 Mil Plastic SOJ Package
Inches (mm)
Optional
Pin 1
Indicator
3
2
1
0.295 (7.493)
0.305 (7.747)
0.330 (8.382)
0.340 (8.636)
0.094 (2.39)
0.102 (2.59)
0.720 (18.288)
0.730 (18.542)
0.0091 (.23)
0.0125 (.32)
0.128 (3.251)
0.148 (3.759)
0.088 (2.24)
0.098 (2.48)
0.260 (6.604)
0.275 (6.985)
Seating
Plane
0.014 (.36)
0.019 (.48)
0.050 (1.27)
0.035 (0.89)
0.045 (1.14)
Mechanical Data
44 Pin 300 Mil Plastic TSOP-II Package
Inches (mm)
0.741 (18.81) MAX.
0.0315 (0.80) TYP.
0.040 (1.02) TYP.
0.040 (1.02) TYP.
0.040 (1.02) TYP.
7° TYP.
0.044 (1.13) MAX.
0.308 (7.82)
0.292 (7.42)
0.039 (1.00)
0.023 (0.60)
0.024 (0.60)
0.016 (0.40)
0.371 (9.42)
0.355 (9.02)
0.016 (0.40)
0.039 (1.00) TYP.
0.004 (0.10)
0.008 (0.20)
0.000 (0.00)
0.010 (0.24)
0.004 (0.09)
The information contained herein is subject to change without notice. Enhanced Memory Systems Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in
an Enhanced product, nor does it convey or imply any license under patent or other rights.
1-18
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