FM25256B [RAMTRON]
256Kb FRAM Serial 5V Memory; 256KB串行FRAM存储器5V
| 型号： | FM25256B |
| 厂家： | 
RAMTRON INTERNATIONAL CORPORATION |
| 描述： | 256Kb FRAM Serial 5V Memory |
| 文件： | 总13页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FM25256B
256Kb FRAM Serial 5V Memory
Features
Write Protection Scheme
256K bit Ferroelectric Nonvolatile RAM
•
•
Hardware Protection
Software Protection
•
•
•
•
•
Organized as 32,768 x 8 bits
Virtually Unlimited Endurance (1014 Cycles)
10 Year Data Retention
Wide Operating Range
Wide Voltage Operation 4.0V – 5.5V
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
•
Industry Standard Configurations
Very Fast Serial Peripheral Interface - SPI
•
•
Industrial Temperature -40°C to +85°C
8-pin “Green”/RoHS SOIC (-G)
•
•
•
Up to 20 MHz Frequency
Direct Hardware Replacement for EEPROM
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Description
Pin Configuration
The FM25256B is a 256-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
1
8
7
6
5
CS
VDD
HOLD
SCK
SI
2
SO
3
WP
4
VSS
Unlike serial EEPROMs, the FM25256B performs
write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. The
next bus cycle may start immediately. In addition, the
product offers virtually unlimited write endurance.
Also, FRAM exhibits much lower power
consumption than EEPROM.
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
These capabilities make the FM25256B ideal for
nonvolatile memory applications requiring frequent
or rapid writes or low power operation. Examples
range from data collection, where the number of
write cycles may be critical, to demanding industrial
controls where the long write time of EEPROM can
cause data loss.
Supply Voltage (4.0 to 5.5V)
Ground
Ordering Information
FM25256B-G
“Green”/RoHS 8-pin SOIC
The FM25256B provides substantial benefits to users
of serial EEPROM as
a
hardware drop-in
replacement. The FM25256B uses the high-speed SPI
bus, which enhances the high-speed write capability
of FRAM technology. Device specifications are
guaranteed over an industrial temperature range of
-40°C to +85°C.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Rev. 3.0
July 2007
Page 1 of 13
FM25256B
WP
CS
Instruction Decode
Clock Generator
Control Logic
HOLD
SCK
Write Protect
8192 x 32
FRAM Array
Instruction Register
15
8
Address Register
Counter
SI
SO
Data I/O Register
3
Nonvolatile Status
Register
Figure 1. Block Diagram
Pin Descriptions
Pin Name
I/O
Description
/CS
Input
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
SCK
Input
Input
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 20 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
/HOLD
/WP
SI
Input
Input
Write Protect: This active low pin prevents write operations to the status register only.
A complete explanation of write protection is provided on pages 6 and 7.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet IDD specifications.
* SI may be connected to SO for a single pin data interface.
Serial Output: This is the data output pin. It is driven during a read and remains tri-
stated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
SO
Output
* SO may be connected to SI for a single pin data interface.
Power Supply (4.0V to 5.5V)
Ground
VDD
VSS
Supply
Supply
Rev. 3.0
July 2007
Page 2 of 13
FM25256B
host
performance serial communication to
a
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25256B operates in SPI Mode 0 and 3.
Overview
The FM25256B is a serial FRAM memory. The
memory array is logically organized as 32,768 x 8
and is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the FRAM is similar to serial EEPROMs. The
major difference between the FM25256B and a serial
EEPROM with the same pinout is the FRAM’s
superior write performance and power consumption.
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25256B devices
with a microcontroller that has a dedicated SPI port,
as Figure 2 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25256B device.
Memory Architecture
When accessing the FM25256B, the user addresses
32K locations of 8 data bits each. These data bits are
shifted serially. The addresses are accessed using the
SPI protocol, which includes a chip select (to permit
multiple devices on the bus), an op-code, and a two-
byte address. The upper bit of the address range is a
“don’t care” value. The complete address of 15-bits
specifies each byte address uniquely.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins together and tie off the
Hold pin. Figure 3 shows a configuration that uses
only three pins.
Most functions of the FM25256B either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation is essentially zero, beyond the
time needed for the serial protocol. That is, the
memory is read or written at the speed of the SPI bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. So, by the time a new bus transaction can be
shifted into the device, a write operation will be
complete. This is explained in more detail in the
interface section.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data pins. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25256B will begin monitoring
the clock and data lines. The relationship between the
falling edge of /CS, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25256B supports only modes 0 and 3. Figure 4
shows the required signal relationships for modes 0
and 3. For both modes, data is clocked into the
FM25256B on the rising edge of SCK and data is
expected on the first rising edge after /CS goes
active. If the clock starts from a high state, it will fall
prior to the first data transfer in order to create the
first rising edge.
Users expect several obvious system benefits from
the FM25256B due to its fast write cycle and high
endurance as compared to EEPROM. In addition
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/CS is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred. Note that the
WREN and WRDI op-codes are commands with no
subsequent data transfer.
Note that the FM25256B contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to
ensure that VDD is within datasheet tolerances to
prevent incorrect operation. It is recommended
that the part is not powered down with chip
enable active.
Important: The /CS must go inactive after an
operation is complete and before a new op-code
can be issued. There is one valid op-code only per
active chip select.
Serial Peripheral Interface – SPI Bus
The FM25256B employs a Serial Peripheral Interface
(SPI) bus. It is specified to operate at speeds up to 20
MHz. This high-speed serial bus provides high
Rev. 3.0
July 2007
Page 3 of 13
FM25256B
SCK
MOSI
MISO
SO SI SCK
FM25256B
SO SI SCK
FM25256B
SPI
Microcontroller
CS
HOLD
CS
HOLD
SS1
SS2
HOLD1
HOLD2
MOSI: Master Out Slave In
MISO: Master In Slave Out
SS : Slave Select
Figure 2. System Configuration with SPI port
P1.0
P1.1
Microcontroller
SO SI SCK
FM25256B
CS
HOLD
P1.2
Figure 3. System Configuration without SPI port
SPI Mode 0: CPOL=0, CPHA=0
7
6
5
4
3
2
1
0
SPI Mode 3: CPOL=1, CPHA=1
7
6
5
4
3
2
1
0
Figure 4. SPI Modes 0 & 3
Rev. 3.0
July 2007
Page 4 of 13
FM25256B
Power Up to First Access
WREN - Set Write Enable Latch
The FM25256B is not accessible for a period of time
(10 ms) after power up. Users must comply with the
timing parameter tPU, which is the minimum time
from VDD (min) to the first /CS low.
The FM25256B will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Data Transfer
All data transfers to and from the FM25256B occur
in 8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status
register has no effect on the state of this bit.
Completing any write operation will automatically
clear the write-enable latch and prevent further
writes without another WREN command. Figure 5
illustrates the WREN command bus configuration.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25256B. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the status
register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
Table 1. Op-code Commands
Name
Description
Op-code
00000110b
00000100b
00000101b
00000001b
00000011b
00000010b
Set Write Enable Latch
Write Disable
WREN
WRDI
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read Memory Data
Write Memory Data
CS
0
1
2
3
4
5
1
6
1
7
0
SCK
SI
0
0
0
0
0
Hi-Z
SO
Figure 5. WREN Bus Configuration
Rev. 3.0
July 2007
Page 5 of 13
FM25256B
CS
0
1
2
3
4
5
1
6
0
7
0
SCK
0
0
0
0
0
SI
Hi-Z
SO
Figure 6. WRDI Bus Configuration
RDSR - Read Status Register
WRSR – Write Status Register
The RDSR command allows the bus master to verify
the contents of the Status Register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR op-
code, the FM25256B will return one byte with the
contents of the Status Register. The Status Register is
described in detail in a later section.
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status Register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive.
Prior to sending the WRSR command, the user must
send a WREN command to enable writes. Note that
executing a WRSR command is a write operation
and therefore clears the Write Enable Latch.
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration
Table 2. Status Register
Status Register & Write Protection
7
6
0
5
0
4
0
3
2
1
0
0
Bit
The write protection features of the FM25256B are
multi-tiered. Taking the /WP pin to a logic low state
is the hardware write protect function. All write
operations are blocked when /WP is low. To write the
memory with /WP high, a WREN op-code must first
be issued. Assuming that writes are enabled using
WREN and by /WP, writes to memory are controlled
by the Status Register. As described above, writes to
the status register are performed using the WRSR
command and subject to the /WP pin. The Status
Register is organized as follows.
WPEN
BP1
BP0
WEL
Name
Bits 0 and 4-6 are fixed at 0 and cannot be modified.
Note that bit 0 (Ready in EEPROMs) is unnecessary
as the FRAM writes in real-time and is never busy.
The BP1 and BP0 control software write protection
features. They are nonvolatile (shaded yellow). The
WEL flag indicates the state of the Write Enable
Latch. Attempting to directly write the WEL bit in
the status register has no effect on its state. This bit
is internally set by the WREN command and cleared
Rev. 3.0
July 2007
Page 6 of 13
FM25256B
by terminating a write cycle (/CS high) or by using
the WRDI command.
The WPEN bit controls the effect of the hardware
/WP pin. When WPEN is low, the /WP pin is
ignored. When WPEN is high, the /WP pin controls
write access to the status register. Thus the Status
Register is write protected if WPEN=1 and /WP=0.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are write
protected as shown in the following table.
This scheme provides a write protection mechanism,
which can prevent software from writing the
memory under any circumstances. This occurs if the
BP1 and BP0 are set to 1, the WPEN bit is set to 1,
and /WP is set to 0. This occurs because the block
protect bits prevent writing memory and the /WP
signal in hardware prevents altering the block
protect bits (if WPEN is high). Therefore in this
condition, hardware must be involved in allowing a
write operation. The following table summarizes the
write protection conditions.
Table 3. Block Memory Write Protection
BP1
BP0 Protected Address Range
0
0
1
1
0
1
0
1
None
6000h to 7FFFh (upper ¼)
4000h to 7FFFh (upper ½)
0000h to 7FFFh (all)
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
Table 4. Write Protection
WEL
WPEN
/WP
X
X
0
1
Protected Blocks
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Unprotected
Unprotected
Unprotected
Status Register
Protected
Unprotected
Protected
0
1
1
1
X
0
1
1
Unprotected
the middle of a write operation will have no effect
until the next falling edge of /CS.
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the FRAM technology. Unlike SPI-bus
EEPROMs, the FM25256B can perform sequential
writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Following this instruction is a two-
byte address value. The upper bit of the address is a
don’t care. In total, 15-bits specify the address of the
first byte of the read operation. After the op-code and
address are complete, the SI line is ignored. The bus
master issues 8 clocks, with one bit read out for each.
Addresses are incremented internally as long as the
bus master continues to issue clocks. If the last
address of 7FFFh is reached, the counter will roll
over to 0000h. Data is read MSB first. The rising
edge of /CS terminates a READ op-code operation.
A read operation is shown in Figure 10.
Write Operation
All writes to the memory array begin with a WREN
op-code. The next op-code is the WRITE instruction.
This op-code is followed by a two-byte address
value. The upper bit of the address is a “don’t care”.
In total, 15-bits specify the address of the first data
byte of the write operation. Subsequent bytes are data
and they are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks. If the last address of 7FFFh
is reached, the counter will roll over to 0000h. Data is
written MSB first. A write operation is shown in
Figure 9.
Hold
The /HOLD pin can be used to interrupt a serial
operation without aborting it. If the bus master pulls
the /HOLD pin low while SCK is low, the current
operation will pause. Taking the /HOLD pin high
while SCK is low will resume an operation. The
transitions of /HOLD must occur while SCK is low,
but the SCK and /CS pins can toggle during a hold
state.
Unlike EEPROMs, any number of bytes can be
written sequentially and each byte is written to
memory immediately after it is clocked in (after the
8th clock). The rising edge of /CS terminates a
WRITE op-code operation. Asserting /WP active in
Rev. 3.0
July 2007
Page 7 of 13
FM25256B
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
6
7
0
1
6
2
5
3
4
3
5
2
6
1
7
7
SCK
16-bit Address
12 11
Data In
4
Op-code
SI
0
0
0
1
0
X
14
13
1
0
7
0
0
0
0
0
MSB
LSB MSB
LSB
Hi-Z
SO
Figure 9. Memory Write
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
6
7
7
SCK
16-bit Address
12 11
Op-code
0
SI
0
0
0
1
1
X
14
13
1
0
0
0
MSB
LSB
Data Out
4
Hi-Z
SO
7
6
5
3
2
1
0
0
MSB
LSB
Figure 10. Memory Read
A14-A3 and column addresses by A2-A0. For the
FM25256B, there are 8 bytes per row. Each access
causes an endurance cycle for a given row. FRAM
read and write endurance is virtually unlimited even
at 20MHz clock rate. The table below shows that for
a 64-byte continuous loop, it would take more than
10 years to reach the endurance limit at 20MHz.
Endurance
The FM25256B device is capable of operating at
least 1014 read or write cycles. A FRAM memory
operates with
a read and restore mechanism.
Therefore, endurance cycles are applied for each read
or write cycle. The FRAM architecture is based on an
array of rows and columns. Rows are defined by
Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop
SCK Freq Endurance Endurance Years to Reach
(MHz) Cycles/sec. Limit
Cycles/year
20
10
5
298,000
149,000
74,600
14,900
9.40 x 1012
4.71 x 1012
2.35 x 1012
0.47 x 1012
10.6
21
42
1
212
Rev. 3.0
July 2007
Page 8 of 13
FM25256B
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
Ratings
-1.0V to +7.0V
-1.0V to +7.0V
and VIN < VDD+1.0V
-55°C to + 125°C
300° C
VDD
VIN
Power Supply Voltage with respect to VSS
Voltage on any pin with respect to VSS
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (JEDEC Std JESD22-A114-B)
- Charged Device Model (JEDEC Std JESD22-C101-A)
- Machine Model (JEDEC Std JESD22-A115-A)
Package Moisture Sensitivity Level
4kV
1kV
200V
MSL-1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40°C to + 85°C, VDD = 4.0V to 5.5V unless otherwise specified)
Symbol
VDD
IDD
Parameter
Power Supply Voltage
Power Supply Current
@ SCK = 1.0 MHz
@ SCK = 20.0 MHz
Standby Current
Input Leakage Current
Output Leakage Current
Input High Voltage
Input Low Voltage
Output High Voltage
@ IOH = -2 mA
Min
4.0
Typ
5.0
Max
5.5
Units
V
Notes
1
-
-
-
-
-
0.75
15.0
150
mA
mA
µA
µA
µA
V
ISB
ILI
ILO
VIH
VIL
VOH
2
3
3
±1
±1
VDD + 0.5
0.3 VDD
-
0.7 VDD
-0.3
VDD – 0.8
V
V
VOL
Output Low Voltage
@ IOL = 2 mA
-
0.4
V
Notes
1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. SCK = SI = /CS=VDD. All inputs VSS or VDD
.
3. VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD
.
Rev. 3.0
July 2007
Page 9 of 13
FM25256B
Notes
AC Parameters (TA = -40°C to + 85°C, VDD = 4.0V to 5.5V, CL = 30pF)
Symbol
fCK
tCH
tCL
Parameter
Min
0
28
28
10
10
Max
20
Units
MHz
ns
ns
ns
ns
ns
ns
ns
SCK Clock Frequency
Clock High Time
Clock Low Time
Chip Select Setup
Chip Select Hold
Output Disable Time
Output Data Valid Time
Output Hold Time
Deselect Time
1
1
tCSU
tCSH
tOD
tODV
tOH
tD
20
24
2
0
80
ns
tR
tF
tSU
tH
Data In Rise Time
Data In Fall Time
Data Setup Time
Data Hold Time
50
50
ns
ns
ns
ns
2,3
2,3
5
5
tHS
/Hold Setup Time
/Hold Hold Time
/Hold Low to Hi-Z
/Hold High to Data Active
10
10
ns
ns
ns
ns
tHH
tHZ
tLZ
25
20
2
2
Notes
1. tCH + tCL = 1/fCK
.
2. This parameter is characterized but not 100% tested.
3. Rise and fall times measured between 10% and 90% of waveform.
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 4.0V to 5.5V)
Symbol
tPU
tPD
tVR
tVF
Parameter
Power Up (VDD min) to First Access (/CS low)
Last Access (/CS high) to Power Down (VDD min)
VDD Rise Time
Min
10
0
Max
-
-
Units
ms
µs
Notes
50
1
1
µs/V
VDD Fall Time
- For VDD above 2.0V
- For VDD below 2.0V
50
1
-
-
µs/V
ms/V
Notes
1. Slope measured at any point on VDD waveform.
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 5.0V)
Symbol
CO
CI
Parameter
Output Capacitance (SO)
Input Capacitance
Min
-
-
Max
8
6
Units
pF
pF
Notes
1
1
Notes
1. This parameter is characterized and not 100% tested.
AC Test Conditions
Input Pulse Levels
10% and 90% of VDD
Input rise and fall times
Input and output timing levels
Output Load Capacitance
5 ns
0.5 VDD
30 pF
Rev. 3.0
July 2007
Page 10 of 13
FM25256B
Serial Data Bus Timing
/HOLD Timing
tHS
CS
tHH
SCK
tHH
tHS
HOLD
SO
tHZ
tLZ
Power Cycle Timing
VDD min
VDD
tVF
tVR
tPD
tPU
CS
Data Retention (VDD = 4.0V to 5.5V)
Parameter
Data Retention
Min
10
Max
-
Units
Years
Notes
Rev. 3.0
July 2007
Page 11 of 13
FM25256B
Mechanical Drawing
8-pin SOIC (JEDEC MS-012 variation AA)
Recommended PCB Footprint
7.70
3.70
3.90
±
0.10 6.00 ±0.20
2.00
Pin 1
0.65
1.27
0.25
0.50
4.90 ±0.10
1.35
1.75
0.19
0.25
°
45
0.10 mm
1.27
0.10
0.25
0°- 8°
0.40
1.27
0.33
0.51
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
Legend:
XXXXXXX= part number, P= package type
LLLLLLL= lot code
RIC=Ramtron Int’l Corp, YY=year, WW=work week
XXXXXXX-P
LLLLLLL
RICYYWW
Example: FM25256B, “Green” SOIC package, Year 2006, Work Week 39
FM25256B-G
B70003G
RIC0639
Rev. 3.0
July 2007
Page 12 of 13
FM25256B
Revision History
Revision
2.0
Date
4/4/07
7/9/07
Summary
Initial release.
3.0
Changed to Production status. Added ESD ratings. Updated endurance
section.
Rev. 3.0
July 2007
Page 13 of 13
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