FM25CL64-DG [RAMTRON]
Memory Circuit, 8KX8, CMOS, PDSO8, 4 X 4.50 MM, 0.95 MM PITCH, GREEN, TDFN-8;
| 型号： | FM25CL64-DG |
| 厂家： | 
RAMTRON INTERNATIONAL CORPORATION |
| 描述： | Memory Circuit, 8KX8, CMOS, PDSO8, 4 X 4.50 MM, 0.95 MM PITCH, GREEN, TDFN-8 光电二极管 |
| 文件： | 总14页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FM25CL64
64Kb Serial 3V F-RAM Memory
Sophisticated Write Protection Scheme
Features
64K bit Ferroelectric Nonvolatile RAM
•
•
Hardware Protection
Software Protection
•
•
•
•
•
Organized as 8,192 x 8 bits
Unlimited Read/Write Cycles
45 Year Data Retention
Low Power Consumption
•
•
Low Voltage Operation 2.7-3.65V
1 µA Standby Current
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Industry Standard Configuration
Very Fast Serial Peripheral Interface - SPI
•
•
•
Industrial Temperature -40°C to +85°C
•
•
•
Up to 20 MHz Frequency
8-pin “Green”/RoHS SOIC and TDFN Packages
Grade 3 AEC-Q100 Qualified (SOIC only)
Direct Hardware Replacement for EEPROM
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Description
Pin Configuration
The FM25CL64 is a 64-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 45 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
1
8
7
6
5
CS
SO
WP
VDD
HOLD
SCK
SI
2
3
4
VSS
VDD
/CS
SO
/WP
VSS
8
7
6
5
1
2
3
4
Unlike serial EEPROMs, the FM25CL64 performs
write operations at bus speed. No write delays are
incurred. Data is written to the memory array
immediately after each byte has been transferred to
the device. The next bus cycle may commence
without the need for data polling. In addition, the
product offers virtually unlimited write endurance,
orders of magnitude more endurance than EEPROM.
F-RAM also exhibits much lower power during
writes than EEPROM since write operations do not
require an internally elevated power supply voltage
for write circuits.
/HOLD
SCK
SI
Top View
Pin Name
/CS
Function
Chip Select
Write Protect
Hold
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage
Ground
These capabilities make the FM25CL64 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.
Ordering Information
FM25CL64-G †
“Green” 8-pin SOIC
“Green” 8-pin SOIC,
Tape & Reel
“Green” 8-pin TDFN
“Green” 8-pin TDFN,
Tape & Reel
FM25CL64-GTR †
The FM25CL64 provides substantial benefits to users
FM25CL64-DG
FM25CL64-DGTR
of serial EEPROM as
a
hardware drop-in
replacement. The FM25CL64 uses the high-speed
SPI bus, which enhances the high-speed write
FM25CL64-S *
8-pin SOIC
capability
of
F-RAM
technology.
Device
FM25CL64-STR *
8-pin SOIC, Tape & Reel
specifications are guaranteed over an industrial
temperature range of -40°C to +85°C.
† Grade 3 AEC-Q100 Qualified
* End of life. Last time buy June 2009.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Rev. 3.5
Feb. 2011
Page 1 of 14
FM25CL64
WP
CS
Instruction Decode
Clock Generator
Control Logic
HOLD
SCK
Write Protect
2,048 x 32
FRAM Array
Instruction Register
13
8
Address Register
Counter
SI
SO
Data I/O Register
3
Nonvolatile Status
Register
Figure 1. Block Diagram
Pin Descriptions
Pin Name
/CS
I/O
Input
Description
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
SCK
/HOLD
/WP
SI
Input
Input
Input
Input
Output
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 20 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
Write Protect: This active low pin prevents write operations to the Status Register.
This is critical since other write protection features are controlled through the Status
Register. A complete explanation of write protection is provided below. *Note that the
function of /WP is different from the FM25040 where it prevents all writes to the part.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet IDD specifications.
* SI may be connected to SO for a single pin data interface.
SO
Serial Output: This is the data output pin. It is driven during a read and remains tri-
stated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
VDD
VSS
Supply
Supply
Power Supply (2.7V to 3.65V)
Ground
Rev. 3.5
Feb. 2011
Page 2 of 14
FM25CL64
high performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25CL64 operates in SPI Mode 0 and 3.
Overview
The FM25CL64 is a serial F-RAM memory. The
memory array is logically organized as 8,192 x 8 and
is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the F-RAM is similar to serial EEPROMs. The
major difference between the FM25CL64 and a serial
EEPROM with the same pinout is the F-RAM’s
superior write performance.
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25CL64 devices
with a microcontroller that has a dedicated SPI port,
as Figure 2 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25CL64 device.
Memory Architecture
When accessing the FM25CL64, the user addresses
8,192 locations of 8 data bits each. These data bits
are shifted serially. The addresses are accessed using
the SPI protocol, which includes a chip select (to
permit multiple devices on the bus), an op-code, and
a two-byte address. The upper 3 bits of the address
range are ‘don’t care’ values. The complete address
of 13-bits specifies each byte address uniquely.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins (SI, SO) together and tie
off (high) the /HOLD pin. Figure 3 shows a
configuration that uses only three pins.
Most functions of the FM25CL64 either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation is essentially zero, beyond the
time needed for the serial protocol. That is, the
memory is read or written at the speed of the SPI bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. So, by the time a new bus transaction can be
shifted into the device, a write operation will be
complete. This is explained in more detail in the
interface section.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data pins. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25CL64 will begin monitoring
the clock and data lines. The relationship between the
falling edge of /CS, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25CL64 supports Modes 0 and 3. Figure 4 shows
the required signal relationships for Modes 0 and 3.
For both modes, data is clocked into the FM25CL64
on the rising edge of SCK and data is expected on the
first rising edge after /CS goes active. If the clock
begins from a high state, it will fall prior to beginning
data transfer in order to create the first rising edge.
Users expect several obvious system benefits from
the FM25CL64 due to its fast write cycle and high
endurance as compared with EEPROM. In addition
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/CS is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred. Note that the
WREN and WRDI op-codes are commands with no
subsequent data transfer.
Note: The FM25CL64 contains no power
management circuits other than a simple internal
power-on reset circuit. It is the user’s
responsibility to ensure that VDD is within
datasheet tolerances to prevent incorrect
operation. It is recommended that the part is not
powered down with chip enable active.
Important: The /CS pin must go inactive after an
operation is complete and before a new op-code
can be issued. There is one valid op-code only per
active chip select.
Serial Peripheral Interface – SPI Bus
The FM25CL64 employs
a
Serial Peripheral
Interface (SPI) bus. It is specified to operate at speeds
up to 20 MHz. This high-speed serial bus provides
Rev. 3.5
Feb. 2011
Page 3 of 14
FM25CL64
SCK
MOSI
MISO
SO SI
FM25CL64
CS HOLD
SCK
SO SI SCK
FM25CL64
SPI
Microcontroller
CS
HOLD
SS1
SS2
HOLD1
HOLD2
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS : Slave Select
Figure 2. System Configuration with SPI port
Figure 3. System Configuration without SPI port
SPI Mode 0: CPOL=0, CPHA=0
7
6
5
4
3
2
1
0
SPI Mode 3: CPOL=1, CPHA=1
7
6
5
4
3
2
1
0
Figure 4. SPI Modes 0 & 3
Rev. 3.5
Feb. 2011
Page 4 of 14
FM25CL64
Data Transfer
WREN - Set Write Enable Latch
All data transfers to and from the FM25CL64 occur
in 8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
The FM25CL64 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for write
operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
Command Structure
Sending the WREN op-code causes the internal Write
Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit – only
the WREN op-code can set this bit. The WEL bit will
be automatically cleared on the rising edge of /S
following a WRDI, a WRSR, or a WRITE operation.
This prevents further writes to the Status Register or
the F-RAM array without another WREN command.
Figure 5 below illustrates the WREN command bus
configuration.
There are six commands called op-codes that can be
issued by the bus master to the FM25CL64. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the Status
Register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
WRDI - Write Disable
Table 1. Op-code Commands
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in the
Status Register and verifying that WEL=0. Figure 6
illustrates the WRDI command bus configuration.
Name
Description
Op-code
00000110b
00000100b
00000101b
00000001b
00000011b
00000010b
Set Write Enable Latch
Write Disable
WREN
WRDI
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read Memory Data
Write Memory Data
Figure 5. WREN Bus Configuration
Figure 6. WRDI Bus Configuration
Rev. 3.5
Feb. 2011
Page 5 of 14
FM25CL64
RDSR - Read Status Register
WRSR – Write Status Register
The RDSR command allows the bus master to verify
the contents of the Status Register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR op-
code, the FM25CL64 will return one byte with the
contents of the Status Register. The Status Register is
described in detail in a later section.
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status Register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive. Note
that on the FM25CL64, /WP only prevents writing to
the Status Register, not the memory array. Prior to
sending the WRSR command, the user must send a
WREN command to enable writes. Note that
executing a WRSR command is a write operation and
therefore clears the Write Enable Latch.
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration (WREN not shown)
yellow). The WEL flag indicates the state of the
Status Register & Write Protection
Write Enable Latch. Attempting to directly write the
WEL bit in the Status Register has no effect on its
state. This bit is internally set and cleared via the
WREN and WRDI commands, respectively.
The write protection features of the FM25CL64 are
multi-tiered. First, a WREN op-code must be issued
prior to any write operation. Assuming that writes are
enabled using WREN, writes to memory are
controlled by the Status Register. As described
above, writes to the Status Register are performed
using the WRSR command and subject to the /WP
pin. The Status Register is organized as follows.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are write-
protected as shown in the following table.
Table 3. Block Memory Write Protection
Table 2. Status Register
BP1
BP0 Protected Address Range
Bit
7
6
0
5
0
4
0
3
BP1
2
BP0
1
0
0
0
0
1
1
0
1
0
1
None
Name WPEN
WEL
1800h to 1FFFh (upper ¼)
1000h to 1FFFh (upper ½)
0000h to 1FFFh (all)
Bits 0 and 4-6 are fixed at 0 and cannot be modified.
Note that bit
0 (“Ready” in EEPROMs) is
unnecessary as the F-RAM writes in real-time and is
never busy. The WPEN, BP1 and BP0 control write
protection features. They are nonvolatile (shaded
Rev. 3.5
Feb. 2011
Page 6 of 14
FM25CL64
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
This scheme provides a write protection mechanism,
which can prevent software from writing the memory
under any circumstances. This occurs if the BP1 and
BP0 are set to 1, the WPEN bit is set to 1, and /WP is
set to 0. This occurs because the block protect bits
prevent writing memory and the /WP signal in
hardware prevents altering the block protect bits (if
WPEN is high). Therefore in this condition, hardware
must be involved in allowing a write operation. The
following table summarizes the write protection
conditions.
The WPEN bit controls the effect of the hardware
/WP pin. When WPEN is low, the /WP pin is
ignored. When WPEN is high, the /WP pin controls
write access to the Status Register. Thus the Status
Register is write protected if WPEN=1 and /WP=0.
Table 4. Write Protection
WEL
WPEN
/WP
X
Protected Blocks
Protected
Unprotected Blocks
Protected
Unprotected
Unprotected
Unprotected
Status Register
Protected
0
1
1
1
X
0
X
Protected
Unprotected
Protected
1
0
1
Protected
Protected
1
Unprotected
(after the 8th clock). This allows any number of bytes
to be written without page buffer delays.
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the F-RAM technology. Unlike SPI-bus
EEPROMs, the FM25CL64 can perform sequential
writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Following the READ command is
a two-byte address value. The upper 3-bits of the
address are ignored. In total, the 13-bits specify the
address of the first byte of the read operation. This is
the starting address of the first byte of the read
operation. After the op-code and address are issued,
the device drives out the read data on the next 8
clocks. The SI input is ignored during read data
bytes. Subsequent bytes are data bytes, which are
read out sequentially. Addresses are incremented
internally as long as the bus master continues to issue
clocks and /CS is low. If the last address of 1FFFh is
reached, the counter will roll over to 0000h. Data is
read MSB first. The rising edge of /CS terminates a
READ operation. A read operation is shown in
Figure 10.
Write Operation
All writes to the memory begin with a WREN op-
code with /CS being asserted and deasserted. The
next op-code is WRITE. The WRITE op-code is
followed by a two-byte address value. The upper 3-
bits of the address are ignored. In total, the 13-bits
specify the address of the first data byte of the write
operation. This is the starting address of the first data
byte of the write operation. Subsequent bytes are data
bytes, which are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks and keeps /CS low. If the
last address of 1FFFh is reached, the counter will roll
over to 0000h. Data is written MSB first. The rising
edge of /CS terminates a WRITE operation. A write
operation is shown in Figure 9.
Hold
The /HOLD pin can be used to interrupt a serial
operation without aborting it. If the bus master pulls
the /HOLD pin low while SCK is low, the current
operation will pause. Taking the /HOLD pin high
while SCK is low will resume an operation. The
transitions of /HOLD must occur while SCK is low,
but the SCK pin can toggle during a hold state.
EEPROMs use page buffers to increase their write
throughput. This compensates for the technology’s
inherently slow write operations. F-RAM memories
do not have page buffers because each byte is written
to the F-RAM array immediately after it is clocked in
Rev. 3.5
Feb. 2011
Page 7 of 14
FM25CL64
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
op-code
13-bit Address
12 11 10
Data
X
X
X
4
3
2
1
0
7
6
5
4
3
2
1
0
SI
0
0
0
0
0
0
1
0
MSB
LSB MSB
LSB
SO
Figure 9. Memory Write (WREN not shown)
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
op-code
13-bit Address
12 11 10
X
X
X
4
3
2
1
0
0
0
0
0
0
0
1
1
MSB
LSB MSB
7
LSB
0
Data
SO
6
5
4
3
2
1
Figure 10. Memory Read
Rev. 3.5
Feb. 2011
Page 8 of 14
FM25CL64
Electrical Specifications
Absolute Maximum Ratings
Symbol
VDD
Description
Ratings
-1.0V to +5.0V
-1.0V to +5.0V
and VIN < VDD+1.0V
-55°C to + 125°C
300° C
Power Supply Voltage with respect to VSS
Voltage on any pin with respect to VSS
VIN
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (JEDEC Std JESD22-A114-B)
- Machine Model (JEDEC Std JESD22-A115-A)
Package Moisture Sensitivity Level
4kV
300V
MSL-1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 3.65V unless otherwise specified)
Symbol Parameter
Min
Typ
Max
Units
Notes
VDD
IDD
Power Supply Voltage
2.7
3.3
3.65
V
VDD Supply Current
@ SCK = 1.0 MHz
@ SCK = 20.0 MHz
Standby Current
1
-
-
0.35
7
1
mA
mA
µA
µA
µA
V
ISB
ILI
ILO
VIH
VIL
VOH
-
-
-
2
3
3
Input Leakage Current
Output Leakage Current
Input High Voltage
Input Low Voltage
Output High Voltage
@ IOH = -2 mA
Output Low Voltage
@ IOL = 2 mA
Input Hysteresis
1
1
VDD + 0.5
0.3 VDD
-
0.7 VDD
-0.3
VDD – 0.8
V
V
VOL
-
0.4
-
V
V
VHYS
Notes
0.05 VDD
4
1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. SCK = SI = /CS=VDD. All inputs VSS or VDD
.
3.
VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD.
4. Characterized but not 100% tested in production. Applies only to /CS and SCK pins.
Rev. 3.5
Feb. 2011
Page 9 of 14
FM25CL64
Notes
AC Parameters (TA = -40° C to + 85° C, CL = 30pF)
VDD 2.7 to 3.0V
VDD 3.0 to 3.65V
Symbol
fCK
tCH
Parameter
Min
Max
Min
0
Max
20
Units
MHz
ns
SCK Clock Frequency
Clock High Time
Clock Low Time
0
18
25
25
10
10
22
22
10
10
1
1
tCL
ns
tCSU
tCSH
tOD
tODV
tOH
tD
Chip Select Setup
Chip Select Hold
Output Disable Time
Output Data Valid Time
Output Hold Time
Deselect Time
ns
ns
20
25
20
20
ns
2
ns
0
60
0
60
ns
ns
tR
Data In Rise Time
Data In Fall Time
Data Setup Time
50
50
50
50
ns
2,3
2,3
tF
ns
tSU
5
5
10
10
5
5
10
10
ns
tH
Data Hold Time
ns
tHS
/HOLD Setup Time
/HOLD Hold Time
/HOLD Low to Hi-Z
/HOLD High to Data Active
ns
tHH
tHZ
ns
20
20
20
20
ns
2
2
tLZ
ns
Notes
1. tCH + tCL = 1/fCK
.
2. Characterized but not 100% tested in production.
3. Rise and fall times measured between 10% and 90% of waveform.
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V)
Symbol Parameter
Min
-
-
Max
8
6
Units
pF
pF
Notes
1
1
CO
CI
Output Capacitance (SO)
Input Capacitance
Notes
1. This parameter is periodically sampled and not 100% tested.
AC Test Conditions
Input Pulse Levels
10% and 90% of VDD
Input rise and fall times
Input and output timing levels
Output Load Capacitance
5 ns
0.5 VDD
30 pF
Rev. 3.5
Feb. 2011
Page 10 of 14
FM25CL64
Serial Data Bus Timing
tD
tCSH
tF
tR
tCL
tCH
tCSU
tSU
1/fCK
tH
tODV
tOH
tOD
/Hold Timing
Data Retention (VDD = 2.7V to 3.65V, +85°C)
Parameter
Min
45
Max
-
Units
Years
Notes
Data Retention
Rev. 3.5
Feb. 2011
Page 11 of 14
FM25CL64
Mechanical Drawings
8-pin SOIC (JEDEC MS-012 variation AA)
Recommended PCB Footprint
7.70
3.70
3.90
±
0.10 6.00 ±0.20
2.00
Pin 1
0.65
1.27
0.25
0.50
4.90 ±0.10
1.35
1.75
0.19
0.25
°
45
0.10 mm
1.27
0.10
0.25
0°- 8°
0.40
1.27
0.33
0.51
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
Legend:
XXXXX= part number, P= package type, T= temperature (A=automotive, blank=ind.)
LLLLLLL= lot code
XXXXXX-PT
LLLLLLL
RICYYWW
RIC=Ramtron Int’l Corp, YY=year, WW=work week
Example: FM25CL64, “Green” SOIC package, Year 2006, Work Week 29
FM25CL64G
A60013G1
RIC0629
Rev. 3.5
Feb. 2011
Page 12 of 14
FM25CL64
8-pin TDFN (4.0mm x 4.5mm body, 0.95mm pitch)
Exposed metal pad.
Do not connect to
anything except Vss.
4.50 ±0.1
3.60 ±0.10
Pin 1 ID
Pin 1
2.85 REF
0.30 ±0.1
0.0 - 0.05
0.75 ±0.05
Recommended PCB Footprint
0.20 REF.
0.95
0.40 ±0.05
3.70
4.30
2.70
0.50
0.95
0.50
Note: All dimensions in millimeters.
TDFN Package Marking Scheme for Body Size 4.0mm x 4.5mm
Legend:
R=Ramtron, G=”green”/RoHS TDFN package, XXXX=base part number
LLLL= lot code,
RGXXXX
LLLL
YY=year, WW=work week
YYWW
Example: “Green” TDFN package, FM25CL64, Lot 0013, Year 2006, Work Week 29
RG5L64
0013
0629
Rev. 3.5
Feb. 2011
Page 13 of 14
FM25CL64
Revision History
Revision
0.0
Date
5/10/01
7/5/01
Summary
Initial Release
0.1
Updated AC and DC specifications. Changed AC Test Conditions and Load
Circuit.
Added unlimited endurance bullet. Changed Data Retention table.
Changed operating Vdd voltage range to 3.0 – 3.65V. Reduced Idd supply
current limits.
0.2
0.3
10/11/01
1/8/02
2.0
2.1
2/19/03
4/22/03
Updated to Production status. Added note to Output Data Valid spec.
Changed operating Vdd voltage range to 2.7 – 3.65V with separate AC timing
specs defined below 3.0V operation. Reduced input leakage spec.
Added “green” package. Updated package mechanical drawing.
Added DFN packaging option. Added DFN mechanical drawing. New rev.
number to comply with updated scheme.
2.2
3.0
3/17/04
9/3/04
3.1
3/9/05
Improved Data Retention spec to 45 years. Removed “preliminary” from DFN
package drawing. Added note about powering down with /CS active (pg 3).
Added ESD and package MSL ratings.
3.2
3.3
7/19/05
2/28/08
Changed DFN name to TDFN. Added TDFN pcb footprint. Corrected TDFN
package heading from 0.65mm to 0.95mm.
Removed –S package option. It is not recommended for new designs, use –G
instead. Changed/improved IDD spec limits. Removed 5MHz IDD entry.
Changed TDFN Package Marking Scheme.
3.31
3.4
6/3/2008
5/26/2009
Removed sentence referencing Table 4 from Write Operation paragraph (p. 7).
Added tape and reel ordering information. Added note that SOIC device is
Grade 3 AEC-Q100 qualified. Added last time buy notice on –S
ordering numbers.
3.5
2/18/2011
Not recommended for new designs. Alternative: FM25CL64B.
Rev. 3.5
Feb. 2011
Page 14 of 14
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