SM12809DT-6.6 [RAMTRON]
Synchronous DRAM Module, 32MX72, 4.5ns, CMOS, DIMM-168;
| 型号： | SM12809DT-6.6 |
| 厂家： | 
RAMTRON INTERNATIONAL CORPORATION |
| 描述： | Synchronous DRAM Module, 32MX72, 4.5ns, CMOS, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Preliminary Data Sheet
Features
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
•
•
JEDEC PC-133 SDRAM DIMM Compatible
CAS 2 150MHz Modules (2:3:2) @ 150 MHz
1
Vss
DQ0
DQ1
DQ2
DQ3
Vdd
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Vss
DNU
S2#
85
86
Vss
DQ32
DQ33
DQ34
DQ35
Vdd
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Vss
CKE0
S3#
2
•
•
•
CAS Latency = 2
RAS to CAS Delay = 3
Precharge Delay = 2
3
87
4
DQMB2
DQMB3
DNU
Vdd
88
DQMB6
DQMB7
RFU
Vdd
5
89
•
•
•
•
•
•
•
•
•
Fast 4.5 ns Clock Access Time
6
90
Overclock Existing PC Systems to 150 MHz +
Ideal for Low Cost 150 MHz Bus Speed Systems
Supports CAS Latency = 2, 3
On-board Serial Presence Detect (SPD)
Unbuffered 168-pin DIMM
7
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
91
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
8
NC
92
NC
9
NC
93
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CB2
94
CB6
4K Refresh / 64 ms
CB3
95
CB7
Single 3.3V ± 0.3V Power Supply
Available on-line at http://www.pc133memory.com or
http://www.mushkin.com
Vss
96
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vdd
DQ16
DQ17
DQ18
DQ19
Vdd
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vdd
DQ48
DQ49
DQ50
DQ51
Vdd
98
99
Description
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
The Enhanced Memory Systems 64MB and 128MB CAS 2
150MHz HSDRAM DIMMs are the fastest unbuffered
SDRAM DIMMs available. Low latency (2:3:2) at 150 MHz
improves performance in high-end desktop publishing and
graphics applications, particularly with UMA system
architectures. The fast 4.5 ns clock access time allows
unbuffered DIMM operation at 150 MHz for lower memory
latency, and lower costs than registered DIMMs.
DQ20
NC
DQ52
NC
DQ14
DQ15
CB0
CB1
Vss
DQ46
DQ47
CB4
NC
NC
CKE1
Vss
NC
CB5
Vss
DQ21
DQ22
DQ23
Vss
Vss
DQ53
DQ54
DQ55
Vss
The 64MB module (SM6408DT-6.6) is organized as 8Mx64,
and the 128MB module (SM12808DT-6.6) is organized as
16Mx64. The 128MB ECC module (SM12809DT-6.6) is
organized as 16Mx72. Each module contains a serial
presence EEPROM programmed by Enhanced Memory
Systems, which contains information on the module type,
module organization, component speed, and other attributes
relevant to the system controller.
NC
NC
NC
NC
Vdd
Vdd
WE#
DQMB0
DQMB1
S0#
DQ24
DQ25
DQ26
DQ27
Vdd
CAS#
DQMB4
DQMB5
S1#
DQ56
DQ57
DQ58
DQ59
Vdd
DNU
Vss
RAS#
Vss
DQ28
DQ29
DQ30
DQ31
Vss
DQ60
DQ61
DQ62
DQ63
Vss
A0
A1
A2
A3
A4
A5
A6
A7
A8
CK2
A9
CK3
A10/AP
BA1
Vdd
NC
BA0
NC
WP
A11
SA0
SDA
SCL
Vdd
SA1
Vdd
CK1
SA2
CK0
Vdd
RFU
Vdd
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 1 of 12
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Preliminary Data Sheet
Pin Descriptions
Symbol
CK0,1,2,3
CKE0,1
Type
Input
Input
Function
Clocks: All SDRAM input signals are sampled on the positive edge of CK.
Clock Enables: CKE activate (high) or deactivate (low) the CK signals. Deactivating the clock initiates the
Power-Down and Self-Refresh operations (all banks idle), or Clock Suspend operation. CKE is synchronous until
the device enters Power-Down and Self-Refresh modes where it is asynchronous until the mode is exited.
S0,1,2,3#
Input
Input
Chip Select: S# enables (low) or disables (high) the command decoder. When the command decoder is
disabled, new commands are ignored but previous operations continue.
RAS#, CAS#,
WE#
Command Inputs: Sampled on the rising edge of CK, these inputs define the command to be executed.
Bank Addresses: These inputs define to which of the 4 banks a given command is being applied.
BA1, BA0
A0-A11
Input
Input
Address Inputs: A0-A11 define the row address during the Bank Activate command. A0-A8 define the column
address during Read and Write commands. A10/AP invokes the Auto-precharge operation. During manual
Precharge commands, A10/AP low specifies a single bank precharge while A10/AP high precharges all banks.
The address inputs are also used to program the Mode Register.
DQ0-DQ63
Input/
Output
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these pins and must be set-up
and held relative to the rising edge of clock. For Read cycles, the device drives output data on these pins after
the CAS latency is satisfied.
DQMB0-7
CB0-7
Input
Data I/O Mask Inputs: DQMB0-7 inputs mask write data (zero latency) and acts as a synchronous output enable
(2-cycle latency) for read data.
Input/
Output
Supply
ECC Check Bits
VDD
VSS
Power Supply: +3.3 V
Ground
Supply
SDA
Input/
Output
Serial Presence-Detect Data: SDA is a bi-directional pin used to transfer addresses and data into
and data out of the presence-detect portion of the module.
SCL
Input
Serial Clock for Presence-Detect: SCL is used to synchronize the presence detect data transfer to
and from the module
SA0-2
WP
Input
Input
Presence-Detect Address Inputs: These pins are used to configure the presence detect device.
Serial Presence Detect Write Protect: Active high inhibits writes to the SPD EEPROM. WP must be driven low
for normal read/write operations.
RFU
DNU
NC
-
-
-
Reserved for Future Use: These pins should be left unconnected.
Do not use.
No connect - open pin.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 2 of 12
Revision 1.0
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Preliminary Data Sheet
64MB DIMM Functional Block Diagram – SM6408DT-6.6
S0#
Clock Wiring
4 SDRAM+3.3 pf
Termination
4 SDRAM+3.3 pf
Termination
CK0
CK1
CK2
CK3
DQMB0
DQMB1
DQMB4
DQMB5
U0
U1
U4
DQ(7:0)
DQ(39:32)
DQ(47:40)
10
CK0,2
SDRAMs
U5
DQ(15:8)
Clock Termination
10
CK1,3
10 pf
S2#
DQMB2
DQMB6
DQMB7
SDA
WP
SCL
U2
U3
U6
Serial PD
DQ(23:16)
DQ(55:48)
DQ(63:56)
SA0-2
47K
BA0
BA0 SDRAM U0-7
BA1 SDRAM U0-7
DQMB3
BA1
A0-A11
Vdd
U7
DQ(31:24)
A0-A11 SDRAM U0-7
Vdd SDRAM U0-7
Vss
Vss SDRAM U0-7
RAS#
RAS# SDRAM U0-7
CAS# SDRAM U0-7
WE# SDRAM U0-7
CKE0 SDRAM U0-7
CAS#
WE#
CKE0
Note: All DQ resistor values are 10 ohms
All CK resistor values are 10 ohms
U0-U7 are SM3603T-6.6
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 3 of 12
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Preliminary Data Sheet
128MB DIMM Functional Block Diagram – SM12808DT-6.6
S0#
S1#
Clock Wiring
DQMB0
DQ(7:0)
DQMB4
U4
U5
U12
U13
U0
U1
U8
U9
4 SDRAM+3.3 pf
4 SDRAM+3.3 pf
4 SDRAM+3.3 pf
4 SDRAM+3.3 pf
DQ(39:32)
CK0
CK1
CK2
CK3
DQMB5
DQMB1
DQ(47:40)
DQ(15:8)
10
CK0-3
SCL
SDRAMs
S2#
S3#
DQMB2
DQMB6
U6
U7
U14
U15
U2
U3
U10
U11
DQ(55:48)
DQ(23:16)
SDA
Serial PD
WP
SA0-2
47K
DQMB7
DQMB3
DQ(63:56)
DQ(31:24)
BA0
BA1
BA0 SDRAM U0-15
BA1 SDRAM U0-15
A0-A11 SDRAM U0-15
Vdd SDRAM U0-15
A0-A11
Vdd
Vss
Vss SDRAM U0-15
RAS#
RAS# SDRAM U0-15
CAS# SDRAM U0-15
WE# SDRAM U0-15
CKE0 SDRAM U0-7
CAS#
WE#
CKE0
Vdd
10K
CKE1
CKE1 SDRAM U8-15
Note: All DQ resistor values are 10 ohms
All CK resistor values are 10 ohms
U0-U15 are SM3603T-6.6
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 4 of 12
Revision 1.0
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Preliminary Data Sheet
128MB ECC DIMM Functional Block Diagram – SM12809DT-6.6
S0#
S1#
Clock Wiring
DQMB0
DQ(7:0)
DQMB4
5 SDRAM
5 SDRAM
4 SDRAM+3.3 pf
4 SDRAM+3.3 pf
CK0
CK1
CK2
CK3
U5
U6
U14
U15
U0
U1
U2
U9
U10
U11
DQ(39:32)
DQMB5
DQMB1
DQ(47:40)
DQ(15:8)
10
CK0-3
SCL
SDRAMs
Note: SDRAM U11 DQM input MUST
be wired to DQMB5
CB(7:0)
S2#
SDA
S3#
Serial PD
WP
SA0-2
47K
DQMB2
DQMB6
U7
U8
U16
U17
U3
U4
U12
U13
DQ(55:48)
DQ(23:16)
BA0
BA1
BA0 SDRAM U0-17
BA1 SDRAM U0-17
A0-A11 SDRAM U0-17
Vdd SDRAM U0-17
DQMB7
DQMB3
A0-A11
Vdd
DQ(63:56)
DQ(31:24)
Vss
Vss SDRAM U0-17
RAS#
RAS# SDRAM U0-17
CAS# SDRAM U0-17
WE# SDRAM U0-17
CKE0 SDRAM U0-8
CAS#
WE#
CKE0
Vdd
10K
CKE1
CKE1 SDRAM U9-17
Note: All DQ resistor values are 10 ohms
All CK resistor values are 10 ohms
U0-U15 are SM3603T-6.6
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 5 of 12
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Preliminary Data Sheet
Electrical Characteristics
Absolute Maximum Ratings
Description
Symbol
VDD
Value
Power Supply Voltage
-1V to +4.6V
Voltage on any Pin with Respect to Ground
Operating Temperature (ambient)
Storage Temperature
VIN, VOUT
TA
-0.5V to +4.6V
0°C to +70°C
-55°C to +125°C
TBD
Tstg
Power Dissipation
PD
DC Output Current (I/O pins)
IOUT
50mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these, or any other conditions above those listed in the operational section of the
specification, is not implied. Exposure to conditions at absolute maximum ratings for extended periods may affect device reliability.
DC Operating Conditions (TA = 0°C to 70°C)
Symbol
VDD
VIH
Parameter
Supply Voltage
Min
3.0
2.0
-0.3
-
Typical
Max
3.6
Units
V
Notes
3.3
Input High Voltage
3.3
VDD + 0.3
0.8
V
VIL
Input Low Voltage
0.0
V
II(L)
Input Leakage Current
-
-
-
-
±1
µA
µA
V
IO(L)
VOH
VOL
Output Leakage Current
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = +4mA)
-
±1
2.4
0.0
VDD
0.4
V
Capacitance (TA = 25°C, f = 1MHz, VDD = 3.3V ±0.3V, not 100% tested)
Symbol
Parameter
64MB
non-ECC
38
128MB
non-ECC
Units
ECC
71
24
26
42
14
12
12
13
CIn1
CIn2
CIn3
CIn4
CIn5
CIn6
CI/O1
CI/O2
Input Capacitance (BA1, BA0, A0-11, RAS, CAS)
Input Capacitance (S0 - S3)
65
21
26
38
14
12
12
13
pF
pF
pF
pF
pF
pF
pF
pF
21
Input Capacitance (CK0 - CK3)
Input Capacitance (CKE0, CKE1)
Input Capacitance (DQMB0-7)
Input Capacitance (SCL, SA0-2)
I/O Capacitance (SDA)
26
38
12
12
12
I/O Capacitance (DQ0-63, CB0-7)
8.5
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 6 of 12
Revision 1.0
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Preliminary Data Sheet
AC Characteristics (TA = 0°C to 70°C)
1. An initial pause of 200µs is required after power-up, then a Precharge All Banks command must be given followed by a minimum
of eight Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.
2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the VTT = 1.4V crossover point.
VTT
tT
VIH
VTT
VIL
Clock
RT = 50 ohm
tSETUP tHOLD
Z0 = 50 ohm
Output
Input
CLOAD = 50pF
tOH
tAC
tLZ
VTT
Output
AC Output Load Circuit
3. The transition time is measured between VIH and VIL (or between VIH and VIL).
4. AC measurements assume tT = 1ns.
5. In addition to meeting the transition rate specification, the clock and CKE must transition VIH and VIL (or between VIH and VIL) in
a monotonic manner.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 7 of 12
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Preliminary Data Sheet
AC Operating Conditions (TA = 0°C to 70°C)
Clock and Clock Enable Parameters
Symbol
Parameter
-6.6
Units
Notes
Min
6.6
6.6
2.5
2.5
1.5
0.8
1.5
-
Max
tCK3
Clock Cycle Time, CL = 3
ns
ns
ns
ns
ns
ns
ns
ns
tCK2
Clock Cycle Time, CL = 2
tCKH3, tCKL3
tCKH2, tCKL2
tCKES
Clock High & Low Times, CL=3
Clock High & Low Times, CL=2
Clock Enable Set-Up Time
Clock Enable Hold Time
-
-
1
1
-
tCKEH
-
tCKSP
CKE Set-Up Time (Power down mode)
Transition Time (Rise and Fall)
-
tT
4
Notes:
1. Assumes clock rise and fall times are equal to 1ns. If rise or fall time exceeds 1ns, other AC timing parameters must be compensated by an
additional [(trise+tfall)/2-1] ns.
Common Parameters
Symbol
Parameter
-6.6
Units
Notes
Min
1.5
Max
tCS
Command and Address Set-Up Time
Command and Address Hold Time
RAS to CAS Delay Time
-
ns
ns
tCH
0.8
-
tRCD
tRC
tRAS
tRP
18.0
53.3
33.3
13.3
13.3
6.6
-
ns
Bank Cycle Time
120K
ns
Bank Active Time
120K
ns
Precharge Time
-
-
-
-
ns
tRRD
tCCD
tMRD
Bank to Bank Delay Time (Alt. Bank)
CAS to CAS Delay Time (Same Bank)
Mode Register Set to Active Delay
ns
ns
2
CLK
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 8 of 12
Revision 1.0
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Preliminary Data Sheet
Read and Write Parameters
Symbol
Parameter
-6.6
Units
Notes
Min
-
Max
tAC3
tAC2
tOH3
tOH2
tLZ
Clock Access Time, CL = 3
Clock Access Time, CL = 2
Data Output Hold Time (CL=3)
Data Output Hold Time (CL=2)
Data Output to Low-Z Time
Data Output to High-Z Time (CL=2, 3)
Data Input Set-Up Time
4.5
ns
ns
1,2
1,2
-
4.5
2.7
2.7
1
-
ns
-
ns
-
ns
tHZ2
tDS
-
4.5
ns
3
4
1.5
0.8
13.3
4
-
-
-
-
-
-
ns
tDH
Data Input Hold Time
ns
tDPL
tDAL
tDQW
Data Input to Precharge
ns
Data Input to ACTV/Refresh
Data Write Mask Latency
CLK
CLK
CLK
0
tDQZ
DQM Data Output Disable Time
2
Notes:
1. Access time is measured at 1.4V (LVTTL) at max clock rate for the CAS latency specified. See AC Test Load.
2. Access time is based on a clock rise time of 1ns. If clock rise time is longer than 1ns, then (trise/2-0.5) ns must be added to the access time.
3. Referenced to the time at which the output achieves an open circuit condition.
4. tDAL is equal to tDPL + tRP and can be less than 4 clocks if tDPL and tRP are both satisfied.
Refresh Parameters
Symbol
Parameter
-6.6
Units
Notes
Min
-
Max
64
-
tREF
Refresh Period
ms
ns
ns
1, 2
3
tSREX
Self Refresh Exit Time
Refresh Cycle Time
2CLK+tRC
60.0
tRFC
Notes:
1. 4096 cycles.
2. Any time that the refresh period has been exceeded, a minimum of two Auto-Refresh (CBR) commands must be given to “wake up” the device.
3. Self-Refresh exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self-Refresh Exit is not
completed until tRC is satisfied once the Self-Refresh Exit command is registered.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 9 of 12
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Preliminary Data Sheet
Serial Presence Detect (SPD) for PC-150 DIMMs
64MB
8Mx8 (8 pcs)
128MB
2 x 8Mx8 (16 pcs)
64MB
8Mx8 (8)
128MB
2 x 8Mx8 (8)
Byte
Description
** HEX CODE **
0
1
2
3
4
5
6
Number of bytes written into EEPROM
Total number of SPD bytes
Memory Type
128
256
SDRAM
12
9
1
x64
128
256
SDRAM
12
9
2
x64
x72
80
08
04
0C
09
01
40
80
08
04
0C
09
02
40
48
00
01
66
45
00
02
80
08
00
08
01
8F
04
06
01
01
00
0E
66
45
00
00
0E
0E
12
22
10
15
08
15
08
00
12
18
2A
Number of Row Addresses
Number of Column Addresses
Number of Module Banks
Module Data Width
x64
x72
7
8
9
10
11
Module Data Width (cont’d)
Voltage Interface Levels
Cycle Time at max CAS Latency
SDRAM Clock Access Time (CL=3)
DIMM config (non-parity, parity, ECC)
0
0
00
01
66
45
00
LVTTL
6.6 ns
4.5 ns
LVTTL
6.6 ns
4.5 ns
x64
x72
--- Non-parity ---
--- ECC ---
12
13
14
Refresh Rate and Type
Primary SDRAM Width
Error Checking Data Width
--- 15.625us / Self ---
x8
N/A
80
08
00
x8
N/A
x8
x64
x72
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
Min. CAS-to-CAS Delay (tCCD)
Burst Lengths Supported
Number of Banks on SDRAM Device
CAS Latencies Supported
CS Latency
1 clk
1 clk
01
8F
04
06
01
01
00
0E
66
45
00
00
0E
0E
12
22
10
15
08
15
08
00
12
17
--- 1,2,4,8,Full Pg ---
4
2,3
0
4
2,3
0
Write Latency
0
0
SDRAM Module Attributes
SDRAM Device Attributes
Min. Clock Cycle Time at CL=2
Clock Access Time at CL=2 (tAC2)
Min. Clock Cycle Time at CL=1
Clock Access Time at CL=1 (tAC1)
Min. Row Precharge Time (tRP)
Min. Row-to-Row Delay (tRRD)
Min. RAS-to-CAS Delay (tRCD)
Min. RAS Pulse Width (tRAS)
Density of each bank on module
Cmd/Addr input set-up time
Cmd/Addr input hold time
Data input set-up time
--- Unbuffered ---
+/-10% Vdd, Precharge All, Wr-1/RdBrst
6.6 ns
4.5 ns
N/A
6.6 ns
4.5 ns
N/A
N/A
N/A
13.3 ns
13.3 ns
18 ns
33.3 ns
64MB
1.5 ns
0.8 ns
1.5 ns
0.8 ns
-
13.3 ns
13.3 ns
18 ns
33.3 ns
64MB
1.5 ns
0.8 ns
1.5 ns
0.8 ns
Data input hold time
Superset Information
SPD Rev.
Checksum for bytes 0-62
1.2
x64
x72
64-71
72
JEDEC ID code
Enhanced Memory Systems
SM6408DT SM12808DT
7F32FFFFFFFFFFFF
Manufacturing Location
Manufacturer’s Part #
PCB Rev. Code
Manufacturing Date
Assembly Serial #
Manufacturer’s Specific Data
Intel specification frequency
Intel specification CL and clock support
xxxx
xxxx
rrrr
xxxx
xxxx
rrrr
73-90
91,92
93,94
95-98
99-125
126
yyww code
serial number
open
yyww
ssss
00
yyww
ssss
00
133MHz
85
85
127
A5
F5
128-255 Open for Customer Use
00
00
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 10 of 12
Revision 1.0
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Preliminary Data Sheet
Revision Log
Revision
Date
Summary of Changes
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 11 of 12
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Preliminary Data Sheet
Ordering Information
These CAS2/150MHz HSDRAM DIMMs may be purchased on-line at http://www.pc133memory.com, or http://www.mushkin.com,
which are e-commerce functions of Enhanced Memory Systems Inc., or call 1-800-569-1868.
Maximum
Operating
Frequency
(MHz)
Part Number
Capacity
I/O Width
I/O Type
Package
Power
Supply
SM6408DT-6.6
SM12808DT-6.6
SM12809DT-6.6
64 MB
128 MB
128 MB
x64
x64
x72
LVTTL
LVTTL
LVTTL
168-pin DIMM
168-pin DIMM
168-pin DIMM
3.3V
3.3V
3.3V
150
150
150
Note: Enhanced Memory Systems Low Latency PC-150 HSDRAM DIMMs are labeled per the Intel PC SDRAM DIMM Naming
Convention. This convention requires identification of the bus speed, latency, clock access time, and SPD revision code. The code for
these DIMM modules is PC150-232-45120.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 12 of 12
Revision 1.0
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