ALC262-VB0-GR [REALTEK]
4-CHANNEL DAC AND 6-CHANNEL ADC HIGH DEFINITION AUDIO CODEC;
| 型号： | ALC262-VB0-GR |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | 4-CHANNEL DAC AND 6-CHANNEL ADC HIGH DEFINITION AUDIO CODEC |
| 文件： | 总87页 (文件大小：1649K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC262-GR
ALC262-VB Series
(ALC262-VB0-GR, ALC262SRS-GR, ALC262H-GR)
ALC262-VC Series (ALC262-VC1-GR, ALC262-VC2-GR)
ALC262-VD Series (ALC262-VD2-GR, ALC262W-VD2-GR)
4-CHANNEL DAC AND 6-CHANNEL ADC
HIGH DEFINITION AUDIO CODEC
DATASHEET
Rev. 1.9
15 April 2008
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
ALC262 Series
Datasheet
COPYRIGHT
©2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC262 Series Audio Codecs.
Though every effort has been made to ensure that this document is current and accurate, more
information may have become available subsequent to the production of this guide. In that event, please
contact your Realtek representative for additional information that may help in the development process.
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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ALC262 Series
Datasheet
REVISION HISTORY
Revision
Release Date Summary
1.0
2005/05/02
2005/06/09
First release.
1.1
Update section 12 Ordering Information, page 78.
Revise analog output port information in section 1 General Description, page 1.
Add ordering information note (see section 12 Ordering Information, page 78).
Revise Figure 2, page 7.
1.2
1.3
2005/08/25
2005/10/17
Revise Table 84, page 72.
Update section 122 Ordering Information, page 78.
Update section 12 Ordering Information, page 78.
Release for ALC262 ‘C’ version.
1.4
1.5
2005/11/25
2006/06/22
Revise section 4 Block Diagram, page 6
Improve DAC/ADC filter characteristics, Table 79, page 68.
Support low voltage (1.5V~3.3V) IO for HAD link.
Add digital microphone input support (pins 2 and 46), see Figure 5, page 10.
Add digital microphone application note (section 10.4 Digital Microphone
Implementation, page 74).
Update section 12 Ordering Information, page 78.
Update section 12 Ordering Information, page 78.
Cosmetic changes to Figure 5, page 10.
1.6
1.7
1.8
2007/01/15
2007/01/22
2007/07/04
Release for ALC262 ‘D’ version.
This release was never checked/reviewed/approved
Supports 2nd SPDIF output:
Update section 8.2 Verb – Get Connection Select Control (Verb ID=F01h), page 40.
Update section 8.3 Verb – Set Connection Select (Verb ID=701h), page 41.
Meets Intel low power ECR compliant and power status control for all analog converter
and pin widgets. See section 7.5 Power Management, page 28.
1.9
2008/04/15
Added information for all ALC262 series (version A/B/C/D).
Added part number ALC262W-VD2-GR in section 12 Ordering Information, page 78.
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ALC262 Series
Datasheet
Table of Contents
1.
2.
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................3
2.1.
2.2.
HARDWARE FEATURES ................................................................................................................................................3
SOFTWARE FEATURES..................................................................................................................................................4
3.
4.
SYSTEM APPLICATIONS...............................................................................................................................................5
BLOCK DIAGRAM...........................................................................................................................................................6
4.1.
ALC262 A/B VERSION ................................................................................................................................................6
ALC262 C VERSION ....................................................................................................................................................7
ALC262 D VERSION....................................................................................................................................................8
ANALOG INPUT/OUTPUT UNIT .....................................................................................................................................9
4.2.
4.3.
4.4.
5.
PIN ASSIGNMENTS .......................................................................................................................................................10
5.1.
ALC262 A/B VERSION ..............................................................................................................................................10
GREEN PACKAGE AND VERSION IDENTIFICATION ......................................................................................................10
ALC262 C VERSION ..................................................................................................................................................11
GREEN PACKAGE AND VERSION IDENTIFICATION ......................................................................................................11
ALC262 D VERSION..................................................................................................................................................12
GREEN PACKAGE AND VERSION IDENTIFICATION ......................................................................................................12
5.2.
5.3.
5.4.
5.5.
5.6.
6.
7.
PIN DESCRIPTIONS.......................................................................................................................................................13
6.1.
DIGITAL I/O PINS.......................................................................................................................................................13
ANALOG I/O PINS ......................................................................................................................................................13
FILTER/REFERENCE....................................................................................................................................................14
POWER/GROUND........................................................................................................................................................14
6.2.
6.3.
6.4.
HIGH DEFINITION AUDIO LINK PROTOCOL .......................................................................................................15
7.1.
LINK SIGNALS............................................................................................................................................................15
7.1.1. Signal Definitions.................................................................................................................................................16
7.1.2. Signaling Topology...............................................................................................................................................17
7.2.
FRAME COMPOSITION ................................................................................................................................................18
7.2.1. Outbound Frame – Single SDO............................................................................................................................18
7.2.2. Outbound Frame – Multiple SDO ........................................................................................................................19
7.2.3. Inbound Frame – Single SDI................................................................................................................................20
7.2.4. Inbound Frame – Multiple SDI ............................................................................................................................21
7.2.5. Variable Sample Rates .........................................................................................................................................21
7.3.
RESET AND INITIALIZATION .......................................................................................................................................24
7.3.1. Link Reset .............................................................................................................................................................24
7.3.2. Codec Reset..........................................................................................................................................................25
7.3.3. Codec Initialization Sequence ..............................................................................................................................26
7.4.
VERB AND RESPONSE FORMAT ..................................................................................................................................27
7.4.1. Command Verb Format........................................................................................................................................27
7.4.2. Response Format..................................................................................................................................................27
7.5.
POWER MANAGEMENT...............................................................................................................................................28
7.5.1. ALC262 A/B/C Versions.......................................................................................................................................28
7.5.2. ALC262 D Version ...............................................................................................................................................29
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ALC262 Series
Datasheet
8.
SUPPORTED VERBS AND PARAMETERS................................................................................................................31
8.1.
VERB – GET PARAMETERS (VERB ID=F00H).............................................................................................................31
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)............................................................................31
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)..........................................................................32
8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h).....................................................32
8.1.4. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) ..........................................................32
8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h) ...............................................33
8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ..................................................33
8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ................................................34
8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh).................................................35
8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)..................................................................35
8.1.10.
8.1.11.
8.1.12.
8.1.13.
8.1.14.
8.1.15.
8.1.16.
8.1.17.
Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) ..........................36
Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ........................36
Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) .......................................................37
Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) (ALC262 A/B/C Version) ........37
Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) (ALC262 D Version)...............38
Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)..................................................38
Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)..........................................................39
Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)..............................................39
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H)................................................................................40
VERB – SET CONNECTION SELECT (VERB ID=701H).................................................................................................41
VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) .........................................................................................41
VERB – GET PROCESSING STATE (VERB ID=F03H) ...................................................................................................44
VERB – SET PROCESSING STATE (VERB ID=703H) ....................................................................................................44
VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................45
VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................45
VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................45
VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................46
VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................46
VERB – SET AMPLIFIER GAIN (VERB ID=3H) ............................................................................................................48
VERB – GET CONVERTER FORMAT (VERB ID=AH)....................................................................................................49
VERB – SET CONVERTER FORMAT (VERB ID=2H).....................................................................................................50
VERB – GET POWER STATE (VERB ID=F05H) (ALC262 A/B/C VERSION)................................................................51
VERB – GET POWER STATE (VERB ID=F05H) (ALC262 D VERSION) .......................................................................52
VERB – SET POWER STATE (VERB ID=705H) ............................................................................................................53
VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...............................................................................53
VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H)................................................................................54
VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) ..............................................................................................54
VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...............................................................................................55
VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...........................................................................55
VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H)............................................................................56
VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................56
VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................57
VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) .......................................................................................57
VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 58
VERB – GET BEEP GENERATOR (VERB ID=F0AH)...................................................................................................58
VERB – SET BEEP GENERATOR (VERB ID=70AH)....................................................................................................59
VERB – GET GPIO DATA (VERB ID=F15H)...............................................................................................................59
VERB – SET GPIO DATA (VERB ID=715H)................................................................................................................60
VERB – GET GPIO ENABLE MASK (VERB ID=F16H).................................................................................................60
VERB – SET GPIO ENABLE MASK (VERB ID=716H) .................................................................................................61
VERB – GET GPIO DIRECTION (VERB ID=F17H).......................................................................................................61
VERB – SET GPIO DIRECTION (VERB ID=717H) .......................................................................................................62
VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H).........................................................62
VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..........................................................63
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
8.17.
8.18.
8.19.
8.20.
8.21.
8.22.
8.23.
8.24.
8.25.
8.26.
8.27.
8.28.
8.29.
8.30.
8.31.
8.32.
8.33.
8.34.
8.35.
8.36.
8.37.
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ALC262 Series
Datasheet
8.38.
8.39.
8.40.
8.41.
8.42.
VERB – FUNCTION RESET (VERB ID=7FFH)..............................................................................................................63
VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=F0DH, F0EH)...........................................64
VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH)............................................65
GET/SET VOLUME KNOB WIDGET (NID=21H) (VERB ID=F0FH/70FH) ....................................................................66
GET/SET SUBSYSTEM ID [31:0] (VERB ID=F20H/723H~720H TO SET BIT[31:0]).....................................................66
9.
ELECTRICAL CHARACTERISTICS ..........................................................................................................................67
9.1.
DC CHARACTERISTICS...............................................................................................................................................67
9.1.1. Absolute Maximum Ratings..................................................................................................................................67
9.1.2. Threshold Voltage ................................................................................................................................................67
9.1.3. Digital Filter Characteristics...............................................................................................................................68
9.1.4. S/PDIF Input/Output Characteristics...................................................................................................................68
9.2.
AC CHARACTERISTICS...............................................................................................................................................69
9.2.1. Link Reset and Initialization Timing.....................................................................................................................69
9.2.2. Link Timing Parameters at the Codec..................................................................................................................70
9.2.3. S/PDIF Output and Input Timing .........................................................................................................................71
9.2.4. Test Mode .............................................................................................................................................................71
9.3.
ANALOG PERFORMANCE............................................................................................................................................72
10.
APPLICATION NOTES.............................................................................................................................................73
10.1.
10.2.
10.3.
10.4.
APPLICATION CIRCUIT ...............................................................................................................................................73
VOLUME CONTROL VIA EXTERNAL VARIABLE RESISTOR .........................................................................................73
VOLUME CONTROL VIA GPIO0/GPIO1.....................................................................................................................74
DIGITAL MICROPHONE IMPLEMENTATION .................................................................................................................74
11.
MECHANICAL DIMENSIONS.................................................................................................................................76
MECHANICAL DIMENSIONS NOTES ............................................................................................................................77
ORDERING INFORMATION...................................................................................................................................78
11.1.
12.
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ALC262 Series
Datasheet
List of Tables
TABLE 1. DIGITAL I/O PINS........................................................................................................................................................13
TABLE 2. ANALOG I/O PINS .......................................................................................................................................................13
TABLE 3. FILTER/REFERENCE ....................................................................................................................................................14
TABLE 4. POWER/GROUND.........................................................................................................................................................14
TABLE 5. LINK SIGNAL DEFINITIONS .........................................................................................................................................16
TABLE 6. HDA SIGNAL DEFINITIONS.........................................................................................................................................16
TABLE 7. DEFINED SAMPLE RATE AND TRANSMISSION RATE....................................................................................................22
TABLE 8. 48KHZ VARIABLE RATE OF DELIVERY TIMING ..........................................................................................................22
TABLE 9. 44.1KHZ VARIABLE RATE OF DELIVERY TIMING .......................................................................................................23
TABLE 10. 40-BIT COMMANDS IN 4-BIT VERB FORMAT...............................................................................................................27
TABLE 11. 40-BIT COMMANDS IN 12-BIT VERB FORMAT.............................................................................................................27
TABLE 12. SOLICITED RESPONSE FORMAT ..................................................................................................................................27
TABLE 13. UNSOLICITED RESPONSE FORMAT .............................................................................................................................27
TABLE 14. SYSTEM POWER STATE DEFINITIONS .........................................................................................................................28
TABLE 15. POWER CONTROLS IN NID IS 01H, 02H~05H, 07H~09H .............................................................................................28
TABLE 16. ALC262 VERSION A/B/C POWERED DOWN CONDITIONS..........................................................................................29
TABLE 17. ALC262-VD SUPPORTS POWER CONTROLS IN NID 01H, 02H~03H, 06H, 07H~0AH, 10H~12H, 14H~1FH ................30
TABLE 18. ALC262 VERSION D POWERED DOWN CONDITIONS .................................................................................................31
TABLE 19. VERB – GET PARAMETERS (VERB ID=F00H).............................................................................................................31
TABLE 20. PARAMETER – VENDOR ID (VERB ID=F00H, PARAMETER ID=00H)..........................................................................31
TABLE 21. PARAMETER – REVISION ID (VERB ID=F00H, PARAMETER ID=02H)........................................................................32
TABLE 22. PARAMETER – SUBORDINATE NODE COUNT (VERB ID=F00H, PARAMETER ID=04H)...............................................32
TABLE 23. PARAMETER – FUNCTION GROUP TYPE (VERB ID=F00H, PARAMETER ID=05H) ......................................................32
TABLE 24. PARAMETER – AUDIO FUNCTION CAPABILITIES (VERB ID=F00H, PARAMETER ID=08H)..........................................33
TABLE 25. PARAMETER – AUDIO WIDGET CAPABILITIES (VERB ID=F00H, PARAMETER ID=09H).............................................33
TABLE 26. PARAMETER – SUPPORTED PCM SIZE, RATES (VERB ID=F00H, PARAMETER ID=0AH) ...........................................34
TABLE 27. PARAMETER – SUPPORTED STREAM FORMATS (VERB ID=F00H, PARAMETER ID=0BH)...........................................35
TABLE 28. PARAMETER – PIN CAPABILITIES (VERB ID=F00H, PARAMETER ID=0CH) ...............................................................35
TABLE 29. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, INPUT AMPLIFIER PARAMETER ID=0DH).......................36
TABLE 30. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, OUTPUT AMPLIFIER PARAMETER ID=12H) ....................36
TABLE 31. PARAMETER – CONNECT LIST LENGTH (VERB ID=F00H, PARAMETER ID=0EH) ......................................................37
TABLE 32. PARAMETER – SUPPORTED POWER STATES (VERB ID=F00H, PARAMETER ID=0FH) (ALC262 A/B/C VERSION).....37
TABLE 33. PARAMETER – SUPPORTED POWER STATES (VERB ID=F00H, PARAMETER ID=0FH) (ALC262 D VERSION) ............38
TABLE 34. PARAMETER – PROCESSING CAPABILITIES (VERB ID=F00H, PARAMETER ID=10H)..................................................38
TABLE 35. PARAMETER – GPIO CAPABILITIES (VERB ID=F00H, PARAMETER ID=11H) ............................................................39
TABLE 36. PARAMETER – VOLUME KNOB CAPABILITIES (VERB ID=F00H, PARAMETER ID=13H).............................................39
TABLE 37. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H)................................................................................40
TABLE 38. VERB – SET CONNECTION SELECT (VERB ID=701H) .................................................................................................41
TABLE 39. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) .........................................................................................41
TABLE 40. VERB – GET PROCESSING STATE (VERB ID=F03H) ...................................................................................................44
TABLE 41. VERB – SET PROCESSING STATE (VERB ID=703H) ....................................................................................................44
TABLE 42. VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................45
TABLE 43. VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................45
TABLE 44. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................45
TABLE 45. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................46
TABLE 46. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................46
TABLE 47. VERB – SET AMPLIFIER GAIN (VERB ID=3H).............................................................................................................48
TABLE 48. VERB – GET CONVERTER FORMAT (VERB ID=AH)....................................................................................................49
TABLE 49. VERB – SET CONVERTER FORMAT (VERB ID=2H) .....................................................................................................50
TABLE 50. VERB – GET POWER STATE (VERB ID=F05H) (ALC262 A/B/C VERSION)................................................................51
TABLE 51. VERB – GET POWER STATE (VERB ID=F05H) (ALC262 D VERSION)........................................................................52
TABLE 52. VERB – SET POWER STATE (VERB ID=705H).............................................................................................................53
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Datasheet
TABLE 53. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H)................................................................................54
TABLE 54. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) ..............................................................................................54
TABLE 55. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...............................................................................................55
TABLE 56. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...........................................................................55
TABLE 57. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ............................................................................56
TABLE 58. VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................56
TABLE 59. VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................57
TABLE 60. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) .......................................................................................57
TABLE 61. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3)58
TABLE 62. VERB – GET BEEP GENERATOR (VERB ID=F0AH) ...................................................................................................58
TABLE 63. VERB – SET BEEP GENERATOR (VERB ID=70AH)....................................................................................................59
TABLE 64. VERB – GET GPIO DATA (VERB ID=F15H)...............................................................................................................59
TABLE 65. VERB – SET GPIO DATA (VERB ID=715H)................................................................................................................60
TABLE 66. VERB – GET GPIO ENABLE MASK (VERB ID=F16H).................................................................................................60
TABLE 67. VERB – SET GPIO ENABLE MASK (VERB ID=716H) .................................................................................................61
TABLE 68. VERB – GET GPIO DIRECTION (VERB ID=F17H).......................................................................................................61
TABLE 69. VERB – SET GPIO DIRECTION (VERB ID=717H) .......................................................................................................62
TABLE 70. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H).........................................................62
TABLE 71. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..........................................................63
TABLE 72. VERB – FUNCTION RESET (VERB ID=7FFH) ..............................................................................................................63
TABLE 73. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=F0DH, F0EH)...........................................64
TABLE 74. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH)............................................65
TABLE 75. GET/SET VOLUME KNOB WIDGET (NID=21H) (VERB ID=F0FH/70FH) ....................................................................66
TABLE 76. GET/SET SUBSYSTEM ID [31:0] (VERB ID=F20H / 723H~720H TO SET BIT[31:0])....................................................66
TABLE 77. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................67
TABLE 78. THRESHOLD VOLTAGE...............................................................................................................................................67
TABLE 79. DIGITAL FILTER CHARACTERISTICS...........................................................................................................................68
TABLE 80. S/PDIF INPUT/OUTPUT CHARACTERISTICS................................................................................................................68
TABLE 81. LINK RESET AND INITIALIZATION TIMING..................................................................................................................69
TABLE 82. LINK TIMING PARAMETERS AT THE CODEC ...............................................................................................................70
TABLE 83. S/PDIF OUTPUT AND INPUT TIMING ..........................................................................................................................71
TABLE 84. ANALOG PERFORMANCE............................................................................................................................................72
TABLE 85. ORDERING INFORMATION ..........................................................................................................................................78
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ALC262 Series
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM – ALC262 A/B VERSION ................................................................................................................6
FIGURE 2. BLOCK DIAGRAM – ALC262 C VERSION ....................................................................................................................7
FIGURE 3. BLOCK DIAGRAM – ALC262 D VERSION ....................................................................................................................8
FIGURE 4. ANALOG INPUT/OUTPUT UNIT.....................................................................................................................................9
FIGURE 5. ALC262 A/B VERSION PIN ASSIGNMENTS................................................................................................................10
FIGURE 6. ALC262 C VERSION PIN ASSIGNMENTS....................................................................................................................11
FIGURE 7. ALC262 D VERSION PIN ASSIGNMENTS....................................................................................................................12
FIGURE 8. HDA LINK PROTOCOL...............................................................................................................................................15
FIGURE 9. BIT TIMING................................................................................................................................................................16
FIGURE 10. SIGNALING TOPOLOGY .............................................................................................................................................17
FIGURE 11. SDO OUTBOUND FRAME ..........................................................................................................................................18
FIGURE 12. SDO STREAM TAG IS INDICATED IN SYNC..............................................................................................................18
FIGURE 13. STRIPED STREAM ON MULTIPLE SDOS.....................................................................................................................19
FIGURE 14. SDI INBOUND STREAM .............................................................................................................................................20
FIGURE 15. SDI STREAM TAG AND DATA ...................................................................................................................................20
FIGURE 16. CODEC TRANSMITS DATA OVER MULTIPLE SDIS ....................................................................................................21
FIGURE 17. LINK RESET TIMING..................................................................................................................................................25
FIGURE 18. CODEC INITIALIZATION SEQUENCE...........................................................................................................................26
FIGURE 19. CODEC INITIALIZATION SEQUENCE...........................................................................................................................30
FIGURE 20. LINK RESET AND INITIALIZATION TIMING ................................................................................................................69
FIGURE 21. LINK SIGNALS TIMING ..............................................................................................................................................70
FIGURE 22. OUTPUT AND INPUT TIMING......................................................................................................................................71
FIGURE 23. VOLUME CONTROL BY EXTERNAL VARIABLE RESISTOR ..........................................................................................73
FIGURE 24. VOLUME CONTROL VIA GPIO0 AND GPIO1.............................................................................................................74
FIGURE 25. DIGITAL MICROPHONE IMPLEMENTATION-1.............................................................................................................74
FIGURE 26. DIGITAL MICROPHONE IMPLEMENTATION-2.............................................................................................................75
FIGURE 27. DIGITAL MICROPHONE TIMING.................................................................................................................................75
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Track ID: JATR-1076-21 Rev. 1.9
ALC262 Series
Datasheet
1. General Description
The ALC262 series are 4-Channel DAC and 6-Channel ADC High Definition Audio Codecs with UAA
(Universal Audio Architecture). Featuring two 24-bit stereo DACs and three 24-bit stereo ADCs (the
ALC262, ALC262-VB and ALC262-VC support 20-bit ADC format, the ALC262-VD supports 24-bit
ADC format), they are designed for high-performance multimedia desktop and laptop systems. The
ALC262 series incorporates proprietary converter technology to achieve over 100dB Signal-to-Noise
ratio playback quality.
The ALC series meets the current WLP3.10 (Windows® Logo Program) requirements, and the
ALC262-VD (D version) meets future WLP requirements that become effective from 01 June 2008,
bringing PC sound quality closer to consumer electronic devices.
The ALC262 series provide 4 channels of DAC, supporting stereo sound playback on the rear panel and
independent stereo sound output on the front panel simultaneously (multiple streaming), along with
flexible mixing, mute, and fine gain control functions to provide a complete integrated audio solution.
The ALC262 series also integrates three stereo ADCs that can support a microphone array with Acoustic
Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology simultaneously,
significantly improving sound quality for PC VoIP applications. With this unique feature (3 stereo ADCs),
the ALC262 can provide high-quality audio using S/PDIF to output analog data, or for multiple-source
recording applications.
All analog IO are input and output capable and can be re-tasked according to user’s definitions.
Headphone amplifiers are also integrated at analog output ports A, B, C, D, E, and F. The ALC262 series
supports 16/20/24 S/PDIF input and output to offer easy connection of PCs to high quality consumer
electronic products such as digital decoders and speakers.
The ALC262 series supports host/soft audio from the Intel ICH chipset, and also from any other HDA
compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and excellent
software utilities like Karaoke mode, environment emulation, software equalizer, HRTF 3D positional
audio, and optional Dolby®, SRS®, Fortemedia® and Waves® audio technology the ALC262 provides an
excellent entertainment package and game experience for PC users.
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Datasheet
Two functions are added in the ALC262 C version:
• Addition of a digital microphone interface. The ALC262 C version supports most digital microphones
currently available. With digital microphone implementation, a notebook computer can achieve better
voice input quality without noise interference caused by geometric PCB layout and radio frequency
devices
• The ALC262 C supports scalable I/O voltage (1.5V to 3.3V) on an HDA link, which will be a
requirement in future chipsets designed for low voltage operation.
The ALC262 D supports a secondary S/PDIF output converter and a dedicated output pin (S/PDIF-OUT2)
to a HDMI transmitter, and all ADCs support up to192K sample rate and 24-bit PCM format. The
ALC262 D version conforms to Intel’s Audio Codec low power state white paper and is ECR compliant,
with improved frequency response at a 44.1kHz sampling rate, and THD+N measured at -1dB full scale
in compliance with future WLP requirements that become effective from 01 June 2008.
Note: ALC262 version differences are listed in section 12 Ordering Information, page 78.
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ALC262 Series
Datasheet
2. Features
2.1. Hardware Features
High-performance DACs with 100dB SNR
ADCs with 90dB SNR (A-weighting)
Meets WLP (Windows Logo Program) 3.10 and future WLP requirements that become effective
from 01 June 2008
Two stereo DACs support 16/20/24-bit PCM for stereo audio playback on the rear panel, plus 2
channels of independent stereo sound output (multiple streaming) through the Front-Out-Left and
Front-Out-Right channels
Three stereo ADCs support 16/20-bit PCM for multiple input streaming (ALC262A/B/C versions)
Three stereo ADCs support 16/20/24-bit PCM for multiple input streaming (ALC262D version)
All DACs supports 44.1/48/96/192kHz sample rate
All ADCs support 44.1/48/96kHz sample rate (ALC262 A/B/C version)
All ADCs support 44.1/48/96/192kHz sample rate (ALC262 D version)
16/20/24-bit S/PDIF-OUT supports 44.1/48/96/192kHz sample rate
16/20/24-bit S/PDIF-IN supports 44.1/48/96/192kHz sample rate
Up to four channels of microphone input are supported for AEC/BF applications
Supports MONO line output with independent volume control
High-quality analog differential CD input
Supports external PCBEEP input and built-in digital BEEP generator
Software selectable 2.5V/3.75V VREFOUT
Two jack detection pins each designed to detect up to 4 jacks
Wide range (–80dB ~ +42dB) volume control with 1.5dB resolution of analog to analog mixer gain
All analog jacks are stereo input and output re-tasking for analog plug & play
Built-in headphone amplifiers for port-A/D/E/F
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ALC262 Series
Datasheet
Supports both analog DC volume control and GPI digital volume control (requires driver support)
4 GPIOs (General Purpose Input/Output) for customized applications
Optional EAPD (External Amplifier Power Down) is supported
Power support: Digital: 3.3V; Analog: 3.3V/5.0V
Power management and enhanced power saving features
48-pin LQFP ‘Green’ package; pin compatible with the ALC260
Supports low voltage (1.5V~3.3V) IO for HDA link (ALC262 C/D version)
Supports stereo digital microphone input (ALC262 C/D version)
Supports 2nd S/PDIF output. (ALC262 D version)
Intel low power ECR compliant and power status control for all widgets (ALC262 D version)
2.2. Software Features
Meets Microsoft Windows Logo Program requirements
EAX™ 1.0 & 2.0 compatible
Direct Sound 3D™ compatible
A3D™ compatible
I3DL2 compatible
HRTF 3D Positional Audio (Windows XP only)
Emulation of 26 sound environments to enhance gaming experience
Multi-band software equalizer and tools
Voice Cancellation and Key Shifting in Karaoke mode
Dynamic range control (expander, compressor and limiter) with adjustable parameters
Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience
Provides 10-foot GUI for Windows Media Center
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ALC262 Series
Datasheet
Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF)
technology for voice application
Smart multiple streaming operation
HDMI audio driver for AMD platform
Dolby® PCEE program™ (optional software feature)
SRS® TrueSurround HD (optional software feature)
Fortemedia® SAM™ technology for voice processing (Beam Forming and Acoustic Echo
Cancellation) (optional software feature)
MaxxAudio technologies from Waves (optional software feature, ALC262-VD2 only)
3. System Applications
Multimedia desktop and laptop PCs
Information appliances (IA)
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ALC262 Series
Datasheet
4. Block Diagram
4.1. ALC262 A/B Version
Figure 1. Block Diagram – ALC262 A/B Version
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ALC262 Series
Datasheet
4.2. ALC262 C Version
Note: The ALC262 C Version supports digital MIC (DMIC-CLK, DMIC-DATA).
Figure 2. Block Diagram – ALC262 C Version
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ALC262 Series
Datasheet
4.3. ALC262 D Version
Note: The ALC262 D Version supports digital MIC (DMIC-CLK, DMIC-DATA) and S/DPIF-OUT2.
Figure 3. Block Diagram – ALC262 D Version
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ALC262 Series
Datasheet
4.4. Analog Input/Output Unit
Pin Complex widgets NID=14h~16h, 18h~1Bh are re-tasking IO.
Left
A
EN_AMP
R
EN_OBUF
Right
R
Output_Signal_Left
Output_Signal_Right
Input_Signal_Left
EN_OBUF
EN_IBUF
Input_Signal_Right
Figure 4. Analog Input/Output Unit
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ALC262 Series
Datasheet
5. Pin Assignments
5.1. ALC262 A/B Version
Note: C and D versions (Figure 6, page 11, and Figure 7, page 12) support digital MIC (pin 2, 46) and
Scalable I/O Power (pin 9).
Figure 5. ALC262 A/B Version Pin Assignments
5.2. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 5. The version number is shown
in the location marked ‘VV’. For example, ‘VV=B0’ indicates silicon version ‘B’ and stepping version
‘0’, which is the first stepping of the ALC262 version B.
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ALC262 Series
Datasheet
5.3. ALC262 C Version
The C version supports digital MIC (pin 2, 46) and Scalable I/O Power (pin 9).
Figure 6. ALC262 C Version Pin Assignments
5.4. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 6. The version number is shown
in the location marked ‘VV’. For example, ‘VV=C0’ indicates silicon version ‘C’ and stepping version
‘0’, which is the first stepping of the ALC262-VC.
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ALC262 Series
Datasheet
5.5. ALC262 D Version
The D version supports digital MIC (pin 2, 46), Scalable I/O Power (pin 9), and S/PDIFO2 (pin45).
Figure 7. ALC262 D Version Pin Assignments
5.6. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 7. The version number is shown
in the location marked ‘VV’. For example, ‘VV=D0’ indicates silicon version ‘D’ and stepping version
‘0’, which is the first stepping of the ALC262-VD.
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ALC262 Series
Datasheet
6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Type Pin No. Description Characteristic Definition
Vt=0.5*DVDD
Name
RESET#
SYNC
I
I
11
10
6
H/W Reset Control
Sample Sync (48kHz)
24MHz Bit Clock Input
Serial TDM Data Input
Serial TDM Data Output
S/PDIF Input /
Schmitt trigger input, VIL=1.0V, VIH=2.0V
Schmitt trigger input, VIL=1.0V, VIH=2.0V
Vt=0.5*DVDD
BITCLK
SDATA-OUT
SDATA-IN
SPDIFI /
EAPD
I
I
5
O
IO
8
VOH=0.9*DVDD, VOL=0.1*DVDD
Self bias to Vt=1.5V /
47
Signal to Power Down Ext. Amp Output VOH=0.9*DVDD, VOL=0.1*DVDD
SPDIFO
SPDIFO2
GPIO0
O
O
48
451
43
S/PDIF Output
Output has 12mA@75Ω driving capability.
Output has 12mA@75Ω driving capability.
Input Vt=(2/3)*DVDD, output VOH=0.9*DVDD,
S/PDIF Output
IO
General Purpose Input/Output 0
VOL=0.1*DVDD, internal pulled up by 50KΩ
GPIO1
IO
IO
IO
O
44
22
General Purpose Input/Output 1
Input Vt=(2/3)*DVDD, output VOH=0.9*DVDD,
VOL=0.1*DVDD, internal pulled up by 50KΩ
Input Vt=(2/3)*DVDD, output VOH=0.9*DVDD,
VOL=0.1*DVDD, internal pulled up by 50KΩ
GPIO2 /
DMIC-DATA
GPIO3
General Purpose Input/Output 2.
Data Input from Digital MIC
General Purpose Input/Output 3
3
Input Vt=(2/3)*DVDD, output VOH=0.9*DVDD,
VOL=0.1*DVDD, internal pulled up by 50KΩ
Default 2.048MHz clock output
Total: 13 Pins
DMIC-CLK
462
Clock Output for Digital MIC
Note 1: Only the D version supports SPDIFO2.
Note 2: Only the C version and D version support DMIC-DATA and DMIC-CLK.
6.2. Analog I/O Pins
Table 2. Analog I/O Pins
Name
Type Pin No. Description
Characteristic Definition
LINE2-L
LINE2-R
MIC2-L
IO
IO
IO
14
15
16
2nd Line Input Left Channel
2nd Line Input Right Channel
Analog input/output, default is input (PORT-E)
Analog input/output, default is input (PORT-E)
2
nd Stereo Microphone Input Left Analog input/output, default is input (PORT-F)
Channel
MIC2-R
IO
17
2
nd Stereo Microphone Input
Analog input/output, default is input (PORT-F)
Right Channel
CD-L
I
I
18
19
20
21
CD Input Left Channel
CD Input Reference Ground
CD Input Right Channel
Analog input, 1.6Vrms of full scale input
Analog input, 1.6Vrms of full scale input
Analog input, 1.6Vrms of full scale input
CD-GND
CD-R
I
MIC1-L
IO
1st Stereo Microphone Input Left Analog input/output, default is input (PORT-B)
Channel
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ALC262 Series
Datasheet
Name
Type Pin No. Description
Characteristic Definition
MIC1-R
IO
22
1st Stereo Microphone Input Right Analog input/output, default is input (PORT-B)
Channel
LINE1-L
IO
IO
I
23
24
12
35
36
39
41
37
13
34
33
1st Line Input Left Channel
1st Line Input Right Channel
External PCBEEP Input
Line Output Left Channel
Line Output Right Channel
Headphone Out Left Channel
Headphone Out Right Channel
MONO Output
Analog input/output, default is input (PORT-C)
Analog input/output, default is input (PORT-C)
Analog input, 1.6Vrms of full scale input
Analog output (PORT-D)
LINE1-R
PCBEEP
LINE-OUT-L
LINE-OUT-R
HP-OUT-L
HP-OUT-R
MONO-OUT
Sense A
IO
IO
IO
IO
O
I
Analog output (PORT-D)
Analog output (PORT-A)
Analog output (PORT-A)
Analog mono output is summation of (L+R)/2
Jack resistor network input 1
Jack Detect Pin l
Sense B
I
Jack Detect Pin 2
Jack resistor network input 2
DCVOL
I
DC Sense for Volume Control
Analog DC input for external volume control
Total: 20 Pins
6.3. Filter/Reference
Table 3. Filter/Reference
Type Pin No. Description
Name
Characteristic Definition
1µF capacitor to analog ground
2.5V/3.75Vreference voltage
2.5V/3.75Vreference voltage
2.5V/3.75Vreference voltage
2.5V/3.75Vreference voltage
2.5V/3.75Vreference voltage
20K, 1% resistor to analog ground
-
VREF
-
27
28
29
30
31
32
40
2.5V Reference Voltage
MIC1-VREFO-L
LINE1-VREFO
MIC2-VREFO
LINE2-VREFO
MIC1-VREFO-R
JDREF
O
O
O
O
O
-
Bias Voltage for MIC1 Jack
Bias Voltage for LINE1 Jack
Bias Voltage for MIC2 Jack
Bias Voltage for LINE2 Jack
Bias Voltage for MIC1 Jack
Ref. Resistor for Jack Detect
NC
-
45, 46 Not Connected
Total: 7 Pins
6.4. Power/Ground
Table 4. Power/Ground
Name
Type Pin No Description
Characteristic Definition
AVDD1
I
I
I
I
I
I
I
25
26
38
42
1
Analog VDD (5V or 3.3V)
Analog GND
Analog power for mixer and amplifier
Analog ground for mixer and amplifier
Analog power for DACs and ADCs
Analog ground for DACs and ADCs
Digital power
AVSS1
AVDD2
Analog VDD (5V or 3.3V)
Analog GND
AVSS2
DVDD-CORE
DVSS
Digital VDD (3.3V)
Digital GND
4
Digital ground
DVDD-CORE
DVDD-IO
DVSS
9
Digital VDD (3.3V)
Digital VDD (1.5V~3.3V)
Digital GND
A/B version: Digital power for core and HDA link.
C/D version: Scalable digital power for HDA link.
Digital ground
I
7
Total: 8 Pins
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ALC262 Series
Datasheet
7. High Definition Audio Link Protocol
7.1. Link Signals
The High Definition Audio (HDA) Link is the digital serial interface that connects the HDA codecs to the
HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent
by the HDA controller. The input and output streams, including command and PCM data, are isochronous
with a 48kHz frame rate. Figure 8 shows the basic concept of the HDA link protocol.
Figure 8. HDA Link Protocol
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Datasheet
7.1.1.
Signal Definitions
Table 5. Link Signal Definitions
Item
Description
BCLK
SYNC
24.0MHz of bit clock sourced from the HDA controller and connecting to all codecs.
48kHz of signal is used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs.
SDO
Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are
carried on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec
samples data present on SDO with respect to each edge of BCLK. The HDA controller must support at
least one SDO. To extend outbound bandwidth, multiple SDOs may be supported.
SDI
Serial data input signal driven by the codec. It is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be
supported. SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each
rising edge of BCLK. SDI can be driven by the controller to initialize the codec’s ID.
RST#
Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the
HDA controller and connects to all codecs.
Table 6. HDA Signal Definitions
Signal Name
BCLK
SYNC
SDO
Source
Controller
Controller Type
Output
Description
Global 24.0MHz Bit Clock.
Controller
Output
Global 48kHz Frame Sync and Outbound Tag Signal.
Serial Data Output from Controller.
Serial Data Input from Codec.
Weakly pulled down by the controller.
Global Active Low Reset Signal.
Controller
Output
SDI
Codec/Controller
Input/Output
RST#
Controller
Output
BCLK
8-Bit Frame SYNC
SYNC
Start of Frame
7
6
5
4
3
2
1
0
999 998 997 996995 994 993 992 991 990
SDO
SDI
3
2
1
0
499
498
497
496
495
494
Codec samples SDO at both rising and falling edge of BCLK
Controller samples SDI at rising edge of BCLK
Figure 9. Bit Timing
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Datasheet
7.1.2.
Signaling Topology
The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.
RST#, BCLK, SYNC, SDO0, and SDO1 are driven by controller to codecs. Each codec drives its own
point-to-point SDI signal(s) to the controller.
Figure 10 shows the possible connections between the HDA controller and codecs:
• Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission
• Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate
• Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate
• Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and
codecs. Section 7.2 Frame Composition, page 18, describes the detailed outbound and inbound stream
compositions for single and multiple SDOs/SDIs.
The connections shown in Figure 10 can be implemented concurrently in an HDA system. The ALC262
is designed to receive a single SDO stream.
SDI14
.
.
.
.
.
.
SDI13
SDI2
HDA
Controller
SDI1
SDI0
SDO1
SDO0
SYNC
BCLK
RST#
. . .
Codec 0
Codec 1
Codec 2
Codec N
Single SDO
Single SDI
Two SDOs
Single SDI
Single SDO
Two SDIs
Two SDOs
Multiple SDIs
Figure 10. Signaling Topology
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Datasheet
7.2. Frame Composition
7.2.1.
Outbound Frame – Single SDO
An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one
or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA
controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the
sample rate is a multiple of 48kHz. This means there should be 2 blocks in the same stream to carry
96kHz samples (Figure 11).
For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started
at the end of the stream tag. The stream tag includes a 4-bit preamble and 4-bit stream ID (Figure 12).
To keep the cadence of converters bound to the same stream, samples for these converters must be placed
in the same block.
A 48kHz Frame is composed of Command stream and multiple Data streams
Previous Frame
Next Frame
Frame SYNC
Stream 'A' Tag
(Here 'A' = 5)
Stream 'X' Tag
(Here 'X' = 6)
SYNC
SDO
Command Stream
0s
Stream 'A' Data
Stream 'X' Data
Padded at the
end of Frame
Null Field
One or multiple blocks in a stream
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block1 includes (N)th time of samples, Block2
includes (N+1)th time of samples
..
.
Block 1
Block 2
Block Y
..
.
Sample 1 Sample 2
Sample Z
Z channels of PCM Sample
...
msb first in a sample
msb
lsb
Figure 11. SDO Outbound Frame
BCLK
SYNC
Stream Tag
msb lsb
1 0 1 0
Stream=10
(4-Bit)
Preamble
(4-Bit)
Data of Stream 10
7 6 5 4 3 2 1 0
Previous Stream
SDO
Figure 12. SDO Stream Tag is Indicated in SYNC
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ALC262 Series
Datasheet
7.2.2.
Outbound Frame – Multiple SDO
The HDA controller allows two SDO signals to be used to stripe outbound data, completing transmission
in less time to get more bandwidth. If software determines the target codec supports multiple SDO
capability, it enables the ‘Stripe Control’ bit in the controller’s Output Stream Control Register to initiate
a specific stream (Stream ‘A’ in Figure 13) to be transmitted on multiple SDOs. In this case, the MSB of
stream data is always carried on SDO0, the second bit on SDO1 and so forth.
SDO1 is for transmitting a striped stream. The codec does not support multiple SDOs connected to
SDO0.
To guarantee all codecs can determine their corresponding stream, the command stream is not striped. It
is always transmitted on SDO0, and copied on SDO1.
Figure 13. Striped Stream on Multiple SDOs
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Datasheet
7.2.3.
Inbound Frame – Single SDI
An Inbound Frame – A single SDI is composed of one 36-bit response stream and multiple data streams.
Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at each
rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 14).
The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream
includes one 4-bit stream tag, one 6-bit data length, and n-bit sample blocks. Zeros will be padded if the
total length of the contiguous sample blocks within a given stream is not of integral byte
length (Figure 15).
A 48kHz Frame is Composed of a Response Stream and Multiple Data streams
Previous Frame
Frame SYNC
Next Frame
SYNC
SDI
0s
Stream 'X'
Response Stream
Stream 'A'
Null Field
Padded at the end of Frame
Stream Tag
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples
...
Block Y Null Pad
Block 1
Block 2
Sample 1 Sample 2
msb ...
...
Sample Z Z channels of PCM Sample
lsb msb first in a sample
Figure 14. SDI Inbound Stream
BCLK
SDI
n-Bit Sample Block
Null Pad
Next Stream
Stream Tag
Data Length in Bytes
B5 B4 B3 B2 B1
B8
Dn-1 Dn-2
0
0
B9
B7 B6
B0
D0
0
0
(Data Length in Bytes *8)-Bit
A Complete Stream
Figure 15. SDI Stream Tag and Data
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Datasheet
7.2.4.
Inbound Frame – Multiple SDI
A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound
stream exceeds the data transfer limits of a single SDI, the codec can divide the data onto separate SDI
signals, each of which operate independently, with different stream numbers at the same frame time. This
is similar to having multiple codecs connected to the controller. The controller samples the divided stream
into separate memory with multiple DMA descriptors, then software re-combines the divided data into a
meaningful stream.
SYNC
Frame SYNC
Stream 'A'
SDI
Tag A
Data A
Response Stream
Stream 'X'
0s
Stream 'Y'
0s
0
Stream 'B'
Data B
SDI
Tag B
Response Stream
1
Stream A, B, X, and Y are independent and have separate IDs
Codec drives SDI0 and SDI1
Figure 16. Codec Transmits Data Over Multiple SDIs
7.2.5.
Variable Sample Rates
The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or
sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample
block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate
of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own
sample rate, independent of any other stream.
The HDA controller supports 48kHz and 44.1kHz base rates. Table 7, page 22, shows the recommended
sample rates based on multiples or sub-multiples of one of the two base rates.
Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in
multiples (n) of 48kHz contain n sample blocks in a frame. Table 8, page 22, shows the delivery cadence
of variable rates based on 48kHz.
The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple
rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid
frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample
blocks are transmitted every 160 frames.
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The cadence ‘12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)’ interleaves 13 frames containing no
sample blocks in every 160 frames. It provides a low long-term frequency drift for 44.1kHz of delivery
rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence and interleave n empty frames.
Rates in multiples (n) of 44.1kHz applying this cadence contain n sample blocks in the non-empty frame
and interleave an empty frame between non-empty frames (Table 9, page 23).
Table 7. Defined Sample Rate and Transmission Rate
(Sub) Multiple 48kHz Base
44.1kHz Base
1/6
1/4
1/3
1/2
2/3
1
8kHz (1 sample block every 6 frames)
-
12kHz (1 sample block every 4 frames)
16kHz (1 sample block every 3 frames)
-
11.025kHz (1 sample block every 4 frames)
-
22.05kHz (1 sample block every 2 frames)
-
32kHz (2 sample blocks every 3 frames)
48kHz (1 sample block per frame)
96kHz (2 sample blocks per frame)
192kHz (4 sample blocks per frame)
44.1kHz (1 sample block per frame)
88.2kHz (2 sample blocks per frame)
176.4kHz (4 sample blocks per frame)
2
4
Table 8. 48kHz Variable Rate of Delivery Timing
Rate
8kHz
Delivery Cadence
YNNNNN (repeat)
YNNN (repeat)
YNN (repeat)
Y2NN (repeat)
Y (repeat)
Description
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 4 frames
One sample block is transmitted in every 3 frames
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 6 frames
Two sample blocks are transmitted in each frame
Four sample blocks are transmitted in each frame
12kHz
16kHz
32kHz
48kHz
96kHz
192kHz
Y2 (repeat)
Y4 (repeat)
N: No sample block in a frame.
Y: One sample block in a frame.
Yx: X sample blocks in a frame.
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Table 9. 44.1kHz Variable Rate of Delivery Timing
Delivery Cadence
Rate
11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
22.05kHz
{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
44.1kHz
88.2kHz
174.4kHz
12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)
122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat)
124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)
11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{ - }=NNNN
22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN
{11}=YNYNYNYNYNYNYNYNYNYNYN
{ - }=NN
44.1kHz
88.2kHz
174.4kHz
12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with
no sample block.
122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with
no sample block.
124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with
no sample block.
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7.3. Reset and Initialization
There are two types of reset within an HDA link:
• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
• Codec Reset. Generated by software directing a command to reset a specific codec back to its default
state
An initialization sequence is requested after any of the following three events:
1. Link Reset
2. Codec Reset
3. Codec changes its power state (For example, hot docking a codec to an HDA system)
7.3.1.
Link Reset
A link reset may be caused by 3 events:
1. The HDA controller asserts RST# for any reason (power up, or PCI reset)
2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA
controller
3. Software initiates power management sequences. Figure 17, page 25, shows the ‘Link Reset’ timing
including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v)
Enter ‘Link Reset’:
n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a
link reset
o As the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at the
end of the frame
p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low
q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state
r All link signals driven by controller and codecs should be tri-state by internal pull low resistors
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Exit from ‘Link Reset’:
s If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
t Software is responsible for de-asserting RST# after a minimum of 100µsec BCLK running time (the
100µsec provides time for the codec PLL to stabilize)
u Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
v When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
last bit of frame SYNC, it means the codec requests an initialization sequence)
>=100 usec >= 4 BCLK
Initialization Sequence
Previous Frame
4 BCLK
4 BCLK
Link in Reset
BCLK
SYNC
SDOs
SDIs
Normal Frame
SYNC
Normal Frame
SYNC is absent
Driven Low
Pulled Low
2
8
Driven Low
Driven Low
Pulled Low
Pulled Low
Wake Event
9
RST#
Pulled Low
1
3
4
5
6
7
Figure 17. Link Reset Timing
7.3.2.
Codec Reset
A ‘Codec Reset’ is initiated via the Codec RESET command verb. It results in the target codec being
reset to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.
In ALC262 D version, the extend power state of conforming to Intel low power ECR the function reset
could not initialize the register setting. Host SW needs to send ‘two’ function reset consecutively to reset
all settings.
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7.3.3.
Codec Initialization Sequence
n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the
controller.
o The codec will stop driving the SDI during this turnaround period.
pqrs The controller drives SDI to assign a CAD to the codec.
t The controller releases the SDI after the CAD has been assigned.
u Normal operation state
Figure 18. Codec Initialization Sequence
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7.4. Verb and Response Format
7.4.1.
Command Verb Format
There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with
12-bit identifiers (12-bit verbs) and 8-bits of data. Table 10 shows the 4-bit verb structure of a command
stream sent from the controller to operate the codec. Table 11 is the 12-bit verb structure that gets and
controls parameters in the codec.
Table 10. 40-bit Commands in 4-bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Bit [15:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
Table 11. 40-bit Commands in 12-bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Bit [7:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
7.4.2.
Response Format
There are two types of response from the codec to the controller. Solicited Responses are returned by the
codec in response to a current command verb. The codec will send Solicited Response data in the next
frame, without regard to the Set (Write) or Get (Read) command. The 32-bit Response is interpreted by
software, opaque to the controller.
Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI
status information can be actively delivered to the controller and interpreted by software. The ‘Tag’ in
Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Table 12. Solicited Response Format
Bit [35]
Bit [34]
Bit [33:32]
Bit [31:0]
Valid
Unsol=0
Reserved
Response
Table 13. Unsolicited Response Format
Bit [35]
Valid
Bit [34]
Unsol=1
Bit [33:32]
Bit [31:28]
Tag
Bit [27:0]
Response
Reserved
Note: The response stream in the link protocol is 36-bits wide. The response is placed in the lower 32-bit
field. Bit-35 is a ‘Valid’ bit to indicate the response is ‘Ready’. Bit-34 is set to indicate that an unsolicited
response was sent.
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7.5. Power Management
7.5.1.
ALC262 A/B/C Versions
The ALC262 does not support Wake-Up events when in low power mode. All power management state
changes in widgets are driven by software. Table 14 shows the System Power State Definitions.
In the ALC262, all the widgets include output/input converters support power control. Software may have
various power states depending on system configuration. Table 15 indicates those nodes that support
power management. To simplify power control, software can configure whole codec power states through
the audio function (NID=01h). Output converters (DACs) and input converters (ADCs) have no
individual power control to supply fine-grained power control.
7.5.1.1
System Power State Definitions
Table 14. System Power State Definitions
Power States
Definitions
D0
D1
All Power On. Individual DACs and ADCs can be powered up or down as required.
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog
reference stays up.
D2
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog
reference off (D1 + analog reference off).
D3 (Hot)
Power Still Supplied. The codec stops the internal clock. State is maintained.
All Power Removed. State lost.
D3 (Cold)
7.5.1.2
Power Controls in NID is 01h, 02h~05h, 07h~09h
Table 15. Power Controls in NID is 01h, 02h~05h, 07h~09h
Description
Audio Function LINK Response
D0
D1
Normal
PD
D2
Normal
PD
D3 (Hot/Cold)
Link Reset
PD
Normal
Normal
Normal
Normal
Normal
Normal
Normal
PD
PD
PD
PD
PD
PD
PD
(NID=01h)
DAC
PD
LINE ADC
MIX ADC
PD
PD
PD
PD
PD
PD
All Headphone Drivers
All Mixers
Normal
Normal
Normal
PD
Normal
Normal
Normal
PD
All Reference
PD
Note: PD=Powered Down.
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7.5.1.3
ALC262 Version A/B/C Powered Down Conditions
Table 16. ALC262 Version A/B/C Powered Down Conditions
Condition
Description
LINK Response powered down
Internal clock is stopped. SDATA-IN and S/PDIF-OUT are floated with pulled low
47K resistors internally. Detection of ‘Link Reset Entry’ and ‘Link Reset Exit’
sequences are supported. All states are maintained if DVDD is supplied.
LOUT DAC powered down
LINE ADC powered down
MIX ADC powered down
Analog block and digital filter are powered down.
Analog block and digital filter are powered down. The data on SDATA-IN is quiet.
Analog block and digital filter are powered down. The data on SDATA-IN is quiet.
Headphone Driver powered down All headphone drivers are powered down.
Mixers powered down
All internal mixer widgets are powered down. The DC reference and VREFOUTx at
individual pin complex are still alive.
Reference power down
All internal references, DC reference, and VREFOUTx at individual pin complexes
are off.
7.5.2.
ALC262 D Version
The ALC262 version D is designed to meet Intel’s low-power-state white paper and is ECR HDA-015B
compliant. It meets the five attributes discussed in the white paper:
1. D3 state power < 30mW.
2. Exit latency (D3 to D0 transfer) < 10ms.
3. Audio pop/click suppression during D3 and D0 transition < -65dBV.
4. Supports Jack detection in D3 state.
5. D3 functions with or without the BITCLK
The ALC262-VD minimizes D3 state idle mode power consumption and increases overall battery life in
mobile systems.
In D3 mode, only a power on reset or a ‘double function reset’ resets all ALC262-VD settings, cutting
software configuration time spent entering/leaving D3 state, and reducing latency time for D3 to D0
transitions.
The ALC262-VD supports Wake-Up events in D3 mode, including jack detection and GPIO status
changes. If the HDA-Link was alive (with BCLK), the ALC262-VD Wake-Up response is as normal. If
no BITCLK is present, the ALC262-VD drives the SDI high in order to wake up the system.
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Figure 19. Codec Initialization Sequence
All power management state changes in widgets are driven by software. Table 17 indicates the definitions
of power states.
In the ALC262-VD, the Audio Function (NID=01h), input converter, output converter, and each pin
widget supports power control. Software may have various power states dependent on system
configuration. Table 17 indicates those Nodes that support power management. To simplify power
control, software can configure whole codec power states using only the Audio Function (NID=01h).
Output converters (DACs) and input converters (ADCs) have no individual power control to supply
fine-Grained power control.
7.5.2.1
ALC262-VD Supports Power Controls in NID 01h, 02h~03h, 06h,
07h~0Ah, 10h~12h, 14h~1Fh
Table 17. ALC262-VD Supports Power Controls in NID 01h, 02h~03h, 06h, 07h~0Ah, 10h~12h, 14h~1Fh
Description
D0
D1
D2
D3
PD
PD
PD
PD
PD
PD
PD
D3 (No BCLK) Link Reset
Audio Function LINK Response
Normal Normal Normal
PD
PD
PD
PD
PD
PD
PD
PD
PD
(NID=01h)
DAC
Normal
Normal
Normal
PD
PD
PD
PD
PD
PD
PD
PD
PD
LINE ADC
MIX ADC
PD
PD
All Headphone Drivers
All Mixers
Normal Normal
Normal Normal
Normal Normal
Normal
Normal
Normal
All Reference
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7.5.2.2
ALC262 Version D Powered Down Conditions
Table 18. ALC262 Version D Powered Down Conditions
Condition
Description
LINK Response powered down
Internal clock is stopped. SDATA-IN and S/PDIF-OUT are floated with pulled low
47K resistors internally. Detection of ‘Link Reset Entry’ and ‘Link Reset Exit’
sequences are supported. All states are maintained if DVDD is supplied.
LOUT DAC powered down
LINE ADC powered down
MIX ADC powered down
Analog block and digital filter are powered down.
Analog block and digital filter are powered down. The data on SDATA-IN is quiet.
Analog block and digital filter are powered down. The data on SDATA-IN is quiet.
Headphone Driver powered down All headphone drivers are powered down.
Mixers powered down
All internal mixer widgets are powered down. The DC reference and VREFOUTx at
individual pin complexes are still alive.
Reference power down
All internal references, DC reference, and VREFOUTx at individual pin complexes
are off.
8. Supported Verbs and Parameters
This section describes the Verbs and Parameters supported by various widgets in the ALC262. If a verb is
not supported by the addressed widget, it will respond with 32 bits of ‘0’.
8.1. Verb – Get Parameters (Verb ID=F00h)
The ‘Get Parameters’ verb is used to get system information and the function capabilities of the HDA
codec. All the parameters are read-only. Refer to section 7.4.1 Command Verb Format, page 27, to get
detailed information about supported parameters.
Table 19. Verb – Get Parameters (Verb ID=F00h)
Get Parameter Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=00h Verb ID=F00h
Parameter ID[7:0]
32-bit Response
Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’.
8.1.1.
Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Table 20. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Codec Response Format
Bit
Description
31:16
15:0
Vendor ID=10ECh (Realtek’s PCI vendor ID).
Device ID=0262h.
Note: The Root Node (NID=00h) supports this parameter.
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8.1.2.
Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Table 21. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Codec Response Format
Bit
Description
31:24
23:20
Reserved. Read as 0’s.
MajRev. The major version number (in decimal) of the HDA Spec to which the ALC262 is fully
compliant.
19:16
15:8
MinRev. The minor version number (in decimal) of the HDA Spec to which the ALC262 is fully
compliant.
Revision ID. The vendor’s revision number.
00h is for the first silicon version, 01h is for the second version, etc.
Stepping ID. The vendor’s stepping number within the given Revision ID.
7:0
Note: The Root Node (NID=00h in the ALC262) supports this parameter.
8.1.3.
Parameter – Subordinate Node Count
(Verb ID=F00h, Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes
associated with the root node.
For function group nodes, it provides the total number of widgets associated with this function node.
Table 22. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
Codec Response Format
Bit
Description
31:24 Reserved. Read as 0’s.
23:16 Starting Node Number. The starting node number in the sequential widgets.
15:8 Reserved. Read as 0’s.
7:0
Total Number of Nodes. For a root node, the total number of function groups in the root node.
For a function group, the total number of widget nodes in the function group.
8.1.4.
Parameter – Function Group Type
(Verb ID=F00h, Parameter ID=05h)
Table 23. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)
Codec Response Format
Bit
Description
31:8 Reserved. Read as 0’s.
7:0
Function Group Type.
00h: Reserved
01h: Audio Function
03h~7Fh: Reserved
02h: Modem Function
80h~FFh: Vendor Defined Function.
Note: The Audio Function Group (NID=01h) supports this parameter.
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8.1.5.
Parameter – Audio Function Capabilities
(Verb ID=F00h, Parameter ID=08h)
Table 24. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Codec Response Format
Bit
Description
31:17 Reserved. Read as 0’s.
16
Beep Generator. A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group.
15:12 Reserved. Read as 0’s.
11:8 Input Delay.
7:4
3:0
Reserved. Read as 0’s.
Output Delay.
Note: The Audio Function Group (NID=01h) supports this parameter.
8.1.6.
Parameter – Audio Widget Capabilities
(Verb ID=F00h, Parameter ID=09h)
Table 25. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Codec Response Format
Bit
Description
31:24
23:20
Reserved. Read as 0’s.
Widget Type.
0h: Audio Output
3h: Selector
6h: Volume Knob Widget
1h: Audio Input
4h: Pin Complex
7h~Eh: Reserved
2h: Mixer
5h: Power Widget
Fh: Vendor defined audio widget
19:16
15:11
10
Delay. Samples delayed between the HDA link and widgets.
Reserved. Read as 0’s.
Power Control.
0: Power state control is not supported on this widget
1: Power state is supported on this widget
9
8
Digital.
0: An analog input or output converter
1: A widget translating digital data between the HDA link and digital I/O (S/PDIF, I2S, etc.)
ConnList. Connection List.
0: Connected to HDA link. No Connection List Entry should be queried
1: Connection List Entry must be queried
7
6
UnsolCap. Unsolicited Capable.
0: Unsolicited response is not supported
1: Unsolicited response is supported
ProcWidget. Processing Widget.
0: No processing control
1: Processing control is supported
5
4
3
2
1
0
Reserved. Read as 0.
Format Override.
AmpParOvr, AMP Param Override.
OutAmpPre, Out AMP Present.
InAmpPre, In AMP Present.
Stereo.
0: Mono Widget
1: Stereo Widget
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8.1.7.
Parameter – Supported PCM Size, Rates
(Verb ID=F00h, Parameter ID=0Ah)
Parameter in audio function provides default information about formats. Individual converters have their
own parameters to provide supported formats if their ‘Format Override’ bit is set.
Table 26. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Codec Response Format
Bit
31:21
20
Description
Reserved. Read as 0’s.
B32: Indicates whether 32-bit audio format is supported.
0: Not supported
B24: Indicates whether 24-bit audio format is supported.
0: Not supported 1: Supported
B20: Indicates whether 20-bit audio format is supported.
0: Not supported 1: Supported
B16: Indicates whether 16-bit audio format is supported.
0: Not supported 1: Supported
B8: Indicates whether 8-bit audio format is supported.
1: Supported
19
18
17
16
0: Not supported
1: Supported
15:12
11
Reserved. Read as 0’s.
R12: Indicates whether 384kHz (=8*48kHz) rate is supported.
0: Not supported 1: Supported
R11: Indicates whether 192kHz (=4*48kHz) rate is supported.
0: Not supported 1: Supported
R10: Indicates whether 176.4kHz (=4*44.1kHz) rate is supported.
0: Not supported 1: Supported
R9: Indicates whether 96kHz (=2*48kHz) rate is supported.
0: Not supported 1: Supported
R8: Indicates whether 88.2kHz (=2*44.1kHz) rate is supported.
0: Not supported 1: Supported
R7: Indicates whether 48kHz rate is supported.
0: Not supported 1: Supported
R6: Indicates whether 44.1kHz rate is supported.
0: Not supported 1: Supported
R5: Indicates whether 32kHz (=2/3*48kHz) rate is supported.
0: Not supported 1: Supported
R4: Indicates whether 22.05kHz (=1/2*44.1kHz) rate is supported.
0: Not supported 1: Supported
R3: Indicates whether 16kHz (=1/3*48kHz) rate is supported.
0: Not supported 1: Supported
R2: Indicates whether 11.025kHz (=1/4*44.1kHz) rate is supported.
0: Not supported 1: Supported
R1: Indicates whether 8kHz (=1/6*48kHz) rate is supported.
0: Not supported 1: Supported
10
9
8
7
6
5
4
3
2
1
0
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8.1.8.
Parameter – Supported Stream Formats
(Verb ID=F00h, Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters
have their own parameters to provide supported formats if the ‘Format Override’ bit is set.
Table 27. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Codec Response Format
Bit
31:3
2
Description
Reserved. Read as 0’s.
AC3.
0: Not supported
Float32.
0: Not supported
PCM.
1: Supported
1: Supported
1: Supported
1
0
0: Not supported
Note: Input converters and output converters support this parameter.
8.1.9.
Parameter – Pin Capabilities
(Verb ID=F00h, Parameter ID=0Ch)
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 28. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
Codec Response Format
Bit
31:16
15:8
Description
Reserved. Read as 0’s.
VREF Control Capability. ‘1’ in corresponding bit field indicates signal levels of associated Vrefout are
specified as a percentage of AVDD.
7:6
5
4
3
2
1
0
Reserved
100%
80%
Reserved
Ground
50%
Hi-Z
7
6
5
4
3
2
1
0
L-R Swap. Indicates the capability of swapping the left and rights.
Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins.
Input Capable. ‘1’ indicates this pin complex supports input.
Output Capable. ‘1’ indicates this pin complex supports output.
Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone.
Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is anything plugged in.
Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement.
Impedance Sense Capable.
‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type.
Note: Only Pin Complex widgets support this parameter.
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Datasheet
8.1.10.
Parameter – Amplifier Capabilities
(Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 29. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Codec Response Format
Bit
31
Description
(Input) Mute Capable.
30:23
22:16
Reserved. Read as 0.
Step Size.
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB.
15
Reserved. Read as 0.
14:8
Number of Steps.
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed.
7
Reserved. Read as 0.
Offset.
6:0
Indicates which step is 0dB.
8.1.11.
Parameter – Amplifier Capabilities
(Verb ID=F00h, Output Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 30. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Codec Response Format
Bit
31
Description
(Output) Mute Capable.
30:23
22:16
Reserved. Read as 0.
Step Size.
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB.
Reserved. Read as 0.
15
14:8
Number of Steps.
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed.
Reserved. Read as 0.
7
6:0
Offset. Indicates which step is 0dB.
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ALC262 Series
Datasheet
8.1.12.
Parameter – Connect List Length
(Verb ID=F00h, Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 31. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Codec Response Format
Bit
31:8
7
Description
Reserved. Read as 0.
Short Form.
0: Short Form
1: Long Form
6:0
Connect List Length.
Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one
input, and there is no Connection Select Control (Not a MUX widget).
8.1.13.
Parameter – Supported Power States
(Verb ID=F00h, Parameter ID=0Fh) (ALC262 A/B/C Version)
Table 32. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) (ALC262 A/B/C Version)
Bit
31:4
3
Description
Reserved. Read as 0’s.
D3Sup.
1: Power state D3 is supported.
D2Sup.
1: Power state D2 is supported.
D1Sup.
1: Power state D1 is supported.
D0Sup
2
1
0
1: Power state D0 is supported.
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ALC262 Series
Datasheet
8.1.14.
Parameter – Supported Power States
(Verb ID=F00h, Parameter ID=0Fh) (ALC262 D Version)
The ALC262 version D is designed to meet Intel’s low-power-state white paper and is ECR HDA-015B
compliant.
Table 33. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) (ALC262 D Version)
Codec Response Format
Bit
Description
31
Extended Power States Supported (EPSS)
1: Extended power state EPSS is supported.
30
CLKSTOP
1: D3 mode operates even when no BITCLK presents on the link.
29:4
3
Reserved, read as 0s.
D3Sup.
1: Power state D3 is supported.
D2Sup.
1: Power state D2 is supported.
D1Sup.
1: Power state D1 is supported.
D0Sup
2
1
0
1: Power state D0 is supported.
8.1.15.
Parameter – Processing Capabilities
(Verb ID=F00h, Parameter ID=10h)
Table 34. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Codec Response Format
Bit
31:16
15:8
7:1
Description
Reserved. Read as 0’s.
NumCoeff. Number of Coefficient
Reserved. Read as 0’s.
0
Benign.
0: Processing unit is not linear, nor is it time variant
1: Processing unit is linear and is time invariant
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Datasheet
8.1.16.
Parameter – GPIO Capabilities
(Verb ID=F00h, Parameter ID=11h)
Table 35. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Codec Response Format
Bit
Description
31
GPIWake=0.
The ALC262 does not support GPIO wake up function.
GPIUnsol=1.
30
The ALC262 supports GPIO unsolicited response.
Reserved. Read as 0’s.
NumGPIs=00h.
29:24
23:16
No GPI pin is supported.
NumGPOs=00h.
No GPO pin is supported.
NumGPIOs=04h.
15:8
7:0
Two GPIO pins are supported.
8.1.17.
Parameter – Volume Knob Capabilities
(Verb ID=F00h, Parameter ID=13h)
Table 36. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Codec Response Format for NID=21h (Volume Control Knob)
Bit
31:8
7
Description
Reserved. Read as 0’s.
Delta.
0: Software cannot modify the Volume Control Knob volume
1: Software can write a base volume to the Volume Control Knob
NumSteps.
6:0
The number of steps in the range of the Volume Control Knob
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ALC262 Series
Datasheet
8.2. Verb – Get Connection Select Control (Verb ID=F01h)
Table 37. Verb – Get Connection Select Control (Verb ID=F01h)
Codec Response Format
Get Command Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F01h
0’s
Bit[7:0] are Connection Index
Codec Response for Analog Port-A/B/C/D/E/F
Bit
31:8
7:0
Description
0’s.
Connection Index Currently Set (Default value is 00h).
00h: Sum Widget NID=0Ch
01h: Sum Widget NID=0Dh
Other: Reserved
Codec Response for Digital Pin S/PDIF-OUT
Bit
31:8
7:0
Description
0’s.
Connection Index Currently Set (Default value is 00h).
00h: Digital Converter (S/PDIF-OUT)
Other: Reserved
Other: Reserved
Codec Response for Digital Pin S/PDIF-OUT2 (ALC262 D version only)
Bit
31:8
7:0
Description
0’s.
Connection Index Currently Set (Default value is 00h).
00h: Digital Converter (S/PDIF-OUT)
Codec Response for NID=22hh (Mixer) (ALC262 C version only)
Bit
31:8
7:0
Description
0’s.
Connection Index Currently Set (Default value is 00h).
00h: Pin Complex – MIC1 NID=18h
02h: Pin Complex – LINE1 NID=1Ah
04h: Pin Complex – CD_IN NID=1Ch
06h: Pin Complex – LINE_OUT NID=14h
08h: Pin Complex – Sum Widget NID=0Bh
Other: Reserved
01h: Pin Complex – MIC2 NID=19h
03h: Pin Complex – LINE2 NID=1Bh
05h: Pin Complex – PCBEEP NID=1Dh
07h: Pin Complex – HP_OUT NID=15h
09h: Pin Complex – DMIC NID=12h
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Track ID: JATR-1076-21 Rev. 1.9
ALC262 Series
Datasheet
8.3. Verb – Set Connection Select (Verb ID=701h)
Table 38. Verb – Set Connection Select (Verb ID=701h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=701h
Select Index [7:0]
8.4. Verb – Get Connection List Entry (Verb ID=F02h)
Table 39. Verb – Get Connection List Entry (Verb ID=F02h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F02h
Offset Index - N[7:0]
32-bit Response
Codec Response for NID=07h (MIC ADC)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 24h (Sum Widget) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Returns 00h for N>3.
Returns 00h for N>3.
Codec Response for NID=08h (LINE ADC)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 23h (Sum Widget) for N=0~3.
Codec Response for NID=09h (MIX ADC)
Bit
Description
15:8
Connection List Entry (N+3), (N+2) and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 22h (Sum Widget) for N=0~3.
Codec Response for NID=0Ah (S/PDIF-IN Converter)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 1Fh (S/PDIF-IN Pin Widget) for N=0~3.
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ALC262 Series
Datasheet
Codec Response for NID=0Bh (Mixer)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 1Bh (Pin Complex - LINE2) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
23:16
15:8
Connection List Entry (N+2).
Returns 1Ah (Pin Complex - LINE1) for N=0~3.
Connection List Entry (N+1).
Returns 19h (Pin Complex - MIC2) for N=0~3.
Returns 1Dh (Pin Complex - BEEP) for N=4~7.
Returns 00h for N>7.
Returns 00h for N>7.
7:0
Connection List Entry (N).
Returns 18h (Pin Complex - MIC1) for N=0~3.
Returns 1Ch (Pin Complex - CD) for N=4~7.
Codec Response for NID=0Ch
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Connection List Entry (N).
Returns 02h (LOUT DAC) for N=0~3.
Codec Response for NID=0Dh
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Connection List Entry (N).
Returns 03h (HP-OUT DAC) for N=0~3.
Codec Response for NID=0Eh)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Connection List Entry (N).
Returns 02h (LINE-OUT DAC) for N=0~3.
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ALC262 Series
Datasheet
Codec Response for NID =14h~15h, 18h~1Bh (PORT-A ~ PORT-F)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 00h.
23:16
15:8
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Dh (Sum Widget NID=0Dh) for N=0~3.
Returns 00h for N>7.
7:0
Connection List Entry (N).
Returns 0Ch (Sum Widget NID=0Ch) for N=0~3.
Returns 00h for N>7.
Codec Response for NID=16h (Pin Widget: MONO-OUT)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 0Eh for N=0~3.
Returns 00h for N>3.
Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT)
Bit
Description
31:16
Connection List Entry (N+3) and (N+2).
Returns 0000h.
15:8
7:0
Connection List Entry (N+1).
Returns 00h for N>3.
Connection List Entry (N).
Returns 06h (S/PDIF-OUT converter) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=11h (Pin Widget: S/PDIF-OUT2 for ALC262 D Version)
Bit
Description
31:16
Connection List Entry (N+3) and (N+2).
Returns 0000h.
15:8
7:0
Connection List Entry (N+1).
Returns 00h for N>3.
Connection List Entry (N).
Returns 06h (S/PDIF-OUT converter) for N=0~3.
Returns 00h for N>3.
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Datasheet
Codec Response for NID=22h/23h/24h (Sum Widget before MIX/LINE/MIC ADCs)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 1Bh (Pin Complex - LINE2) for N=0~3.
Returns 15h (Pin Complex-SURR) for N=4~7.
Connection List Entry (N+2).
Returns 1Ah (Pin Complex - LINE1) for N=0~3.
Returns 14h (Pin Complex - FRONT) for N=4~7.
Connection List Entry (N+1).
Returns 19h (Pin Complex - MIC2) for N=0~3.
Returns 1Dh (Pin Complex - PCBEEP) for N=4~7.
Connection List Entry (N).
Returns 00h for N>7.
Returns 00h for N>7.
Returns 00h for N>7.
23:16
15:8
7:0
Returns 18h (Pin Complex - MIC1) for N=0~3.
Returns 0Bh (Mixer) for N=8~11.
Returns 1Ch (Pin Complex - CD) for N=4~7.
Returns 00h for N>11.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.5. Verb – Get Processing State (Verb ID=F03h)
Table 40. Verb – Get Processing State (Verb ID=F03h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F03h
0’s
32-bit response
Codec Response for All NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.6. Verb – Set Processing State (Verb ID=703h)
Table 41. Verb – Set Processing State (Verb ID=703h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=703h
Processing State [7:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s.
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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ALC262 Series
Datasheet
8.7. Verb – Get Coefficient Index (Verb ID=Dh)
Table 42. Verb – Get Coefficient Index (Verb ID=Dh)
Get Command Format
Codec Response Format
Response [31:0]
Bit [15:0] are Coefficient Index
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=Dh
0’s
Codec Response for NID=20h (Realtek Defined Hidden Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s.
Coefficient Index.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.8. Verb – Set Coefficient Index (Verb ID=5h)
Table 43. Verb – Set Coefficient Index (Verb ID=5h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=5h
Coefficient Index [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s.
8.9. Verb – Get Processing Coefficient (Verb ID=Ch)
Table 44. Verb – Get Processing Coefficient (Verb ID=Ch)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Verb ID=Ch
0’s
Processing Coefficient [15:0]
Codec Response for NID=20h (Realtek Defined Hidden Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s.
Processing Coefficient.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Track ID: JATR-1076-21 Rev. 1.9
ALC262 Series
Datasheet
8.10. Verb – Set Processing Coefficient (Verb ID=4h)
Table 45. Verb – Set Processing Coefficient (Verb ID=4h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Verb ID=4h
Coefficient [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s.
8.11. Verb – Get Amplifier Gain (Verb ID=Bh)
This verb is used to get gain/attenuation settings from each widget.
Table 46. Verb – Get Amplifier Gain (Verb ID=Bh)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
CAd=X
Node ID=Xh
Verb ID=Bh
‘Get’ payload [15:0]
Bit[7:0] are responsible for ‘Get’
‘Get’ Payload in Command Bit[15:0]
Bit
Description
15
Get Input/Output.
0: Input amplifier gain is requested1: Output amplifier gain is requested
14
13
Reserved. Read as 0.
Get Left/Right.
0: Right amplifier gain is requested
Reserved. Read as 0’s.
1: Left amplifier gain is requested
12:4
3:0
Index[3:0] for Input Source.
Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored
Codec Response for NID=07h (MIC ADC), 08h(LINE ADC) and 09h (MIX ADC)
Bit
31:8
7
Description
0’s.
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute 1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –16.5B~+30dB in 1.5dB steps.
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
6:0
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Datasheet
Codec Response for NID=0Bh (MIXER Sum Widget)
Bit
31:8
7
Description
0’s.
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute 1: Mute (Default for all Index).
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –34.5dB~+12dB in 1.5dB steps.
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
6:0
Codec Response for NID=0Ch~0Eh (Sum Widgets)
Bit
31:8
7
Description
0’s.
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute
1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Gain [6:0].
6:0
7-bit step value (0~31) specifying the volume from –46.5dB~0dB in 1.5dB steps.
Codec Response for NID=14h, 15h, 18h~1Bh (Pin Complex: LINE-OUT/HP-OUT/MIC1/MIC2/LINE1/LINE2)
Bit
31:8
7
Description
0’s.
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0.
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute.
0:Unmute
1:Mute (Default=1)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0.
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
Codec Response for NID=22h, 23h, 24h (Sum Widgets) – In C version, NID=22h is a selector will not support this verb.
Bit
31:8
7
Description
0’s.
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute
1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
6:0
Codec Response to Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Track ID: JATR-1076-21 Rev. 1.9
ALC262 Series
Datasheet
8.12. Verb – Set Amplifier Gain (Verb ID=3h)
This verb is used to set amplifier gain/attenuation in each widget.
Table 47. Verb – Set Amplifier Gain (Verb ID=3h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=3h
‘Set’ payload [7:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
Description
15
Set Output Amp.
‘1’ indicates output amplifier gain will be set.
Set Input Amp.
‘1’ indicates input amplifier gain will be set.
Set Left Amp.
14
13
‘1’ indicates left amplifier gain will be set.
Set Right Amp.
12
‘1’ indicates right amplifier gain will be set.
Index Offset (for input amplifiers on Sum widgets and Selector Widgets).
11:8
5 bits index offset in connection list is used to select which input gain will be set on a Sum or a Selector
widget. The index is ignored if the node is not a Sum or a Selector widget, or the ‘Set Input Amp’ bit is not
set.
7
Mute.
0: Unmute
1: Mute (-∞gain)
6:0
Gain[6:0].
A 7-bit step value specifying the amplifier gain.
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Datasheet
8.13. Verb – Get Converter Format (Verb ID=Ah)
Table 48. Verb – Get Converter Format (Verb ID=Ah)
Get Command Format
Codec Response Format
Response [31:0]
Bit[15:0] are converter format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=Ah
0’s
Codec Response for NID=02h, 03h, 06h (Output Converters: LINE-OUT DAC, HP-OUT DAC, S/PDIF-OUT).
Codec Response for NID=07h~0Ah (Input Converters: MIC ADC, LINE ADC, MIX DAC, and S/PDIF-IN)
Bit
31:16
15
Description
Reserved. Read as 0.
Stream Type (TYPE).
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE).
0: 48kHz
1: 44.1kHz
13:11
10:8
Sample Base Rate Multiple (MULT).
000b: *1
001b: *2
010b: *3
011b: *4
100b~111b: Reserved.
Sample Base Rate Divisor (DIV).
000b: /1
100b: /5
001b: /2
101b: /6
010b: /3
110b: /7
011b: /4
111b: /8
The ALC262 does not support Divisor. Always read as 000b.
Reserved. Read as 0.
7
6:4
Bits per Sample (BITS).
000b: 8 bits
001b: 16 bits
010b: 20 bits
011b: 24 bits
100b: 32 bits
101b~111b: Reserved
3:0
Number of Channels.
0: 1 channel
1: 2 channels
2: 3 channels
………
15: 16 channels
Codec Response for other NID
Bit
Description
Not Supported (returns 00000000h).
31:0
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Datasheet
8.14. Verb – Set Converter Format (Verb ID=2h)
Table 49. Verb – Set Converter Format (Verb ID=2h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Verb ID=2h
Set format [15:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
31:16
15
Description
Reserved. Read as 0.
Stream Type (TYPE).
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE).
0: 48kHz
1: 44.1kHz
13:11
10:8
Sample Base Rate Multiple (MULT).
000b: *1
001b: *2
010b: *3
011b: *4
100b~111b: Reserved.
Sample Base Rate Divisor (DIV).
000b: /1
100b: /5
001b: /2
101b: /6
010b: /3
110b: /7
011b: /4
111b: /8
7
Reserved. Read as 0.
6:4
Bits per Sample (BITS).
000b: 8 bits
100b: 32 bits
001b: 16 bits
101b~111b: Reserved
010b: 20 bits
011b: 24 bits
………
3:0
Number of Channels.
0: 1 channel
1: 2 channels
2: 3 channels
15: 16 channels
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Datasheet
8.15. Verb – Get Power State (Verb ID=F05h)
(ALC262 A/B/C Version)
Table 50. Verb – Get Power State (Verb ID=F05h) (ALC262 A/B/C Version)
Get Command Format Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=Ah
0’s
Power State [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:6
5:4
Description
Reserved. Read as 0’s.
PS-Act. Actual Power State [1:0].
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes
(NID=01h), PS-Act is always equal to PS-Set.
3:2
1:0
Reserved. Read as 0’s.
PS-Set. Set Power State [1:0].
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
PS-Set controls the current power setting of the referenced node.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
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Datasheet
8.16. Verb – Get Power State (Verb ID=F05h)
(ALC262 D Version)
Table 51. Verb – Get Power State (Verb ID=F05h) (ALC262 D Version)
Get Command Format
Codec Response Format
Response [31:0]
Power State [7:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=Ah
0’s
Codec Response for NID=01h (Audio Function Group)
Codec Response for NID=02h, 03h, 07h, 08h, 09h (Analog Input/Output Converter)
Codec Response for NID=11h, 12h, 14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh, 1Ch, 1Dh, 1Eh, 1Fh (Pin Widgets)
Codec Response for NID=06h, 0Ah, 10h (Digital Input/Output Converter)
Bit
31:11
10
Description
Reserved. Read as 0’s.
PS-SettingsReset.
0: Setting of widgets has been reset during any low power state
1: Setting that were changed from the default have been reset to their default during any low power state
PS-ClkStopOk.
9
0: No capability to operate normally with BITCLK stop
1: Operate normally with no BICLK
8
PS-Error. No support in ALC262-VD.
7:4
PS-Act. Actual Power State [1:0].
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes
(NID=01h), PS-Act is always equal to PS-Set.
3:2
1:0
Reserved. Read as 0’s.
PS-Set. Set Power State [1:0].
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
PS-Set controls the current power setting of the referenced node.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Datasheet
8.17. Verb – Set Power State (Verb ID=705h)
Table 52. Verb – Set Power State (Verb ID=705h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=705h
Power State [7:0]
0’s for all nodes
‘Power State’ in Command Bit[7:0]
Bit
7:6
5:4
Description
Reserved. Read as 0’s.
PS-Act. Actual Power State [1:0].
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
PS-Act indicates the actual power state of the referenced node.
Reserved. Read as 0’s.
3:2
1:0
PS-Set. Set Power State [1:0].
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
8.18. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Table 51. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F06h
0’s
Stream & Channel [7:0]
Codec Response for NID=02h, 03h, 06h (Output Converters: LINE-OUT DAC, HP-OUT DAC, S/PDIF-OUT).
Codec Response for NID=07h~0Ah (Input Converters: MIC ADC, LINE ADC, MIX DAC, and S/PDIF-IN)
Bit
31:8
7:4
Description
Reserved. Read as 0’s.
Stream[3:0].
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
Channel[3:0].
3:0
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its
left and right channel.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Datasheet
8.19. Verb – Set Converter Stream, Channel (Verb ID=706h)
Table 53. Verb – Set Converter Stream, Channel (Verb ID=706h)
Codec Response Format
Set Command Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=706h
Stream & Channel [7:0]
0’s for all nodes
‘Stream and Channel’ in Command Bit[7:0]
Bit
31:8
7:4
Description
Reserved. Read as 0’s.
Set Stream[3:0]. The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
1:0
Set Channel[3:0]. The lowest channel used by the converter. A stereo converter will use the set channel n as
well as n+1 for its left and right channel.
Note: This verb assigns stream and channel for output converters (NID=02h, 03h, 06h) and input converters
(NID=07h~0Ah). Other widgets will ignore this verb.
8.20. Verb – Get Pin Widget Control (Verb ID=F07h)
Table 54. Verb – Get Pin Widget Control (Verb ID=F07h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F07h
0’s
Pin Control [7:0]
Codec Response for NID=14h, 15h, 16h, 18h~1Bh (Pin Complex)
Bit
31:1
7
Description
Reserved. Read as 0’s.
H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O unit).
0: Disabled
Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit).
0: Disabled 1: Enabled
In Enable (Input Buffer Enable, EN_IBUF for an I/O unit).
1: Enabled
6
5
0: Disabled
1: Enabled
4:
Reserved.
2:0
VrefEn (Vrefout Enable Control).
000b: Hi-Z (Disabled)
011b: Reserved
001b: 50% of AVDD
100b: 80% of AVDD
010b: Ground 0V
101b: 100% of AVDD
110b~111b: Reserved
Codec Response for other NID
Bit
Description
Not Supported (returns 00000000h).
31:0
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Datasheet
8.21. Verb – Set Pin Widget Control (Verb ID=707h)
Table 55. Verb – Set Pin Widget Control (Verb ID=707h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=707h
Pin Control [7:0]
‘Pin Control’ in command [7:0]: (NID=14h, 15h, 16h, 18h~1Bh)
Bit
31:1
7
Description
Reserved. Read as 0’s.
H-Phn Enable.
0: Disabled
1: Enabled
1: Enabled
6
5
Out Enable.
0: Disabled
In Enable (Input Buffer Enable, EN_IBUF for an I/O unit).
0: Disabled
1: Enabled
4:
Reserved.
2:0
VrefEn (Vrefout Enable Control).
000b: Hi-Z (Disabled)
011b: Reserved
001b: 50% of AVDD
100b: 80% of AVDD
010b: Ground 0V
101b: 100% of AVDD
110b~111b: Reserved
8.22. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an
unsolicited response to inform software of a real-time event.
Table 56. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F08h
0’s
32-bit Response
Codec Response for NID=01h (GPIO), 0Ah (S/PDIF-IN), 14h~16h, 18h~1Bh (Port), 21h (Volume in Step)
Bit
31:8
7
Description
Reserved. Read as 0’s.
Unsolicited Response is Enabled.
0: Disabled
1: Enabled
6:4
3:0
Reserved. Read as 0’s.
Assigned Tag for Unsolicited Response.
The tag[3:0] is assigned by software to determine which widget generates unsolicited responses.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Track ID: JATR-1076-21 Rev. 1.9
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Datasheet
8.23. Verb – Set Unsolicited Response Control (Verb ID=708h)
Enable a widget to generate an unsolicited response.
Table 57. Verb – Set Unsolicited Response Control (Verb ID=708h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=708h
EnableUnsol [7:0]
0’s for all nodes
‘EnableUnsol’ in Command Bit[7:0]
Bit
31:8
7
Description
Reserved. Read as 0’s.
Enable Unsolicited Response.
0: Disable
1: Enable
6:4
3:0
Reserved. Read as 0’s.
Tag for Unsolicited Response.
Tag[3:0] is defined by software to assign a 4-bit tag for nodes that are enabled to generate unsolicited
responses.
8.24. Verb – Get Pin Sense (Verb ID=F09h)
Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 58. Verb – Get Pin Sense (Verb ID=F09h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F09h
0’s
32-bit Response
Codec Response for NID =14h~16h, 18h~1Bh, 1Eh, 1Fh
Bit
Description
31
Presence Detect Status.
0: No device is attached to the pin
1: Device is attached to the pin
Measured Impedance.
30:0
0x7FFFFFFF or 0xFFFFFFFF: Valid sense is not available or is busy.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Datasheet
8.25. Verb – Execute Pin Sense (Verb ID=709h)
Table 59. Verb – Execute Pin Sense (Verb ID=709h)
Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=709h
Right Channel[0]
0’s for all nodes
‘Payload’ in Command Bit[7:0]
Bit
7:1
0
Description
Reserved. Read as 0’s.
Right (Ring) Channel Select.
0: Sense Left channel (Tip)
1: Sense Right channel (Ring)
8.26. Verb – Get Configuration Default (Verb ID=F1Ch)
Read the 32-bit sticky register for each Pin Widget configured by software.
Table 60. Verb – Get Configuration Default (Verb ID=F1Ch)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F1Ch
0’s
32-bit Response
Codec Response for NID=14h, 15h, 16h, 18h~1Fh
Bit
Description
32-bit configuration information for each pin widget.
31:0
Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function
Reset Verb).
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Datasheet
8.27. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh and
1Eh~1Fh such as placement and expected default device.
Table 61. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=71Ch,
Label [7:0]
0’s for all nodes
71Dh, 71Eh, 71Fh
Note: Supported by Pin Widget NID=14h~16h, 18h~1Fh. Other widgets will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
8.28. Verb – Get BEEP Generator (Verb ID=F0Ah)
Table 62. Verb – Get BEEP Generator (Verb ID=F0Ah)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F1Bh
0’s
Divider [7:0]
‘Response’ for NID=01h (Audio Function Group)
Bit
31:8
7:0
Description
Reserved.
Frequency Divider, F[7:0].
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in
F[7:0].
The lowest tone is 48kHz/(255*4)=47Hz.
The highest tone is 48kHz/(1*4)=12kHz.
A value of 00h in F[7:0] disables internal BEEP generator and allows external PCBEEP input.
Codec Response for Other NID
Bit
Description
31:0
0’s.
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Datasheet
8.29. Verb – Set BEEP Generator (Verb ID=70Ah)
Table 63. Verb – Set BEEP Generator (Verb ID=70Ah)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=71Bh
Divider [7:0]
‘Divider’ in Set Command
Bit
31:8
7:0
Description
Reserved.
Frequency Divider, F[7:0].
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in
F[7:0].
The lowest tone is 48kHz/(255*4)=47Hz.
The highest tone is 48kHz/(1*4)=12kHz.
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
8.30. Verb – Get GPIO Data (Verb ID=F15h)
Table 64. Verb – Get GPIO Data (Verb ID=F15h)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=F15h
0’s
32-bit Response
Codec Response for NID=01h (Audio Function Group)
Bit
31:4
3:0
Description
Reserved.
GPIO[3:0] Data.
The value written (output) or sensed (input) on the corresponding pin if it is enabled.
Codec Response for Other NID
Bit
Description
31:0
0’s.
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Datasheet
8.31. Verb – Set GPIO Data (Verb ID=715h)
Table 65. Verb – Set GPIO Data (Verb ID=715h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=715h
Data [7:0]
0’s for all nodes
‘Data’ in Set command for NID=01h (Audio Function Group)
Bit
31:4
3:0
Description
Reserved.
GPIO[3:0] Output Data.
The value written determines the value driven on a pin that is configured as an output pin.
Codec Response for All NID
Bit
Description
31:0
0’s.
8.32. Verb – Get GPIO Enable Mask (Verb ID=F16h)
Table 66. Verb – Get GPIO Enable Mask (Verb ID=F16h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F16h
0’s
EnableMask [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:4
3:0
Description
Reserved.
GPIO[3:0] Enable Mask.
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Datasheet
8.33. Verb – Set GPIO Enable Mask (Verb ID=716h)
Table 67. Verb – Set GPIO Enable Mask (Verb ID=716h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=716h
Enable Mask [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:4
3:0
Description
Reserved.
GPIO[3:0] Enable Mask.
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
8.34. Verb – Get GPIO Direction (Verb ID=F17h)
Table 68. Verb – Get GPIO Direction (Verb ID=F17h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F17h
0’s
Direction [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:4
3:0
Description
Reserved.
GPIO[3:0] Direction Control.
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Datasheet
8.35. Verb – Set GPIO Direction (Verb ID=717h)
Table 69. Verb – Set GPIO Direction (Verb ID=717h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=717h
Direction [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:4
3:0
Description
Reserved.
GPIO[3:0] Direction Control.
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.36. Verb – Get GPIO Unsolicited Response Enable Mask
(Verb ID=F19h)
Table 70. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F19h
0’s
UnsolEnable [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:4
3:0
Description
Reserved.
GPIO[3:0] Unsolicited Enable Mask.
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
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Datasheet
8.37. Verb – Set GPIO Unsolicited Response Enable Mask
(Verb ID=719h)
Table 71. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=719h
UnsolEnable [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:4
3:0
Description
Reserved.
GPIO[3:0] Unsolicited Enable Mask.
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb.
Note 2: The unsolicited response of corresponding GPIO is enabled when it’s ‘Enable Mask’and Verb-‘Unsolicited
Response’for NID=01h are enabled.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.38. Verb – Function Reset (Verb ID=7FFh)
Table 72. Verb – Function Reset (Verb ID=7FFh)
Command Format (NID=01H)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=7FFh
0’s
Codec Response
Bit
Description
Reserved. Read as 0’s.
31:0
Note: The Function Reset command causes all widgets in the ALC262 to return to their power on default state.
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Datasheet
8.39. Verb – Get Digital Converter Control 1 & Control 2
(Verb ID=F0Dh, F0Eh)
Table 73. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID=F0Dh, F0Eh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F0Dh/F0Eh
0’s
Bit[31:16]=0’s, Bit[15:0] are SIC bit
NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0]).
NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Eh (Control 2 for SIC bit[15:0])
Bit
31:16
15
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Read as 0’s.
Reserved. Read as 0’s.
14:8
7
CC[6:0] (Category Code).
LEVEL (Generation Level).
6
PRO (Professional or Consumer Format).
0: Consumer format
/AUDIO (Non-Audio Data Type).
0: PCM data
COPY (Copyright).
0: Asserted
1: Professional format
5
4
3
1: AC3 or other digital non-audio data
1: Not asserted
PRE (Pre-Emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
2
1
0
VCFG for Validity Control (control V bit and data in Sub-Frame).
V for Validity Control (control V bit and data in Sub-Frame).
Digital Enable. DigEn.
0: OFF
1: ON
NID=0Ah (S/PDIF-IN) Response to ‘Get verb (F0Dh)’. NID=0Ah (S/PDIF-IN) Response to ‘Get verb (F0Eh)’
Bit
31:16
15
Description (a part of S/PDIF-IN Channel Status)
Reserved. Read as 0’s.
Reserved. Read as 0’s.
14:8
7
CC[6:0] (Category Code).
LEVEL (Generation Level).
6
PRO (Professional or Consumer Format).
0: Consumer format
/AUDIO (Non-Audio Data Type).
0: PCM data
COPY (Copyright).
0: Asserted
1: Professional format
5
4
3
1: AC3 or other digital non-audio data
1: Not asserted
PRE (Pre-Emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
2
1
Reserved.
In‘V’alid. V Bit in Sub-Frame of S/PDIF-IN.
0: Data X and Y are valid, or S/PDIF-IN is not locked
1: At least one of data X and Y is invalid
Digital Enable. DigEn. 0: OFF; 1: ON
0
Codec Response for Other NID
Bit
Description
31:0
0’s.
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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Datasheet
8.40. Verb – Set Digital Converter Control 1 & Control 2
(Verb ID=70Dh, 70Eh)
Table 74. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Set Command Format (Verb ID=70Xh, Set Control 1)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=70Dh
SIC [7:0]
Set Command Format (Verb ID=70Yh, Set Control 2)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=70Eh
SIC [15:8]
‘Payload’ in Set Control 1 for NID=06h (S/PDIF-OUT)
Bit
7
Description – SIC (S/PDIF IEC Control) Bit[7:0]
LEVEL (Generation Level).
6
PRO (Professional or Consumer Format).
0: Consumer format
1: Professional format
5
4
3
/AUDIO (Non-Audio Data Type).
0: PCM data
1: AC3 or other digital non-audio data
1: Not asserted
COPY (Copyright).
0: Asserted
PRE (Pre-Emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
2
1
0
VCFG for Validity Control (control V bit and data in Sub-Frame).
V for Validity Control (control V bit and data in Sub-Frame).
Digital Enable. DigEn.
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=06h (S/PDIF-OUT)
Bit
7
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Reserved. Read as 0’s.
6:0
CC[6:0] (Category Code).
‘Payload’ in Set Control 1 for NID=0Ah (S/PDIF-IN)
Bit
7:1
0
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Reserved.
Digital Enable. DigEn.
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=0Ah (S/PDIF-IN)
Bit
Description – SIC (S/PDIF IEC Control) Bit[7:0]
7:0
Reserved. Read as 0’s.
Note: Other widgets will ignore this verb.
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Datasheet
8.41. Get/Set Volume Knob Widget (NID=21h)
(Verb ID=F0Fh/70Fh)
Table 75. Get/Set Volume Knob Widget (NID=21h) (Verb ID=F0Fh/70Fh)
Get Command Format Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F0Fh
0’s
Bit[31:8]=0’s, Bit[7:0] is volume
Codec Response for NID=21h (Volume Knob Widget)
Bit
31:8
7
Description
Reserved.
Direct.
0: The volume generated by an external HW volume control will be sent by unsolicited response. Software
is responsible for programming the amplifier appropriately
1: The volume generated by an external HW volume control will directly affect amplifier volume
6:0
Volume in steps.
Set Command Format (Verb ID=70Yh, Set Control 2)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=70Fh Bit[7] is ‘Direct’ control
‘Payload’ in Set Command for NID=21h (Volume Knob Widget)
Bit
31:8
7
Description
Reserved.
Direct.
0: The volume generated by an external HW volume control will be sent by unsolicited response. Software
is responsible for programming the amplifier appropriately
1: The volume generated by an external HW volume control will directly affect amplifier volume
6:0
Reserved.
Note: Other nodes will ignore this verb.
8.42. Get/Set Subsystem ID [31:0]
(Verb ID=F20h/723h~720h to Set Bit[31:0])
Table 76. Get/Set Subsystem ID [31:0] (Verb ID=F20h / 723h~720h to Set Bit[31:0])
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F20h
0’s
32 bits response
Codec Response for NID=01h (Audio Function Group)
Bit
31:16
15:8
7:0
Description
Subsystem ID[23:8]. (Default=10ECh).
Subsystem ID[7:0]. (Default=02h).
Assembly ID[7:0]. (Default=62h).
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Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1.
Absolute Maximum Ratings
Table 77. Absolute Maximum Ratings
Parameter
Symbol
Minimum
Typical
Maximum
Units
Power Supplies
Digital Power for Core
Digital Power for Link (C, D)*
Analog Power
DVDD-CORE
DVDD-IO
AVDD**
3.0
1.3
3.0
3.3
3.3
3.3
3.6
3.6
5.5
V
V
V
oC
oC
Ambient Operating Temperature
Storage Temperature
Ta
Ts
0
-
-
-
+70
+125
ESD (Electrostatic Discharge)
Susceptibility Voltage
3000V
Pin 33 (DCVOL) (ver. A/B/C)
All Pins (ver. D)
4000V
*: The digital link power DVDD-IO must be lower than the digital core power DVDD.
**: The standard testing condition before shipping is AVDD = 5.0V unless specified. Customers designing with a different
AVDD should contact Realtek technical support representatives for special testing support.
9.1.2.
Threshold Voltage
DVDD-IO=3.3V±5%, Tambient=25°C, with 50pF external load.
Table 78. Threshold Voltage
Parameter
Symbol
Vin
Minimum
Typical
Maximum
DVDD +0.30
0.30*DVDD-IO
Units
V
Input Voltage Range
-0.30
-
-
-
Low Level Input Voltage
VIL
V
(BCLK, RST#, SDO, SYNC, SDI)
High Level Input Voltage
(BCLK, RST#, SDO, SYNC, SDI)
VIH
VIL
0.65*DVDD-IO
-
-
-
-
-
-
-
V
V
V
V
V
Low Level Input Voltage
(S/PDIF-IN/OUT, GPIOs)
0.44*DVDD
(1.45)
High Level Input Voltage
(S/PDIF-IN/OUT, GPIOs)
VIH
VOH
VOL
0.56*DVDD
(1.85)
-
High Level Output Voltage
(BCLK, RST#, SDO, SYNC, SDI)
0.9*DVDD-IO
-
Low Level Output Voltage
-
0.1*DVDD-IO
(BCLK, RST#, SDO, SYNC, SDI)
Input Leakage Current
-
-
-
-
-10
-10
-
-
-
10
10
-
µA
µA
mA
Ω
Output Leakage Current (Hi-Z)
Output Buffer Drive Current
Internal Pull Up Resistance
5
-
50k
-
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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ALC262 Series
Datasheet
9.1.3.
Digital Filter Characteristics
Table 79. Digital Filter Characteristics
Filter
Symbol
Minimum
Typical
Maximum
Units
kHz
kHz
kHz
dB
ADC Lowpass Filter
Passband (A/B silicon)
Passband (C/D silicon)
Stopband
0
-
19.2 (-3dB)
0.458*Fs (-1dB)
0.6*Fs
-
-
-
-
-
Stopband Rejection
Passband Ripple (A/B)
Passband Ripple (C/D)
-
-
-
-76.0
±0.20
±0.05
-
dB
dB
DAC Lowpass Filter
Passband (A/B silicon)
Passband (C/D silicon)
Stopband
0
0
19.2 (-3dB)
0.435*Fs (-1dB)
kHz
kHz
kHz
dB
-
0.6*Fs
-
-
-
-
-
Stopband Rejection
Passband Ripple (A/B)
Passband Ripple (C/D)
-
-
-
-78.5
±0.20
±0.03
dB
dB
9.1.4.
S/PDIF Input/Output Characteristics
DVDD=3.3V, Tambient=25°C, with 75Ω external load.
Table 80. S/PDIF Input/Output Characteristics
Parameter
Symbol
VOH
VOL
VIH
Minimum
Typical
Maximum
Units
S/PDIF-OUT High Level Output
S/PDIF-OUT Low Level Output
S/PDIF-IN High Level Input
S/PDIF-IN Low Level Input
S/PDIF-IN Bias Level
3.0
3.3
-
0.3
-
V
V
V
V
V
-
0
1.85
-
-
VIL
-
-
1.45
-
Vt
1.65
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Datasheet
9.2. AC Characteristics
9.2.1.
Link Reset and Initialization Timing
Table 81. Link Reset and Initialization Timing
Parameter
Symbol
TRST
Minimum
Typical
Maximum
Units
µs
RESET# Active Low Pulse Width
RESET# Inactive to BCLK
1.0
20
-
-
-
-
TPLL
µs
Startup Delay for PLL Ready Time
SDI Initialization Request
TFRAME
-
-
1
Frame Time
Initialization
Sequence
>= 4 BCLK
4 BCLK
4 BCLK
BCLK
SYNC
Normal Frame
SYNC
SDO
SDI
Initialization
Request
RESET#
TRST
TPLL
TFRAME
Figure 20. Link Reset and Initialization Timing
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Datasheet
9.2.2.
Link Timing Parameters at the Codec
Table 82. Link Timing Parameters at the Codec
Parameter
Symbol
Minimum
Typical
Maximum
Units
MHz
ns
BCLK Frequency
BCLK Period
-
-
24.0
-
-
-
T_cycle
41.67
BCLK Jitter
T_jitter
T_high
T_low
-
-
-
-
-
2.0
24.16
24.16
-
ns
BCLK High Pulse Width
BCLK Low Pulse Width
17.5
17.5
2.1
ns
ns
SDO Setup Time at Both Rising and
Falling Edge of BCLK
T_setup
ns
SDO Hold Time at Both Rising and
Falling Edge of BCLK
T_hold
T_tco
2.1
-
-
-
-
ns
ns
SDI Valid Time After Rising Edge of
BCLK (1:50pF external load)
(DVDD-IO=3.3V)
7.5
SDI Valid Time After Rising Edge of
BCLK (1:50pF external load)
(DVDD-IO=1.5V)
T_tco
-
-
10.0
2.0
-
-
ns
ns
SDI Flight Time
T_flight
T_cycle
T_high
V
IH
BCLK
SDO
V
V
T
IL
T_low
T_setup T_hold
T_tco
V
OH
SDI
V
OL
T_flight
Figure 21. Link Signals Timing
4-Ch DAC and 6-Ch ADC High Definition Audio Code
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ALC262 Series
Datasheet
9.2.3.
S/PDIF Output and Input Timing
Table 83. S/PDIF Output and Input Timing
Parameter
Symbol
-
Minimum
Typical
6.144
Maximum
Units
MHz
ns
S/PDIF-OUT Frequency*1
S/PDIF-OUT Period*1
-
-
Tcycle
Tjitter
THigh
TLow
Trise
-
162.8
-
S/PDIF-OUT Jitter
-
-
4
ns
S/PDIF-OUT High Level Width*1
S/PDIF-OUT Low Level Width*1
S/PDIF-OUT Rising Time
S/PDIF-OUT Falling Time
S/PDIF-IN Period*2
78.1 (48%)
81.4 (50%)
81.4 (50%)
2.0
84.6 (52%)
ns (%)
ns (%)
ns
78.1 (48%)
84.6 (52%)
-
-
Tfall
-
2.0
-
ns
Tcycle
Tjitter
THigh
TLow
-
162.8
-
ns
S/PDIF-IN Jitter
-
-
10
ns
S/PDIF-IN High Level Width*2
S/PDIF-IN Low Level Width*2
73.2 (45%)
73.2 (45%)
81.4 (50%)
81.4 (50%)
89.5 (55%)
89.5 (55%)
ns (%)
ns (%)
*1: Bit parameters for 48kHz sample rate of S/PDIF-OUT
*2: Bit parameters for 48kHz sample rate of S/PDIF-IN
T
cycle
T
T
low
high
V
OH
V
IH
V
t
V
IL
V
OL
T
T
rise
fall
Figure 22. Output and Input Timing
9.2.4.
Test Mode
The ALC262 series does not support codec test mode or Automatic Test Equipment (ATE) mode.
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Datasheet
9.3. Analog Performance
• Tambient=25 oC, DVDD-CORE=3.3V ±5%, AVDD=5.0V±5%
Standard Test Conditions
• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
• 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz,
0dB attenuation
Table 84. Analog Performance
Parameter
Min
Typ
Max
Units
Full Scale Input Voltage
All Inputs (Gain=0dB)
All ADC
-
-
1.5
1.1
-
-
Vrms
Vrms
Full Scale Output Voltage
All DAC (Ver. A/B/C)
All DAC (Ver. D)
-
-
1.4
1.2
-
-
Vrms
Vrms
S/N (A Weighted)
ADC
-
-
90
100
-
-
dB FSA
dB FSA
DAC
THD+N
ADC
DAC
-
-
-
-82
-87
-75
-
-
-
dB FS
dB FS
dB FS
Headphone Out @32Ω Load (Version B0)
Frequency Response
Mixers
10
16
10
-
-
-
22,000
19,200
0.454*Fs
Hz
Hz
Hz
ADC, DAC (Ver. B Silicon, -3dB Band Edge)
ADC, DAC (Ver. C/D Silicon, -1dB Band Edge)*
Power Supply Rejection
-
-
-
-
-
-40
-60
1.5
-80
64
-
-
-
-
-
dB
dB
dB
dB
KΩ
Total Out-of-Band Noise (28.8kHz~100kHz)
Amplifier Gain Step
Crosstalk Between Input Channels
Input Impedance (Gain=0dB)
Output Impedance
Amplified Output
-
-
1
200
-
-
Ω
Ω
Non-Amplified Output
Digital Power Supply Current (Normal Operation)
DVDD-CORE=3.3V, DVDD-IO=3.3V
-
-
-
-
40
-
mA
µA
mA
µA
Digital Power Supply Current (Power Down Mode)
DVDD-CORE=3.3V, DVDD-IO=3.3V
-
600
-
Analog Power Supply Current (Normal Operation)
AVDD=5.0V
52
-
Analog Power Supply Current (Power Down Mode)
AVDD=5.0V
600
VREFOUTx Output Voltage
VREFOUTx Output Current
*Fs = Sample rate.
2.25
-
2.50
5
3.75
-
V
mA
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ALC262 Series
Datasheet
10. Application Notes
10.1. Application Circuit
Please contact Realtek for the latest application circuits. To get the best compatibility in hardware design
and software driver, any modification should be confirmed by Realtek. Realtek may upload the latest
application circuits onto our web site (www.realtek.com.tw) without modifying this datasheet.
10.2. Volume Control Via External Variable Resistor
The input range of DCVOL is from GND to AVDD. A 5-bit resolution ADC converts the DC level on the
variable resistor into 32 steps for the Volume knob. DC level changes will be reflected to software to
control the master volume.
ALC262
AVDD=5V
5-bit
Variable
Resistor
DCVOL (Pin 33)
ADC
Volume Code [4:0]
+5V: DCVOL=31
0V: DCVOL=0
Figure 23. Volume Control by External Variable Resistor
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Datasheet
10.3. Volume Control Via GPIO0/GPIO1
Detected low pulses generated at GPIO0 and GPIO1 are used to calculate the Up and Down count into 7
bits of volume steps. ‘Mute’ is also sampled to toggle the mute status. Hardware will not adjust volume.
The count value will be reported via unsolicited response to software to control the master volume.
+3.3V (VCC)
+3.3 (VCC)
50K
50K
4.7K
GPIO0 (pin 43)
GPIO1 (pin 44)
Up: Counter+1
Dn:Counter-1
0~127
Volume[6:0]
Mute
Down
Up
ALC262
4.7K
Figure 24. Volume Control via GPIO0 and GPIO1
10.4. Digital Microphone Implementation
This section describes the ALC262 digital microphone implementation. There is one Clock output pin
and 1 Data input pin in the ALC262. The ALC262 provides the clock signal to the digital microphone.
When the digital microphone receives the external sound input, it converts the analog signals to digital in
a 1-bit format. The 1-bit data is delivered to the codec though the data input pin. The Digital Filter in the
audio codec converts the 1-bit data stream into Pulse Code Modulation (PCM) data. The PCM data is sent
to the HDA controller through the HDA link.
Figure 25. Digital Microphone Implementation-1
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ALC262 Series
Datasheet
The ALC262 supports a two-wire interface for the digital microphone and operates in single channel
(mono type) or stereo channels (stereo) digital microphone mode. One pin is clock output to the digital
microphone, and the other is a serial pin. The default clock output is 2.048MHz.
In Type 1 (Figure 26), the ALC262 uses one data pin to support mono input from digital microphones
with an LMV1024 (L), SPD0205ND (L), or AKU2000 (L).
In Type 2 (Figure 26), the ALC262 uses one data pin to support stereo inputs from digital microphones
with an LMV1024/1026 (L/R), SPD0205ND (L & R), or AKU2000 (L & R).
Figure 26. Digital Microphone Implementation-2
By default the left channel digital microphone data is sampled at the rising edge of clock, and the right
channel data at the falling edge of clock. Figure 27 indicates 20nsec setup time and 5ns hold time are
required to allow the ALC262 to get individual data correctly.
DMIC-CLK
20ns
20ns
Right
Left
DMIC-DATA
5ns
5ns
Figure 27. Digital Microphone Timing
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ALC262 Series
Datasheet
11. Mechanical Dimensions
L
L1
See the Mechanical Dimensions notes on the next page.
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Track ID: JATR-1076-21 Rev. 1.9
ALC262 Series
Datasheet
11.1. Mechanical Dimensions Notes
SYMBOL
MILLIMETER
MIN TYP MAX MIN
INCH
TYP MAX
A
A1
A2
c
-
-
-
1.60
0.15
1.45
0.20
-
-
-
0.063
0.006
0.05
1.35
0.09
0.002
1.40
0.053 0.055 0.057
TITLE: LQFP-48 (7.0x7.0x1.6mm)
PACKAGE OUTLINE DRAWING,
FOOTPRINT 2.0mm
-
0.004
-
0.008
D
9.00 BSC
7.00 BSC
5.50
0.354 BSC
0.276 BSC
0.217
LEADFRAME MATERIAL
D1
D2
E
APPROVE
DOC. NO.
9.00 BSC
7.00 BSC
5.50
0.354 BSC
0.276 BSC
0.217
VERSION 02
DWG NO. PKGC-065
DATE
E1
E2
b
CHECK
0.17
0.20
0.27
0.007 0.008 0.011
0.0196 BSC
0o
REALTEK SEMICONDUCTOR CORP.
e
0.50 BSC
3.5o
TH
L
0o
0.45
-
7o
0.75
-
3.5o
7o
0.60
0.018 0.0236 0.030
0.0393
L1
1.00
-
-
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ALC262 Series
Datasheet
12. Ordering Information
Table 85. Ordering Information
Part Number
ALC262-GR
Package
Status
Version A2 silicon, LQFP-48 &‘Green’ package
Version B0 silicon, LQFP-48 &‘Green’ package
ALC262-VB0-GR + SRS TruSurround XT (software feature)
ALC262-VB0-GR + Dolby® Home Theater (software feature)
Version C1 silicon, LQFP-48 &‘Green’ package
Version C2 silicon, LQFP-48 &‘Green’ package
Version D2 silicon, LQFP-48 &‘Green’ package
ALC262-VD2-GR + Waves MaxxAudio (software feature)
Production
Production
Production
Production
Production
Production
Production
Production
ALC262-VB0-GR
ALC262SRS-GR
ALC262H-GR
ALC262-VC1-GR
ALC262-VC2-GR
ALC262-VD2-GR
ALC262W-VD2-GR
Note 1: See section 5 Pin Assignments, page 10 for Green package and version identification.
Note 2: Above parts are tested under AVDD =5.0V. If customers have lower AVDD request, please contact Realtek sales
representatives or agents.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
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Track ID: JATR-1076-21 Rev. 1.9
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