ALC5616-CGT [REALTEK]
Consumer Circuit, PQCC32, QFN-32;
| 型号： | ALC5616-CGT |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | Consumer Circuit, PQCC32, QFN-32 LTE 商用集成电路 |
| 文件： | 总104页 (文件大小：1573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC5616
Ultra-Low Power Audio CODEC
for Mobile Devices
Datasheet
Rev. 0.1
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
ALC5616
Datasheet
COPYRIGHT
© 2012 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC5616 Audio Codec IC.
Though every effort has been made to ensure that this document is current and accurate, more
information may have become available subsequent to the production of this guide.
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Datasheet
REVISION HISTORY
Revision
Release Date
Summary
0.1
2012/7/29
Preliminary version
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Datasheet
Table of Contents
1.
2.
3.
4.
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................2
SYSTEM APPLICATION.................................................................................................................................................2
FUNCTION BLOCK AND MIXER PATH .....................................................................................................................3
4.1.
4.2.
4.3.
FUNCTION BLOCK........................................................................................................................................................3
AUDIO MIXER PATH.....................................................................................................................................................4
DIGITAL MIXER PATH..................................................................................................................................................5
5.
6.
PIN ASSIGNMENTS .........................................................................................................................................................6
PIN DESCRIPTIONS.........................................................................................................................................................7
6.1.
DIGITAL I/O PINS.........................................................................................................................................................7
ANALOG I/O PINS ........................................................................................................................................................7
FILTER/REFERENCE......................................................................................................................................................8
POWER/GROUND..........................................................................................................................................................9
6.2.
6.3.
6.4.
7.
FUNCTION DESCRIPTION ..........................................................................................................................................10
7.1.
7.2.
7.3.
POWER .......................................................................................................................................................................10
POWER SUPPLY ON/OFF SEQUENCE...........................................................................................................................11
RESET ........................................................................................................................................................................12
7.3.1. Power-On Reset (POR) ........................................................................................................................................12
7.3.2. Software Reset ......................................................................................................................................................12
7.4.
CLOCKING..................................................................................................................................................................13
7.4.1. Phase-Locked Loop ..............................................................................................................................................14
7.4.2. I2C and I2S/PCM Interface ...................................................................................................................................15
7.5.
DIGITAL DATA INTERFACE ........................................................................................................................................16
7.5.1. Two I2S/PCM Interface.........................................................................................................................................16
7.6.
AUDIO DATA PATH ....................................................................................................................................................19
7.6.1. Stereo Analog ADCs Record Path........................................................................................................................19
7.6.2. Stereo Analog DACs with Playback Path.............................................................................................................20
7.6.3. Mixers...................................................................................................................................................................21
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
ANALOG AUDIO INPUT PORT .....................................................................................................................................22
ANALOG AUDIO OUTPUT PORT..................................................................................................................................23
MULTI-FUNCTION PINS..............................................................................................................................................24
DRC AND AGC FUNCTION ........................................................................................................................................25
EQUALIZER BLOCK ....................................................................................................................................................28
WIND FILTER WITH DYNAMIC WIND NOISE DETECTOR.............................................................................................28
7.12.1.
7.13.
Wind Filter.......................................................................................................................................................28
I2C CONTROL INTERFACE ..........................................................................................................................................31
7.13.1.
7.13.2.
7.14.
7.15.
Address Setting ................................................................................................................................................31
Complete Data Transfer ..................................................................................................................................31
GPIO, INTERRUPT AND JACK DETECTION..................................................................................................................33
POWER MANAGEMENT...............................................................................................................................................36
8.
REGISTERS LIST ...........................................................................................................................................................37
8.1.
8.2.
8.3.
REGISTER MAP ..........................................................................................................................................................37
MX-00H: S/W RESET & DEVICE ID...........................................................................................................................39
MX-02H: HEADPHONE OUTPUT CONTROL.................................................................................................................39
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8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
MX-03H: LINE OUTPUT CONTROL 1.........................................................................................................................41
MX-05H: LINE OUTPUT CONTROL 2.........................................................................................................................42
MX-0DH: IN1/2 INPUT CONTROL..............................................................................................................................42
MX-0FH: INL & INR VOLUME CONTROL .................................................................................................................43
MX-19H: DACL1/R1 DIGITAL VOLUME ...................................................................................................................44
MX-1CH: STEREO1 ADC DIGITAL VOLUME CONTROL.............................................................................................46
MX-1EH: ADC DIGITAL BOOST GAIN CONTROL ......................................................................................................48
MX-27H: STEREO1 ADC DIGITAL MIXER CONTROL.................................................................................................48
MX-29H: STEREO ADC TO DAC DIGITAL MIXER CONTROL.....................................................................................49
MX-2AH: STEREO DAC DIGITAL MIXER CONTROL..................................................................................................49
MX-3BH: RECMIXL CONTROL 1 .............................................................................................................................50
MX-3CH: RECMIXL CONTROL 2 .............................................................................................................................51
MX-3DH: RECMIXR CONTROL 1.............................................................................................................................51
MX-3EH: RECMIXR CONTROL 2 .............................................................................................................................52
MX-45H: HPOMIX CONTROL...................................................................................................................................53
MX-4DH: OUTMIXL CONTROL 1 ............................................................................................................................53
MX-4EH: OUTMIXL CONTROL 2.............................................................................................................................54
MX-4FH: OUTMIXL CONTROL 3 .............................................................................................................................54
MX-50H: OUTMIXR CONTROL 1 .............................................................................................................................55
MX-51H: OUTMIXR CONTROL 2 .............................................................................................................................56
MX-52H: OUTMIXR CONTROL 3 .............................................................................................................................56
MX-53H: LOUTMIX CONTROL ................................................................................................................................57
MX-61H: POWER MANAGEMENT CONTROL 1............................................................................................................58
MX-62H: POWER MANAGEMENT CONTROL 2............................................................................................................58
MX-63H: POWER MANAGEMENT CONTROL 3............................................................................................................59
MX-64H: POWER MANAGEMENT CONTROL 4............................................................................................................60
MX-65H: POWER MANAGEMENT CONTROL 5............................................................................................................60
MX-66H: POWER MANAGEMENT CONTROL 6............................................................................................................61
MX-6AH: PRIVATE REGISTER INDEX.........................................................................................................................62
MX-6CH: PRIVATE REGISTER DATA..........................................................................................................................62
MX-70H: I2S1 DIGITAL INTERFACE CONTROL ..........................................................................................................62
MX-73H: ADC/DAC CLOCK CONTROL 1..................................................................................................................63
MX-74H: ADC/DAC CLOCK CONTROL 2..................................................................................................................63
MX-80H: GLOBAL CLOCK CONTROL.........................................................................................................................64
MX-81H: PLL CONTROL 1.........................................................................................................................................64
MX-82H: PLL CONTROL 2.........................................................................................................................................65
MX-8EH: HP AMP CONTROL 1..................................................................................................................................65
MX-8FH: HP AMP CONTROL 2 ..................................................................................................................................66
MX-93H: MICBIAS CONTROL..................................................................................................................................66
MX-94H: JACK DETECTION CONTROL.......................................................................................................................67
MX-B0H: EQ CONTROL 1..........................................................................................................................................67
MX-B1H: EQ CONTROL 2..........................................................................................................................................68
MX-B4H: DRC/AGC CONTROL 1 .............................................................................................................................69
MX-B5H: DRC/AGC CONTROL 2 .............................................................................................................................70
MX-B6H: DRC/AGC CONTROL 3 .............................................................................................................................72
MX-BBH: JACK DETECTION CONTROL 1...................................................................................................................73
MX-BCH: JACK DETECTION CONTROL 2...................................................................................................................73
MX-BDH: IRQ CONTROL 1 .......................................................................................................................................74
MX-BEH: IRQ CONTROL 2........................................................................................................................................75
MX-BFH: GPIO AND INTERNAL STATUS...................................................................................................................75
MX-C0H: GPIO CONTROL 1......................................................................................................................................76
MX-C1H: GPIO CONTROL 2......................................................................................................................................76
MX-D3H: WIND FILTER CONTROL 1 .........................................................................................................................77
MX-D4H: WIND FILTER CONTROL 2 .........................................................................................................................77
MX-D9H: SOFT VOLUME & ZCD CONTROL..............................................................................................................78
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
8.17.
8.18.
8.19.
8.20.
8.21.
8.22.
8.23.
8.24.
8.25.
8.26.
8.27.
8.28.
8.29.
8.30.
8.31.
8.32.
8.33.
8.34.
8.35.
8.36.
8.37.
8.38.
8.39.
8.40.
8.41.
8.42.
8.43.
8.44.
8.45.
8.46.
8.47.
8.48.
8.49.
8.50.
8.51.
8.52.
8.53.
8.54.
8.55.
8.56.
8.57.
8.58.
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8.59.
8.60.
8.61.
8.62.
8.63.
8.64.
8.65.
8.66.
8.67.
8.68.
8.69.
8.70.
8.71.
8.72.
8.73.
8.74.
8.75.
8.76.
8.77.
8.78.
8.79.
8.80.
8.81.
8.82.
MX-FAH: GENERAL CONTROL 1 ...............................................................................................................................79
PR-3DH: ADC/DAC RESET CONTROL ....................................................................................................................79
PR-A0H: EQ LOW PASS FILTER COEFFICIENT (LPF:A1) ...........................................................................................80
PR-A1H: EQ LOW PASS FILTER GAIN (LPF:H0) .......................................................................................................80
PR-A2H: EQ BAND 1 COEFFICIENT (BPF1:A1) .........................................................................................................80
PR-A3H: EQ BAND 1 COEFFICIENT (BPF1:A2) .........................................................................................................80
PR-A4H: EQ BAND 1 GAIN (BPF1:H0) .....................................................................................................................81
PR-A5H: EQ BAND 2 COEFFICIENT (BPF2:A1) .........................................................................................................81
PR-A6H: EQ BAND 2 COEFFICIENT (BPF2:A2) .........................................................................................................81
PR-A7H: EQ BAND 2 GAIN (BPF2:H0) .....................................................................................................................81
PR-A8H: EQ BAND 3 COEFFICIENT (BPF3:A1) .........................................................................................................82
PR-A9H: EQ BAND 3 COEFFICIENT (BPF3:A2) .........................................................................................................82
PR-AAH: EQ BAND 3 GAIN (BPF3:H0) ....................................................................................................................82
PR-ABH: EQ BAND 4 COEFFICIENT (BPF4:A1).........................................................................................................82
PR-ACH: EQ BAND 4 COEFFICIENT (BPF4:A2).........................................................................................................83
PR-ADH: EQ BAND 4 GAIN (BPF4:H0) ....................................................................................................................83
PR-AEH: EQ HIGH PASS FILTER 1 COEFFICIENT (HPF1:A1).....................................................................................83
PR-AFH: EQ HIGH PASS FILTER 1 GAIN (HPF1:H0).................................................................................................83
PR-B0H: EQ HIGH PASS FILTER 2 COEFFICIENT (HPF2:A1)......................................................................................84
PR-B1H: EQ HIGH PASS FILTER 2 COEFFICIENT (HPF2:A2)......................................................................................84
PR-B2H: EQ HIGH PASS FILTER 2 GAIN (HPF2:H0) .................................................................................................84
PR-B3H: EQ PRE VOLUME CONTROL........................................................................................................................84
PR-B4H: EQ POST VOLUME CONTROL ......................................................................................................................85
MX-FEH: VENDOR ID ...............................................................................................................................................85
9.
ELECTRICAL CHARACTERISTICS ..........................................................................................................................86
9.1.
DC CHARACTERISTICS...............................................................................................................................................86
9.1.1. Absolute Maximum Ratings..................................................................................................................................86
9.1.2. Recommended Operating Conditions...................................................................................................................86
9.1.3. Static Characteristics ...........................................................................................................................................86
9.2.
9.3.
ANALOG PERFORMANCE CHARACTERISTICS..............................................................................................................87
SIGNAL TIMING..........................................................................................................................................................89
9.3.1. I2C Control Interface............................................................................................................................................89
9.3.2. I2S/PCM Interface Master Mode ..........................................................................................................................90
9.3.3. I2S/PCM Interface Slave Mode.............................................................................................................................91
10.
11.
12.
APPLICATION CIRCUITS .......................................................................................................................................92
PACKAGE INFORMATION.....................................................................................................................................94
ORDERING INFORMATION...................................................................................................................................95
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Datasheet
List of Tables
TABLE 1. DIGITAL I/O PINS ..........................................................................................................................................................7
TABLE 2. ANALOG I/O PINS..........................................................................................................................................................7
TABLE 3. FILTER/REFERENCE.......................................................................................................................................................8
TABLE 4. POWER/GROUND ...........................................................................................................................................................9
TABLE 5. POWER SUPPLY FOR BEST PERFORMANCE...................................................................................................................10
TABLE 6. POWER SUPPLY CONDITION FOR POWER DOWN LEAKAGE..........................................................................................10
TABLE 7. RESET OPERATION ......................................................................................................................................................12
TABLE 8. POWER-ON RESET VOLTAGE.......................................................................................................................................12
TABLE 9. CLOCK SETTING TABLE FOR 48K (UNIT: MHZ) ..........................................................................................................14
TABLE 10. CLOCK SETTING TABLE FOR 44.1K (UNIT: MHZ) .....................................................................................................14
TABLE 11. THE RELATIVE OF SYSCLK/BCLK/LRCK...............................................................................................................15
TABLE 12. SAMPLE RATE WITH FILTER COEFFICIENT FOR WIND FILTER.....................................................................................29
TABLE 13. ADDRESS SETTING (0X36H) ......................................................................................................................................31
TABLE 14. WRITE WORD PROTOCOL ........................................................................................................................................32
TABLE 15. READ WORD PROTOCOL..........................................................................................................................................32
TABLE 16. REGISTER MAP ..........................................................................................................................................................37
TABLE 17. MX-00H: S/W RESET & DEVICE ID ..........................................................................................................................39
TABLE 18. MX-02H: HEADPHONE OUTPUT CONTROL................................................................................................................39
TABLE 19. MX-03H: LINE OUTPUT CONTROL 1 ........................................................................................................................41
TABLE 20. MX-05H: LINE OUTPUT CONTROL 2 ........................................................................................................................42
TABLE 21. MX-0DH: IN1/2 INPUT CONTROL .............................................................................................................................42
TABLE 22. MX-0FH: INL & INR VOLUME CONTROL.................................................................................................................43
TABLE 23. MX-19H: DACL1/R1 DIGITAL VOLUME ..................................................................................................................44
TABLE 24. MX-1CH: STEREO1 ADC DIGITAL VOLUME CONTROL ............................................................................................46
TABLE 25. MX-1EH: ADC DIGITAL BOOST GAIN CONTROL......................................................................................................48
TABLE 26. MX-27H: STEREO1 ADC DIGITAL MIXER CONTROL ................................................................................................48
TABLE 27. MX-29H: STEREO ADC TO DAC DIGITAL MIXER CONTROL....................................................................................49
TABLE 28. MX-2AH: STEREO DAC DIGITAL MIXER CONTROL .................................................................................................49
TABLE 29. MX-3BH: RECMIXL CONTROL 1 ............................................................................................................................50
TABLE 30. MX-3CH: RECMIXL CONTROL 2 ............................................................................................................................51
TABLE 31. MX-3DH: RECMIXR CONTROL 1............................................................................................................................51
TABLE 32. MX-3EH: RECMIXR CONTROL 2 ............................................................................................................................52
TABLE 33. MX-45H: HPOMIX CONTROL ..................................................................................................................................53
TABLE 34. MX-4DH: OUTMIXL CONTROL 1............................................................................................................................53
TABLE 35. MX-4EH: OUTMIXL CONTROL 2 ............................................................................................................................54
TABLE 36. MX-4FH: OUTMIXL CONTROL 3 ............................................................................................................................54
TABLE 37. MX-50H: OUTMIXR CONTROL 1 ............................................................................................................................55
TABLE 38 MX-51H: OUTMIXR CONTROL 2 .............................................................................................................................56
TABLE 39. MX-52H: OUTMIXR CONTROL 3 ............................................................................................................................56
TABLE 40 MX-53H: LOUTMIX CONTROL ................................................................................................................................57
TABLE 41. MX-61H: POWER MANAGEMENT CONTROL 1...........................................................................................................58
TABLE 42. MX-62H: POWER MANAGEMENT CONTROL 2...........................................................................................................58
TABLE 43. MX-63H: POWER MANAGEMENT CONTROL 3...........................................................................................................59
TABLE 44. MX-64H: POWER MANAGEMENT CONTROL 4...........................................................................................................60
TABLE 45. MX-65H: POWER MANAGEMENT CONTROL 5...........................................................................................................60
TABLE 46. MX-66H: POWER MANAGEMENT CONTROL 6...........................................................................................................61
TABLE 47. MX-6AH: PRIVATE REGISTER INDEX........................................................................................................................62
TABLE 48. MX-6CH: PRIVATE REGISTER DATA.........................................................................................................................62
TABLE 49. MX-70H: I2S1 DIGITAL INTERFACE CONTROL..........................................................................................................62
TABLE 50. MX-73H: ADC/DAC CLOCK CONTROL 1 .................................................................................................................63
TABLE 51. MX-74H: ADC/DAC CLOCK CONTROL 2 .................................................................................................................63
TABLE 52. MX-80H: GLOBAL CLOCK CONTROL ........................................................................................................................64
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TABLE 53. MX-81H: PLL CONTROL 1........................................................................................................................................64
TABLE 54. MX-82H: PLL CONTROL 2........................................................................................................................................65
TABLE 55. MX-8EH: HP AMP CONTROL 1 .................................................................................................................................65
TABLE 56. MX-8FH: HP AMP CONTROL 2 .................................................................................................................................66
TABLE 57. MX-93H: MICBIAS CONTROL .................................................................................................................................66
TABLE 58. MX-94H: JACK DETECTION CONTROL ......................................................................................................................67
TABLE 59. MX-B0H: EQ CONTROL 1 .........................................................................................................................................67
TABLE 60. MX-B1H: EQ CONTROL 2 .........................................................................................................................................68
TABLE 61. MX-B4H: DRC/AGC CONTROL 1.............................................................................................................................69
TABLE 62. MX-B5H: DRC/AGC CONTROL 2.............................................................................................................................70
TABLE 63. MX-B6H: DRC/AGC CONTROL 3.............................................................................................................................72
TABLE 64. MX-BBH: JACK DETECTION CONTROL 1 ..................................................................................................................73
TABLE 65. MX-BCH: JACK DETECTION CONTROL 2 ..................................................................................................................73
TABLE 66. MX-BDH: IRQ CONTROL 1.......................................................................................................................................74
TABLE 67. MX-BEH: IRQ CONTROL 2 .......................................................................................................................................75
TABLE 68. MX-BFH: GPIO AND INTERNAL STATUS ..................................................................................................................75
TABLE 69. MX-C0H: GPIO CONTROL 1 .....................................................................................................................................76
TABLE 70. MX-C1H: GPIO CONTROL 2 .....................................................................................................................................76
TABLE 71. MX-D3H: WIND FILTER CONTROL 1.........................................................................................................................77
TABLE 72. MX-D3H: WIND FILTER CONTROL 2.........................................................................................................................77
TABLE 73. MX-D9H: SOFT VOLUME & ZCD CONTROL .............................................................................................................78
TABLE 74. MX-FAH: GENERAL CONTROL 1...............................................................................................................................79
TABLE 75. PR-3DH: ADC/DAC RESET CONTROL....................................................................................................................79
TABLE 76. PR-A0H: EQ LOW PASS FILTER COEFFICIENT (LPF:A1)...........................................................................................80
TABLE 77. PR-A1H: EQ LOW PASS FILTER GAIN (LPF:H0).......................................................................................................80
TABLE 78. PR-A2H: EQ BAND 1 COEFFICIENT (BPF1:A1).........................................................................................................80
TABLE 79. PR-A3H: EQ BAND 1 COEFFICIENT (BPF1:A2).........................................................................................................80
TABLE 80. PR-A4H: EQ BAND 1 GAIN (BPF1:H0).....................................................................................................................81
TABLE 81 PR-A5H: EQ BAND 2 COEFFICIENT (BPF2:A1)..........................................................................................................81
TABLE 82. PR-A6H: EQ BAND 2 COEFFICIENT (BPF2:A2).........................................................................................................81
TABLE 83. PR-A7H: EQ BAND 2 GAIN (BPF2:H0).....................................................................................................................81
TABLE 84. PR-A8H: EQ BAND 3 COEFFICIENT (BPF3:A1).........................................................................................................82
TABLE 85. PR-A9H: EQ BAND 3 COEFFICIENT (BPF3:A2).........................................................................................................82
TABLE 86. PR-AAH: EQ BAND 3 GAIN (BPF3:H0)....................................................................................................................82
TABLE 87. PR-ABH: EQ BAND 4 COEFFICIENT (BPF4:A1) ........................................................................................................82
TABLE 88. PR-ACH: EQ BAND 4 COEFFICIENT (BPF4:A2) ........................................................................................................83
TABLE 89. PR-ADH: EQ BAND 4 GAIN (BPF4:H0)....................................................................................................................83
TABLE 90. PR-AEH: EQ HIGH PASS FILTER 1 COEFFICIENT (HPF1:A1) ....................................................................................83
TABLE 91. PR-AFH: EQ HIGH PASS FILTER 1 GAIN (HPF1:H0) ................................................................................................83
TABLE 92. PR-B0H: EQ HIGH PASS FILTER 2 COEFFICIENT (HPF2:A1).....................................................................................84
TABLE 93. PR-B1H: EQ HIGH PASS FILTER 2 COEFFICIENT (HPF2:A2).....................................................................................84
TABLE 94. PR-B2H: EQ HIGH PASS FILTER 2 GAIN (HPF2:H0).................................................................................................84
TABLE 95. PR-B3H: EQ PRE VOLUME CONTROL .......................................................................................................................84
TABLE 96. PR-B4H: EQ POST VOLUME CONTROL .....................................................................................................................85
TABLE 97. MX-FEH: VENDOR ID...............................................................................................................................................85
TABLE 98. ABSOLUTE MAXIMUM RATINGS................................................................................................................................86
TABLE 99. RECOMMENDED OPERATING CONDITIONS ................................................................................................................86
TABLE 110. STATIC CHARACTERISTICS ......................................................................................................................................86
TABLE 111. ANALOG PERFORMANCE CHARACTERISTICS ...........................................................................................................87
TABLE 112. I2C TIMING..............................................................................................................................................................89
TABLE 113 TIMING OF I2S/PCM MASTER MODE........................................................................................................................90
TABLE 114. I2S/PCM SLAVE MODE TIMING...............................................................................................................................91
TABLE 115. ORDERING INFORMATION........................................................................................................................................95
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Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................3
FIGURE 2. AUDIO MIXER PATH ...................................................................................................................................................4
FIGURE 3. DIGITAL MIXER PATH ................................................................................................................................................5
FIGURE 4. PIN ASSIGNMENTS ......................................................................................................................................................6
FIGURE 5. AUDIO CLOCK TREE .................................................................................................................................................13
FIGURE 6. PCM MONO DATA MODE A FORMAT (BCLK POLARITY=0)..............................................................................16
FIGURE 7. PCM MONO DATA MODE A FORMAT (BCLK POLARITY=1)..............................................................................16
FIGURE 8. PCM MONO DATA MODE B FORMAT (BCLK POLARITY=0) ..............................................................................17
FIGURE 9. PCM STEREO DATA MODE A FORMAT (BCLK POLARITY=0)..............................................................................17
FIGURE 10. PCM STEREO DATA MODE B FORMAT (BCLK POLARITY=0)..............................................................................17
FIGURE 11. I2S DATA FORMAT (BCLK POLARITY=0).............................................................................................................18
FIGURE 12. LEFT-JUSTIFIED DATA FORMAT (BCLK POLARITY=0) ........................................................................................18
FIGURE 13. 2-CHANNEL RECORDING PATH ................................................................................................................................19
FIGURE 14. 4-CHANNEL PLAYBACK PATH..................................................................................................................................20
FIGURE 15. DAC DRC FUNCTION BLOCK ..................................................................................................................................25
FIGURE 16. ADC AGC FUNCTION BLOCK..................................................................................................................................25
FIGURE 17. DRC/AGC FOR PLAYBACK/RECORDING MODE.......................................................................................................26
FIGURE 18. DRC/AGC FOR NOISE GATE MODE.........................................................................................................................27
FIGURE 19. DATA TRANSFER OVER I2C CONTROL INTERFACE ...................................................................................................31
FIGURE 20. GPIO FUNCTION BLOCK ..........................................................................................................................................33
FIGURE 21. IRQ FUNCTION BLOCK.............................................................................................................................................33
FIGURE 22. JD SOURCE SELECTION ............................................................................................................................................34
FIGURE 23. POWER MANAGEMENT.............................................................................................................................................36
FIGURE 24. I2C CONTROL INTERFACE.........................................................................................................................................89
FIGURE 25. TIMING OF I2S/PCM MASTER MODE........................................................................................................................90
FIGURE 26. I2S/PCM SLAVE MODE TIMING ...............................................................................................................................91
FIGURE 27. APPLICATION CIRCUIT .............................................................................................................................................93
FIGURE 28. PACKAGE DIMENSION ..............................................................................................................................................94
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Datasheet
1. General Description
The ALC5616 is a high performance, low power, stereo channel I2S interface audio CODEC. The
transmitted data can from analog input or digital microphone input. Also the received data can to
headphone output, line output.
The ALC5616 features an ultra low power cap-free headphone amplifier. It consumes only less than
6.5mW power during playback, providing mobile system longer battery life under headphone listening
mode.
The integrated DRC(Dynamic Range Controller) and 7-band parametric Equalizer provide further digital
sound processing capability of audio playback paths. The DRC in ALC5616 continuously monitors the
DAC output level. When the power level is low, it increases the input signal gain to make it sound louder.
At the same time, if a peaking signal is detected, it autonomously reduces the applied gain to avoid hard
clipping. It ensures the maximum/consistent signal amplitude without producing audio clipping and
speaker damage. The 7-band parametric Equalizer contains 7 independent filters with programmable gain,
center frequency and bandwidth to tailor the frequency characteristics of embedded speaker system
according to user preferences.
For microphone recording, the DRC in ALC5616 can be used as AGC(Auto Gain Controller) to maintain
a constant recording volume. Besides, a dynamic wind reduction filter is built in on recording path. The
filter can detect the level of wind noise and on/off dynamically to keep the recording quality.
ALC5616 only requires two voltage supplies and consume ultra low power, making it ideal for mobile
devices.
Two-Channel Audio Hub/CODEC and SounzRealTM
Digital Sound Effect for Mobile Devices
1
Rev. 0.1
ALC5616
Datasheet
2. Features
Analog Features:
Digital-to-Analog Converter with 98dBA SNR
Analog-to-Digital Converter with 94dBA SNR
Differential analog microphone inputs with boost pre-amplifiers and low noise microphone bias
+20/+24/+30/+35/+40/+44/+50/+52 dB microphone boost gain
MIC input to ADC with 50dB boost gain, SNR > 66dBA and THD+N < -65dB
Adjustable MICBIAS (0.9*MICVDD or 0.75*MICVDD)
Stereo line inputs
Line input to ADC with 0dB gain, SNR >= 94dBA, THD+N <= -83dB
Stereo line outputs
DAC to line output with 0dB gain, SNR >= 98dBA, THD+N <= -86dB
Stereo Cap-Free headphone amplifier with ultra low power consumption for playback
20mW/CH (AVDD=CPVDD=1.8V, THD+N <= -80dB, 16Ohm Load)
Playback power consumption <= 6.5mW (AVDD=VBVDD=CPVDD=1.8V, 16Ohm, With I2S
Clock, Playback Silence)
Playback power consumption <= 14mW (AVDD=VBVDD=CPVDD=1.8V, 16Ohm, With I2S
Clock, Playback 1mW/CH)
Audio jack detection
Inside PLL can receiver wide range clock input
Digital Features:
One 24bit/8kHz ~ 192kHz I2S/PCM interface for stereo DAC and stereo ADC
I2C control interface
7-bands flexible equalizer (EQ) for DAC path or ADC path
Enhanced DRC(Dynamic Range Control)/AGC(Auto Gain Control) function for DAC path or ADC
path
One wind noise reduction filter
Zero detection and soft volume for pop noise suppression
3. System Application
Smart Phones
Tablet
I2S Audio CODEC for Mobile Devices
2
Rev. 0.1
ALC5616
Datasheet
4. Function Block and Mixer Path
4.1. Function Block
CPP
CPN
CPP2
CPN2
Digtial I/O
Analog Core
Charge Pump
Headphone
block
MICBIAS
0.9 * MICVDD
0.75 * MICVDD
DCVDD
Digital Core
CPVEE
CPVPP
LDO
CPGND
DGND
AGND
Charge Pump
HPOL
HPOR
AIN
IN1P
BST1
ADC_L
INL_Vol
Output
Mixer
&
REC
Mixer
DACL1
Audio Signal
Processing
INR_Vol
ADC
Volume
DAC
Volume
LOUTL/P
LOUTR/N
Volume
ADC_R
High Pass
Filter
High Pass
Filter
IN2P/INL1
IN2N/INR1
DACR1
BST2
Analog JD
MICBIAS
JD1/2
LDO
MICBIAS
AVDD
Reference
Voltage
Digital Audio Interface
VREF
I2C
Control
PLL
Figure 1. Block Diagram
I2S Audio CODEC for Mobile Devices
3
Rev. 0.1
ALC5616
Datasheet
4.2. Audio Mixer Path
HPOVOLL
Gain
RECMIXL
mu_hpvol_hpo, MX45[13]
HPOL
En_bst_hp
MX45[12]
-18 ~ 0dB, 3dB/step
Gain
-18 ~ 0dB, 3dB/step
Gain
0/20/24/30/35/40/44/50/52
mu_hpo_l
MX02[15]
BST2
HPOVOLL
OUTVOLL
DACL1
IN1P
Gain
BST2
BST1
HPOVOLL
vol_hpol
MX02[13:8]
mu_bst2_outmixl, MX4F[6]
BST1
mu_hpovoll_in
MX02[14]
Gain_bst2_outmixl, MX4D[12:10]
mu_dac1_hpo, MX45[14]
-6 ~ 0dB, 6dB/step
mu_bst2_recmixl
BST1
HPOLMIX
Gain_bst2_recmixl, MX3B[3:1]
MX3C[2]
Gain
(-46.5 ~ +12dB, 1.5dB/step)
mu_bst1_outmixl, MX4F[5]
INL1
Gain_bst1_outmixl, MX4D[9:7]
Gain
ADC_L
Sel_bst1
Gain
VMID
MX0D[15:12]
mu_bst1_recmixl
MX3C[1]
Gain_bst1_recmixl, MX3C[15:13]
BST1
mu_inl1_outmixl, MX4F[4]
RECMIXL
DACL1
Gain_inl1_outmixl, MX4D[6:4]
Gain
Gain_recmixl_outmixl, MX4D[3:1]
DAC_L1
INL1
Gain
OUTVOLL
mu_inl1_recmixl
MX3C[5]
mu_recmixl_outmixl, MX4F[3]
DACL1
mu_outvoll_in
MX03[14]
vol_outl
MX03[13:8]
(-46.5 ~ +12dB, 1.5dB/step)
Gain_inl1_recmixl, MX3B[12:10]
RECMIXL
DACL1
Gain
Gain
0/20/24/30/35/40/44/50/52
BST2
mu_dacl1_outmixl, MX4F[0]
mu_dacl1_lout, MX53[15]
Gain_inl2_outmixl, MX4E[6:4]
LOUTL
bst_lout
IN2P
IN2N
mu_lout_l
OUTMIXL
MX53[11]
MX03[15]
LOUTL/P
En_in2_df
OUTVOLL
Gain
Gain
MX0D[6]
mu_outvoll_lout, MX53[13]
DACR1
Sel_bst2
MX0D[11:8]
mu_lout_r
MX03[7]
BST2
VMID
mu_dacr1_lout, MX53[14]
LOUTR/N
LOUTR
bst_lout
MX53[11]
-18 ~ 0dB, 3dB/step
Audio Signal
Processing
INR1
-18 ~ 0dB, 3dB/step
Gain
INR1
OUTVOLR
Gain
DACR1
DACR1
Gain
DAC_R1
mu_inr1_recmixr
MX3E[5]
OUTVOLR
HPOVOLR
Gain_inr1_recmixr, MX3D[12:10]
mu_outvolr_lout, MX53[12]
-34.5~+12dB,1.5dB/step
vol_inr1
MX0F[4:0]
OUTVOLR
mu_dacr1_outmixr, MX52[0]
RECMIXR
mu_outvolr_in
MX03[6]
Gain_dacr1_outmixr, MX51[9:7]
vol_outr
LOUTMIX
BST1
-6 ~ 0dB, 6dB/step
ADC_R
Gain
MX03[5:0]
(-46.5 ~ +12dB, 1.5dB/step)
mu_bst1_recmixr
MX3E[1]
Gain
Gain_bst1_recmixr, MX3E[15:13]
mu_recmixr_outmixr, MX52[3]
INR1
Gain_recmixr_outmixr, MX50[3:1]
BST2
Gain
INL1
-28.5~+18dB,1.5dB/step
vol_inl1
MX0F[12:8]
Gain
mu_bst2_recmixr
MX3E[2]
mu_inr1_outmixr, MX52[4]
BST1
Gain_inr1_outmixr, MX50[6:4]
Gain_bst2_recmixr, MX3D[3:1]
RECMIXR
Gain
HPOVOLR
mu_bst1_outmixr, MX52[5]
BST2
Gain_bst1_outmixr, MX50[9:7]
Gain
mu_hpovolr_in
MX02[6]
vol_hpor
MX02[5:0]
RECMIXR
HPOVOLR
Gain
mu_bst2_outmixr, MX52[6]
mu_hpvol_hpo, MX45[13]
-46.5 ~ +12dB, 1.5dB/step)
HPOR
En_bst_hp
MX45[12]
Gain
Gain_bst2_outmixr, MX50[12:10]
OUTMIXR
mu_hpo_r
MX02[7]
DACR1
mu_dac1_hpo, MX45[14]
HPORMIX
-6 ~ 0dB, 6dB/step
Figure 2.
Audio Mixer Path
Two-Channel Audio Hub/CODEC and SounzRealTM
Digital Sound Effect for Mobile Devices
4
Rev. 0.1
ALC5616
Datasheet
4.3. Digital Mixer Path
Stereo1_ADC_Mixer_R
IF1_DAC1_L
mu_stereo1_adc_mixer_1
MX29[15]
gain_dacl1_to_stereo_l, MX2A[13]
Gain
mu_stereo1_adcl1
MX27[13]
mu_stereo_dacl1_mixl
MX2A[14]
DACL1
DACR1
EQ
ALC
EQ
ALC
Wind
filter
ADC_L
VOL
Stereo_DAC_MIXL
DACL1
mu_adc1_vol_l
MX1C[15]
VOL
vol_adc1_l
MX1C[14:8]
mu_dac1_l
MX29[14]
mu_stereo_dacr1_mixl
MX2A[9]
vol_dac1_l
MX19[15:8]
Gain
Only one of DAC/ADC
path pass through RTK
Effect
Only one of DAC/ADC
path pass through RTK
Effect
gain_dacr1_to_stereo_l, MX2A[8]
mu_dac1_r
MX29[6]
IF1_DAC1_R
VOL
gain_dacr1_to_stereo_r, MX2A[5]
Gain
vol_dac1_r
MX19[7:0]
DACR1
DACL1
mu_stereo_dacr1_mixr
MX2A[6]
mu_stereo1_adcr1
MX27[6]
Wind
filter
EQ
ALC
VOL
EQ
ALC
ADC_R
mu_adc1_vol_r
MX1C[7]
Stereo_DAC_MIXR
DACR1
vol_adc1_r
MX1C[6:0]
mu_stereo1_adc_mixer_r
MX29[7]
mu_stereo_dacl1_mixr
MX2A[1]
Gain
gain_dacl1_to_stereo_r, MX2A[0]
Stereo1_ADC_Mixer_L
Stereo1_ADC_Mixer_L
Stereo1_ADC_Mixer_R
IF1_ADC1
Digital Interface
I2S Digital Interface Process
Figure 3. Digital Mixer Path
Two-Channel Audio Hub/CODEC and SounzRealTM
Digital Sound Effect for Mobile Devices
5
Rev. 0.1
ALC5616
Datasheet
5. Pin Assignments
24
23
22
21
20
19
18
17
25
16
15
14
13
12
11
10
9
MCLK
CPVPP
CPVDD
26
SCL
27
SDA
CPP1
CPN1
CPP2
CPN2
28
GPIO1/IRQ1
ALC5616
29
DBVDD
30
DCVDD
xxxxxxx
ywwvs
(Top View)
31
MICVDD
LOUTR/N
LOUTL/P
32
MICBIAS1
1
2
3
4
5
6
7
8
Figure 4. Pin Assignments
Two-Channel Audio Hub/CODEC and SounzRealTM
Digital Sound Effect for Mobile Devices
6
Rev. 0.1
ALC5616
Datasheet
6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Name
Type Pin
Description
Characteristic Definition
Schmitt trigger
First I2S interface serial data input
DACDAT1
ADCDAT1
I
22
(VIL=0.35*DBVDD, VIH=0.65*DBVDD)
VOL=0.1*DBVDD, VOH=0.9*DBVDD
Master: VOL =0.1*DBVDD, VOH =0.9*DBVDD
O
21 First I2S interface serial data output
First I2S interface serial bit clock
24
BCLK1
LRCK1
I/O
I/O
Slave: Schmitt trigger
(VIL=0.35*DBVDD, VIH=0.65*DBVDD)
Master: VOL =0.1*DBVDD, VOH =0.9*DBVDD
First I2S interface synchronous signal
23
Slave: Schmitt trigger
(VIL=0.35*DBVDD, VIH=0.65*DBVDD)
Open drain structure
SDA
SCL
I/O
I
27 I2C interface serial data
26 I2C interface clock input
Schmitt trigger
Schmitt trigger
I2S interface master clock input
25
MCLK
I
(VIL=0.35*DBVDD, VIH=0.65*DBVDD)
Output: VOL =0.1*DBVDD, VOH =0.9*DBVDD
General purpose input and output
GPIO1/IRQ
I/O
28
Interrupt output
Input: Schmitt trigger
Total: 8 Pins
6.2. Analog I/O Pins
Table 2. Analog I/O Pins
Description
Line output type
Name
Type Pin
Characteristic Definition
Analog output
LOUTR/N
O
O
I
10 Right channel single-end output
Negative channel differential output
Line output type
Analog output
LOUTL/P
IN2P
9
Left channel single-end output
Positive channel differential output
Positive differential input for microphone Analog input
2
3
Left channel line input
Negative differential input for
microphone 2
Right channel line input
Second jack detection pin
Analog input
JD threshold: VIL = 0.5V, VIH = 1.2V
IN2N/JD2
I
4
I2S Audio CODEC for Mobile Devices
7
Rev. 0.1
ALC5616
Datasheet
Name
Type Pin
Description
Single-end input for microphone 1
First jack detection pin
Characteristic Definition
Analog input
IN1P
I
2
Multi-level jack detection pin
JD threshold:
JD1
I
1
Vt1 = 1.485V
Vt2 = 1.925V
Vt3 = 2.7V
Headphone amplifier output
Right channel
Analog output
HPO_R
HPO_L
O
O
17
20
Headphone amplifier output
Left channel
Analog output
Total: 8 Pins
6.3. Filter/Reference
Table 3. Filter/Reference
Description
32 Bias voltage output for microphone
Internal reference voltage
Name
MICBIAS1
VREF
Type Pin
Characteristic Definition
O
O
-
Programmable analog DC output
4.7uF capacitor to analog ground
Headphone ground
8
CPVREF
CPN1
18 Headphone reference ground
-
13 First charge pump bucket capacitor
14 First charge pump bucket capacitor
11 Second charge pump bucket capacitor
12 Second charge pump bucket capacitor
2.2uf capacitor to CPP1
2.2uf capacitor to CPN1
2.2uf capacitor to CPP2
2.2uf capacitor to CPN2
Total: 7 Pins
CPP1
-
CPN2
-
CPP2
-
I2S Audio CODEC for Mobile Devices
8
Rev. 0.1
ALC5616
Datasheet
6.4. Power/Ground
Table 4. Power/Ground
Name
MICVDD
AVDD
Type Pin
Description
Characteristic Definition
P
P
P
P
31 Analog power for MICBIAS
3.0V ~ 3.3V (Default 3.3V is recommended)
1.71V ~ 1.9V (Default 1.8V is recommended)
1.71V ~ 1.9V (Default 1.8V is recommended)
6
5
7
Analog power
Analog power
Analog ground
DACREF
AGND
Analog power for headphone charge
pump
1.71V ~ 1.9V (Default 1.8V is recommended)
CPVDD
P
15
CPVEE
CPVPP
DCVDD
DBVDD
CPGND/
DGND
P
P
P
P
19 Charge pump negative voltage output
16 Charge pump positive voltage output
30 Digital power for digital core.
2.2uf capacitor to analog ground
2.2uf capacitor to analog ground
Internal LDO generated
29 Digital power for digital I/O buffer
1.71V~3.3V (Default 1.8V is recommended)
Exposed-Pad
Charge pump ground
33*
P
Digital ground
Total: 9 Pins
I2S Audio CODEC for Mobile Devices
9
Rev. 0.1
ALC5616
Datasheet
7. Function Description
7.1. Power
There are different power types in ALC5616. DBVDD is for digital I/O power, DCVDD is for digital
core power, AVDD and DACREF are for analog power, CPVDD is for charge pump power, MICVDD is
for MICBIAS power.
The power supplier limit condition are MICVDD > AVDD = DACREF = CPVDD, and for the best
performance, our design setting is show on below.
Table 5. Power Supply for Best Performance
Power
DBVDD
DCVDD
AVDD
DACREF
CPVDD
MICVDD
Setting
1.8V
1.2V
1.8V
1.8V
1.8V
3.3V
*1.2V DCVDD was generated by internal LDO.
To prevent all power down leakage, needs keep all power supply on.
Table 6. Power Supply Condition for Power Down Leakage
Power
DBVDD
AVDD
DACREF
CPVDD
MICVDD
Setting
Supplied
Supplied
Supplied
Supplied
Supplied
I2S Audio CODEC for Mobile Devices
10
Rev. 0.1
ALC5616
Datasheet
7.2. Power Supply On/Off Sequence
To prevent pop noise and make sure function work normally, following power on and off sequence are
recommended.
Power On Sequence: (Sequentially turn on power pins)
1. DBVDD/AVDD/DACREF/CPVDD power supply on.
2. MICVDD power supply on.
3. Software starts to initialize ALC5616.
Power Off Sequence: (Sequentially turn off power pins)
1. Power down all Codec function (Write 0x0000’h to register MX-00’h).
2. MICVDD power supply off.
3. DBVDD/AVDD/DACREF/CPVDD power supply off
I2S Audio CODEC for Mobile Devices
11
Rev. 0.1
ALC5616
Datasheet
7.3. Reset
There are 2 types of reset operation: power on reset (POR) and register reset.
Table 7. Reset Operation
Reset Type
Trigger Condition
CODEC Response
POR
Monitor digital power supply voltage reach Reset all hardware logic and all registers to default
VPOR
values.
Register Reset
Write MX-00h
Reset all registers to default values except some specify
control registers and logic.
7.3.1. Power-On Reset (POR)
When powered on, DCVDD passes through the VPOR band of the ALC5616 (VPOR_ON ~VPOR_OFF). A
power on reset (POR) will generate an internal reset signal (POR reset ‘LOW’) to reset the whole chip.
Table 8. Power-On Reset Voltage
Symbol
VPOR_ON
VPOR_OFF
Min
Typical
0.8
Max
Unit
V
-
-
-
-
0.52
V
Note:
1.VPOR_OFF must be below VPOR_ON
2. ToC = 25oC
3. When DCVDD is supplied 1.2V
7.3.2. Software Reset
When MX-00h is wrote, all registers become to default value.
I2S Audio CODEC for Mobile Devices
12
Rev. 0.1
ALC5616
Datasheet
7.4. Clocking
The system clock of ALC5616 can be selected from MCLK or PLL. MCLK is always provided externally
while the reference clock of PLL can be selected from MCLK, BCLK1. The driver should arrange the
clock of each block and setup each divider.
The Clk_sys_i2s1=256*Fs provides clocks into stereo1 DAC/ADC filter that can be selected from MCLK
or PLL. Refer to Figure 5. Audio SYSCLK
When ALC5616 at master mode, the clock source from MCLK will be divided and be sent to external
device. The ratio of BCLK and LRCK can set by register – MX73.
MX80[15:14]
MCLK
MX73[14:12]
Stereo1
DAC/ADC
Clk_sys_i2s1(256FS)
MX80[3]
DIV_F1
MX80[13:12]
÷2
MCLK
Inter. Clock
(Slave)
PLL
PLL
MX81 & MX82
MX70[15]
BCLK1(Master)
LRCK1(Master)
BCLK1
LRCK1
Master Mode
LRCK/BCLK
Clk_sys_i2s1 (256FS)
Ratio
(64FS)
MX70[15]
LRCK1(Slave)
Figure 5.
Audio Clock Tree
I2S Audio CODEC for Mobile Devices
13
Rev. 0.1
ALC5616
Datasheet
7.4.1. Phase-Locked Loop
A Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz to 40MHz. The
source of the PLL can be set to MCLK, BCLK1 by setting register.
The S/W driver can set up the PLL to output a frequency to match the requirement of system clock.
The PLL transmit formula as below:
FOUT = (MCLK * (N+2)) / ((M+2) * (K+2)) {Typical K=2}
Table 9. Clock Setting Table for 48K (Unit: MHz)
MCLK
13
N
M
7
FVCO
98.222
98.304
98.304
98.304
98.4
K
2
2
2
2
2
2
2
2
2
2
FOUT
24.555
24.576
24.576
24.576
24.6
66
78
94
70
80
81
78
80
78
39
3.6864
2.048
4.096
12
1
0
1
8
15.36
16
11
11
14
14
8
98.068
98.462
98.4
24.517
24.615
24.6
19.2
19.68
24
98.4
24.6
98.4
24.6
Table 10. Clock Setting Table for 44.1K (Unit: MHz)
MCLK
13
N
M
8
FVCO
91
K
2
2
2
2
2
2
2
2
2
2
FOUT
68
72
86
64
66
63
66
64
67
62
22.75
3.6864
2.048
4.096
12
1
90.931
90.112
90.112
90.667
90.764
90.667
90.514
90.528
90.352
22.733
22.528
22.528
22.667
22.691
22.667
22.629
22.632
22.588
0
1
7
15.36
16
9
10
12
13
15
19.2
19.68
24
I2S Audio CODEC for Mobile Devices
14
Rev. 0.1
ALC5616
Datasheet
7.4.2. I2C and I2S/PCM Interface
The ALC5616 supports I2C for the digital control interface, and has one I2S/PCM for digital data
interface. The I2S/PCM audio digital interface was used to send data to stereo DACs or receive data from
a stereo ADC. The I2S/PCM audio digital interface was also can be configured to Master mode or Slave
mode.
Master Mode
Under master mode, BCLK and LRCK are configured as output. If I2S SYSCLK is selected from MCLK
source, sel_sysclk1 (MX-80[15:14]) should set as 00’b. If selected from PLL output, sel_sysclk1 should
set as 01’b. PLL’s source is suggested to provide frequency from 2.048MHz to 40MHz. The driver
should set each divider (MX-73 and MX-89) to arrange the clock distribution. Refer to Figure5. Audio
Clock Tree, for details.
Table 11. The relative of SYSCLK/BCLK/LRCK
Register Settings
MX-73[15]=0’b
MX-73[15]=1’b
MX-73[15]=0’b
MX-73[15]=1’b
MCLK
BCLK
LRCK
256*FS=12.288MHz
256*FS=12.288MHz
256*FS=11.2896MHz
256*FS=11.2896MHz
32*FS=1.536MHz
64*FS=3.072MHz
32*FS=1.4112MHz
64*FS=2.8224MHz
FS=48KHz
FS=48KHz
FS=44.1KHz
FS=44.1KHz
Example for master mode:
Target format:
Sample Rate: 48 KHz
Channel Length: 32 bits
LRCK=48KHz
BCLK=3.071MHz (64 * 48KHz)
MCLK clock request:
MCLK=12.288MHz (256 * 48 KHz)
Register settings:
Set MX-FA[0] to “1”
Set MX-61[15] to “1”
Set MX-70[15] to “0”
// For MCLK input clock getting control
// Enable I2S-1
// Enable Master mode
Slave Mode
Under slave mode BCLK and LRCK are configured as input. The SYSCLK can be input from MCLK or
PLL and BCLK is need to synchronous to MCLK. If the SYSCLK is selected from PLL, the internal PLL
should generate 256*FS by BCLK. And the driver should set each divider to arrange the clock
distribution. Refer to Figure5. Audio Clock Tree, for details.
I2S Audio CODEC for Mobile Devices
15
Rev. 0.1
ALC5616
Datasheet
7.5. Digital Data Interface
7.5.1. Two I2S/PCM Interface
The two I2S/PCM interface can be configured as master mode or slave mode. Four audio data formats are
supported:
PCM mode
Left justified mode
I2S mode
1/Fs
LRCK
BLCK
DACDAT/
ADCDAT
1
2
n-1 n
LSB
MSB
Figure 6. PCM MONO Data Mode A Format (BCLK POLARITY=0)
1/Fs
LRCK
BLCK
DACDAT/
ADCDAT
1
2
n-1 n
LSB
MSB
Figure 7. PCM MONO Data Mode A Format (BCLK POLARITY=1)
I2S Audio CODEC for Mobile Devices
16
Rev. 0.1
ALC5616
Datasheet
1/Fs
LRCK
BLCK
DACDAT/
ADCDAT
1
2
n-1 n
LSB
MSB
Figure 8. PCM MONO Data Mode B Format (BCLK POLARITY=0)
1/Fs
LRCK
BLCK
DACDAT/
ADCDAT
1
2
3
n-1 n
LSB
Right-Channel
1
2
3
n-1 n
MSB
LSBMSB
Left-Channel
Figure 9. PCM Stereo Data Mode A Format (BCLK POLARITY=0)
1/Fs
LRCK
BLCK
DACDAT/
ADCDAT
1
2
3
n-1 n
LSB
1
2
3
n-1 n
MSB
LSBMSB
Left-Channel
Right-Channel
Figure 10. PCM Stereo Data Mode B Format (BCLK POLARITY=0)
I2S Audio CODEC for Mobile Devices
17
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1/Fs
Left Channel
Right Channel
LRCK
BLCK
DACDAT/
ADCDAT
1
2
n-1
n
1
2
n-1 n
LSB
MSB
LSB
MSB
Figure 11. I2S Data Format (BCLK POLARITY=0)
1/Fs
Left Channel
Right Channel
LRCK
BLCK
DACDAT/
ADCDAT
1
2
n-1
n
1
2
n-1
n
LSB
MSB
LSB
MSB
Figure 12. Left-Justified Data Format (BCLK POLARITY=0)
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7.6. Audio Data Path
The ALC5616 provides 2-channel analog DACs for playback and 2-channel analog ADCs for recording.
7.6.1. Stereo Analog ADCs Record Path
There are two analog ADCs and with 2-channel recording path. You can use two analog microphones
pass to analog ADCs or stereo line inputs to analog ADCs.
The full scale input of analog ADC with 0dB path setting is around 0.7Vrms. In order to save power, the
left and right analog ADC can be powered down separately by setting pow_adc_l (MX-61[2]) and
pow_adc_r (MX-61[1]). And the volume control of the stereo ADC is also separately controlled by
ad_gain_l (MX-1C[14:8]) and ad_gain_r (MX-1C[6:0]).
Analog ADC_L
CH1
IF1_ADC
I2S
Analog ADC_R
CH2
Figure 13. 2-Channel Recording Path
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7.6.2. Stereo Analog DACs with Playback Path
There are two analog DACs and with 2-channel playback path. The stereo analog DACs can output audio
signal to headphone output or line output.
The full scale output of analog DAC with 0dB path setting is around 1Vrms at line output port. In order to
save power, the two analog DACs can be powered down separately by setting pow_dac_l_1 (MX-61[12]),
pow_dac_r_1 (MX-61[11]). And the two digital volume controls are also separately controlled by
vol_dac1_l (MX-19[15:8]) and vol_dac1_r (MX-19[7:0]).
L
R
Analog DACL1
CH1
CH2
IF1_DAC
I2S
Analog DACR1
Figure 14. 4-Channel Playback Path
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7.6.3. Mixers
The ALC5616 has analog mixers build-in.
Output mixer - OUTMIXL/R
The stereo analog mixer can do mixing for DAC output and analog input. The mixer output is mainly
for headphone output and line output. Each input path has individual mute control to the mixer block
in MX-4D ~ MX-52. pow_outmixl and pow_outmixr can be used to power on/off OUTMIXL/R
Record mixer – RECMIXL/R
The stereo analog mixer can do mixing for analog input and OUTMIX output. The mixer output is for
ADC input. Each input path has individual mute control to the mixer block in MX-3B ~ MX-3E.
pow_recmixl and pow_recmixr can be used to power on/off RECMIXL/R.
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7.7. Analog Audio Input Port
The ALC5616 has two types analog input ports: microphone input and line input.
IN1P
The IN1P is a microphone type input port. The input port is single-ended type input. The microphone
input port has its microphone bias and microphone boost. The low noise microphone bias can improve
recording performance and enhance recording quality. Build-in short current detection scheme can be
used for switch detection. Multi-steps microphone boost gain set by sel_bst1 (MX-0D[15:12]) is easy
to use for microphone application. Pow_bst1 can be used to power down the MIC1 boost and
pow_micbias1 can be used to power down the microphone bias 1.
IN2P/N
The IN2P/N is a dual type input port: microphone input and line input. Microphone input can be
configured to differential input or single-ended input by MX-0D[6]. Multi-steps microphone boost
gain set by sel_bst2 (MX-0D[11:8]) is easy to use for microphone application. Pow_bst2 can be used
to power down the MIC2 boost. As line input, it has volume control for tuning by MX-0F[12:8] and
MX-0F[4:0].
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7.8. Analog Audio Output Port
The ALC5616 supports two type output ports:
HPO_L/R
The headphone output of ALC5616 is a stereo output with cap-free type headphone amplifier. It does
not need to connect external capacitor and can connect to earphone device directly. The headphone
output source can mix from output mixer (OUTMIX) or DAC by setting MX-45. The front stage of
headphone output has volume control and gain control. The volume range is from +12dB to -46.5dB
with 1.5dB/step by MX-02.
En_l_hp and en_r_hp (MX-63[7/6]) can be used to power on/off Headphone Amplifier, and
pow_hpo_voll and pow_hpo_volr (MX-66[11/10]) can be used to power on/off headphone volume
control. In addition, pow_pump_hp (MX-8E[3]) can be used to power on/off charge pump circuit for
Headphone Amplifier.
Line_OUT_L/R/P/N
The output type is line type output. The output is a stereo single ended output or mono differential
output. The input can be selected from OUTVOL or DAC output by setting MX-53[15:12]. The front
stage of LOUT output has gain control for attenuation. The gain control is 0dB or -6dB by
MX-53[11].
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7.9. Multi-Function Pins
There are two multi-function pins in ALC5616. For different function on pin is controlled by register.
You need to set the right register settings for multi-function pin by your application.
GPIO1/IRQ – Pin 38
The pin default is GPIO function. If want to change to IRQ output, write MX-C0[15] to 1’b that will
switch to IRQ function.
IN2N/JD2 – Pin 4
In IN2N microphone input function, need to disable JD2 jack detection function – MX-64[1] = 0’b.
In JD2 jack detection function, need to set these register settings:
1. Power on JD2 – MX-64[1] = 1’b
2. Mute IN2 to each analog mixer - (RECMIXL/RECMIXR/OUTMIXR).
3. Set MX-64[4] = 1’b
4. Enable JD2 as jack detection source – MX-BC[11:9] = 011’b
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7.10. DRC and AGC Function
The Dynamic Range Controller (DRC) dynamically adjusts the input signal and let the output signal
achieve the target level. The ALC5616 supports playback DRC for DAC path, and the DRC can also be
used as AGC(Auto Gain Controller) for ADC path. The control register is at MX-B4[15:14]. The function
block is shown as below. The signal input pass through the Pre-Gain first, then DRC volume and
Post-Gain then output. The Pre-Gain is use to enlarge the input signal. The DRC volume is use to
attenuate the signal after detected by DRC. The Post-Gain is use to fine tune the signal after pass DRC
tuning.
0 ~ 28.5dB, 1.5/step
MXB5[4:0]
-95.625 ~ 0dB
0.375/step
-11.625 ~ 12dB, 0.375/step
MXB5[13:8]
DRC
Volume
I2C Interface
Pre-Gain
Post-Gain
DAC
DRC
1. Limiter level
2. Attack / Release time
3. Zero data
Figure 15. DAC DRC Function Block
-95.625 ~ 0dB
0.375/step
0 ~ 28.5dB, 1.5/step
MXB5[4:0]
-11.625 ~ 12dB, 0.375/step
MXB5[13:8]
Analog
Pre-Boost
AGC
Volume
ADC
Pre-Gain
Post-Gain
I2S Interface
AGC
1. Limiter level
2. Attack / Release time
3. Noise gate
Figure 16. ADC AGC Function Block
Two-Channel Audio Hub/CODEC and SounzRealTM
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Playback/Recording Mode:
For DAC playback or ADC recording mode, when the input signal exceeds target threshold, the signal
will decrease “DRC/AGC Digital Volume” (0.375dB/step at every zero-crossing) until drop to target
level then keep the digital volume. When input signal is below the target threshold, the signal will step-up
“DRC/AGC Digital Volume” (0.375dB/step every zero-crossing) until return to original level. If want to
return to the target level, need to set the pre-gain to achieve.
Fine tune parameters:
Limiter Threshold: 0 ~ -46.5dB, 1.5dB/step, MX-B6[11:7]
Attack Rate: T=(4*2^n)/sample rate, n = MX-B4[12:8]
Recovery Rate: T=(4*2^n)/sample rate, n = MX-B4[4:0]
Input signal
Target Level
Volume
0dB
Attack Rate
Recovery Rate
Output signal
Figure 17. DRC/AGC for Playback/Recording Mode
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Noise Gate Mode:
The Noise Gate Function is use to reduce the noise floor for DAC path or ADC path. When input signal is
below noise gate level, the input signal will be reduced by DRC/AGC volume in order to suppress the
background noise. The reducing level can be set by register. And when input signal is above noise gate,
the input signal will be boosted to target level.
Fine tune parameters:
Noise Gate Threshold: -36 ~ -82.5dB, 1.5dB/step, MX-B6[4:0]
Noise Gate Attack Rate: T=(4*2^n)/sample rate, n = PR-06[4:0]
Noise Gate Recovery Rate: T=(4*2^n)/sample rate, n = PR-02[12:8]
Reducing Noise Level: 0 ~ 45dB, 3dB/step, MX-B6[15:12]
Input signal
Target Level
Noise Gate
Volume
0dB
Attack Rate
Recovery Rate
Attack Rate
Recovery Rate
Noise Reduction
Output signal
Target Level
Noise Gate
Figure 18. DRC/AGC for Noise Gate Mode
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7.11. Equalizer Block
The equalizer block cascades 7 bands of equalizer to tailor the frequency characteristics of embedded
speaker system according to user preferences and to emulate environment sound. The 7 bands equalizer
includes two high pass filter, four band pass filter and one low pass filter. One high pass filter cascaded in
the front end is used to drop low frequency tone, The tone has a large amplitude and may damage a mini
speaker. The high pass filter can be used to adjust Treble strength with gain control. One low pass filter
with gain control can adjust the Bass strength. Four bands of bi-quad band pass filters are used to emulate
environment sounds, e.g., ‘Pub’, ‘Live’, ‘Rock’,… etc.. The gain, center frequency and bandwidth of each
filter are all programmable.
7.12. Wind Filter with Dynamic Wind Noise Detector
7.12.1. Wind Filter
The wind filter is implemented by a high pass filter. The wind filter is mainly for ADC recording used.
The cut-off frequency of wind filter is programmable and is varied according to different sample rate. The
filter is used to remove DC offset at normal condition, and to remove wind noise at application mode.
Wind filter setting procedure:
Step1: Disable wind filter – MX-D3[15]
Step2: Select target sample rate – MX-D3[14:12] and MX-D3[10:8]
Step3: Fine tune wind filter Fc – MX-D4[13:8] and MX-D4[5:0]
Step4: Enable wind filter – MX-D3[15]
The following table is shown the Fc with sample rate selection.
For the formula of Fc calculation is also shown as:
Fc = (Fs * tan-1(a/(2-a))) / π
Where:
Sample rate = 8K/12K/16K (MX-D3[14:12] & [10:8]), a = 2-6 + n * 2-6 (n is MX-D4[13:8] & [5:0])
Sample rate = 24K/32K (MX-D3[14:12] & [10:8]), a = 2-7 + n * 2-7 (n is MX-D4[13:8] & [5:0])
Sample rate = 44.1K/48L (MX-D3[14:12] & [10:8]), a = 2-8 + n * 2-8 (n is MX-D4[13:8] & [5:0])
Sample rate = 88.2K/96L (MX-D3[14:12] & [10:8]), a = 2-9 + n * 2-9 (n is MX-D4[13:8] & [5:0])
Sample rate = 176.4K/192L (MX-D3[14:12] & [10:8]), a = 2-10 + n * 2-10 (n is MX-D4[13:8] & [5:0])
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Table 12. Sample Rate with filter coefficient for Wind Filter
L & R Channel Sample Rate Setting
MX-D4
n
8K
20.0
16K
40.1
32K
39.9
44.1K
27.4
48K
29.8
000000’b, 0
000001’b, 1
000010’b, 2
000011’b, 3
000100’b, 4
000101’b, 5
000110’b, 6
000111’b, 7
001000’b, 8
001001’b, 9
001010’b, 10
001011’b, 11
001100’b, 12
001101’b, 13
001110’b, 14
001111’b, 15
010000’b, 16
010001’b, 17
010010’b, 18
010011’b, 19
010100’b, 20
010101’b, 21
010110’b, 22
010111’b, 23
011000’b, 24
011001’b, 25
011010’b, 26
011011’b, 27
011100’b, 28
011101’b, 29
011110’b, 30
011111’b, 31
100000’b, 32
100001’b, 33
100010’b, 34
100011’b, 35
100100’b, 36
100101’b, 37
100110’b, 38
100111’b, 39
101000’b, 40
101001’b, 41
101010’b, 42
101011’b, 43
101100’b, 44
101101’b, 45
101110’b, 46
101111’b, 47
110000’b, 48
110001’b, 49
40.4
61.1
82.1
80.8
122.2
164.2
206.9
250.2
294.3
339.0
384.4
430.5
477.4
524.9
573.2
622.3
672.1
722.6
773.9
80.2
120.7
161.6
202.8
244.4
286.2
328.4
371.0
413.8
457.0
500.5
544.4
588.6
633.2
678.1
723.3
55.0
82.7
59.9
90.0
110.5
138.4
166.4
194.5
222.7
251.1
279.5
308.1
336.8
365.6
394.5
423.5
452.6
481.9
511.2
540.7
570.3
600.0
629.8
659.7
689.8
719.9
750.2
780.6
811.1
841.8
872.5
903.4
934.4
965.5
996.8
1028.1
1059.6
1091.2
1122.9
1154.8
1186.7
1218.8
1251.0
1283.4
1315.8
1348.4
1381.1
1414.0
1447.0
1480.0
1513.3
120.3
150.6
181.1
211.7
242.5
273.3
304.3
335.4
366.6
397.9
429.4
460.9
492.6
524.5
556.4
588.5
620.7
653.0
685.5
718.1
750.8
783.6
816.6
849.6
882.9
916.2
949.7
983.3
1017.0
1050.9
1084.9
1119.0
1153.3
1187.7
1222.2
1256.9
1291.7
1326.6
1361.7
1396.9
1432.2
1467.7
1503.3
1539.0
1574.9
1610.9
1647.1
103.4
125.1
147.1
169.5
192.2
215.2
238.7
262.4
286.6
311.1
336.0
361.3
386.9
413.0
439.4
466.2
493.5
521.1
549.1
577.5
606.3
635.5
665.1
695.2
725.6
756.4
787.6
819.3
851.3
883.7
916.6
949.8
983.3
1017.3
1051.6
1086.3
1121.4
1156.8
1192.6
1228.7
1265.1
1301.8
1338.8
1376.1
1413.7
1451.5
826.0
878.9
932.5
987.0
768.9
814.9
861.2
907.8
1042.2
1098.2
1155.0
1212.7
1271.1
1330.3
1390.4
1451.2
1512.9
1575.3
1638.6
1702.7
1767.5
1822.3
1899.6
1966.7
2034.7
2103.3
2172.7
2242.9
2313.7
2385.2
2457.4
2530.2
2603.6
2677.7
2752.3
2827.5
2903.1
954.9
1002.2
1050.0
1098.1
1146.6
1195.5
1244.7
1294.3
1344.3
1394.7
1445.4
1496.5
1548.0
1599.9
1652.2
1704.9
1757.9
1811.4
1865.2
1919.5
1974.1
2029.1
2084.6
2140.4
2196.6
2253.3
2310.3
2367.7
2425.5
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L & R Channel Sample Rate Setting
MX-D4
n
8K
16K
32K
44.1K
48K
110010’b, 50
110011’b, 51
110100’b, 52
110101’b, 53
110110’b, 54
110111’b, 55
111000’b, 56
111001’b, 57
111010’b, 58
111011’b, 59
111100’b, 60
111101’b, 61
111110’b, 62
111111’b, 63
1489.6
1528.0
1566.5
1605.3
1644.2
1683.3
1722.5
1761.9
1801.4
1841.0
1880.7
1920.4
1960.2
2000.0
2979.3
3056.0
3133.1
3210.6
3288.4
3366.6
3445.1
3523.9
3602.9
3682.1
3761.4
3840.8
3920.4
4000.0
2483.8
2542.4
2601.5
2660.9
2720.8
2781.0
2841.7
2902.7
2964.2
3026.1
3088.3
3151.0
3214.1
3277.5
1546.6
1580.1
1613.7
1647.4
1681.3
1715.3
1749.4
1783.6
1818.0
1852.5
1887.1
1921.9
1956.8
1991.8
1683.4
1719.8
1756.4
1793.1
1830.0
1867.0
1904.1
1941.4
1978.8
2016.3
2054.0
2091.9
2129.9
2168.0
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7.13. I2C Control Interface
I2C is a 2-wire (SCL/SDA) half-duplex serial communication interface, supporting only slave mode. SCL
is used for clock and SDA is for data. SCL clock supports up to 400KHz rate and SDA data is a open
drain structure.
7.13.1. Address Setting
Table 13. Address Setting (0x36h)
(MSB)
BIT
(LSB)
0
0
1
1
0
1
0
R/W
7.13.2. Complete Data Transfer
Data Transfer over I2C Control Interface
Figure 19. Data Transfer Over I2C Control Interface
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Write WORD Protocol
Table 14. Write WORD Protocol
1
7
1
1
8
1
8
1
8
1
1
S
Device Address Wr A
Register Address
A
Data Byte High
A
Data Byte Low
A
P
Read WORD Protocol
Table 15. Read WORD Protocol
1
7
1
1
8
1
7
1
8
1
8
1
1
S
Device Address Wr
A
Register Address
A
S
Device Address Rd
A
Data Byte High
A
Data Byte Low
NA
P
Start Condition
0 for ACK, 1 for NACK
16-bit Mixer data
Master-to-Slave
S:
Slave Address:
Wr:
A:
7-bit Device Address
0 for Write Command
1 for Read Command
8-bit Register Address
Data Byte:
:
:
Slave-to-Master
Rd:
Command Code:
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7.14. GPIO, Interrupt and Jack Detection
The ALC5616 supports one GPIO – GPIO1 and two jack detection pins.
For GPIO function, the GPIO can be configured to input or output. For input type, the internal circuit can
read pin status and report to register table. For output type, the internal circuit can drive this pin to high or
low to control external device. In GPIO function, the pin polarity can be controlled by register at output
type.
MX-C2[3]
MX-C2[4]
GPIO1
High
EN_OBUF
Low
MX-BF[11]
EN_IBUF
MX-C2[5]
Figure 20. GPIO Function Block
For IRQ function is shown at Figure 22, the IRQ output source can be selected from gpio_jd Status, jd1_1
Status, jd1_2 Status, jd2 Status and MICBIAS1 Over-Current Status. When either status is trigged, the
GPIO will output a flag as interrupt signal to external device.
MX-BD[11]
MX-BD[13]
sta_gpio_jd(MX-BF[4])
sta_jd1_1(MX-BF[12])
Sticky Control
MX-BD[7]
MX-BD[4]
MX-BE[7]
MX-BD[8]
MX-BD[3]
MX-BE[15]
MX-BD[6]
MX-BD[9]
MX-FB[15]
Sticky Control
MX-BD[5]
IRQ
sta_jd1_2(MX-BF[13])
Sticky Control
MX-BE[11]
sta_micbias1_ovcd(MX-BE[3])
Sticky Control
MX-BD[1]
MX-BD[2]
sta_jd2(MX-BF[14])
Sticky Control
Figure 21. IRQ Function Block
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In general, the IRQ output needs to combine with JD function. When JD is trigger, IRQ will output a flag
to host to notice S/W driver. The S/W driver will do something by system design. The behavior flow
chard as following:
Initial Settings
(For JD and IRQ)
Device Plug-In
JD Triggered
IRQ Flag Output to Host
S/W Driver Settings
Clear JD Status for Next
JD Trigger
The MICBIAS supports short detection function. When MICBIAS circuit is short, MICBIAS circuit will
generate an over-current flag. The flag can generate an interrupt signal to notice host and let S/W do
follow-up processes.
For jack detection pins are shown at Figure 23. There is GPIO1 pins can be selected and control by
MX-BB[15:13]. When has GPIO been triggered, the status sta_jd_internal – MX-BF[4] will change. JD1
pin can used to detect two jacks and has two statuses for each jack. JD2 pin only used to detection one
jack.
MX-BF[4]
sta_gpio_jd
GPIO1
MX-BB[15:13]
MX-BF[12]
sta_jd1_1
JD1
MX-BF[13]
sta_jd1_2
MX-BF[14]
sta_jd2
JD2
Figure 22. JD Source Selection
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The jack detect function can be used to turn-on or turn-off the related output ports. When jack detect pin
is trigged, the selected output ports will turn-on or turn-off. For example on HP and LOUT auto switch
when JD is trigger.
Setting procedure:
1. Select JD source: use sta_jd1_1 as JD status. MX-BC[11:9] = 001’b
2. Set target behavior by JD active – HP & LOUT auto switch when JD is triggered.
MX-BB[11:10] = 11’b & MX-BB[3:2] = 10’b
3. When JD status is low, HP_OUT is mute and LOUT is un-mute.
When JD status is low go high, HP is un-mute and LOUT is mute.
Note: For HP and SPK jack switch function, driver need to turn-on DAC to HP path and DAC to LOUT
path first. The register control of MX-BB is only do mute/un-mute function for HP and SPK.
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7.15. Power Management
ALC5616 detailed Power Management control registers are supported in MX-61h, 62h, 63h, 64h, 65h and
66h. Each particular block will only be active when each bit of each register is set to enable.
MX-61
I2S-1 Power
DACL1 Power
DACR1 Power
MX-62
ADCL Power
ADCR Power
AD Digital
Filter Power
DA Digital
Filter Power
MX-63
MX-64
MX-65
Analog MBias
Analog Vref
Power
LOUT Mixer
Power
Headphone
Amp Power
Power
MIC BST1
Power
MIC BST2
Power
MICBIAS1
Power
PLL
Power
JD1
Power
JD2
Power
OUTMIXR
Power
OUTMIXL
Power
RECMIXR
Power
RECMIXL
Power
MX-66
OUTVOLL
Power
OUTVOLR
Power
HPOVOLR
Power
HPOVOLL
Power
INRVOL
Power
INLVOL
Power
Figure 23. Power Management
I2S Audio CODEC for Mobile Devices
36
Rev. 0.1
ALC5616
Datasheet
8. Registers List
ALC5616 register map as shown as following and accessing unimplemented registers will return a 0.
8.1. Register Map
Table 16. Register Map
Type
Name
Description
Register Address Reset State
Reset
S/W Reset
HPOUT
S/W Reset & Device ID
Headphone Output Volume & Mute/Un-Mute
Line Output Control 1
Line Output Control 2
IN1/2 Mode and Gain Boost Control
INL/INR Volume Control
DACL1/R1 Digital Volume Control
ADCL/R Digital Volume & Mute/Un-Mute Control
ADC Boost Gain
ADC Stereo1 Digital Mixer Control
ADC to DAC Digital Mixer Control
DAC Stereo Digital Mixer Control
MX-00h
MX-02h
MX-03h
MX-05h
MX-0Dh
MX-0Fh
MX-19h
MX-1Ch
MX-1Eh
MX-27h
MX-29h
MX-2Ah
MX-3Bh
MX-3Ch
MX-3Dh
MX-3Eh
MX-45h
MX-4Dh
MX-4Eh
MX-4Fh
MX-50h
MX-51h
MX-52h
MX-53h
0x0000’h
0xC8C8’h
0xC8C8’h
0x0000’h
0x0000’h
0x0808’h
0xAFAF’h
0x2F2F’h
0x0000’h
0x7860’h
0x8080’h
0x5252’h
0x0000’h
0x006F’h
0x0000’h
0x006F’h
0x6000’h
0x0000’h
0x0000’h
0x0279’h
0x0000’h
0x0000’h
0x0279’h
0xF000’h
Line Output
MIC Input
Line Input
DACL1/R1
ADCL/R-1
ADCL/R-2
ADC-1
Digital
Gain/Volume
Digital Mixer ADC-2
DAC-1
RECMIXL-1 RECMIXL Gain Control
RECMIXL-2 RECMIXL Gain & Selection Control
RECMIXR-1 RECMIXR Gain Control
RECMIXR-2 RECMIXR Gain & Selection Control
HPOMIX
OUTMIXL-1 OUTMIXL Control 1
OUTMIXL-2 OUTMIXL Control 2
OUTMIXL-3 OUTMIXL Control 3
OUTMIXR-1 OUTMIXR Control 1
OUTMIXR-2 OUTMIXR Control 2
OUTMIXR-3 OUTMIXR Control 3
Input Mixer
HPOMIX Gain & Selection Control
Output Mixer
LOUTMIX
LOUTMIX Control
Management-
1
Management-
2
I2S & DAC & ADC & Power Control
MX-61h
MX-62h
MX-63h
MX-64h
MX-65h
MX-66h
0x0000’h
0x0000’h
0x00C0’h
0x0000’h
0x0000’h
0x0000’h
Digital Filter Power Control
Management- VREF & MBias & LOUTMIX & HP & LDO Power
3
Management-
4
Management-
5
Management-
6
Control
Power
Management
MICBST & MICBIAS & JD Power Control
OUTMIX & RECMIX Power Control
OUTVOL & HPOVOL & INVOL Power Control
PR Index
PR Data
PR Register Index
PR Register Data
MX-6Ah
Mx-6Ch
MX-70h
0x0000’h
0x0000’h
0x8000’h
PR Register
I2S1 Port Ctrl I2S-1 Interface Control
Digital
Interface
ADC/DAC
ADC/DAC Clock Control-1
Clock-1
MX-73h
0x1104’h
Two-Channel Audio Hub/CODEC and SounzRealTM
Digital Sound Effect for Mobile Devices
37
Rev. 0.1
ALC5616
Datasheet
Type
Name
Description
Register Address Reset State
ADC/DAC
Clock-2
ADC/DAC Clock Control-2
MX-74h
0x0C00’h
Global Clock Global Clock Control
MX-80h
MX-81h
MX-82h
MX-8Eh
MX-8Fh
MX-93h
MX-94h
MX-B0h
MX-B1h
PR-A0h
PR-A1h
PR-A2h
PR-A3h
PR-A4h
PR-A5h
PR-A6h
PR-A7h
PR-A8h
PR-A9h
PR-AAh
PR-ABh
PR-ACh
PR-ADh
PR-AEh
PR-AFh
PR-B0h
PR-B1h
PR-B2h
MX-B4h
MX-B5h
MX-B6h
MX-BBh
MX-BCh
MX-BDh
MX-BEh
MX-BFh
MX-C0h
MX-C1h
MX-D3h
MX-D4h
MX-D9h
MX-FAh
PR-3Dh
MX-FEh
0x0000’h
0x0000’h
0x0000’h
0x0004’h
0x1100’h
0x2000’h
0x0200’h
0x2080’h
0x0000’h
0x1C10’h
0x01F4’h
0xC5E9’h
0x1A98’h
0x1D2C’h
0xC882’h
0x1C10’h
0x01F4’h
0xE904’h
0x1C10’h
0x01F4’h
0xE904’h
0x1C10’h
0x01F4’h
0x1C10’h
0x01F4’h
0x2000’h
0x0000’h
0x2000’h
0x2206’h
0x1F00’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0100’h
0x0000’h
0xB320’h
0x0000’h
0x0809’h
0x0010’h
0x2800’h
0x10EC’h
Global Clock PLL-1
PLL-2
PLL Control-1
PLL Control-2
HP Amp Control 1
HP Amp Control 2
MICBIAS Control
Jack Detection Control
EQ Control-1
HP Amp
HP
MICBIAS
JD
MICBIAS
JD
EQ-1
EQ-2
EQ Control-2
EQ-Parameter EQ Low Pass Filter – a1
EQ-Parameter EQ Low Pass Filter – H0
EQ-Parameter EQ Band Pass Filter 1 – a1
EQ-Parameter EQ Band Pass Filter 1 – a2
EQ-Parameter EQ Band Pass Filter 1 – H0
EQ-Parameter EQ Band Pass Filter 2 – a1
EQ-Parameter EQ Band Pass Filter 2 – a2
EQ-Parameter EQ Band Pass Filter 2 – H0
EQ-Parameter EQ Band Pass Filter 3 – a1
EQ-Parameter EQ Band Pass Filter 3 – a2
EQ-Parameter EQ Band Pass Filter 3 – H0
EQ-Parameter EQ Band Pass Filter 4 – a1
EQ-Parameter EQ Band Pass Filter 4 – a2
EQ-Parameter EQ Band Pass Filter 4 – H0
EQ-Parameter EQ High Pass Filter 1 – a1
EQ-Parameter EQ High Pass Filter 1 – H0
EQ-Parameter EQ High Pass Filter 2 – a1
EQ-Parameter EQ High Pass Filter 2 – a2
EQ-Parameter EQ High Pass Filter 2 – H0
DRC/AGC-1 DRC/AGC Control-1
EQ
DRC/AGC
DRC/AGC-2 DRC/AGC Control-2
DRC/AGC-3 DRC/AGC Control-3
JD-1
JD-2
IRQ-1
Jack Detection Control-1
Jack Detection Control-2
IRQ Control-1
Jack Detection
IRQ
IRQ-2
IRQ Control-2
Flag Status
GPIO
Status
GPIO & Internal Status
GPIO Control-1
GPIO Control-2
Wind Filter Control 1
Wind Filter Control 2
GPIO-1
GPIO-2
Control-1
Control-2
Wind Filter
SVOL & ZCD SVOL & ZCD Soft Volume and ZCD Control
General Control 1
ADC/DAC RESET Control
Vendor ID
General
Control
Vendor ID
ID
I2S Audio CODEC for Mobile Devices
38
Rev. 0.1
ALC5616
Datasheet
8.2. MX-00h: S/W Reset & Device ID
Default: 0020’h
Table 17. MX-00h: S/W Reset & Device ID
Read/Write Reset State Description
0020’h
Port Name
Bits
15:6
R
Reserved
Reserved
Note: Writes to this register will reset all registers to their default values.
8.3. MX-02h: Headphone Output Control
Default: C8C8’h
Table 18. MX-02h: Headphone Output Control
Name
Bits
Read/Write Reset State Description
mu_hpo_l
15
R/W
1’h
Mute Control for Left Headphone Output Port (HPOL)
0’b: Un-Mute
1’b: Mute
Mu_hpovoll_in
vol_hpol
Mute Control for Left Headphone Volume Channel
14
R/W
1’h
(HPOVOLL)
0’b: Un-Mute
1’b: Mute
13:8
R/W
8’h
Left Headphone Channel Volume Control (HPOVOLL)
00’h: +12dB
…
08’h: 0dB
…
27’h: -46.5dB, with 1.5dB/step
mu_hpo_r
7
6
R/W
R/W
1’h
1’h
Mute Control Right Headphone Output Port (HPOR)
0’b: Un-Mute
1’b: Mute
Mu_hpovolr_in
Mute Control for Right Headphone Volume Channel
(HPOVOLR)
0’b: Un-Mute
1’b: Mute
I2S Audio CODEC for Mobile Devices
39
Rev. 0.1
ALC5616
Datasheet
Name
Vol_hpor
Bits
5:0
Read/Write Reset State Description
R/W 8’h Right Headphone Channel Volume Control (HPOVOLR)
00’h: +12dB
…
08’h: 0dB
…
27’h: -46.5dB, with 1.5dB/step
Volume Table
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain
12
10.5
9
32
33
34
35
36
37
38
39
20
21
22
23
24
25
26
27
0
1
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
-12
-13.5
-15
-36
-37.5
-39
2
2
7.5
6
3
3
-16.5
-18
-40.5
-42
4
4
4.5
3
5
5
-19.5
-21
-43.5
-45
6
6
1.5
0
7
7
-22.5
-24
-46.5
8
8
9
9
-1.5
-3
-25.5
-27
10
11
12
13
14
15
A
B
C
D
E
F
-4.5
-6
-28.5
-30
-7.5
-9
-31.5
-33
-10.5
-34.5
I2S Audio CODEC for Mobile Devices
40
Rev. 0.1
ALC5616
Datasheet
8.4. MX-03h: LINE Output Control 1
Default: C8C8’h
Table 19. MX-03h: LINE Output Control 1
Read/Write Reset State Description
Name
Bits
Mu_lout_l
15
R/W
R/W
R/W
1’h
Mute Control for Left Line Output Port(LOUTL)
0’b: Un-Mute
1’b: Mute
Mute Control for Left Output Volume Channel (OUTVOLL)
0’b: Un-Mute
1’b: Mute
Mu_outvoll_in
Vol_outl
14
1’h
13:8
08’h
Left Output Volume Control (OUTVOLL)
00’h: +12dB
…
08’h: 0dB
…
27’h: -46.5dB, with 1.5dB/step
Mute Control for Right Line Output Port (LOUTR)
0’b: Un-Mute
Mu_lout_r
7
6
R/W
R/W
1’h
1’h
1’b: Mute
Mu_outvolr_in
Mute Control for Right Output Volume Channel
(OUTVOLR)
0’b: Un-Mute
1’b: Mute
Vol_outr
5:0
R/W
08’h
Right Output Volume Control
00’h: +12dB
…
08’h: 0dB
…
27’h: -46.5dB, with 1.5dB/step
Volume Table
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain
12
10.5
9
32
33
34
35
36
37
38
39
20
21
22
23
24
25
26
27
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
16
17
18
19
20
21
22
23
24
25
10
11
12
13
14
15
16
17
18
19
-12
-13.5
-15
-36
-37.5
-39
7.5
6
-16.5
-18
-40.5
-42
4.5
3
-19.5
-21
-43.5
-45
1.5
0
-22.5
-24
-46.5
-1.5
-25.5
I2S Audio CODEC for Mobile Devices
41
Rev. 0.1
ALC5616
Datasheet
-3
-4.5
-6
10
11
12
13
14
15
A
B
C
D
E
F
26
27
28
29
30
31
1A
1B
1C
1D
1E
1F
-27
-28.5
-30
-7.5
-9
-31.5
-33
-10.5
-34.5
8.5. MX-05h: LINE Output Control 2
Default: 0000’h
Table 20. MX-05h: LINE Output Control 2
Read/Write Reset State Description
Name
Bits
En_dfo
15
R/W
0’h
Enable Differential Line Output
0’b: Disable
1’b: Enable (LP / RN)
Reserved
reserved
14:0
R
0’h
8.6. MX-0Dh: IN1/2 Input Control
Default: 0000’h
Table 21. MX-0Dh: IN1/2 Input Control
Name
Bits
Read/Write
Reset State Description
Sel_bst1
15:12
R/W
0’h IN1 Boost Control (BST1)
0000’b: Bypass
0001’b: +20dB
0010’b: +24dB
0011’b: +30dB
0100’b: +35dB
0101’b: +40dB
0110’b: +44dB
0111’b: +50dB
1000’b: +52dB
Others : Reserved
I2S Audio CODEC for Mobile Devices
42
Rev. 0.1
ALC5616
Datasheet
Name
Bits
Read/Write
Reset State Description
Sel_bst2
11:8
R/W
0’h
IN2 Boost Control (BST2)
0000’b: Bypass
0001’b: +20dB
0010’b: +24dB
0011’b: +30dB
0100’b: +35dB
0101’b: +40dB
0110’b: +44dB
0111’b: +50dB
1000’b: +52dB
Others : Reserved
IN1 Input Mode Control
En_in1_df
En_in2_df
reserved
7
6
R/W
R/W
0’h
0’h
0’b: Single Ended Mode
1’b: Differential Mode
IN2 Input Mode Control
0’b: Single Ended Mode
1’b: Differential Mode
5:0
R/W
0’h
Reserved
8.7. MX-0Fh: INL & INR Volume Control
Default: 0808’h
Table 22. MX-0Fh: INL & INR Volume Control
Name
Bits
Read/Write
Reset State Description
reserved
15:13
R
0’h
Reserved
Vol_inl
12:8
R/W
8’h
INL Channel Volume Control
00’h: +12dB
…
08’h: 0dB
…
1F’h: -34.5dB, with 1.5dB/step
Reserved
Vol_inr
7:5
4:0
R
0’h
Reserved
R/W
8’h
INR Channel Volume Control
00’h: +12dB
…
08’h: 0dB
…
1F’h: -34.5dB, with 1.5dB/step
Volume Table:
DEC HEX Boost Gain DEC HEX Boost Gain
I2S Audio CODEC for Mobile Devices
43
Rev. 0.1
ALC5616
Datasheet
12
10.5
9
0
1
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
-12
-13.5
-15
2
2
7.5
6
3
3
-16.5
-18
4
4
4.5
3
5
5
-19.5
-21
6
6
1.5
0
7
7
-22.5
-24
8
8
9
9
-1.5
-3
-25.5
-27
10
11
12
13
14
15
A
B
C
D
E
F
-4.5
-6
-28.5
-30
-7.5
-9
-31.5
-33
-10.5
-34.5
8.8. MX-19h: DACL1/R1 Digital Volume
Default: AFAF’h
Table 23. MX-19h: DACL1/R1 Digital Volume
Name
Bits
Read/Write Reset State Description
vol_dac1_l
15:8
R/W
AF’h
DAC1 Left Channel Digital Volume
00’h: -65.625dB
…
AF’h: 0dB, with 0.375dB/Step
DAC1 Right Channel Digital Volume
00’h: -65.625dB
vol_dac1_r
7:0
R/W
AF’h
…
AF’h: 0dB, with 0.375dB/Step
Volume Table:
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain
-65.625
-65.25
106 6A
159
9F
-6
212 D4
213 D5
214 D6
0
1
2
0
1
2
53
54
55
35
36
37
-45.75
-45.375
-45
-25.875
-25.5
107
108
6B
6C
160 A0
161 A1
-5.625
-5.25
-64.875
-25.125
I2S Audio CODEC for Mobile Devices
44
Rev. 0.1
ALC5616
Datasheet
-64.5
-64.125
-63.75
-63.375
-63
109 6D
162 A2
163 A3
164 A4
165 A5
166 A6
167 A7
168 A8
169 A9
170 AA
171 AB
172 AC
173 AD
174 AE
175 AF
176 B0
177 B1
178 B2
179 B3
180 B4
181 B5
182 B6
183 B7
184 B8
185 B9
186 BA
187 BB
188 BC
189 BD
190 BE
191 BF
192 C0
193 C1
194 C2
195 C3
196 C4
197 C5
-4.875
-4.5
215 D7
3
3
4
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
-44.625
-44.25
-43.875
-43.5
-24.75
-24.375
-24
110
111
112
113
114
115
116
117
118
119
120
121
6E
6F
70
71
72
73
74
75
76
77
78
79
216 D8
217 D9
218 DA
219 DB
220 DC
221 DD
222 DE
223 DF
4
-4.125
-3.75
-3.375
-3
5
5
6
6
-23.625
-23.25
-22.875
-22.5
7
7
-43.125
-42.75
-42.375
-42
-62.625
-62.25
-61.875
-61.5
8
8
-2.625
-2.25
-1.875
-1.5
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A
-22.125
-21.75
-21.375
-21
B
-41.625
-41.25
-40.875
-40.5
-61.125
-60.75
-60.375
-60
224
E0
C
-1.125
-0.75
-0.375
0
D
225 E1
226
227
E
-20.625
-20.25
-19.875
-19.5
E2
E3
F
-40.125
-39.75
-39.375
-39
-59.625
-59.25
-58.875
-58.5
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
122 7A
123 7B
124 7C
125 7D
126 7E
127 7F
228 E4
229 E5
230 E6
231 E7
232 E8
233 E9
234 EA
235 EB
236 EC
237 ED
238 EE
239 EF
240 F0
241 F1
242 F2
243 F3
244 F4
245 F5
246 F6
247 F7
248 F8
249 F9
250 FA
-19.125
-18.75
-18.375
-18
-38.625
-38.25
-37.875
-37.5
-58.125
-57.75
-57.375
-57
128
129
130
131
132
133
134
135
136
137
80
81
82
83
84
85
86
87
88
89
-17.625
-17.25
-16.875
-16.5
-37.125
-36.75
-36.375
-36
-56.625
-56.25
-55.875
-55.5
-16.125
-15.75
-15.375
-15
-35.625
-35.25
-34.875
-34.5
-55.125
-54.75
-54.375
-54
-14.625
-14.25
-13.875
-13.5
-34.125
-33.75
-33.375
-33
-53.625
-53.25
-52.875
-52.5
138 8A
139 8B
140 8C
141 8D
142 8E
143 8F
-13.125
-12.75
-12.375
-12
-32.625
-32.25
-31.875
-31.5
-52.125
-51.75
-51.375
-11.625
144
90
I2S Audio CODEC for Mobile Devices
45
Rev. 0.1
ALC5616
Datasheet
-51
-31.125
-30.75
-30.375
-30
-11.25
-10.875
-10.5
39
40
41
42
43
44
45
46
47
48
49
50
51
52
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
92
93
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
145
146
147
148
149
150
151
152
153
91
92
93
94
95
96
97
98
99
198 C6
199 C7
200 C8
201 C9
202 CA
203 CB
204 CC
205 CD
206 CE
207 CF
208 D0
209 D1
210 D2
211 D3
251 FB
-50.625
-50.25
-49.875
-49.5
252 FC
253 FD
254 FE
255 FF
94
-10.125
-9.75
95
96
-29.625
-29.25
-28.875
-28.5
-9.375
-9
-49.125
-48.75
-48.375
-48
97
98
-8.625
-8.25
99
100
101
102
103
104
105
-28.125
-27.75
-27.375
-27
-7.875
-7.5
-47.625
-47.25
-46.875
-46.5
154 9A
155 9B
156 9C
157 9D
158 9E
-7.125
-6.75
-26.625
-26.25
-6.375
-46.125
8.9. MX-1Ch: Stereo1 ADC Digital Volume Control
Default: 2F2F’h
Table 24. MX-1Ch: Stereo1 ADC Digital Volume Control
Name
Bits
Read/Write
Reset State Description
Mu_adc_vol_l
15
R/W
0’h
Mute Control for Stereo1 ADC Left Volume Channel
0’b: Un-Mute
1’b: Mute
Vol_adc1_l
14:8
R/W
2F’h
Stereo1 ADC Left Channel Volume Control
00’h: -17.625dB
…
2F’h: 0dB
…
7F’h: +30dB, with 0.375dB/Step
Mute Control for Stereo1 ADC Right Volume Channel
0’b: Un-Mute
Mu_adc_vol_r
7
R/W
0’h
1’b: Mute
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Datasheet
Vol_adc1_r
6:0
R/W
2F’h
Stereo1 ADC Right Channel Volume Control
00’h: -17.625dB
…
2F’h: 0dB
…
7F’h: +30dB, with 0.375dB/Step
Volume Table:
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain
-17.625
-17.25
-16.875
-16.5
-7.875
1.875
2.25
2.625
3
11.625
21.375
21.75
22.125
22.5
0
1
0
1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
104
105
68
69
-7.5
12
-7.125
-6.75
-6.375
-6
12.375
12.75
13.125
13.5
2
2
106 6A
107 6B
108 6C
109 6D
110 6E
111 6F
3
3
-16.125
-15.75
-15.375
-15
3.375
3.75
4.125
4.5
22.875
23.25
23.625
24
4
4
5
5
-5.625
-5.25
-4.875
-4.5
13.875
14.25
14.625
15
6
6
7
7
-14.625
-14.25
-13.875
-13.5
4.875
5.25
5.625
6
24.375
24.75
25.125
25.5
8
8
112
113
114
115
116
117
118
119
120
121
70
71
72
73
74
75
76
77
78
79
9
9
-4.125
-3.75
-3.375
-3
15.375
15.75
16.125
16.5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A
B
-13.125
-12.75
-12.375
-12
6.375
6.75
7.125
7.5
25.875
26.25
26.625
27
C
D
E
-2.625
-2.25
-1.875
-1.5
16.875
17.25
17.625
18
F
-11.625
-11.25
-10.875
-10.5
7.875
8.25
8.625
9
27.375
27.75
28.125
28.5
10
11
12
13
14
15
16
17
18
19
-1.125
-0.75
-0.375
0
18.375
18.75
19.125
19.5
122 7A
123 7B
124 7C
125 7D
126 7E
127 7F
-10.125
-9.75
9.375
9.75
10.125
10.5
10.875
11.25
28.875
29.25
29.625
30
-9.375
-9
0.375
0.75
19.875
20.25
20.625
-8.625
-8.25
1.125
1.5
21
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Datasheet
8.10. MX-1Eh: ADC Digital Boost Gain Control
Default: 0000’h
Table 25. MX-1Eh: ADC Digital Boost Gain Control
Name
Bits
Read/Write
Reset State Description
Ad_boost_gain_l
15:14
R/W
0’h
0’h
0’h
ADC Left Channel Digital Boost Gain
00’b: 0dB
01’b: 12dB
10’b: 24dB
11’b: 36dB
Ad_boost_gain_r
13:12
R/W
R/W
ADC Right Channel Digital Boost Gain
00’b: 0dB
01’b: 12dB
10’b: 24dB
11’b: 36dB
reserved
11:0
Reserved
8.11. MX-27h: Stereo1 ADC Digital Mixer Control
Default: 7860’h
Table 26. MX-27h: Stereo1 ADC Digital Mixer Control
Name
reserved
mu_stereo1_adcl1
Bits
15
14
Read/Write
Reset State Description
R
R/W
0’h
1’h
reserved
Mute Control for Stereo1 ADC1 Left Channel
0’b: Un-Mute
1’b: Mute
reserved
mu_stereo1_adcr1
13:7
6
R
R/W
70’h
1’h
Reserved
Mute Control for Stereo1 ADC1 Right Channel
0’b: Un-Mute
1’b: Mute
reserved
reserved
4:0
R
20’h
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Datasheet
8.12. MX-29h: Stereo ADC to DAC Digital Mixer Control
Default: 8080’h
Table 27. MX-29h: Stereo ADC to DAC Digital Mixer Control
Name
Bits Read/Write Reset State Description
mu_stereo1_adc_mix 15
er_l
R/W
1’h
Mute Control for Stereo1 ADC Left Channel to DAC
0’b: Un-Mute
1’b: Mute
mu_dac1_l
14
R/W
0’h
Mute Control for I2S-1 to DAC Left Channel
0’b: Un-Mute
1’b: Mute
Reserved
mu_stereo1_adc_mix
er_r
13:8
7
R
R/W
0’h
1’h
Reserved
Mute Control for Stereo1 ADC Right Channel to DAC
0’b: Un-Mute
1’b: Mute
mu_dac1_r
reserved
6
R/W
R
0’h
0’h
Mute Control for I2S-1 to DAC Right Channel
0’b: Un-Mute
1’b: Mute
reserved
5:0
8.13. MX-2Ah: Stereo DAC Digital Mixer Control
Default: 5252’h
Table 28. MX-2Ah: Stereo DAC Digital Mixer Control
Name
Bits Read/Write Reset State Description
reserved
mu_stereo_dacl1_mix 14
l
15
R
R/W
0’h
1’h
reserved
Mute Control for DACL1 to Stereo DAC Left Mixer
0’b: Un-Mute
1’b: Mute
gain_dacl1_to_stereo 13
_l
R/W
0’h
Gain Control for DACL1 to Stereo DAC Left Mixer
0’b: 0dB
1’b: -6dB
Reserved
mu_stereo_dacr1_mi
xl
12:10
9
R
R/W
4’h
1’h
reserved
Mute Control for DACR1 to Stereo DAC Left Mixer
0’b: Un-Mute
1’b: Mute
gain_dacr1_to_stereo
_l
8
R/W
0’h
Gain Control for DACR1 to Stereo DAC Left Mixer
0’b: 0dB
1’b: -6dB
Reserved
mu_stereo_dacr1_mi
xr
7
6
R
R/W
0’h
1’h
reserved
Mute Control for DACR1 to Stereo DAC Right Mixer
0’b: Un-Mute
1’b: Mute
gain_dacr1_to_stereo
_r
5
R/W
0’h
Gain Control for DACR1 to Stereo DAC Right Mixer
0’b: 0dB
1’b: -6dB
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Name
Bits Read/Write Reset State Description
reserved
mu_stereo_dacl1_mix
r
4:2
1
R
R/W
4’h
1’h
reserved
Mute Control for DACL1 to Stereo DAC Right Mixer
0’b: Un-Mute
1’b: Mute
gain_dacl1_to_stereo
_r
0
R/W
0’h
Gain Control for DACL1 to Stereo DAC Right Mixer
0’b: 0dB
1’b: -6dB
8.14. MX-3Bh: RECMIXL Control 1
Default: 0000’h
Table 29. MX-3Bh: RECMIXL Control 1
Bits Read/Write Reset State Description
Name
reserved
Gain_inl_recmixl
15:13
12:10
R
R/W
0’h
0’h
reserved
Gain Control for INL to RECMIXL
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: Reserved
Reserved
Gain Control for BST2 to RECMIXL
000’b: 0dB
Reserved
Gain_bst2_recmixl
9:4
3:1
R
R/W
0’h
0’h
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: Reserved
reserved
reserved
0
R
0’h
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Datasheet
8.15. MX-3Ch: RECMIXL Control 2
Default: 006F’h
Table 30. MX-3Ch: RECMIXL Control 2
Bits Read/Write Reset State Description
Name
Gain_bst1_recmixl
15:13
R/W
0’h
Gain Control for BST1 to RECMIXL
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: Reserved
reserved
Mute Control for INL to RECMIXL
0’b: Un-Mute
reserved
Mu_inl_rexmixl
12:6
5
R
R/W
1’h
1’h
1’b: Mute
reserved
Mu_bst2_recmixl
4:3
2
R
R/W
1’h
1’h
reserved
Mute Control for BST2 to RECMIXL
0’b: Un-Mute
1’b: Mute
Mu_bst1_recmixl
Reserved
1
0
R/W
R
1’h
1’h
Mute Control for BST1 to RECMIXL
0’b: Un-Mute
1’b: Mute
Reserved
8.16. MX-3Dh: RECMIXR Control 1
Default: 0000’h
Table 31. MX-3Dh: RECMIXR Control 1
Bits Read/Write Reset State Description
Name
reserved
Gain_inr_recmixr
15:13
12:10
R
R/W
0’h
0’h
Reserved
Gain Control for INR to RECMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: Reserved
Reserved
reserved
9:4
R
0’h
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Datasheet
Name
Bits Read/Write Reset State Description
Gain_bst2_recmixr
3:1
R/W
0’h
Gain Control for BST2 to RECMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: Reserved
Reserved
reserved
0
R
0’h
8.17. MX-3Eh: RECMIXR Control 2
Default: 006F’h
Table 32. MX-3Eh: RECMIXR Control 2
Bits Read/Write Reset State Description
Name
Gain_bst1_recmixr
15:13
R/W
0’h
Gain Control for BST1 to RECMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: Reserved
reserved
Mute Control for INR to RECMIXR
0’b: Un-Mute
reserved
Mu_inr_rexmixr
12:6
5
R
R/W
1’h
1’h
1’b: Mute
reserved
Mu_bst2_recmixr
4:3
2
R
R/W
1’h
1’h
reserved
Mute Control for BST2 to RECMIXR
0’b: Un-Mute
1’b: Mute
Mu_bst1_recmixr
Reserved
1
0
R/W
R
1’h
1’h
Mute Control for BST1 to RECMIXR
0’b: Un-Mute
1’b: Mute
Reserved
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Datasheet
8.18. MX-45h: HPOMIX Control
Default: 6000’h
Table 33. MX-45h: HPOMIX Control
Bits Read/Write Reset State Description
Name
Reserved
mu_dac1_hpomix
15
14
R
R/W
0’h
1’h
Reserved
Mute Control for DAC1 to HPOMIX
0’b: Un-Mute
1’b: Mute
mu_hpovol_hpomix
Gain_hpomix
Reserved
13
12
R/W
R/W
R
1’h
0’h
0’h
Mute Control for HPOVOL to HPOMIX
0’b: Un-Mute
1’b: Mute
Gain Control for HPOMIX
0’b: 0dB
1’b: -6dB
11:0
Reserved
8.19. MX-4Dh: OUTMIXL Control 1
Default: 0000’h
Table 34. MX-4Dh: OUTMIXL Control 1
Bits Read/Write Reset State Description
Name
reserved
Gain_bst2_outmixl
15:13
12:10
R
R/W
0’h
0’h
Reserved
Gain Control for BST2 to OUTMIXL
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
Gain Control for BST1 to OUTMIXL
000’b: 0dB
Gain_bst1_outmixl
9:7
R/W
0’h
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
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Datasheet
Name
Bits Read/Write Reset State Description
Gain_inl_outmixl
6:4
R/W
R/W
R
0’h
0’h
0’h
Gain Control for INL to OUTMIXL
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
Gain Control for RECMIXL to OUTMIXL
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Gain_recmixl_outmix 3:1
l
Others: reserved
reserved
Reserved
0
8.20. MX-4Eh: OUTMIXL Control 2
Default: 0000’h
Table 35. MX-4Eh: OUTMIXL Control 2
Bits Read/Write Reset State Description
Name
Reserved
Gain_dacl1_outmixl
15:10
9:7
R
R/W
0’h
0’h
Reserved
Gain Control for DACL1 to OUTMIXL
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
Reserved
reserved
6:0
R
0’h
8.21. MX-4Fh: OUTMIXL Control 3
Default: 0279’h
Table 36. MX-4Fh: OUTMIXL Control 3
Bits Read/Write Reset State Description
15:7 4’h Reserved
Name
reserved
R
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Datasheet
Name
Bits Read/Write Reset State Description
Mu_bst2_outmixl
6
5
4
3
R/W
R/W
R/W
R/W
1’h
1’h
1’h
1’h
Mute Control for BST2 to OUTMIXL
0’b: Un-Mute
1’b: Mute
Mute Control for BST1 to OUTMIXL
0’b: Un-Mute
1’b: Mute
Mute Control for INL to OUTMIXL
0’b: Un-Mute
1’b: Mute
Mute Control for RECMIXL to OUTMIXL
0’b: Un-Mute
Mu_bst1_outmixl
Mu_inl_outmixl
Mu_recmixl_outmixl
1’b: Mute
reserved
Mu_dacl1_outmixl
2:1
0
R
R/W
0’h
1’h
Reserved
Mute Control for DACL1 to OUTMIXL
0’b: Un-Mute
1’b: Mute
8.22. MX-50h: OUTMIXR Control 1
Default: 0000’h
Table 37. MX-50h: OUTMIXR Control 1
Bits Read/Write Reset State Description
Name
reserved
Gain_bst2_outmixr
15:13
12:10
R
R/W
0’h
0’h
Reserved
Gain Control for BST2 to OUTMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
Gain Control for BST1 to OUTMIXR
000’b: 0dB
Gain_bst1_outmixr
9:7
R/W
0’h
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
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Datasheet
Name
Bits Read/Write Reset State Description
Gain_inr_outmixr
6:4
R/W
R/W
R
0’h
0’h
0’h
Gain Control for INR to OUTMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
Gain Control for RECMIXR to OUTMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Gain_recmixr_outmix 3:1
r
Others: reserved
Reserved
reserved
0
8.23. MX-51h: OUTMIXR Control 2
Default: 0000’h
Table 38 MX-51h: OUTMIXR Control 2
Bits Read/Write Reset State Description
Name
Reserved
Gain_dacr1_outmixr 9:7
15:10
R
R/W
0’h
0’h
Reserved
Gain Control for DACR1 to OUTMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
Reserved
reserved
6:0
R
0’h
8.24. MX-52h: OUTMIXR Control 3
Default: 0279’h
Table 39. MX-52h: OUTMIXR Control 3
Bits Read/Write Reset State Description
15:7 4’h Reserved
Name
reserved
R
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Datasheet
Name
Bits Read/Write Reset State Description
Mu_bst2_outmixr
6
5
4
3
R/W
R/W
R/W
R/W
1’h
1’h
1’h
1’h
Mute Control for BST2 to OUTMIXR
0’b: Un-Mute
1’b: Mute
Mute Control for BST1 to OUTMIXR
0’b: Un-Mute
1’b: Mute
Mute Control for INR to OUTMIXR
0’b: Un-Mute
1’b: Mute
Mute Control for RECMIXR to OUTMIXR
0’b: Un-Mute
Mu_bst1_outmixr
Mu_inr_outmixr
Mu_recmixr_outmixr
1’b: Mute
Reserved
Mu_dacr1_outmixr
2:1
0
R
R/W
0’h
1’h
Reserved
Mute Control for DACR1 to OUTMIXR
0’b: Un-Mute
1’b: Mute
8.25. MX-53h: LOUTMIX Control
Default: F000’h
Table 40 MX-53h: LOUTMIX Control
Bits Read/Write Reset State Description
Name
Mu_dacl1_lout
15
R/W
R/W
R/W
R/W
R/W
R/W
1’h
1’h
1’h
1’h
0’h
0’h
Mute Control for DACL1 to LOUTMIX
0’b: Un-Mute
1’b: Mute
Mute Control for DACR1 to LOUTMIX
0’b: Un-Mute
1’b: Mute
Mute Control for OUTVOLL to LOUTMIX
0’b: Un-Mute
1’b: Mute
Mute Control for OUTVOLR to LOUTMIX
0’b: Un-Mute
1’b: Mute
Gain Control for LOUTMIX
0’b: 0dB
1’b: -6dB
Mu_dacr1_lout
Mu_outvoll_lout
Mu_outvolr_lout
Gain_lout
14
13
12
11
reserved
10:0
Reserved
I2S Audio CODEC for Mobile Devices
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Rev. 0.1
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Datasheet
8.26. MX-61h: Power Management Control 1
Default: 0000’h
Table 41. MX-61h: Power Management Control 1
Name
Bits Read/Write Reset State Description
En_i2s1
15
R/W
0’h
I2S1 Digital Interface Power Control
0’b: Power Down
1’b: Power On
reserved
Pow_dac_l_1
14:13
12
R/W
R/W
0’h
0’h
Reserved
Analog DACL1 Power Control
0’b: Power Down
1’b: Power On
Pow_dac_r_1
11
R/W
0’h
Analog DACR1 Power Control
0’b: Power Down
1’b: Power On
reserved
Pow_adc_l
10:3
2
R
R/W
0’h
0’h
Reserved
Analog ADCL Power Control
0’b: Power Down
1’b: Power On
Pow_adc_r
Reserved
1
0
R/W
R
0’h
0’h
Analog ADCR Power Control
0’b: Power Down
1’b: Power On
Reserved
8.27. MX-62h: Power Management Control 2
Default: 0000’h
Table 42. MX-62h: Power Management Control 2
Name
Bits Read/Write Reset State Description
Pow_adc_stereo1_filt 15
er
R/W
0’h
Stereo1 ADC Digital Filter Power Control
0’b: Power Down
1’b: Power On
reserved
Pow_dac_stereo1_filt 11
er
14:12
R
R/W
0’h
0’h
Reserved
Stereo1 DAC Digital Filter Power Control
0’b: Power Down
1’b: Power On
Reserved
10:0
R
0’h
Reserved
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Datasheet
8.28. MX-63h: Power Management Control 3
Default: 00C0’h
Table 43. MX-63h: Power Management Control 3
Name
Bits Read/Write Reset State Description
Pow_vref1
15
14
13
12
11
R/W
R/W
R/W
R/W
R/W
0’h
0’h
0’h
0’h
0’h
VREF1 Power Control
0’b: Power Down
1’b: Power On
VREF1 Fast Mode Control
0’b: Fast VREF
1’b: Slow VREF, (For good analog performance)
MBIAS Power Control
0’b: Power Down
1’b: Power On
LOUTMIX Power Control
0’b: Power Down
1’b: Power On
MBIAS Bandgap Power Control
0’b: Power Down
En_fastb1
Pow_main_bias
Pow_lout
Pow_bg_bias
1’b: Power On
reserved
En_l_hp
10:8
7
R
R/W
0’h
1’h
Reserved
Left Headphone Amp Power Control
0’b: Power Down
1’b: Power On
En_r_hp
6
5
4
3
R/W
R/W
R/W
R/W
1’h
0’h
0’h
0’h
Right Headphone Amp Power Control
0’b: Power Down
1’b: Power On
Improve HP Amp Driving
0’b: Disable
1’b: Enable
VREF2 Power Control
0’b: Power Down
1’b: Power On
VREF2 Fast Mode Control
0’b: Fast VREF
En_amp_hp
Pow_vref2
En_fastb2
1’b: Slow VREF, (For good analog performance)
Reserved
LDO Output Control
00’b: 1.1V
Reserved
Ldo_dvo
2
1:0
R
R/W
0’h
0’h
01’b: 1.2V
10’b: 1.3V
11’b: 1.4V
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8.29. MX-64h: Power Management Control 4
Default: 0000’h
Table 44. MX-64h: Power Management Control 4
Name
Bits Read/Write Reset State Description
Pow_bst1
15
R/W
0’h
MIC BST1 Power Control
0’b: Power Down
1’b: Power On
Pow_bst2
14
R/W
0’h
MIC BST2 Power Control
0’b: Power Down
1’b: Power On
Reserved
Pow_micbias1
13:12
11
R
R/W
0’h
0’h
Reserved
MICBIAS1 Power Control
0’b: Power Down
1’b: Power On
reserved
Pow_pll
10
9
R/W
R/W
0’h
0’h
reserved
PLL Power Control
0’b: Power Down
1’b: Power On
reserved
Pow_bst1_op2
8:6
5
R
R/W
0’h
0’h
Reserved
MIC1 SE Mode Control
0’b: For differential mode
1’b: For single-end mode
MIC2 SE Mode Control
0’b: For differential mode
1’b: For single-end mode or line-input mode
Reserved
Pow_bst2_op2
4
R/W
0’h
Reserved
Pow_jd_m
3
2
R
R/W
0’h
0’h
JD_Multilevel Power Control
0’b: Power down
1’b: Power on
Pow_jd2
Reserved
1
0
R/W
R
0’h
0’h
JD2 Power Control
0’b: Power down
1’b: Power on
Reserved
8.30. MX-65h: Power Management Control 5
Default: 0000’h
Table 45. MX-65h: Power Management Control 5
Name
Bits Read/Write Reset State Description
Pow_outmixl
15
R/W
R/W
R
0’h
0’h
0’h
OUTMIXL Power Control
0’b: Power Down
1’b: Power On
OUTMIXR Power Control
0’b: Power Down
1’b: Power On
Pow_outmixr
reserved
14
13:12
Reserved
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Name
Bits Read/Write Reset State Description
Pow_recmixl
11
R/W
R/W
R
0’h
0’h
0’h
RECMIXL Power Control
0’b: Power Down
1’b: Power On
RECMIXR Power Control
0’b: Power Down
1’b: Power On
Pow_recmixr
reserved
10
9:0
Reserved
8.31. MX-66h: Power Management Control 6
Default: 0000’h
Table 46. MX-66h: Power Management Control 6
Name
Bits Read/Write Reset State Description
reserved
Pow_outvoll
15:14
13
R
R/W
0’h
0’h
Reserved
OUTVOLL Power Control
0’b: Power Down
1’b: Power On
Pow_outvolr
Pow_hpovoll
Pow_hpovolr
Pow_inlvol
Pow_inrvol
reserved
12
11
10
9
R/W
R/W
R/W
R/W
R/W
R
0’h
0’h
0’h
0’h
0’h
0’h
OUTVOLR Power Control
0’b: Power Down
1’b: Power On
HPOVOLL Power Control
0’b: Power Down
1’b: Power On
HPOVOLR Power Control
0’b: Power Down
1’b: Power On
INLVOL Power Control
0’b: Power Down
1’b: Power On
8
INRVOL Power Control
0’b: Power Down
1’b: Power On
7:0
Reserved
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Datasheet
8.32. MX-6Ah: Private Register Index
Default: 0000’h
Table 47. MX-6Ah: Private Register Index
Bits Read/Write Reset State Description
Name
reserved
Pr_index
15:8
7:0
R
R/W
0’h
0’h
reserved
PR Register Index
8.33. MX-6Ch: Private Register Data
Default: 0000’h
Table 48. MX-6Ch: Private Register Data
Bits Read/Write Reset State Description
15:0 R/W 0’h PR Register Data
Name
Pr_data
8.34. MX-70h: I2S1 Digital Interface Control
Default: 8000’h
Table 49. MX-70h: I2S1 Digital Interface Control
Name
Bits Read/Write Reset State Description
Sel_i2s1_ms
15
R/W
1’h
I2S1 Digital Interface Mode Control
0’b: Master Mode
1’b: Slave Mode
Reserved
en_i2s1_out_comp
14:12
11:10
R
R/W
0’h
0’h
Reserved
I2S1 Output Data Compress (For ADCDAT1 Output)
00’b: OFF
01’b: µ law
10’b: A law
11’b: Reserved
I2S1 Input Data Compress (For DACDAT1 Input)
00’b: OFF
01’b: µ law
10’b: A law
11’b: Reserved
I2S1 BCLK Polarity Control
0’b: Normal
en_i2s1_in_comp
Inv_i2s1_bclk
9:8
7
R/W
R/W
0’h
0’h
1’b: Invert
reserved
sel_i2s1_len
6:4
3:2
R
R/W
0’h
0’h
Reserved
I2S1 Data Length Selection
00’b: 16 bits
01’b: 20 bits
10’b: 24 bits
11’b: 8 bits
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Name
Bits Read/Write Reset State Description
sel_i2s1_format
1:0
R/W
0’h
I2S1 PCM Data Format Selection
00’b: I2S format
01’b: Left justified
10’b: PCM Mode A (LRCK One Plus at Master Mode)
11’b: PCM Mode B (LRCK One Plus at Master Mode)
8.35. MX-73h: ADC/DAC Clock Control 1
Default: 1104’h
Table 50. MX-73h: ADC/DAC Clock Control 1
Name
Bits Read/Write Reset State Description
Reserved
I2S Clock Pre-Divider 1
000’b: ÷ 1
Reserved
sel_i2s_pre_div1
15
14:12
R
R/W
0’h
1’h
001’b: ÷ 2
010’b: ÷ 3
011’b: ÷ 4
100’b: ÷ 6
101’b: ÷ 8
110’b: ÷ 12
111’b: ÷ 16
Reserved
reserved
sel_dac_osr
11:4
3:2
R
R/W
10’h
1’h
Stereo DAC Over Sample Rate Select
00’b: 128Fs
01’b: 64Fs
10’b: 32Fs
11’b: 128Fs/3
Stereo ADC Over Sample Rate Select
00’b: 128Fs
sel_adc_osr
1:0
R/W
0’h
01’b: 64Fs
10’b: 32Fs
11’b: 128Fs/3
8.36. MX-74h: ADC/DAC Clock Control 2
Default: 0C00’h
Table 51. MX-74h: ADC/DAC Clock Control 2
Name
Bits Read/Write Reset State Description
Reserved
Dahpf_en
15:12
11
R
R/W
0’h
1’h
Reserved
Stereo1 DAC Filter HPF Power Control
0’b: Disable
1’b: Enable
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Name
Bits Read/Write Reset State Description
adhpf_en
10
R/W
1’h
Stereo1 ADC Filter HPF Power Control
0’b: Disable
1’b: Enable
Reserved
reserved
9:0
R
0’h
8.37. MX-80h: Global Clock Control
Default: 0000’h
Table 52. MX-80h: Global Clock Control
Bits Read/Write Reset State Description
Name
sel_sysclk1
15:14
R/W
0’h
System Clock Source MUX Control
00’b: MCLK
01’b: PLL
10’b: Reserved
11’b: Reserved
PLL Source Selection
00’b: From MCLK
01’b: From BCLK1
10’b: Reserved
11’b: Reserved
Reserved
sel_pll_sour
13:12
R/W
0’h
reserved
sel_pll_pre_div
11:4
3
R
R/W
0’h
0’h
PLL Pre-Divider
0’b: ÷ 1
1’b: ÷ 2
reserved
2:0
R
0’h
Reserved
8.38. MX-81h: PLL Control 1
Default: 0000’h
Table 53. MX-81h: PLL Control 1
Bits Read/Write Reset State Description
Name
Pll_n_code
15:7
R/W
0’h
PLL N[8:0] Code
000000000’b: Div 2
000000001’b: Div 3
…
111111111’b: Div 513
Reserved
PLL K[4:0] Code
00000’b: Div 2
00001’b: Div 3
…
Reserved
Pll_k_code
6:5
4:0
R
R/W
0’h
0’h
11111’b: Div 33
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8.39. MX-82h: PLL Control 2
Default: 0000’h
Table 54. MX-82h: PLL Control 2
Bits Read/Write Reset State Description
Name
Pll_m_code
15:12
R/W
0’h
PLL M[3:0] Code
0000’b: Div 2
0001’b: Div 3
…
1111’b: Div 17
Bypass PLL M Code
0’b : No bypass
1’b : Bypass
Reserved
Pll_m_bypass
Reserved
11
R/W
R
0’h
0’h
10:0
8.40. MX-8Eh: HPAmp Control 1
Default: 0004’h
Table 55. MX-8Eh: HP Amp Control 1
Bits Read/Write Reset State Description
Name
Enable Softgen Trigger for Soft Mute Depop
Smttrig_hp
15
R/W
0’h
0’b: Disable
1’b: Enable
Reserved
Enable HP_L Mute/Un-Mute Depop
0’b: Disbale
reserved
En_smt_l_hp
14:10
9
R/W
R/W
0’h
0’h
1’b: Enable
Enable HP_R Mute/Un-Mute Depop
0’b: Disbale
1’b: Enable
Capless Depop Power Down Control
0’b: Disbale
1’b: Enable
Reset Softgen to Initialize SOFTP=1
0’b: Disbale
1’b: Reset
Reset Softgen to Initialize SOFTP=0
0’b: Disbale
1’b: Reset
Enable Headphone Output
0’b: Disable
1’b: Enable
Charge Pump Power Control
0’b: Power Down
1’b: Power On
Power On Soft Generator
0’b: Power down
1’b: Power on
En_smt_r_hp
Pdn_hp
8
7
6
5
4
3
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0’h
0’h
0’h
0’h
0’h
0’h
1’h
Softgen_rstn
Softgen_rstp
En_out_hp
Pow_pump_hp
En_softgen_hp
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Name
Bits Read/Write Reset State Description
Reserved
reserved
Pow_capless
1
0
R/W
R/W
0’h
0’h
HP Amp All Power On Control
0’b: Power Down
1’b: Power On
8.41. MX-8Fh: HPAmp Control 2
Default: 1100’h
Table 56. MX-8Fh: HP Amp Control 2
Bits Read/Write Reset State Description
Name
Reserved
reserved
Depop_mode_hp
15:14
13
R
R/W
0’h
0’h
Select HP Depop Mode
0’b: Depop mode 1
1’b: Depop mode 2
Reserved
HP Depop Mode 1 Control
0’b: Disbale
reserved
En_depop_mode1
12:7
6
R/W
R/W
22’h
0’h
1’b: Enable
Reserved
reserved
5:0
R/W
0’h
8.42. MX-93h: MICBIAS Control
Default: 2000’h
Table 57. MX-93h: MICBIAS Control
Bits Read/Write Reset State Description
Name
Sel_micbias1
15
R/W
0’h
MICBIAS1 Output Voltage Control
0’b: 0.9 * MICVDD
1’b: 0.75 * MICVDD
Reserved
MICBIAS1 Short Current Detector Control
0’b: Disable
reserved
Pow_mic1_ovcd
14:12
11
R/W
R/W
2’h
0’h
1’b: Enable
Mic1_ovcd_th_sel
reserved
10:9
8:0
R/W
R/W
0’h
0’h
MICBIAS1 Short Current Detector Threshold
00’b: 600uA
01’b: 1500uA
1x’b: 2000uA
Note: tolerance is 200uA
reserved
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8.43. MX-94h: Jack Detection Control
Default: 0200’h
Table 58. MX-94h: Jack Detection Control
Bits Read/Write Reset State Description
Name
Reserved
Jad_cmp
Pullup_jd
15:14
13
11
R
R
R/W
0’h
0’h
0’h
Reserved
JD2 Status
JD2 Pull Up Control
0’b: Off
1’b: Pull up
Pulldown_jd
10
R/W
0’h
JD2 Pull Down Control
0’b: Off
1’b: Pull down
Reserved
JD_M Output
JD_M Pull Up Control
0’b: Off
Reserved
Jd_m_cmp
Pullup_jd_m
9:7
6:4
3
R/W
R
R/W
4’h
0’h
0’h
1’b: Pull up
Pulldown_jd_m
Reserved
2
R/W
R/W
0’h
0’h
JD_M Pull Down Control
0’b: Off
1’b: Pull down
Reserved
1:0
8.44. MX-B0h: EQ Control 1
Default: 2080’h
Table 59. MX-B0h: EQ Control 1
Name
Bits Read/Write Reset State Description
0’h
eq_sour
15
R/W
EQ Path Control
0’b: DAC path
1’b: ADC path
0’h
eq_para_update
14
R/W
EQ Parameter Update Control
0’b: No action
1’b: Update parameter
Reserved
EQ High Pass Filter (HPF2) Status.
0’b: Normal
reserved
sta_hpf2
13:7
6
R/W
R
41’h
0’h
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
sta_hpf1
5
R
0’h
EQ High Pass Filter (HPF1) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
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Name
Bits Read/Write Reset State Description
sta_bpf4
4
3
2
1
0
R
R
R
R
R
0’h
0’h
0’h
0’h
0’h
EQ Band-4 (BP4) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
EQ Band-3 (BP3) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
EQ Band-2 (BP2) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
EQ Band-1 (BP1) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
sta_bpf3
sta_bpf2
sta_bpf1
sta_lpf
EQ Low Pass Filter (LPF) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
8.45. MX-B1h: EQ Control 2
Default: 0000’h
Table 60. MX-B1h: EQ Control 2
Bits Read/Write Reset State Description
Name
0’h
0’h
reserved
reg_typ_hpf_en
15:9
8
R
R/W
Reserved
EQ High Pass Filter1 Mode Control
0’b: High frequency shelving filter
1’b: 1st order Butterworth HPF (-20dB per decade)
EQ Low Pass Filter Mode Control
0’b: Low frequency shelving filter
1’b: 1st order Butterworth LPF (-20dB per decade)
EQ High Pass 2nd Butterworth Filter (HPF) Control.
0’b: Disabled (bypass) and reset
1’b: Enabled
EQ High Pass Filter (HPF) Control.
0’b: Disabled (bypass) and reset
1’b: Enabled
EQ Band-4 (BP4) shelving Filter Control.
0’b: Disabled and reset
0’h
0’h
0’h
0’h
reg_typ_lpf_en
en_hpf2
7
6
5
4
R/W
R/W
R/W
R/W
en_hpf1
en_bpf4
1’b: Enabled.
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Name
Bits Read/Write Reset State Description
0’h
0’h
0’h
0’h
en_bpf3
3
2
1
0
R/W
R/W
R/W
R/W
EQ Band-3 (BP3) shelving Filter Control.
0’b: Disabled and reset
1’b: Enabled.
EQ Band-2 (BP2) shelving Filter Control.
0’b: Disabled and reset
1’b: Enabled.
EQ Band-1 (BP1) shelving Filter Control.
0’b: Disabled and reset
1’b: Enabled.
EQ Low Pass Filter (LPF) Filter Control.
0’b: Disabled and reset
en_bpf2
en_bpf1
en_lpf
1’b: Enabled.
8.46. MX-B4h: DRC/AGC Control 1
Default: 2206’h
Table 61. MX-B4h: DRC/AGC Control 1
Bits Read/Write Reset State Description
Name
sel_drc_agc
15:14
R/W
0’h
DRC/AGC Enable
00’b: Disable DRC/AGC
01’b: Enable DRC to DAC Path
10’b: Disable DRC/AGC
11’b: Enable AGC to ADC Path
Update DRC/AGC Parameter
Write 1’b to update all DRC/AGC parameter
Select DRC/AGC attack rate (0.375dB/TU)
00’h: 83 uSec
update_drc_agc_para
m
13
R
1’h
2’h
sel_drc_agc_atk
12:8
R/W
01’h: 0.167 mSec
…
10’h: 5.46 Sec
Others: Reserved
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Name
Bits Read/Write Reset State Description
Drc_agc_rate_sel
7:5
R/W
0’h
DRC/AGC Rate Control for Sample Rate Change
001’b: 48kHz
010’b: 96kHz
011’b: 192kHz
101’b: 44.1kHz
110’b: 88.2kHz
111’b: 176.4kHz
Others: Reserved
Select DRC/AGC recovery rate (0.375dB/TU)
00’h: 83 uSec
sel_rc_rate
4:0
R/W
6’h
01’h: 0.167 mSec
…
10’h: 5.46 Sec
Others: Reserved
attack time=(4*2^n)/Sample_Rate, n = MX-B4[12:8], default=0.33mS
recovery time=(4*2^n)/Sample_Rate, n = MX-B4[4:0], default=5.3mS
When change I2S’s sample rate, the DRC/AGC rate control is need to be changed same with I2S’s sample rate. When
change the DRC/AGC rate, the parameter of DRC/AGC isn’t need be modified.
When I2S’s sample rate is below 48kHz, that need to set the DRC/AGC rate to 48kHz and re-calculate the DRC/AGC’s
parameter by I2S’s sample rate.
8.47. MX-B5h: DRC/AGC Control 2
Default: 1F00’h
Table 62. MX-B5h: DRC/AGC Control 2
Name
Bits Read/Write Reset State Description
reserved
15:14
R
0’h
Reserved
sel_drc_agc_post_bst 13:8
R/W
1f’h
DRC/AGC Digital Post-Boost Gain (0.375dB/step)
00’h= -11.625dB
………………..
3F’h= 12dB
Others: Reserved
DRC/AGC Compression Function Control
0’b: Disable
En_drc_agc_compres
s
7
R/W
0’h
1’b: Enable
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Name
Bits Read/Write Reset State Description
Sel_ratio
6:5
R/W
0’h
DRC/AGC Compression Ratio Selection
00’b: 1:1
01’b: 1:2
10’b: 1:4
11’b: 1:8
sel_drc/agc_pre_bst
4:0
R/W
0’h
DRC/AGC Digital Pre-Boost Gain (1.5dB/step)
00’h= 0dB
01’h= 1.5dB
02’h= 3dB
03’h= 4.5dB
………………..
13’h= 28.5dBFS
Others: Reserved
Gain table:
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain
-11.625
-11.25
-10.875
-10.5
-10.125
-9.75
-9.375
-9
-5.625
-5.25
-4.875
-4.5
0
1
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
0.375
0.75
1.125
1.5
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
6.375
6.75
64
65
66
67
68
69
70
71
72
73
74
75
76
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
2
2
7.125
7.5
3
3
-4.125
-3.75
-3.375
-3
4
4
1.875
2.25
2.625
3
7.875
8.25
5
5
6
6
8.625
9
7
7
-8.625
-8.25
-7.875
-7.5
-2.625
-2.25
-1.875
-1.5
8
8
3.375
3.75
4.125
4.5
9.375
9.75
9
9
10
11
12
13
14
15
A
B
C
D
E
F
10.125
10.5
-7.125
-6.75
-6.375
-6
-1.125
-0.75
-0.375
0
4.875
5.25
5.625
6
10.875
11.25
11.625
12
DEC HEX Boost Gain DEC HEX Boost Gain
24
25.5
27
0
1
2
0
1
2
0
1.5
3
16
17
18
10
11
12
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28.5
3
4
3
4
4.5
6
19
20
21
22
23
24
25
26
27
28
29
30
31
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
5
5
7.5
9
6
6
7
7
10.5
12
8
8
13.5
15
9
9
10
11
12
13
14
15
A
B
C
D
E
F
16.5
18
19.5
21
22.5
8.48. MX-B6h: DRC/AGC Control 3
Default: 0000’h
Table 63. MX-B6h: DRC/AGC Control 3
Bits Read/Write Reset State Description
Name
Noise_gate_boost
15:12
11:7
6
R/W
R/W
R/W
0’h
0’h
0’h
Select Compensation Gain When Signal is Below Noise Gate
0’h: 0dB
1’h: 3dB
2’h: 6dB
…
E’h: 42dB
F’h: 45dB
sel_drc_agc_thmax
DRC/AGC Limiter Level (1.5dB/step)
00’h= 0dBFS
01’h= -1.5dBFS
02’h= -3dBFS
03’h= -4.5dBFS
…
1F’h= -46.5dBFS
Enable Noise Gate function
0’b: Diaable
en_drc_agc_noise_ga
te
1’b: Enable
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Name
Bits Read/Write Reset State Description
En_drc_agc_noise_ga
5
R/W
0’h
Enable Noise Gate Hold Data Function
te_hold
0’b: Disable
1’b: Enable
sel_drc_agc_noise_th
4:0
R/W
0’h
Noise Gate Threshold (-1.5dB/step)
00’h: -36dBFS
01’h: -375dBFS
………………..
1F’h: -82.5 dBFS
8.49. MX-BBh: Jack Detection Control 1
Default: 0000’h
Table 64. MX-BBh: Jack Detection Control 1
Bits Read/Write Reset State Description
Name
sel_gpio_jd
15:13
R/W
0’h
Jack Detect Selection
000’b: OFF
001’b: GPIO1
Others: Reserved
reserved
en_jd_hpo
12
11
R
R/W
0’h
0’h
Reserved
Enable Jack Detect Trigger HPOUT
0’b: Disable
1’b: Enable
polarity_jd_tri_hpo
10
R/W
0’h
Select Jack Detect Polarity Trigger HPOUT
0’b: Low trigger
1’b: High trigger
reserved
en_jd_lout
9:4
3
R
R/W
0’h
0’h
Reserved
Enable Jack Detect Trigger LOUT
0’b: Disable
1’b: Enable
polarity_jd_tri_lout
reserved
2
R/W
R/W
0’h
0’h
Select Jack Detect Polarity Trigger LOUT
0’b: Low trigger
1’b: High trigger
1:0
reserved
8.50. MX-BCh: Jack Detection Control 2
Default: 0000’h
Table 65. MX-BCh: Jack Detection Control 2
Bits Read/Write Reset State Description
15:12 0’h Reserved
Name
reserved
R
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Name
Bits Read/Write Reset State Description
Sel_jd_trigger
11:9
R/W
0’h
JD Trigger Source Selection
000’b: From sta_gpio_jd
001’b: From sta_jd1_1
010’b: From sta_jd1_2
011’b: From sta_jd2
Others: Reserved
reserved
8:0
R
0’h
Reserved
8.51. MX-BDh: IRQ Control 1
Default: 0000’h
Table 66. MX-BDh: IRQ Control 1
Bits Read/Write Reset State Description
Name
en_irq_gpio_jd
15
R/W
0’h
IRQ Output Source Configure of GPIO Jack Detection Status
0’b: Disable
1’b: Enable
Reserved
en_gpio_jd_sticky
14
13
R
R/W
0’h
0’h
Reserved
Sticky Control for GPIO Jack Detect
0’b: Disable
1’b: Enable
Reserved
inv_gpio_jd
12
11
R
R/W
0’h
0’h
Reserved
GPIO Jack Detection Status Polarity
0’b: Normal
1’b: Output Invert
reserved
en_irq_jd1_1
10
9
R
R/W
0’h
0’h
Reserved
IRQ Output Source Configure of JD1_1 Jack Detection
Status
0’b: Disable
1’b: Enable
en_jd1_1_sticky
inv_jd1_1
8
7
6
R/W
R/W
R/W
0’h
0’h
0’h
Sticky Control for JD1_1 Jack Detect
0’b: Disable
1’b: Enable
JD1_1 Jack Detection Status Polarity
0’b: Normal
1’b: Output Invert
IRQ Output Source Configure of JD1_2 Jack Detection
en_irq_jd1_2
Status
0’b: Disable
1’b: Enable
en_jd1_2_sticky
inv_jd1_2
5
4
R/W
R/W
0’h
0’h
Sticky Control for JD1_2 Jack Detect
0’b: Disable
1’b: Enable
JD1_2 Jack Detection Status Polarity
0’b: Normal
1’b: Output Invert
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Name
Bits Read/Write Reset State Description
en_irq_jd2
3
2
1
0
R/W
R/W
R/W
R
0’h
0’h
0’h
0’h
IRQ Output Source Configure of JD2 Jack Detection Status
0’b: Disable
1’b: Enable
Sticky Control for JD2 Jack Detect
0’b: Disable
1’b: Enable
JD2 Jack Detection Status Polarity
0’b: Normal
1’b: Output Invert
Reserved
en_jd2_sticky
inv_jd2
reserved
8.52. MX-BEh: IRQ Control 2
Default: 0000’h
Table 67. MX-BEh: IRQ Control 2
Bits Read/Write Reset State Description
Name
en_irq_micbias1_ovc
d
15
R/W
0’h
IRQ Output Source Configure of MICBIAS1 Over Current
Status
0’b: Disable
1’b: Enable
reserved
en_micbias1_ovcd_st
icky
14:12
11
R/W
R/W
0’h
0’h
Reserved
Sticky Control for MICBIAS1 Over Current
0’b: Disable
1’b: Enable
reserved
inv_micbias1_ovcd
10:8
7
R/W
R/W
0’h
0’h
Reserved
MICBIAS1 over current status polarity
0’b: Normal
1’b: Output Invert
reserved
Ovc_micbias1
6:4
3
R
R
0’h
0’h
Reserved
MICBIAS1 Over Current Status
Read: return status of each status pin
Write: Write ‘0’ to clear stick bit
Reserved
Reserved
2:0
R
0’h
8.53. MX-BFh: GPIO and Internal Status
Default: 0000’h
Table 68. MX-BFh: GPIO and Internal Status
Name
Bits Read/Write Reset State Description
Reserved
sta_jd2
15
14
R
R
0’h
0’h
Reserved
JD2 Pin Status
Read: return status of JD2 pin
Write: Write ‘0’ to clear stick bit
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Name
Bits Read/Write Reset State Description
sta_jd1_2
13
R
0’h
JD1 Pin Status
Read: return status of JD1_2
Write: Write ‘0’ to clear stick bit
JD1 Pin Status
sta_jd1_1
12
R
0’h
Read: return status of JD1_1
Write: Write ‘0’ to clear stick bit
Reserved
Reserved
sta_gpio1
11:9
8
R
R
0’h
0’h
GPIO1 Pin Status
Read: return status of GPIO1 pin
Reserved
GPIO_JD Status
Reserved
sta_gpio_jd
7:5
4
R
R
0’h
0’h
Read: Return status of Jack Detect Select output
Write: Write ‘0’ to clear stick bit
Reserved
reserved
3:0
R
0’h
8.54. MX-C0h: GPIO Control 1
Default: 0100’h
Table 69. MX-C0h: GPIO Control 1
Bits Read/Write Reset State Description
Name
sel_gpio1_type
15
R/W
0’h
GPIO1 Pin Function Select
0’b: GPIO1
1’b: IRQ output
Reserved
reserved
14:0
R
100’h
8.55. MX-C1h: GPIO Control 2
Default: 0000’h
Table 70. MX-C1h: GPIO Control 2
Name
Bits Read/Write Reset State Description
reserved
sel_gpio1
15:3
2
R
R/W
0’h
0’h
Reserved
GPIO1 Pin Configuration
0’b: Input
1’b: Output
sel_gpio1_logic
inv_gpio1
1
0
R/W
R/W
0’h
0’h
GPIO1 Output Pin Control
0’b: Drive Low
1’b: Drive High
GPIO1 Pin Polarity
0’b: Normal
1’b: Output Invert
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8.56. MX-D3h: Wind Filter Control 1
Default: B320’h
Table 71. MX-D3h: Wind Filter Control 1
Bits Read/Write Reset State Description
Name
Enable Adjustable 2nd Wind Filter
0'b : Disable (bypass mode)
1'b : Enable
adj_hpf_2nd_en
15
R/W
1’h
adj_hpf_coef_l_sel
14:12
R/W
3’h
Left Channel Coefficient Sample Rate Selection
000'b: 8K/12K/16K Hz
001'b: 24K/32K Hz
010'b: 48K/44.1K Hz
011'b: 96K/88.2K Hz
100'b: 192K/176.4K Hz
Others: Reserved
Reserved
adj_hpf_coef_r_sel
11
10:8
R
R/W
0’h
2’h
Reserved
Right Channel Coefficient Sample Rate Selection
000'b: 8K/12K/16K Hz
001'b: 24K/32K Hz
010'b: 48K/44.1K Hz
011'b: 96K/88.2K Hz
100'b: 192K/176.4K Hz
Others: Reserved
reserved
7:0
R/W
20’h
Reserved
8.57. MX-D4h: Wind Filter Control 2
Default: 0000’h
Table 72. MX-D3h: Wind Filter Control 2
Bits Read/Write Reset State Description
Name
Reserved
adj_hpf_coef_l_num
15:14
13:8
R
R/W
0’h
0’h
Reserved
Left Channel Coefficient Fine Parameter Selection
(0 ~ 63)
Reserved
adj_hpf_coef_r_num
7:6
5:0
R
R/W
0’h
0’h
Reserved
Right Channel Coefficient Fine Parameter Selection
(0 ~ 63)
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8.58. MX-D9h: Soft Volume & ZCD Control
Default: 0809’h
Table 73. MX-D9h: Soft Volume & ZCD Control
Name
Bits Read/Write Reset State Description
en_softvol
15
R/W
0’h
Digital Soft Volume Delay Control
0’b: Disable
1’b: Enable
Reserved
en_o_svol
14
13
R
R/W
0’h
0’h
Reserved
OUTVOLL/R Soft Volume Delay Control
0’b: Disable
1’b: Enable
en_hpo_svol
en_zcd_digital
pow_zcd
12
11
10
R/W
R/W
R/W
0’h
1’h
0’h
HPOVOLL/R Soft Volume Delay Control
0’b: Disable
1’b: Enable
Digital Volume Zero Crossing Detection Control
0’b: Disable
1’b: Enable
Power On Zero Crossing
0’b: Power Down
1’b: Power On
Reserved
En_zcd_outmixr
9:8
7
R
R/W
0’h
0’h
Reserved
OUTMIXR Mute/Un-Mute ZCD Control
0’b: Disable
1’b: Enable
En_zcd_outmixl
En_zcd_recmixr
En_zcd_recmixl
sel_svol
6
5
R/W
R/W
R/W
R/W
0’h
0’h
0’h
9’h
OUTMIXL Mute/Un-Mute ZCD Control
0’b: Disable
1’b: Enable
RECMIXR Mute/Un-Mute ZCD Control
0’b: Disable
1’b: Enable
RECMIXL Mute/Un-Mute ZCD Control
0’b: Disable
1’b: Enable
Soft Volume Change Delay Time
0000: 1 SVSYNC
4
3:0
0001: 2 SVSYNC
0010: 4 SVSYNC
0011: 8 SVSYNC
0100: 16 SVSYNC
0101: 32 SVSYNC
0110: 64 SVSYNC
0111: 128 SVSYNC
1000: 256 SVSYNC
1001: 512 SVSYNC
1010: 1024 SVSYNC
Others: Reserved
Note: SVSYNC=1/Fs, Step:-1.5dBFS
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8.59. MX-FAh: General Control 1
Default: 0010’h
Table 74. MX-FAh: General Control 1
Bits Read/Write Reset State Description
Name
Reserved
En_detect_clk_sys
15:4
3
R
R/W
1’h
0’h
Reserved
Enable MCLK Detection and Auto Switch to Internal Clock
0’b: Disable
1’b: Enable
Reserved
Digital_gate_ctrl
2:1
0’h
R/W
R/W
0’h
0’h
Reserved
MCLK Clock Gating Control
0’b: Gating input clock
0’b: Enable input clock
8.60. PR-3Dh: ADC/DAC RESET Control
Default: 2000’h
Table 75. PR-3Dh: ADC/DAC RESET Control
Name
Bits Read/Write Reset State Description
Reserved
En_ckgen_adc
15:13
12
R/W
R/W
1’h
0’h
Reserved
Enable ADC Clock Generator
0’b: Disable
1’b: Enable
Reserved
Ckxen_dac
11
10
R/W
R/W
0’h
0’h
Reserved
Enable DAC Clock1 Generator
0’b: Disable
1’b: Enable
En_ckgen_dac
Reserved
9
R/W
R/W
0’h
0’h
Enable DAC Clock2 Generator
0’b: Disable
1’b: Enable
8:0
Reserved
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8.61. PR-A0h: EQ Low Pass Filter Coefficient (LPF:a1)
Default: 1C10’h
Table 76. PR-A0h: EQ Low Pass Filter Coefficient (LPF:a1)
Name
Bits Read/Write Reset State Description
lpf_a1
15:0
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
8.62. PR-A1h: EQ Low Pass Filter Gain (LPF:H0)
Default: 01F4’h
Table 77. PR-A1h: EQ Low Pass Filter Gain (LPF:H0)
Name
Bits Read/Write Reset State Description
lpf_h0
15:0
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
8.63. PR-A2h: EQ Band 1 Coefficient (BPF1:a1)
Default: C5E9’h
Table 78. PR-A2h: EQ Band 1 Coefficient (BPF1:a1)
Name
Bits Read/Write Reset State Description
Bpf1_a1
15:0
R/W
C5E9’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
8.64. PR-A3h: EQ Band 1 Coefficient (BPF1:a2)
Default: 1A98’h
Table 79. PR-A3h: EQ Band 1 Coefficient (BPF1:a2)
Name
Bits Read/Write Reset State Description
Bpf1_a2
15:0
R/W
1A98’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
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8.65. PR-A4h: EQ Band 1 Gain (BPF1:H0)
Default: 1D2C’h
Table 80. PR-A4h: EQ Band 1 Gain (BPF1:H0)
Name
Bits Read/Write Reset State Description
Bpf1_h0
15:0
R/W
1D2C’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
8.66. PR-A5h: EQ Band 2 Coefficient (BPF2:a1)
Default: C882’h
Table 81 PR-A5h: EQ Band 2 Coefficient (BPF2:a1)
Name
Bits Read/Write Reset State Description
Bpf2_a1
15:0
R/W
C882’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
8.67. PR-A6h: EQ Band 2 Coefficient (BPF2:a2)
Default: 1C10’h
Table 82. PR-A6h: EQ Band 2 Coefficient (BPF2:a2)
Name
Bits Read/Write Reset State Description
Bpf2_a2
15:0
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
8.68. PR-A7h: EQ Band 2 Gain (BPF2:H0)
Default: 01F4’h
Table 83. PR-A7h: EQ Band 2 Gain (BPF2:H0)
Name
Bits Read/Write Reset State Description
Bpf2_h0
15:0
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
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8.69. PR-A8h: EQ Band 3 Coefficient (BPF3:a1)
Default: E904’h
Table 84. PR-A8h: EQ Band 3 Coefficient (BPF3:a1)
Name
Bits Read/Write Reset State Description
Bpf3_a1
15:0
R/W
E904’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
8.70. PR-A9h: EQ Band 3 Coefficient (BPF3:a2)
Default: 1C10’h
Table 85. PR-A9h: EQ Band 3 Coefficient (BPF3:a2)
Name
Bits Read/Write Reset State Description
Bpf3_a2
15:0
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
8.71. PR-AAh: EQ Band 3 Gain (BPF3:H0)
Default: 01F4’h
Table 86. PR-AAh: EQ Band 3 Gain (BPF3:H0)
Name
Bits Read/Write Reset State Description
Bpf3_h0
15:0
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
8.72. PR-ABh: EQ Band 4 Coefficient (BPF4:a1)
Default: E904’h
Table 87. PR-ABh: EQ Band 4 Coefficient (BPF4:a1)
Name
Bits Read/Write Reset State Description
Bpf4_a1
15:0
R/W
E904’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
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8.73. PR-ACh: EQ Band 4 Coefficient (BPF4:a2)
Default: 1C10’h
Table 88. PR-ACh: EQ Band 4 Coefficient (BPF4:a2)
Name
Bits Read/Write Reset State Description
Bpf4_a2
15:0
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
8.74. PR-ADh: EQ Band 4 Gain (BPF4:H0)
Default: 01F4’h
Table 89. PR-ADh: EQ Band 4 Gain (BPF4:H0)
Name
Bits Read/Write Reset State Description
Bpf4_h0
15:0
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
8.75. PR-AEh: EQ High Pass Filter 1 Coefficient (HPF1:a1)
Default: 1C10’h
Table 90. PR-AEh: EQ High Pass Filter 1 Coefficient (HPF1:a1)
Name
Bits Read/Write Reset State Description
Hpf1_a1
15:0
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
8.76. PR-AFh: EQ High Pass Filter 1 Gain (HPF1:H0)
Default: 01F4’h
Table 91. PR-AFh: EQ High Pass Filter 1 Gain (HPF1:H0)
Name
Bits Read/Write Reset State Description
Hpf1_h0
15:0
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
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8.77. PR-B0h: EQ High Pass Filter 2 Coefficient (HPF2:a1)
Default: 2000’h
Table 92. PR-B0h: EQ High Pass Filter 2 Coefficient (HPF2:a1)
Name
Bits Read/Write Reset State Description
Hpf2_a1
15:0
R/W
2000’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
8.78. PR-B1h: EQ High Pass Filter 2 Coefficient (HPF2:a2)
Default: 0000’h
Table 93. PR-B1h: EQ High Pass Filter 2 Coefficient (HPF2:a2)
Name
Bits Read/Write Reset State Description
Hpf2_a2
15:0
R/W
0000’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
8.79. PR-B2h: EQ High Pass Filter 2 Gain (HPF2:H0)
Default: 2000’h
Table 94. PR-B2h: EQ High Pass Filter 2 Gain (HPF2:H0)
Name
Bits Read/Write Reset State Description
Hpf2_h0
15:0
R/W
2000’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
8.80. PR-B3h: EQ Pre Volume Control
Default: 0800’h
Table 95. PR-B3h: EQ Pre Volume Control
Bits Read/Write Reset State Description
Name
Eq_pre_vol
15:0
R/W
0800’h
2’s complement in 5.11 format. (Default is 0dB)
(The range is from –16~15.99, pre-gain should be in 0 ~
15.99 [+24dB ~ -66dB])
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8.81. PR-B4h: EQ Post Volume Control
Default: 0800’h
Table 96. PR-B4h: EQ Post Volume Control
Bits Read/Write Reset State Description
15:0 R/W 0800’h 2’s complement in 5.11 format. (Default is 0dB)
Name
Eq_post_vol
(The range is from –16~15.99, pre-gain should be in 0 ~
15.99 [+24dB ~ -66dB])
8.82. MX-FEh: Vendor ID
Default: 10EC’h
Table 97. MX-FEh: Vendor ID
Name
Bits Read/Write Reset State Description
Vendor_id
15:0
R
10EC’h
Vendor ID
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Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 98. Absolute Maximum Ratings
Parameter
Symbol
Min
Typ
Max
Units
Power Supplies
Digital IO Buffer
Digital Core
Analog
Analog
Headphone
Micbias
Operating Ambient Temperature
Storage Temperature
DBVDD
DCVDD
AVDD
DACREF
CPVDD
MICVDD
Ta
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-25
-
-
-
-
-
-
-
-
3.63
1.98
1.98
1.98
1.98
3.63
+85
V
V
V
V
V
V
oC
oC
Ts
-55
+125
9.1.2. Recommended Operating Conditions
Table 99. Recommended Operating Conditions
Parameter
Digital IO Buffer
Digital Core
Analog
Analog
Headphone
Micbias
Symbol
DBVDD
DCVDD
AVDD
DACREF
CPVDD
MICVDD
Min
1.71
1.1
1.71
1.71
1.71
3.0
Typ
1.8
1.2
1.8
1.8
1.8
3.3
Max
3.6
1.9
1.9
1.9
1.9
3.6
Units
V
V
V
V
V
V
9.1.3. Static Characteristics
Table 110. Static Characteristics
Parameter
Input Voltage Range
Symbol
Min
-0.30
-
Typ
-
-
-
-
Max
DBVDD+0.30
0.35DBVDD
Units
V
V
V
V
VIN
VIL
VIH
VOH
VOL
-
-
-
-
Low Level Input Voltage
High Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Output Buffer High Drive Current
Output Buffer Low Drive Current
Input Buffer Pull-Up Resistor
Input Buffer Pull-Down Resistor
0.65DBVDD
0.9DBVDD
-
-
0.1DBVDD
4.3
-
-
V
0.6
0.7
55
63
1.8
2.1
110
130
mA
mA
K
K
4.8
270
300
Note: DBVDD=1.8V, DCVDD=1.2V, Tambient=40C.
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9.2. Analog Performance Characteristics
Table 111. Analog Performance Characteristics
Parameter
Min
Typ
Max
Units
Full Scale Input Voltage
Line Inputs (Single-ended)
MIC Inputs (Single-ended )
MIC Inputs (Differential)
-
-
-
0.6
0.6
1.2
-
-
-
Vrms
Vrms
Vrms
Full Scale Output Voltage
Line Outputs (Single-ended)
Line Outputs (Differential)
-
-
-
1.0
1.0
1.0
0.7
-
-
-
Vrms
Vrms
Vrms
Vrms
Headphone Amplifiers Outputs (For 10KOhm Load)
Headphone Amplifiers Outputs (For 16Ohm Load)
S/N Ratio
Stereo DAC Direct to HP_L/R with 32Ohm
-
-
98
100
dBA
Line_In to Stereo ADC with 0dB (Single-end)
MIC_In to Stereo ADC with 0dB (Differential or Single-end)
94
94
89
95
95
dBA
dBA
dBA
MIC_In to Stereo ADC with 20dB and MICBIAS (Differential or
Single-end)
MIC_In to Stereo ADC with 40dB and MICBIAS (Differential or
Single-end)
MIC_In to Stereo ADC with 50dB and MICBIAS (Differential or
Single-end)
78
68
dBA
dBA
Total Harmonic Distortion + Noise
DAC Direct to HP_L/R with 16Ohm
Po = 20mW/CH
-80
-86
-83
dB
dB
DAC Direct to HP_L/R with 10KOhm
-3dBFS
Line_In to Stereo ADC with 0dB (Single-end)
-83
-83
-81
dB
dB
dB
MIC_In to Stereo ADC with 0dB (Differential or Single-end)
MIC_In to Stereo ADC with 20dB and MICBIAS (Differential or
Single-end)
MIC_In to Stereo ADC with 40dB and MICBIAS (Differential or
Single-end)
-74
-65
dB
dB
MIC_In to Stereo ADC with 50dB and MICBIAS (Differential or
Single-end)
Power Consumption (Slave I2S Mode, 24-bit, SR: 44.1KHz)
P_power down (No Clock Input)
<50
uW
P_playback (Stereo DAC to HP_OUT with 16 Ohm Load, With
Clock, play silence)
<= 6.5
mW
P_playback (Stereo DAC to HP_OUT with 16 Ohm Load, With
Clock, Po=1mW/CH)
P_record (LINE_IN to Stereo ADC, With Clock)
<= 14
< 9
mW
mW
Power Down Current
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Datasheet
Parameter
Min
Typ
Max
20
Units
µA
IDD_1.8V
-
-
-
-
IDDD_3.3V
10
µA
MICBIAS1 Output Voltage
Setting 1
Setting 2
0.9*MICVDD
0.75*MICVDD
-
-
-
-
V
V
MICBIAS1 Drive Current
MICBIAS = 0.9*MICVDD
-
4
-
mA
Note: Standard test conditions:
Tambient=25C
DBVDD=1.8V
DCVDD=1.2V
AVDD=1.8V
MICVDD=3.3V
CPVDD=1.8V
1kHz input sine wave; PCM Sampling frequency=48kHz; Test bench Characterization BW: 10Hz~22kHz, 0dB attenuation
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Datasheet
9.3. Signal Timing
9.3.1. I2C Control Interface
t
t
(10)
(9)
w
w
t
sp
SCLK
SDA
t
(7)
su
t
t
t
(8)
(5)
(6)
h
su
h
Figure 24. I2C Control Interface
Table 112. I2C Timing
Parameter
Symbol
tw(9)
tw(10)
F
Min
1.3
600
0
Typ
Max
Units
µs
ns
Clock Pulse Duration
Clock Pulse Duration
Clock Frequency
Start Hold Time
Data Setup Time
Data Hold Time
Rising Time
-
-
-
-
-
-
-
-
-
-
-
-
400K
-
Hz
ns
th(5)
tsu(7)
th(6)
tr
600
100
-
-
ns
900
300
300
-
ns
-
ns
Falling Time
tf
-
ns
Stop Setup Time
tsu(8)
tsp
600
0
ns
Pulse Width of Spikes Suppressed Input Filter
50
ns
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Datasheet
9.3.2. I2S/PCM Interface Master Mode
Figure 25. Timing of I2S/PCM Master Mode
Table 113 Timing of I2S/PCM Master Mode
Parameter
Symbol
tLRD
Min
-
Typ
Max
30
30
-
Units
ns
LRCK Output to BCLK Delay
Data Output to BCLK Delay
Data Input Setup Time
Data Input Hold Time
-
-
-
-
tADD
-
ns
tDAS
10
10
ns
tDAH
-
ns
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Datasheet
9.3.3. I2S/PCM Interface Slave Mode
Figure 26. I2S/PCM Slave Mode Timing
Table 114. I2S/PCM Slave Mode Timing
Parameter
Symbol
tBCH
Min
20
20
30
-
Typ
Max
Units
ns
BCLK High Pulse Width
BCLK Low Pulse Width
LRCK Input Setup Time
Data Output to BCLK Delay
Data Input Setup Time
Data Input Hold Time
-
-
-
-
-
-
-
-
tBCL
ns
tLRS
-
ns
tADD
tDAS
30
-
ns
10
10
ns
tDAH
-
ns
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Datasheet
10. Application Circuits
C32
2.2uF
U1
MICBIAS1
R19 0/5%
32
2
MICBIAS1
IN1P
C41 2.2uF/6.3V
14
13
C7
CPP1
CPN1
MIC_IN
4.7uF/6.3V
12
11
2.2uF/6.3V
C42
CPP2
CPN2
INL
INR
3
4
IN2P
IN2N/JD2
HPOR
HPOL
17
20
HPO_R
HPO_L
MCLK_IC
DACDAT
ADCDAT
BCLK
LOUTL
LOUTR
25
22
21
24
23
9
10
MCLK
LOUTL/P
LOUTR/N
DACDAT1
ADCDAT1
BCLK1
LRCK
LRCK1
C10 2.2uF/6.3V
C12 2.2uF/6.3V
16
19
18
8
CPVPP
CPVEE
CPVREF
VREF2
C18 4.7uF/6.3V
I2C Interface
GPIO1/IRQ
SCL
SDA
28
1
26
27
SCL_Host
SDA_Host
GPIO1/IRQ1
JD1
SCL
SDA
R26
R27
10k/5%
DBVDD
10k/5%
MIC_VDD
R29
10k/5%
JD1_1
JD1_2
ALC5651
0/5%/0805
R5
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Datasheet
Line Output
Heaphone Output
R20
33/5%
33/5%
PH8
HPOL
1
2
3
4
5
JD1_1
RJ4
R21
R24 22/5%
LOUTL
C24 1u/6.3V
C26 1u/6.3V
PH7
HPOR
1
2
3
4
5
C66
C55
LOUTR
0.1uF/6.3V
R23
0.1uF/6.3V
R22
R25 22/5%
10K/5%
22/5%
22/5%
MIC Input
Line Input
MICBIAS1
R3
C25 2.2uF/6.3V
PH9
INL
INR
1
2
3
4
5
MIC1
2.2K/5%
C4 2.2uF/6.3V
JD1_2
C27 2.2uF/6.3V
MIC_IN
SE1
P
N
1
2
RJ5
20K/5%
I2S1 Interface
Power
C45
MICVDD
3.0V ~ 3.6V
NC/22pF/6.3V
CPVDD
AVDD
1.71V ~ 1.9V
DACREF
47/5%
1.71V ~ 1.9V
MCLK_IC
R9 0/5%
R28
MCLK
BCLK1
LRCK1
C33
C22
C43
C44
4.7uF/6.3V
NC/22pF/6.3V
C21
C19
C20
4.7uF/6.3V
C23
4.7uF/6.3V
BCLK
C34
0.1uF/6.3V
R7 0/5%
NC/22pF/6.3V
0.1uF/6.3V
4.7uF/6.3V
0.1uF/6.3V
LRCK
R16 0/5%
C46 NC/22pF/6.3V
DBVDD
DACDAT
R17 0/5%
DACDAT1
1.71V ~ 3.3V
NC/22pF/6.3V
C47
C29
C30
2.2uF/6.3V
ADCDAT
R18 0/5%
ADCDAT1
0.1uF/6.3V
By-Pass Capcity Near The Power Pins
Figure 27. Application Circuit
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Datasheet
11. Package Information
Plastic Quad Flat No-Lead Package 32 Leads 4x4mm2 Outline
Dimension in mm
Symbol
Dimension in inch
Nom
Min
0.80
0.00
—
Nom
0.85
Max
0.90
0.05
0.70
Min
0.031
0.000
—
Max
A
A1
A2
A3
b
D/E
D2/E2
e
0.033
0.001
0.026
0.035
0.002
0.028
0.02
0.65
0.20 REF
0.20
4.00 BSC
2.70
0.008 REF
0.080
0.157 BSC
0.106
0.016 BSC
0.016
0.15
2.55
0.25
2.85
0.006
0.100
0.010
0.112
0.40 BSC
0.40
L
0.30
0.50
0.482
0.012
0.011
0.020
0.019
L1
0.282
0.382
0.015
Notes
1. CONTROLLING DIMENSION MILLIMETER(mm).
2. REFERENCE DOCUMENTL JEDEC MO-220.
Figure 28. Package Dimension
I2S Audio CODEC for Mobile Devices
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Rev. 0.1
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Datasheet
12. Ordering Information
Table 115. Ordering Information
Part Number
ALC5616-CG
ALC5616-CGT
Package
Status
N/A
32-Pin QFN (4mm x 4mm) in ‘Green’ Package (Tray)
32-Pin QFN (4mm x 4mm) in ‘Green’ Package (Tape & Reel)
N/A
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
I2S Audio CODEC for Mobile Devices
95
Rev. 0.1
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