ALC5620 [REALTEK]
I2S AUDIO CODEC VOICE PCM INTERFACE;
| 型号： | ALC5620 |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | I2S AUDIO CODEC VOICE PCM INTERFACE PC |
| 文件： | 总84页 (文件大小：1573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC5620
I2S AUDIO CODEC + VOICE PCM
INTERFACE
DATASHEET
Rev. 1.0
15 August 2007
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
ALC5620
Datasheet
COPYRIGHT
©2007 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC5620 Audio Codec IC.
Though every effort has been made to ensure that this document is current and accurate, more
information may have become available subsequent to the production of this guide. In that event, please
contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
Release Date
Summary
1.0
2007/08/15
First release
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Datasheet
Table of Contents
1.
2.
3.
4.
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................2
SYSTEM APPLICATIONS...............................................................................................................................................2
FUNCTION BLOCK DIAGRAM.....................................................................................................................................3
4.1.
4.2.
FUNCTION BLOCK ........................................................................................................................................................3
AUDIO MIXER PATH.....................................................................................................................................................4
5.
6.
PIN ASSIGNMENTS .........................................................................................................................................................5
5.1.
GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................5
PIN DESCRIPTIONS.........................................................................................................................................................6
6.1.
DIGITAL I/O PINS.........................................................................................................................................................6
ANALOG I/O PINS ........................................................................................................................................................6
FILTER/REFERENCE......................................................................................................................................................7
POWER/GROUND..........................................................................................................................................................7
6.2.
6.3.
6.4.
7.
FUNCTIONAL DESCRIPTION.......................................................................................................................................8
7.1.
7.2.
POWER .........................................................................................................................................................................8
RESET ..........................................................................................................................................................................8
7.2.1. Power-On Reset (POR) ..........................................................................................................................................8
7.3.
CLOCKING....................................................................................................................................................................9
7.3.1. Phase-Locked Loop ................................................................................................................................................9
7.3.2. I2C and Stereo I2S.................................................................................................................................................10
7.3.3. Voice_I2S/PCM Interface .....................................................................................................................................11
7.3.4. Voice ADC............................................................................................................................................................11
7.4.
DIGITAL DATA INTERFACE ........................................................................................................................................12
7.4.1. Stereo and Voice I2S/PCM Interface ....................................................................................................................12
7.5.
AUDIO DATA PATH ....................................................................................................................................................15
7.5.1. Stereo ADC and Voice ADC.................................................................................................................................15
7.5.2. Stereo DAC...........................................................................................................................................................15
7.5.3. Voice to Stereo Digital Path.................................................................................................................................15
7.5.4. Voice DAC............................................................................................................................................................15
7.6.
MIXERS......................................................................................................................................................................16
7.6.1. Headphone Mixer.................................................................................................................................................16
7.6.2. MONO Mixer........................................................................................................................................................16
7.6.3. Speaker Mixer.......................................................................................................................................................17
7.6.4. ADC Record Mixer...............................................................................................................................................17
7.7.
ANALOG AUDIO INPUT PATH .....................................................................................................................................18
7.7.1. Line Input .............................................................................................................................................................18
7.7.2. Phone Input ..........................................................................................................................................................18
7.7.3. Microphone Input.................................................................................................................................................18
7.8.
ANALOG AUDIO OUTPUT DATA PATH .......................................................................................................................19
7.8.1. Speaker Output.....................................................................................................................................................19
7.8.2. Headphone Output................................................................................................................................................20
7.8.3. MONO Output......................................................................................................................................................20
7.9.
7.10.
7.10.1.
AVC CONTROL..........................................................................................................................................................21
HARDWARE SOUND EFFECTS .....................................................................................................................................22
Equalizer Block................................................................................................................................................22
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7.10.2.
7.11.
7.11.1.
7.11.2.
7.12.
7.13.
7.14.
Pseudo Stereo and Spatial 3D Sound ..............................................................................................................22
I2C CONTROL INTERFACE ..........................................................................................................................................23
Addressing Setting ...........................................................................................................................................23
Complete Data Transfer ..................................................................................................................................23
ODD-ADDRESSED REGISTER ACCESS.........................................................................................................................24
POWER MANAGEMENT...............................................................................................................................................24
GPIO AND INTERRUPT ...............................................................................................................................................25
8.
MIXER REGISTERS LIST.............................................................................................................................................26
8.1.
REG-00H: RESET ........................................................................................................................................................26
REG-02H: SPEAKER OUTPUT VOLUME.......................................................................................................................26
REG-04H: HEADPHONE OUTPUT VOLUME .................................................................................................................27
REG-08H: PHONE INPUT/MONO OUTPUT VOLUME...................................................................................................27
REG-0AH: LINE_IN VOLUME ...................................................................................................................................28
REG-0CH: STEREO DAC VOLUME ..........................................................................................................................28
REG-0EH: MIC VOLUME ...........................................................................................................................................29
REG-10H: MIC ROUTING CONTROL...........................................................................................................................29
REG-12H: ADC RECORD GAIN ..................................................................................................................................30
REG-14H: ADC RECORD MIXER CONTROL................................................................................................................31
REG-18H: VOICE DAC OUTPUT VOLUME..................................................................................................................31
REG-1CH: OUTPUT MIXER CONTROL ........................................................................................................................32
REG-22H: MICROPHONE CONTROL ............................................................................................................................33
REG-26H: POWER DOWN CONTROL/STATUS..............................................................................................................33
REG-34H: MAIN SERIAL DATA PORT CONTROL (STEREO I2S) ...................................................................................35
REG-36H: EXTEND SERIAL DATA PORT CONTROL (VODAC_I2S/PCM)...................................................................36
REG-3AH: POWER MANAGEMENT ADDITION 1..........................................................................................................37
REG-3CH: POWER MANAGEMENT ADDITION 2..........................................................................................................38
REG-3EH: POWER MANAGEMENT ADDITION 3 ..........................................................................................................39
REG-40H: GENERAL PURPOSE CONTROL REGISTER 1 ................................................................................................40
REG-42H: GENERAL PURPOSE CONTROL REGISTER 2 ................................................................................................41
REG-44H: PLL CONTROL...........................................................................................................................................41
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
8.17.
8.18.
8.19.
8.20.
8.21.
8.22.
8.22.1.
AC-LINK PLL Clock Setting Table (Unit: MHz).............................................................................................42
REG-4CH: GPIO PIN CONFIGURATION.......................................................................................................................43
REG-4EH: GPIO PIN POLARITY .................................................................................................................................44
REG-50H: GPIO PIN STICKY......................................................................................................................................45
REG-52H: GPIO PIN WAKE-UP..................................................................................................................................46
REG-54H: GPIO PIN STATUS .....................................................................................................................................47
REG-56H: PIN SHARING .............................................................................................................................................48
REG-58H: OVER-TEMP/CURRENT STATUS .................................................................................................................49
REG-5CH: GPIO_OUTPUT PIN CONTROL...................................................................................................................50
REG-5EH: MISC CONTROL........................................................................................................................................50
REG-60H: STEREO DAC CLOCK CONTROL_1 ............................................................................................................52
REG-62H: STEREO DAC CLOCK CONTROL_2 ............................................................................................................53
REG-64H: VODAC_PCM CLOCK CONTROL_1..........................................................................................................54
REG-66H: VODAC_PCM CLOCK CONTROL_2..........................................................................................................55
REG-68H: PSEUDO STEREO AND SPATIAL EFFECT BLOCK CONTROL .........................................................................56
REG-6AH: INDEX ADDRESS .......................................................................................................................................57
REG-6CH: INDEX DATA .............................................................................................................................................57
REG-6EH: EQ STATUS ...............................................................................................................................................57
INDEX-00H: EQ BAND-0 COEFFICIENT (LP0: A1) ......................................................................................................58
INDEX-01H: EQ BAND-0 GAIN (LP0: HO)..................................................................................................................58
INDEX-02H: EQ BAND-1 COEFFICIENT (BP1: A1)......................................................................................................58
INDEX-03H: EQ BAND-1 COEFFICIENT (BP1: A2)......................................................................................................58
INDEX-04H: EQ BAND-1 GAIN (BP1: HO) .................................................................................................................58
INDEX-05H: EQ BAND-2 COEFFICIENT (BP2: A1)......................................................................................................59
8.23.
8.24.
8.25.
8.26.
8.27.
8.28.
8.29.
8.30.
8.31.
8.32.
8.33.
8.34.
8.35.
8.36.
8.37.
8.38.
8.39.
8.40.
8.41.
8.42.
8.43.
8.44.
8.45.
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8.46.
8.47.
8.48.
8.49.
8.50.
8.51.
8.52.
8.53.
8.54.
8.55.
8.56.
8.57.
8.58.
8.59.
8.60.
8.61.
8.62.
8.63.
8.64.
8.65.
8.66.
8.67.
INDEX-06H: EQ BAND-2 COEFFICIENT (BP2: A2)......................................................................................................59
INDEX-07H: EQ BAND-2 GAIN (BP2: HO) .................................................................................................................59
INDEX-08H: EQ BAND-3 COEFFICIENT (BP3: A1)......................................................................................................59
INDEX-09H: EQ BAND-3 COEFFICIENT (BP3: A2)......................................................................................................59
INDEX-0AH: EQ BAND-3 GAIN (BP3: HO).................................................................................................................60
INDEX-0BH: EQ BAND-4 COEFFICIENT (HPF: A1).....................................................................................................60
INDEX-0CH: EQ BAND-4 GAIN (HPF: HO) ................................................................................................................60
INDEX-10H: EQ CONTROL AND STATUS REGISTER ....................................................................................................61
INDEX-11H: EQ INPUT VOLUME CONTROL ................................................................................................................61
INDEX-12H: EQ OUTPUT VOLUME CONTROL.............................................................................................................62
INDEX-20H: AUTO VOLUME CONTROL REGISTER 0...................................................................................................62
INDEX-21H: AUTO VOLUME CONTROL REGISTER 1...................................................................................................63
INDEX-22H: AUTO VOLUME CONTROL REGISTER 2...................................................................................................63
INDEX-23H: AUTO VOLUME CONTROL REGISTER 3...................................................................................................63
INDEX-24H: AUTO VOLUME CONTROL REGISTER 4...................................................................................................63
INDEX-25H: AUTO VOLUME CONTROL REGISTER 5...................................................................................................64
INDEX-39H: DIGITAL INTERNAL REGISTER ................................................................................................................64
INDEX-44H: CLASS AB INTERNAL REGISTER.............................................................................................................64
INDEX-4AH: CLASS D TEMPERATURE SENSOR ..........................................................................................................65
INDEX-54H: AD_DA_MIXER_INTERNAL REGISTER ..................................................................................................65
REG-7CH: VENDOR ID 1 .........................................................................................................................................66
REG-7EH: VENDOR ID 2 .........................................................................................................................................66
9.
ELECTRICAL CHARACTERISTICS ..........................................................................................................................67
9.1.
DC CHARACTERISTICS...............................................................................................................................................67
9.1.1. Absolute Maximum Ratings..................................................................................................................................67
9.1.2. Recommended Operating Conditions...................................................................................................................67
9.1.3. Static Characteristics ...........................................................................................................................................68
9.2.
ANALOG PERFORMANCE CHARACTERISTICS..............................................................................................................68
10.
11.
12.
APPLICATION CIRCUITS .......................................................................................................................................71
MECHANICAL DIMENSIONS.................................................................................................................................72
APPENDIX A: STEREO I2S CLOCK TABLE.........................................................................................................73
MASTER/SLAVE MODE ..............................................................................................................................................73
APPENDIX B: VOICE PCM INTERFACE..............................................................................................................74
12.1.
13.
13.1.
13.2.
MASTER MODE: (VOICE_PORT_SEL=0)......................................................................................................................74
SLAVE MODE: (VOICE_PORT_SEL=1).........................................................................................................................75
14.
ORDERING INFORMATION...................................................................................................................................75
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Datasheet
List of Tables
TABLE 1. DIGITAL I/O PINS.........................................................................................................................................................6
TABLE 2. ANALOG I/O PINS ........................................................................................................................................................6
TABLE 3. FILTER/REFERENCE .....................................................................................................................................................7
TABLE 4. POWER/GROUND..........................................................................................................................................................7
TABLE 5. POWER SETTING FOR BEST PERFORMANCE..................................................................................................................8
TABLE 6. RESET OPERATION.......................................................................................................................................................8
TABLE 7. POWER-ON RESET VOLTAGE .......................................................................................................................................8
TABLE 8. CLOCK SETTING TABLE FOR 48K (UNIT: MHZ)...........................................................................................................9
TABLE 9. CLOCK SETTING TABLE FOR 44.1K (UNIT: MHZ)......................................................................................................10
TABLE 10. ADDRESSING SETTING...............................................................................................................................................23
TABLE 11. WRITE WORD PROTOCOL ........................................................................................................................................24
TABLE 12. READ WORD PROTOCOL..........................................................................................................................................24
TABLE 13. REG-00H: RESET .......................................................................................................................................................26
TABLE 14. REG-02H: SPEAKER OUTPUT VOLUME ......................................................................................................................26
TABLE 15. REG-04H: HEADPHONE OUTPUT VOLUME.................................................................................................................27
TABLE 16. REG-08H: PHONE INPUT / MONO OUTPUT VOLUME.................................................................................................27
TABLE 17. REG-0AH: LINE_IN VOLUME...................................................................................................................................28
TABLE 18. REG-0CH: STEREO DAC VOLUME..........................................................................................................................28
TABLE 19. REG-0EH: MIC VOLUME...........................................................................................................................................29
TABLE 20. REG-10H: MIC ROUTING CONTROL ..........................................................................................................................29
TABLE 21. REG-12H: ADC RECORD GAIN..................................................................................................................................30
TABLE 22. REG-14H: ADC RECORD MIXER CONTROL ...............................................................................................................31
TABLE 23. REG-18H: VOICE DAC OUTPUT VOLUME .................................................................................................................31
TABLE 24. REG-1CH: OUTPUT MIXER CONTROL........................................................................................................................32
TABLE 25. REG-22H: MICROPHONE CONTROL............................................................................................................................33
TABLE 26. REG-26H: POWER DOWN CONTROL/STATUS .............................................................................................................33
TABLE 27. TRUTH TABLE FOR POWER DOWN MODE: (PD= POWER DOWN)...............................................................................34
TABLE 28. REG-34H: MAIN SERIAL DATA PORT CONTROL (STEREO I2S)...................................................................................35
TABLE 29. REG-36H: EXTEND SERIAL DATA PORT CONTROL (VODAC_I2S/PCM)...................................................................36
TABLE 30. REG-3AH: POWER MANAGEMENT ADDITION 1 .........................................................................................................37
TABLE 31. REG-3CH: POWER MANAGEMENT ADDITION 2 .........................................................................................................38
TABLE 32. REG-3EH: POWER MANAGEMENT ADDITION 3..........................................................................................................39
TABLE 33. REG-40H: GENERAL PURPOSE CONTROL REGISTER 1 ...............................................................................................40
TABLE 34. REG-42H: GENERAL PURPOSE CONTROL REGISTER 2 ...............................................................................................41
TABLE 35. REG-44H: PLL CONTROL ..........................................................................................................................................41
TABLE 36. I2C+I2S CLOCK SETTING TABLE FOR 48K: (UNIT: MHZ) ..........................................................................................42
TABLE 37 I2C+I2S CLOCK SETTING TABLE FOR 44.1K: (UNIT: MHZ).......................................................................................42
TABLE 38. REG-4CH: GPIO PIN CONFIGURATION......................................................................................................................43
TABLE 39. REG-4EH: GPIO PIN POLARITY.................................................................................................................................44
TABLE 40. REG-50H: GPIO PIN STICKY .....................................................................................................................................45
TABLE 41. REG-52H: GPIO PIN WAKE-UP .................................................................................................................................46
TABLE 42. REG-54H: GPIO PIN STATUS.....................................................................................................................................47
TABLE 43. REG-56H: PIN SHARING.............................................................................................................................................48
TABLE 44. REG-58H: OVER-TEMP / CURRENT STATUS...............................................................................................................49
TABLE 45. REG-5CH: GPIO_OUTPUT PIN CONTROL..................................................................................................................50
TABLE 46. REG-5EH: MISC CONTROL .......................................................................................................................................50
TABLE 47. REG-60H: STEREO DAC CLOCK CONTROL_1............................................................................................................52
TABLE 48. REG-62H: STEREO DAC CLOCK CONTROL_2............................................................................................................53
TABLE 49. REG-64H: VODAC_PCM CLOCK CONTROL_1 .........................................................................................................54
TABLE 50. REG-66H: VODAC_PCM CLOCK CONTROL_2 .........................................................................................................55
TABLE 51. REG-68H: PSEUDO STEREO AND SPATIAL EFFECT BLOCK CONTROL.........................................................................56
TABLE 52. REG-6AH: INDEX ADDRESS.......................................................................................................................................57
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TABLE 53. REG-6CH: INDEX DATA.............................................................................................................................................57
TABLE 54. REG-6EH: EQ STATUS...............................................................................................................................................57
TABLE 55. INDEX-00H: EQ BAND-0 COEFFICIENT (LP0: A1)......................................................................................................58
TABLE 56. INDEX-01H: EQ BAND-0 GAIN (LP0: HO).................................................................................................................58
TABLE 57. INDEX-02H: EQ BAND-1 COEFFICIENT (BP1: A1) .....................................................................................................58
TABLE 58. INDEX-03H: EQ BAND-1 COEFFICIENT (BP1: A2) .....................................................................................................58
TABLE 59. INDEX-04H: EQ BAND-1 GAIN (BP1: HO).................................................................................................................58
TABLE 60. INDEX-05H: EQ BAND-2 COEFFICIENT (BP2: A1) .....................................................................................................59
TABLE 61. INDEX-06H: EQ BAND-2 COEFFICIENT (BP2: A2) .....................................................................................................59
TABLE 62. INDEX-07H: EQ BAND-2 GAIN (BP2: HO).................................................................................................................59
TABLE 63. INDEX-08H: EQ BAND-3 COEFFICIENT (BP3: A1) .....................................................................................................59
TABLE 64. INDEX-09H: EQ BAND-3 COEFFICIENT (BP3: A2) .....................................................................................................59
TABLE 65. INDEX-0AH: EQ BAND-3 GAIN (BP3: HO)................................................................................................................60
TABLE 66. INDEX-0BH: EQ BAND-4 COEFFICIENT (HPF: A1) ....................................................................................................60
TABLE 67. INDEX-0CH: EQ BAND-4 GAIN (HPF: HO)................................................................................................................60
TABLE 68. INDEX-10H: EQ CONTROL AND STATUS REGISTER ...................................................................................................61
TABLE 69. INDEX-11H: EQ INPUT VOLUME CONTROL ...............................................................................................................61
TABLE 70. INDEX-12H: EQ OUTPUT VOLUME CONTROL............................................................................................................62
TABLE 71. INDEX-20H: AUTO VOLUME CONTROL REGISTER 0 ..................................................................................................62
TABLE 72. INDEX-21H: AUTO VOLUME CONTROL REGISTER 1 ..................................................................................................63
TABLE 73. INDEX-22H: AUTO VOLUME CONTROL REGISTER 2 ..................................................................................................63
TABLE 74. INDEX-23H: AUTO VOLUME CONTROL REGISTER 3 ..................................................................................................63
TABLE 75. INDEX-24H: AUTO VOLUME CONTROL REGISTER 4 ..................................................................................................63
TABLE 76. INDEX-25H: AUTO VOLUME CONTROL REGISTER 5 ..................................................................................................64
TABLE 77. INDEX-39H: DIGITAL INTERNAL REGISTER................................................................................................................64
TABLE 78. INDEX-44H: CLASS AB INTERNAL REGISTER ............................................................................................................64
TABLE 79. INDEX-4AH: CLASS D TEMPERATURE SENSOR..........................................................................................................65
TABLE 80. INDEX-54H: AD_DA_MIXER_INTERNAL REGISTER .................................................................................................65
TABLE 81. REG-7CH: VENDOR ID 1.........................................................................................................................................66
TABLE 82. REG-7EH: VENDOR ID 2.........................................................................................................................................66
TABLE 83. ABSOLUTE MAXIMUM RATINGS................................................................................................................................67
TABLE 84. RECOMMENDED OPERATING CONDITIONS.................................................................................................................67
TABLE 85. STATIC CHARACTERISTICS ........................................................................................................................................68
TABLE 86. ANALOG PERFORMANCE CHARACTERISTICS .............................................................................................................68
TABLE 87. ORDERING INFORMATION..........................................................................................................................................76
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List of Figures
FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................3
FIGURE 2. AUDIO MIXER PATH ...................................................................................................................................................4
FIGURE 3. PIN ASSIGNMENTS ......................................................................................................................................................5
FIGURE 4. PCM MONO DATA MODE A FORMAT (BCLK_POLARITY=0)...................................................................................12
FIGURE 5. PCM MONO DATA MODE A FORMAT (BCLK_POLARITY=1)...................................................................................12
FIGURE 6. PCM MONO DATA MODE B FORMAT (BCLK_POLARITY=0) ...................................................................................13
FIGURE 7. PCM STEREO DATA MODE A FORMAT (BCLK_POLARITY=0)...................................................................................13
FIGURE 8. PCM STEREO DATA MODE B FORMAT (BCLK_POLARITY=0)...................................................................................13
FIGURE 9. I2S DATA FORMAT (BCLK_POLARITY=0)..................................................................................................................14
FIGURE 10. LEFT-JUSTIFIED DATA FORMAT (BCLK_POLARITY=0) .............................................................................................14
FIGURE 11. RIGHT-JUSTIFIED DATA FORMAT (BCLK_POLARITY=0) ...........................................................................................14
FIGURE 12. AUTO VOLUME CONTROL BLOCK DIAGRAM............................................................................................................21
FIGURE 13. DATA TRANSFER OVER I2C CONTROL INTERFACE ...................................................................................................23
FIGURE 14. GPIO IMPLEMENTATION ..........................................................................................................................................25
FIGURE 15. POWER CONTROL TO MIC INPUT .............................................................................................................................40
FIGURE 16. GPIO AND IRQ LOGIC .............................................................................................................................................48
FIGURE 17. JACK-INSERT-DETECT PULL UP RESISTER IMPLEMENTED VIA AN EXTERNAL CIRCUIT............................................51
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1. General Description
The ALC5620 is a highly-integrated dual I2S/PCM interface audio codec with multiple input/output ports
and is designed for mobile computing and communications. It provides a dual-channel Hi-Fi codec for
playback, and dual-channel ADC for recording via an I2S interface. In addition, an Independent Voice
DAC is provided with PCM interface for Bluetooth applications.
Both Stereo audio and voice functions are supported via the I2S/PCM configurable interface. To reduce
component count, the device can connect directly to:
• MONO or stereo differential analog inputs
• Stereo headphone
• Single-end or BTL MONO output
• MONO or Stereo Bridge-Tied Load (BTL) speaker
Multiple analog input and output pins are provided for seamless integration with analog connected
wireless communication devices. Differential input/output connections efficiently reduce noise
interference, providing better sound quality. Class-AB or Class-D amplifiers are easily swapped via
simple register configuration, and the 1 Watt speaker removes the need for an additional amplifier, further
cutting both cost and required board area. Additionally, a flexible hardware 5-band equalizer with
configurable gain, bandwidth, and center frequency, and enriches the sound experience.
The ALC5620 operates at supply voltages from 1.8 to 5 Volts. To extend battery life, each section of the
device can be powered down individually under software control. Leakage current in maximum power
saving state is less than 10µA.
The ALC5620 is available in a 7x7mm ‘Green’ QFN package, making it ideal for use in handheld
portable systems.
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2. Features
High Performance I2S Codec
16-bit stereo DAC SNR 90dB, THD+N -85dB
16-bit stereo ADC SNR 85dB, THD+N -80dB
Supports I2S/PCM input and output interface
One analog stereo input (LINE-IN)
One analog MONO single-ended or differential input (PHONE and PHONEN input)
Stereo, single-ended MONO, or differential analog microphone inputs, with boost pre-amplifiers
(+20/+30/+40dB)
BTL (Bridge-Tied Load) Max. output with on-chip 1W speaker driver (SPKVDD=5V, 8Ω load)
Stereo headphone output with on-chip 45mW headphone driver (HPVDD=3.3V, 16Ω load)
25mW SE or 75mW BTL MONO output support (AVDD=3.3V, 32Ω load)
Microphone switch detection
Integrated 16-bit I2S/PCM interface voice DAC for blue-tooth and other external devices
Power management and enhanced power saving
Supports digital 5 band equalizer (EQ)
Supports digital spatial sound and pseudo stereo effect
Supports pop noise suppression
Internal PLL can receive wide range of clock input (Digital IO power > 2.3V)
Digital power supplies from 1.8V to 3.6V, speaker amplifier power supplies from 2.3V to 5V
Analog power and headphone power supplies from 2.3V to 3.6V
7 x 7mm 48-pin QFN package
3. System Applications
Tablet PC system/Ultra-Mobile PC (UMPC)
GPS/Personal Navigation Device (PND) or Multi-Media phone
PDA Phone/Smartphone
Personal Media Player (PMP)
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4. Function Block Diagram
4.1. Function Block
Figure 1. Block Diagram
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4.2. Audio Mixer Path
Figure 2. Audio Mixer Path
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5. Pin Assignments
Figure 3. Pin Assignments
5.1. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3. The version number is shown
in the location marked ‘V’.
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6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Characteristic Definition
Name
Type Pin Description
MCLK
EXTCLK
SDAC
I
2
3
5
6
Master Clock Input
Schmitt trigger
Schmitt trigger
Schmitt trigger
I/O
I
External Reference Clock Input/Output
Stereo I2S/PCM DAC Data Input
Stereo I2S/PCM Bit Clock
BLCK
I/O
Master: VOL=0.1*DVDD, VOH=0.9*DVDD
Slave: Schmitt trigger
SADC
O
8
Stereo I2S/PCM ADC Data Output
VOL =0.1*DVDD, VOH =0.9*DVDD
Master: VOL=0.1*DVDD, VOH=0.9*DVDD
Slave: Schmitt trigger
SDALRCK I/O
10 Stereo I2S/PCM DAC Synchronous Signal
RESET#
I
11 H/W Reset Input (Low Active)
Schmitt trigger
SADLRCK I/O
12 Stereo I2S/PCM ADC Synchronous Signal
Master: VOL=0.1*DVDD, VOH=0.9*DVDD
Slave: Schmitt trigger
SCL
SDA
A1
I
13 I2C Clock
Schmitt trigger
I/O
I
14 I2C Data
Schmitt trigger
15 I2C Address A1
A1: Input
GPIO1 /
VBCLK
I/O
44 General Purpose Input and Output 1 /
Voice I2S/PCM Bit Clock
GPIO: Input / Output
VBCLK: Slave input / Master output
GPIO: Input / Output
GPIO2 /
IRQOUT
I/O
I/O
I/O
I/O
45 General Purpose Input and Output 2 /
Interrupt Output
IRQOUT: Output
GPIO3 /
VSLRCK
46 General Purpose Input and Output 3 /
Voice I2S/PCM Synchronous Signal
47 General Purpose Input and Output 4 /
Voice I2S/PCM DAC Data Input
48 General Purpose Input and Output 5 /
Voice I2S/PCM ADC Data Output
GPIO: Input / Output
VSLRCK: Slave input / Master output
GPIO: Input / Output
SDAC: Schmitt trigger input
GPIO: Input / Output
SADC: Voice data output
Total: 16 Pins
GPIO4 /
VSDAC
GPIO5 /
VSADC
6.2. Analog I/O Pins
Table 2. Analog I/O Pins
Name
Type Pin Description
Characteristic Definition
Analog Input (1Vrms)
Analog Input (1Vrms)
Analog Input (1Vrms)
Analog Input (1Vrms)
Analog Input (1Vrms)
Analog Input (1Vrms)
Analog Input (1Vrms)
PHONEP
PHONEN
MIC1P
I
I
I
I
I
I
I
19 Phone Positive Input
20 Phone Negative Input
21 First Mic Positive Input
22 First Mic Negative Input
29 Second Mic Positive Input
30 Second Mic Negative Input
23 Line Input Left Channel
MIC1N
MIC2P
MIC2N
LINE_IN_L
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Datasheet
Name
Type Pin Description
Characteristic Definition
Analog Input (1Vrms)
Analog Output (1Vrms)
Analog Output (1Vrms)
Analog Output (1Vrms)
Analog Output (1Vrms)
LINE_IN_R
MONO_OUT
MONO_OUTN
HP_OUT_L
HP_OUT_R
SPK_OUT_L
SPK_OUT_LN
SPK_OUT_R
SPK_OUT_RN
I
24 Line Input Right Channel
O
O
O
O
O
O
O
O
31 Positive MONO Output
32 Negative MONO Output
39 Headphone Output Left Channel
41 Headphone Output Right Channel
35 Speaker Output Left Channel
33 Negative Speaker Output Left Channel
36 Speaker Output Right Channel
37 Negative Speaker Output Right Channel
Analog Output (1.3Vrms, SPKVDD = 4.2V)
Analog Output (1.3Vrms, SPKVDD = 4.2V)
Analog Output (1.3Vrms, SPKVDD = 4.2V)
Analog Output (1.3Vrms, SPKVDD = 4.2V)
Total: 16 Pins
6.3. Filter/Reference
Table 3. Filter/Reference
Name
Type
O
Pin
16
Description
Characteristic Definition
MICBIAS2
MICBIAS
VREF
MIC BIAS Voltage Output 2
MIC BIAS Voltage Output
Internal Reference Voltage
Programmable Analog DC Output with 3mA drive
Programmable Analog DC Output with 3mA drive
1µf capacitor to analog ground
O
28
O
27
Total: 2 Pins
6.4. Power/Ground
Table 4. Power/Ground
Name
Type Pin Description
Characteristic Definition
DVDD1
DGND1
DGND2
DVDD2
AVDD2
AGND3
AVDD1
AGND1
SPKGND
SPKVDD
P
P
P
P
P
P
P
P
P
P
1
4
7
9
Digital VDD
Digital GND
Digital GND
Digital VDD
1.8V~3.6V (IO)
-
-
1.8V~3.6V (Core)
17 Analog VDD
2.3V~3.6V
18 Analog GND
-
25 Analog VDD
2.3V~3.6V
26 Analog GND
-
34 Analog GND for Speaker Amps
38 Analog VDD for Speaker Amps
-
3.0V~5V (For Ohm loading)
2.3V~5V (For kOhm loading)
HPGND
AGND2
HPVDD
LFGND
P
P
P
P
40 Analog GND for Headphone Amps
42 Analog GND
-
-
43 Analog VDD for Headphone Amps
49 Thermal Pad, Connect to SPKGND
2.3V~3.6V
-
Total: 14 Pins
Note: DVDD1 ≧ DVDD2, SPKVDD ≧ AVDD1, HPVDD ≧ AVDD1 = AVDD2 ≧ DVDD2
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Datasheet
7. Functional Description
7.1. Power
The ALC5620 has many power blocks. SPKVDD operates between 2.3V and 5V. HPVDD, AVDD2, and
AVDD1 operate between 2.3V and 3.6V. DVDD1 and DVDD2 operate between 1.8V and 3.6V.
The power supply limit condition are DVDD1≥DVDD2, SPKVDD≥AVDD1=AVDD2, HPVDD≥
AVDD1= AVDD2≥DVDD2.
Table 5. Power Setting for Best Performance
Power
DVDD1
DVDD2
HPVDD
AVDD2
AVDD1
SPKVDD
Setting
3.3V
1.8V
3.3V
3.3V
3.3V
4.2V
7.2. Reset
There are 3 types of reset operation: Power-On Reset (POR), Cold, and Register reset.
Table 6. Reset Operation
Reset Type
Trigger Condition
CODEC Response
POR
Monitor digital power supply voltage reach Reset all hardware logic and all registers to default
VPOR
values.
Cold Reset
Assert RESET# for a specified period
Reset all hardware logic and all registers to default
values except some specify control registers and logic.
Register Reset
Write Reg-00h
Reset all registers to default values except some specify
control registers and logic.
7.2.1.
Power-On Reset (POR)
When powered on, DVDD2 passes through the VPOR band of the ALC5620 (VPOR_ON ~VPOR_OFF). A
Power-On Reset (POR) will generate an internal reset signal (POR reset ‘LOW’) to reset the whole chip.
Table 7. Power-On Reset Voltage
Symbol
VPOR_ON
VPOR_OFF
Min
1.0
-
Typical
Max
1.6
-
Unit
V
-
1.3
V
Note: VPOR_OFF must be below VPOR_ON
.
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7.3. Clocking
The Stereo_SYSCLK can be selected from MCLK or PLL. This means MCLK is always provided
externally, and the driver should arrange the clock of each block and setup each divider.
The voice codec clock can be selected from MCLK (Master mode), PLL (Master mode), EXTCLK (Slave
mode) or VBCLK (Slave mode). The driver should arrange the clock of each block and setup each
divider.
In master mode of voice I2S/PCM, EXTCLK can be output by setting Extclk_dir=1. The output frequency
will be determined by MCLK and the setting of Extclk_out_sel.
7.3.1.
Phase-Locked Loop
A Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz to 40MHz. The
source of the PLL can be set to MCLK or BLCK by setting pll_sour_sel.
The driver can set up the PLL to output a frequency close to the SYSCLK.
The PLL transmit formula is:
FOUT = (MCLK * (N+2)) / ((M+2) * (K+2)) {Typical K=2}
Table 8. Clock Setting Table for 48K (Unit: MHz)
MCLK
13
N
66
78
94
70
80
81
78
80
78
M
7
FVCO
98.222
98.304
98.304
98.304
98.4
K
2
2
2
2
2
2
2
2
2
FOUT
24.555
24.576
24.576
24.576
24.6
3.6864
2.048
4.096
12
1
0
1
8
15.36
16
11
11
14
14
98.068
98.462
98.4
24.517
24.615
24.6
19.2
19.68
98.4
24.6
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Table 9. Clock Setting Table for 44.1K (Unit: MHz)
MCLK
13
N
68
72
86
64
66
63
66
64
67
M
8
FVCO
91
K
2
2
2
2
2
2
2
2
2
FOUT
22.75
3.6864
2.048
4.096
12
1
90.931
90.112
90.112
90.667
90.764
90.667
90.514
90.528
22.733
22.528
22.528
22.667
22.691
22.667
22.629
22.632
0
1
7
15.36
16
9
10
12
13
19.2
19.68
After a Cold Reset, PLL related Registers are reset to default values, however, they are not reset to
default values after a soft-reset (write Reg00). Firmware should not power down the PLL when the PLL
output is used as Stereo_SYSCLK.
7.3.2.
I2C and Stereo I2S
The ALC5620 supports I2C for the digital control interface, and I2S/PCM for the digital data interface.
The I2S/PCM audio digital interface is used to input data to a stereo DAC or output data from a stereo
ADC. The I2S/PCM Audio Digital Interface can be configured to Master mode or Slave mode. For the
Stereo I2S Interface, the source clock is always input from MCLK.
Master Mode
In master mode BCLK/SDALRCK/SADLRCK are configured as output. When PLL is disabled and
sel_sysclk=0, MCLK is used as Stereo SYSCLK. When PLL is enabled, MCLK is suggested to provide
13MHz, and PLL should be configured to support 44.1K and 48K base sampling rates. The driver should
set each divider (Reg60 & Reg62) to arrange the clock distribution. Refer to section 12 Appendix A:
Stereo I2S Clock Table, page 73, for details.
Note: The ALC5620 supports different sample rates between SDALRCK and SADLRCK in Master mode.
Slave Mode
In slave mode BCLK/SDALRCK are configured as input. MCLK should provide the BCLK synchronized
clock externally. Stereo_SYSCLK and the driver should set each divider to arrange the clock distribution.
Refer to section 12 Appendix A: Stereo I2S Clock Table, page 73, for details.
Note: In Slave mode, the ALC5620 does NOT support different sample rates between SDALRCK and
SADLRCK. Only SDALRCK is used in slave mode.
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7.3.3.
Voice_I2S/PCM Interface
The ALC5620 supports an independent digital interface for Voice Audio. The voice audio digital
interface is used to input digital data to the voice DAC, or output digital data from the voice ADC. The
Voice Audio Digital Interface can be configured to Master mode or Slave mode. Whether in Master mode
or Slave mode, the sample rate of the Voice ADC and Voice DAC is set via Reg64 and Reg66.
Master Mode
In Master mode the main clock of the Voice_I2S/PCM interface can be input selected from MCLK (with
or without a PLL) or EXTCLK. VBCLK and VSLRCK will be configured as output. The driver should
set each divider (Reg64 & Reg66) to arrange the clock distribution. See section 13 Appendix B: Voice
PCM Interface, page 74 for details.
Slave Mode
In Slave mode the main clock of the Voice_I2S/PCM can be input from MCLK or EXTCLK. VBCLK is
synchronized externally. VBCLK and VSLRCK should be configured as input. The driver should set each
divider (Reg64 and Reg66) to arrange the clock distribution (see section 13.2 Slave Mode:
(voice_port_sel=1), page 75 for more information.
If VBCLK provides 64Fs, 128Fs, or 256Fs externally, the ALC5620 can use VBCLK input as the main
clock of the Voice_I2S/PCM. See section 12 Appendix A: Stereo I2S Clock Table, page 73.
7.3.4.
Voice ADC
The ALC5620 supports Voice ADC for transmitting voice data to a Bluetooth device. The Voice ADC is
implemented by sharing from the Right Channel of the Stereo ADC (by setting voice_adc_enable).
When voice_adc_enable=0’b, the L/R channel stereo ADC sample rate is set according to the stereo
sample rate, and is output to the Stereo I2S/PCM interface.
When voice_adc_enable=1, the sample rate of the Left channel is set by the stereo sample rate (Reg60 &
Reg62). The sample rate of the Right channel is set by the voice sample rate (Reg64 & Reg66). The Left
channel ADC data is output to the Left frame and duplicated to the Right frame of the I2S/PCM interface.
The Right channel of the Stereo ADC data is then used as a Voice ADC and is output to voice_I2S/PCM.
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7.4. Digital Data Interface
7.4.1.
Stereo and Voice I2S/PCM Interface
The stereo and voice I2S/PCM interface can be configured as Master mode or Slave mode. Four audio
data formats are supported:
• PCM mode
• Left justified mode
• Right justified mode
• I2S mode
Figure 4. PCM MONO Data Mode A Format (bclk_polarity=0)
Figure 5. PCM MONO Data Mode A Format (bclk_polarity=1)
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Figure 6. PCM MONO Data Mode B Format (bclk_polarity=0)
Figure 7. PCM Stereo Data Mode A Format (bclk_polarity=0)
Figure 8. PCM Stereo Data Mode B Format (bclk_polarity=0)
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Figure 9. I2S Data Format (bclk_polarity=0)
Figure 10. Left-Justified Data Format (bclk_polarity=0)
Figure 11. Right-Justified Data Format (bclk_polarity=0)
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7.5. Audio Data Path
7.5.1.
Stereo ADC and Voice ADC
The Stereo ADC is used for recording stereo sound or, by setting voice_adc_enable, can be configured to
MONO PCM ADC (Left channel of Stereo ADC) + voice ADC (Right channel of Stereo ADC) when
using bluetooth and recording at the same time.
• When voice_adc_enabl=0, the sample rate of the Stereo ADC can be configured via setting Reg60 &
Reg62.
• When voice_adc_enabl=1, the sample rate of the voice ADC is set by Reg64 & Reg66, and the
sample rate of the MONO PCM ADC is set by Reg60 & Reg62.
The sample rate of the stereo ADC is independent of the Stereo DAC sample rate. In order to save power,
the left and right ADC can be powered down separately by setting Reg3C [6], [7]).
The volume control of the stereo ADC is set via Reg12[11:7][4:0].
7.5.2.
Stereo DAC
Stereo DAC can be configured to different sample rate by setting the stereo I2S clock divider (Reg60).
Reg0C[12:8][4:0] can be used to control the volume of DAC output
7.5.3.
Voice to Stereo Digital Path
The ALC5620 supports a voice to digital stereo path for voice command through Bluetooth by setting
Reg42[15]=1. The Voice data will be transferred from the voice I2S/PCM to the Main I2S/PCM directly.
This function is only supported when the Voice and Stereo I2S/PCM are in Master Mode. The driver
should set the same sample rate between the Voice DAC and the stereo ADC.
When a voice to stereo digital path is enabled, the signal from Voice_I2S/PCM is direct output to Left
frame and is duplicated to Right frame of the Voice I2S/PCM interface.
The Voice to Stereo Digital Path and Voice ADC functions can exist at the same time.
7.5.4.
Voice DAC
The Voice DAC is dedicated to playback of received voice signals from the voice_I2S/PCM interface.
Typically, it is used at an 8kHz sample rate.
In Voice I2S/PCM Master mode, the sample rate is set by the VoDAC clock Divider (Reg64). In addition,
Reg66[7:4][2:0] is used to set the over-sample rate clock divider of the Voice ADC/DAC filter to 128Fs.
Reg66[13] must be set according to the over-sample rate clock.
Performance at 128Fs is better than 64Fs, but with higher power consumption. The higher frequency will
cause better performance. For best performance, the frequency of the Voice DAC Sigma Delta clock must
be equal to, or higher than, the Voice DA filter over-sampling rate.
The volume control of the Voice DAC is set via Reg18[12:8].
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7.6. Mixers
The ALC5620 supports four mixers for all audio function requirements:
• Headphone mixer for 2 channels
• MONO mixer
• Speaker mixer
• ADC record mixer
7.6.1.
Headphone Mixer
The headphone mixer is used to drive stereo output, including HP_OUT_L/R, SPK_OUT_L/R
(SPK_OUT_LN/RN) and MONO_OUT (MONO_OUTN). The output of the Headphone mixer can be
input to the ADC record mixer.
The following signals can be mixed into the headphone mixer:
• LINE-IN_L/R (Controlled by Reg0A)
• PHONEP/N (Controlled by Reg08)
• MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
• Stereo DAC output (Controlled by Reg0C)
• Voice DAC output (Controlled by Reg18)
• ADC record mixer output (Controlled by Reg12 & Reg14).
Note: The headphone mixer can be powered down by setting Reg3C[5][4].
7.6.2.
MONO Mixer
The MONO mixer is used to drive MONO_OUT (MONO_OUTN) and SPK_OUT_L/R
(SPK_OUT_LN/RN). The output of the MONO mixer can be input to the ADC record mixer. The output
of the MONO mixer is two channels with the same signal.
The following signals can be mixed into the MONO mixer:
• LINE-IN_L/R (Controlled by Reg0A)
• MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
• Stereo DAC output (Controlled by Reg0C)
• Voice DAC output (Controlled by Reg18)
• ADC record mixer output (Controlled by Reg12 & Reg14).
Note: The MONO mixer can be powered down by setting Reg3C[2].
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7.6.3.
Speaker Mixer
The speaker mixer is the same as the MONO mixer and is used to drive MONO_OUT (MONO_OUTN)
and SPK_OUT_L/R (SPK_OUT_LN/RN). The output of the speaker mixer can be input to the ADC
record mixer. The output of the speaker mixer is two channels with the same signal.
The following signals can be mixed into the speaker mixer:
• LINE-IN_L/R (Controlled by Reg0A)
• PHONEP/N (Controlled by Reg08)
• MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
• Stereo DAC output (Controlled by Reg0C)
• Voice DAC output (Controlled by Reg18)
Note: The speaker mixer can be powered down by setting Reg3C[3].
7.6.4.
ADC Record Mixer
The ADC record mixer is used to mix analog signals as input to the Stereo ADC for recording. Output of
the ADC record mixer can be input to the headphone mixer, MONO mixer, and speaker mixer.
The following signals can be mixed into the ADC record mixer:
• LINE-IN_L/R (Controlled by Reg0A)
• PHONEP/N (Controlled by Reg08)
• MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
• Headphone mixer output
• MONO mixer output
• Speaker mixer output
Note: The ADC record mixer can be powered down by setting Reg3C[1][0].
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7.7. Analog Audio Input Path
The ALC5620 supports four Analog Audio Input paths:
• Line_IN_L/R
• PHONEP/N
• MIC1
• MIC2
7.7.1.
Line Input
Line_In_L and Line_In_R provide 2-channel stereo single-ended input that can be mixed into the MONO
mixer, Headphone mixer, Speaker mixer, or the ADC record mixer.
The Line_In_L/R volume and mute are controlled by Reg0A. Reg3E[7:6] can be used to power down the
Line_In volume control.
7.7.2.
Phone Input
PHONEP/N provides one-channel MONO differential or single-ended input configured by Reg08[13]
that can be mixed into the ADC record mixer, or any analog output mixer except for the MONO mixer.
PHONEP is main input when differential mode is disabled.
The PHONEP/N volume and mute are controlled by Reg08.
Reg3E[5:4] can be used to power down PHONEP/N volume control and mixer.
7.7.3.
Microphone Input
MIC1P/N and MIC2P/N provide two-channel stereo differential or single-ended input via Reg10[12], [4],
that can be mixed into the ADC record mixer, or any analog output mixer. MIC1P and MIC2P are main
inputs when differential mode is disabled.
The ALC5620 Microphone input boost provides 20/30/40dB boost, set by Reg22[11:10] (for MIC1), and
by Reg22[9:8] (for MIC2). The MIC1/2 volume and mute are controlled by Reg0E.
For detailed power management of MIC1/2, Reg3E[3][2] can be used to power down the MIC1/2 volume
control. Reg3E[1][0] can be used to power down MIC1/2 and mixer.
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7.8. Analog Audio Output Data Path
The ALC5620 supports three Analog Audio output paths:
• SPK_OUT_L/R
• HP_OUT_L/R
• MONO_OUT
7.8.1.
Speaker Output
SPK_OUT_L/R provides two-channel differential output.
The SPK_OUT_L source is set in Reg1C[15:14]. Sources are shown below:
• Vmid
• Headphone left mixer
• Speaker mixer
• MONO mixer
The SPK_OUT_R source is set in Reg1C[12:11]. Sources are shown below:
• Vmid
• Headphone right mixer
• Speaker mixer
• MONO mixer
The ALC5620 speaker supports Class AB and Class D type amplifiers (set in Reg1C[13]:spk_out_sel).
As the voltage of SPKVDD is usually higher than AVDD, the driver should set the Class AB Vmid ratio
in Reg40[5:3], and the Class D Vmid ratio in Reg40[7:6] in order to extend the output level.
In class AB mode, for L+R MONO speaker solutions, SPK_OUT_R can select a different signal source
(SPKR Volume output or SPKL Volume output by Reg1C[14]) but SPK_OUT_RN only outputs SPKR
Volume Negative Output.
The SPK_OUT_L/R volume and mute are controlled by Reg02.
Reg3E[13]: pow_spk_r and Reg3E[12]:pow_spk_rn can be used to power down SPK output.
Reg3C[14]: pow_clsab is used to power down Class AB output, and Index 46[15:12] is used to power
down each output channel of Class D.
SPK_OUT_L/R supports the zero-cross detect function (enabled at Reg02[6][14]: sp_l_dezero/
sp_r_dezero).
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7.8.2.
Headphone Output
HP_OUT_L/R provides two-channel single-ended output. The HP_OUT_L/R source is set in
Reg1C[9][8]. Sources are shown below:
• Vmid
• Headphone mixer
The HP_OUT_L/R volume and mute are controlled by Reg04.
Reg3E[11]: pow_hp_l_vol and Reg3E[10]: pow_hp_r_vol can be used to power down the volume of HP
output.
HP_OUT supports the zero-cross detect function (enabled at Reg04[14][6]:hp_l_dezero/ hp_r_dezero).
7.8.3.
MONO Output
MONO_OUT provide one-channel differential or single-ended output configured by Reg08[15]. The
MONO_OUT source is set in Reg1C[7:6]. Sources are shown below:
• Vmid
• Headphone mixer (L+R)
• Speaker mixer
• MONO mixer
The MONO_OUT volume and mute are controlled by Reg08.
Reg3E[14]: pow_MONO_out_vol can be used to power down the volume of MONO_OUT.
MONO_OUT supports the zero-cross detect function (enabled at Reg08[6]:MONO_dezero).
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Datasheet
7.9. AVC Control
The Automatic Volume Control (AVC) function dynamically adjusts the input signal quantized by the
ADC to an expected sound level by setting THmax and THmin.
When the average level of input signal is higher than THmax, the AVC will decrease the selected analog
gain to attenuate the quantized Pulse Code Modulation (PCM) signal to a lower amplitude than THmax.
When the average level of input signal is lower than THmin, the AVC will increase the selected analog
gain to amplify the input signal. The quantized Pulse Code Modulation (PCM) signal is then set higher
than THmin. The quantized PCM has an average level between THmin and THmax.
The AVC reference source channel and target channel can be individually set by Index20[0] and
Reg5E[13:12].
The AVC architecture is shown in Figure 12 below:
Figure 12. Auto Volume Control Block Diagram
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7.10. Hardware Sound Effects
The Sound Effect block is composed of Pseudo Stereo, Spatial 3D, and Equalizer blocks. The Pseudo
Stereo block is used to convert a MONO source into virtualized stereo output. The Spatial 3D block is a
surround sound generator with adjustable amplitude (Gain) and surround depth (Ratio). The Equalizer
block can be used to compensate for speaker response, or to make environment sound effects, e.g., ‘Pub’,
‘Live’ , ‘Rock’,… etc..
7.10.1.
Equalizer Block
The Equalizer block cascades 5 bands of equalizer to compensate for speaker response and to emulate
environment sound. One high-pass filter cascaded in the front end is used to drop low frequency tone,
which has a larger amplitude and may damage a mini speaker.
The high-pass filter can also be used to adjust Treble strength with gain control. A low-pass filter with
gain control can adjust the Bass strength. Three bands of bi-quad bandpass filters are used to emulate
environment sounds.
To avoid PCM sample saturation, the digital volume control has up to 18dB of attenuation before the
equalizer. A 0~+18dB digital gain after the equalizer is used to correct PCM output to a suitable level.
7.10.2.
Pseudo Stereo and Spatial 3D Sound
There are two spatial effects in post-processing; the Pseudo-Stereo Effect + Spatial Effect, and the Stereo
Expansion Effect. The Pseudo-Stereo Effect + Spatial Effect converts a MONO signal to a stereo signal
by changing the phase and amplitude of the original signal followed by enhancing the spatial effect. The
Stereo Expansion Effect enhances the spatial effect when the input signal is Stereo.
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7.11. I2C Control Interface
I2C is a 2-wires half-duplex serial communication interface, supporting only slave mode. The host must
support MCLK during register access.
7.11.1.
Addressing Setting
Table 10. Addressing Setting
(MSB)
BIT
(LSB)
R/W
0
0
1
1
0
0
A1
Note: For A1: determined by external connect to VCC or GND
7.11.2.
Complete Data Transfer
Data Transfer over I2C Control Interface
Figure 13. Data Transfer Over I2C Control Interface
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Write WORD Protocol
Read WORD Protocol
Table 11. Write WORD Protocol
Table 12. Read WORD Protocol
1
7
1
1
8
1
7
1
8
1
8
1
1
S
Device Address Wr
A
Register Address
A
S
Device Address Rd
A
Data Byte High
A
Data Byte Low
NA
P
S: Start Condition
Slave Address: 7-bit Device Address
Wr: 0 for Write Command
A: 0 for ACK, 1 for NACK
Data Byte: 16-bit Mixer data
ꢀ: Master-to-Slave
Rd: 1 for Read Command
ꢀ: Slave-to-Master
Command Code: 8-bit Register Address
7.12. Odd-Addressed Register Access
The ALC5620 will return ‘0000h’ when odd-addressed and unimplemented registers are read.
7.13. Power Management
The ALC5620 supports a grouped power down control register (Reg26). More detailed Power
Management control is supported in Reg 3A, 3C, and 3E. Each particular block will only be active when
both Reg26 and Reg3A/3C/3E are set to ‘Enable’.
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7.14. GPIO and Interrupt
The ALC5620 supports up to five GPIOs. Each GPIO can be configured as Input/Output by Reg4C.
When GPIOs are configured as Input, the status will be indicated in Reg54. When GPIOs are configured
as Output, Reg5C is used to drive GPIOs to High (1b) or Low (0b). The status can be read in Reg54.
Interrupt request (IRQ) can be configured as:
• Sticky by setting Reg50
• Changed polarity by setting Reg4E
• Wake-up by setting Reg52
The driver can write each bit of Reg54=1 to clear each IRQ status flag.
When VoPCM_En (Reg36[15])=1, GPIOs 1, 3, 4, and 5 will be dedicated as VoDAC_I2S/PCM interface,
regardless of GPIO Pin Configuration (Reg4C[5:3,1]). These pins cannot be used as GPIOs in this case.
GPIO pin2 can be configured and pin-shared with IRQ_Output by setting Reg56.
Figure 14. GPIO Implementation
There are some internal events (over-temperature, MICBIAS short detect) where GPIOs can be an
interrupt source. GPIO Internal event application is located in Reg4C, Reg4E, Reg50, Reg52, and Reg54.
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8. Mixer Registers List
Accessing odd numbered registers, or reading unimplemented registers, will return a 0.
8.1. Reg-00h: Reset
Default: 59B4h
Table 13. Reg-00h: Reset
Name
Bits
Read/Write
Reset State
0’h
Description
Reserved
15
R
R
R
R
R
R
R
R
R
R
R
R
Reserved. Read as 0
SE[4:0]=10110b
REG-00_b14_b10
REG-00_b9
REG-00_b8
REG-00_b7
REG-00_b6
REG-00_b5
REG-00_b4
Reserved
14:10
16’h
0’h
9
8
7
6
5
4
3
2
1
0
No support for 20-bit ADC
Supports 16-bit ADC
Supports 16-bit DAC
No support for 18-bit DAC
Support for Loudness
Headphone output support
Reserved
1’h
1’h
0’h
1’h
1’h
0’h
REG-00_b2
Reserved
1’h
Supports EQ Control
Reserved. Read as 0
0’h
REG-00_b0
0’h
Dedicated MIC PCM input is not supported.
Note: Writes to this register will reset all registers to their default values except PLL related Register. The written data
will be ignored
8.2. Reg-02h: Speaker Output Volume
Default: 8080h
Table 14. Reg-02h: Speaker Output Volume
Name
Bits
Read/Write
Reset State Description
sp_l_mute
15
R/W
1’h
0’h
Mute Left Control
0: On 1: Mute Left Channel (-∞dB)
Left Zero-Cross Detector Control
0: Disable 1: Enable
sp_l_dezero
14
R/W
Reserved
sp_l_vol
sp_r_mute
13
12:8
7
R
0’h
0’h
1’h
Reserved. Read as 0
R/W
R/W
Speaker Output Left Volume (SPKL[4..0]) in 1.5dB Steps
Mute Right Control
0: On
Right Zero-Cross Detector Control
0: Disable 1: Enable
1: Mute Right Channel (-∞dB)
sp_r_dezero
6
R/W
0’h
Reserved
sp_r_vol
5
R
0’h
0’h
Reserved. Read as 0
4:0
R/W
Speaker Output Right Volume (SPKR[4..0]) in 1.5dB Steps
1Fh: 46.5dB attenuation
Note: For SPKR/SPKL, 00h: 0dB attenuation
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8.3. Reg-04h: Headphone Output Volume
Default: 8080h
Table 15. Reg-04h: Headphone Output Volume
Name
Bits
Read/Write
Reset State Description
hp_l_mute
15
R/W
1’h
0’h
Mute Left Control
0: On 1: Mute Left Channel (-∞dB)
Left Zero-Cross Detector Control
0: Disable 1: Enable
Reserved. Read as 0
hp_l_dezero
14
R/W
Reserved
hp_l_vol
hp_r_mute
13
12:8
7
R
0’h
0’h
1’h
R/W
R/W
Headphone Output Left Volume (HPL[4..0]) in 1.5dB Steps
Mute Right Control
0: On
Right Zero-Cross Detector Control
0: Disable 1: Enable
1: Mute Right Channel (-∞dB)
hp_r_dezero
6
R/W
0’h
Reserved
hp_r_vol
5
R
0’h
0’h
Reserved. Read as 0
4:0
R/W
Headphone Output Right Volume (HPR[4..0]) in 1.5dB Steps
1Fh: 46.5dB attenuation
Note: For HPR/HPL, 00h: 0dB attenuation
8.4. Reg-08h: Phone Input/MONO Output Volume
Default: C880h
Table 16. Reg-08h: Phone Input / MONO Output Volume
Name
Bits Read/Write
Reset State Description
phone2hp_mute
15
14
13
R/W
R/W
R/W
1’h
1’h
0’h
Mute Phone Input to Headphone Mixer Control
0: On 1: Mute (-∞dB)
Mute Phone Input to Speaker Mixer Control
0: On 1: Mute (-∞dB)
Phone Differential Input Control
0: Disable 1: Enable
phone2spk_mute
phone_diff_ctrl
phone_vol
12:8
7
R/W
R/W
8’h
1’h
Phone Input Volume (PV[4:0]) in 1.5dB Steps (not to ADC)
Mute MONO Output Control
MONO_mute
0: On
Zero-Cross Detector Control
0: Disable 1: Enable
1: Mute (-∞dB)
MONO_dezero
MONO_diff_ctrl
MONO_vol
6
5
R/W
R/W
R/W
0’h
0’h
0’h
MONO Output Differential Control
0: Disable (SE) 1: Enable (BTL)
4:0
MONO Output Master Volume (MOV[4..0]) in 1.5dB Steps
Note: For MOV, 00h: 0dB attenuation
For PV, 00h: +12dB gain
1Fh: 46.5dB attenuation
08h: 0dB attenuation
1Fh: 34.5dB attenuation
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8.5. Reg-0Ah: LINE_IN Volume
Default: E808h
Table 17. Reg-0Ah: LINE_IN Volume
Name
Bits
Read/Write
Reset State Description
li2hp_mute
15
R/W
1’h
1’h
1’h
Mute Volume Output to Headphone Mixer Control
0: On 1: Mute
Mute Volume Output to Speaker Mixer Control
0: On 1: Mute
Mute Volume Output to MONO Mixer Control
0: On 1: Mute
li2spk_mute
14
13
R/W
R/W
li2MONO_mute
li_l_vol
Reserved
li_r_vol
12:8
7:5
R/W
R
08’h
0’h
LINE_IN Left Volume (NLV[4..0]) in 1.5dB Steps
Reserved
4:0
R/W
8’h
LINE_IN Right Volume (NRV[4..0]) in 1.5dB Steps
Note: For NRV/NLV, 00h: +12dB gain
08h: 0dB attenuation
1Fh: 34.5dB attenuation
8.6. Reg-0Ch: STEREO DAC Volume
Default: E808h
Table 18. Reg-0Ch: STEREO DAC Volume
Name
Bits
Read/Write
Reset State Description
dac2hp_mute
15
R/W
1’h
1’h
1’h
Mute Volume Output to Headphone Mixer Control
0: On
1: Mute (-∞dB)
Mute Volume Output to Speaker Mixer Control
0: On
dac2spk_mute
14
R/W
R/W
1: Mute (-∞dB)
Mute Volume Output to MONO Mixer Control
dac2MONO_mute 13
0: On
1: Mute (-∞dB)
dac_l_vol
Reserved
dac_r_vol
12:8
7:5
R/W
R
08’h
0’h
PCM Left DAC Volume (PLV[4..0]) in 1.5dB Steps
Reserved
4:0
R/W
8’h
PCM Right DAC Volume (PRV[4..0]) in 1.5dB Steps
Note: For PRV/PLV,: 00h: +12dB gain
08h: 0dB attenuation
1Fh: 34.5dB attenuation
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8.7. Reg-0Eh: MIC Volume
Default: 0808h
Table 19. Reg-0Eh: MIC Volume
Name
Bits
15:13
12:8
7:5
Read/Write
Reset State Description
Reserved
mic1_vol
Reserved
mic2_vol
R
0’h
08’h
0’h
Reserved
R/W
R
MIC1 Volume (M1V[4..0]) in 1.5dB Steps
Reserved
4:0
R/W
8’h
MIC2 Volume (M2V[4..0]) in 1.5dB Steps
For M2V/M1V, 00h: +12dB gain
08h: 0dB attenuation
1Fh: 34.5dB attenuation
8.8. Reg-10h: MIC Routing Control
Default: E0E0h
Table 20. Reg-10h: MIC Routing Control
Read/Write Reset State Description
R/W 1’h Mute MIC1 Volume Output to Headphone Mixer
0: On 1: Mute
Mute MIC1 Volume Output to Speaker Mixer
0: On 1: Mute
Mute MIC1 Volume Output to MONO Mixer
0: On 1: Mute
MIC1 Differential Input Control
Name
Bits
mic12hp_mute
15
mic12spk_mute
mic12MONO_mute
mic1_diff_ctrl
14
13
12
R/W
R/W
R/W
1’h
1’h
0’h
0: Disable
Reserved
1: Enable
Reserved
11:8
7
R
0’h
1’h
mic22hp_mute
R/W
Mute MIC2 Volume Output to Headphone Mixer
0: On 1: Mute
Mute MIC2 Volume Output to Speaker Mixer
0: On 1: Mute
Mute MIC2 Volume Output to MONO Mixer
0: On 1: Mute
MIC2 Differential Input Control
mic22spk_mute
mic22MONO_mute
mic2_diff_ctrl
Reserved
6
5
R/W
R/W
R/W
R
1’h
1’h
0’h
0’h
4
0: Disable
Reserved
1: Enable
3:0
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8.9. Reg-12h: ADC Record Gain
Default: F58Bh
Table 21. Reg-12h: ADC Record Gain
Bits Read/Write Reset State Description
Name
adc2hp_l_mute
15
R/W
R/W
R/W
R/W
R/W
1’h
Mute Left Gain Output to Headphone Mixer Control
0: On
1: Mute (-∞dB)
Mute Right Gain Output to Headphone Mixer Control
0: On
adc2hp_r_mute
14
1’h
1: Mute (-∞dB)
Mute Left Gain Output to MONO Mixer Control
0: On
adc2MONO_l_
mute
13
1’h
1: Mute (-∞dB)
Mute Right Gain Output to MONO Mixer Control
0: On
adc2MONO_r_
mute
12
1’h
1: Mute (-∞dB)
ADC Record Gain Left Channel (LRG[4..0]) in 1.5dB Steps
adc_l_vol
11:7
0B’h
00h: -16.5dB attenuation
0Bh: 0dB gain
1Fh: 30dB gain
adc_l_dezero
adc_r_dezero
adc_r_vol
6
5
R/W
R/W
R/W
0’h
0’h
ADC_L Zero-Cross Detector Control
0: Disable
1: Enable
ADC_R Zero-Cross Detector Control
0: Disable
1: Enable
4:0
0B’h
ADC Record Gain Right Channel (RRG[4..0]) in 1.5dB Steps
00h: -16.5dB attenuation
0Bh: 0dB gain
1Fh: 30dB gain
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8.10. Reg-14h: ADC Record Mixer Control
Default: 7F7Fh
Table 22. Reg-14h: ADC Record Mixer Control
Name
Bits
15
Read/Write
Reset State Description
Reserved
adcrec_l_mute
R
0’h
Reserved
14:8
R/W
7F’h
Left Mixer Mute Control
0: On
Bit 14: MIC1
1: Mute (-∞dB)
Bit 13: MIC2
Bit 12: LINE_IN_L Bit 11: PHONE
Bit 10: Headphone Mixer Left Channel
Bit 9: Speaker Mixer
Bit 8: MONO Mixer
Reserved
7
R
0’h
Reserved
adcrec_r_mute
6:0
R/W
7F’h
Right Mixer Mute Control
0: On
Bit 6: MIC1
Bit 4: LINE_IN_R
1: Mute (-∞dB)
Bit 5: MIC2
Bit 3: PHONE
Bit 2: Headphone Mixer Right Channel
Bit 1: Speaker Mixer
Bit 0: MONO Mixer
8.11. Reg-18h: Voice DAC Output Volume
Default: E800h
Table 23. Reg-18h: Voice DAC Output Volume
Name
Bits
Read/Write Reset State Description
voice2hp_mute
15
R/W
R/W
R/W
1’h
1’h
1’h
Mute DAC Output to Headphone Mixer Control
0: On
1: Mute (-∞dB)
Mute DAC Output to Speaker Mixer Control
0: On
voice2spk_mute
14
13
1: Mute (-∞dB)
Mute DAC Output to MONO Mixer Control
voice2MONO_mute
0: On
1: Mute (-∞dB)
voice_vol
Reserved
12:8
7:0
R/W
R
8’h
0’h
Voice Output Volume (VV[4..0]) in 1.5dB Steps
Reserved
Note: For NRV, 00h: +12dB gain
08h: 0dB attenuation
1Fh: 34.5dB attenuation
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8.12. Reg-1Ch: Output Mixer Control
Default: 0000h
Table 24. Reg-1Ch: Output Mixer Control
Read/Write Reset State Description
Name
Bits
spk_l_vol_in_sel
15:14
R/W
0’h
SPKL Volume Input Select
00: VMID (No input)
01: HP Left Mixer
10: Speaker Mixer
11: MONO
spk_l_out_sel
13
R/W
R/W
0’h
0’h
SPKL and SPKR Output Select
0: Class AB
1: Class D
spk_r_vol_in_sel
12:11
SPKR Volume Input Select
00: VMID (No input)
01: HP Right Mixer
10: Speaker Mixer
11: MONO
Reserved
10
9
R
0’h
0’h
Reserved
hp_l_in_sel
R/W
HPL Volume Input Select
0: VMID (No input)
1: HP Left Mixer
hp_r_in_sel
8
R/W
R/W
0’h
0’h
HPR Volume Input Select
0: VMID (No input)
1: HP Right Mixer
MONO Volume Input Select
00: VMID (No input)
01: HP Left + Right Mixer
10: Speaker Mixer
11: MONO Mixer
Reserved
MONO_in_sel
7:6
Reserved
5
4
R
0’h
0’h
clab_amp_source_sel
R/W
In Class AB Mode
SPK_OUT_R Output Amplifier Source Select
0: SPKR Volume Output
1: SPKL Volume Output
Note: SPK_OUT_RN: SPKR Volume Negative Output
Reserved
Reserved
3:0
R
0’h
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8.13. Reg-22h: Microphone Control
Default: 0000h
Table 25. Reg-22h: Microphone Control
Read/Write Reset State Description
Name
Bits
15:12
11:10
Reserved
R
0’h
0’h
Reserved
mic1_boost_ctrl
R/W
MIC1 Boost Control
00: Bypass
01: +20dB
10: +30dB
11: +40dB
mic2_boost_ctrl
9:8
R/W
0’h
MIC2 Boost Control
00: Bypass
01: +20dB
10: +30dB
11: +40dB
Reserved
7:6
5
R
0’h
0’h
Reserved. Read as 0
MICBIAS1 Output Voltage Control
0: 0.9 * AVDD
1: 0.75 * AVDD
MICBIAS2 Output Voltage Control
0: 0.9 * AVDD
1: 0.75 * AVDD
Reserved. Read as 0
mic1_bias_voltage_ctrl
R/W
mic2_bias_voltage_ctrl
4
R/W
0’h
Reserved
2:3
1:0
R
0’h
0’h
mic_bias_threshold
R/W
MICBIAS1/2 Short Current Detector Threshold
00: 600µA
01: 1200µA
1x: 1800µA
8.14. Reg-26h: Power Down Control/Status
Default: EF00h
Table 26. Reg-26h: Power Down Control/Status
Name
Bits Read/Write
Reset State Description
ac_pr7
15
14
13
R/W
R/W
R/W
1’h
1’h
1’h
PR7
0: Normal
1: Power down Speaker Amplifier
ac_pr6
ac_pr5
PR6
0: Normal
1: Power down Headphone Out and MONO Out
PR5
0: Normal
1: Disable internal clock
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Name
Bits Read/Write
Reset State Description
Reserved
ac_pr3
12
11
R/W
R/W
0’h
1’h
Reserved
PR3
0: Normal
1: Power down Mixer (Vref/Vrefout off)
ac_pr2
ac_pr1
ac_pr0
10
9
R/W
R/W
R/W
1’h
1’h
1’h
PR2
0: Normal
1: Power down Mixer (Vref/Vrefout are still on)
PR1
0: Normal
1: Power down STEREO DAC
PR0
8
0: Normal
1: Power down STEREO ADC, and input MUX
Reserved. Read as 0
Vref Status
Reserved
7:4
3
R
R
0’h
0’h
vref_status
1: Vref is up to normal level
0: Not yet up to normal level
Analog Mixer Status
1: Ready
0: Not yet ready
DAC Status
1: Ready
0: Not yet ready
ADC Status
analog_mixer_status
dac_status
2
1
0
R
R
R
0’h
0’h
0’h
adc_status
1: Ready
0: Not yet ready
Table 27. Truth Table for Power Down Mode: (PD= Power Down)
ADC
DAC
-
Mixer
Vref
ACLINK Int CLK HP-OUT MONO-OUT SPK-OUT
PR0=1
PR1=1
PR2=1
PR3=1
PR4=1
PR5=1
PR6=1
PR7=1
PD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD
-
-
PD
PD
-
-
-
-
PD
PD
-
-
-
PD
PD
PD
-
PD
PD
PD
-
PD
-
-
-
-
-
PD
PD
-
-
-
-
-
-
PD
-
-
-
-
-
-
PD
-
PD
-
-
-
-
-
-
-
-
PD
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8.15. Reg-34h: Main Serial Data Port Control (Stereo I2S)
Default: 0000h
Table 28. Reg-34h: Main Serial Data Port Control (Stereo I2S)
Name
Bits Read/Write Reset State Description
stereo_i2s_mode_sel
15
R/W
0’h
Main Serial Data Port Mode Selection
0: Master
1: Slave
stereo_i2s_sadlrck_
ctrl_en
14
R/W
0’h
SADLRCK Control: Set to “1” when ADC and DAC are
different sampling rate
0: Disable, ADC and DAC use the same Fs
1: Enable
Note: frame clock have to input from SDALRCK when this
bit set to”0”
Reserved
13
12
R
0’h
0’h
Reserved
stereo_i2s_bclk_
polarity_ctrl
R/W
Stereo I2S BCLK Polarity Control
0: Normal
1: Invert
i2s_da_sigma_
delta_clock_sel
11
R/W
R/W
0’h
0’h
I2S_DA Sigma Delta Clock Source Select
0b: From DA Filter
1b: From DA Sigma Delta Clock Divider
I2S DA Sigma Delta Clock Divider
i2s_da_sigma_
delta_clock_div
10:8
000b: ÷ 2
010b: ÷ 8
100b: ÷ 32
001b: ÷ 4
011b: ÷ 16
101b: ÷ 64
Others: Reserved
Reserved
Reserved
7
6
R/W
R/W
0’h
0’h
stereo_i2s_pcm_
mode_sel
PCM Mode Select
0: Mode A
1: Mode B
Non PCM Mode Control
0: Normal SADLRCK / SDALRCK
1: Invert SADLRCK / SDALRCK
Note: Only support when stereo_i2s_sadlrck_ctrl_en =”0”
Reserved
Reserved
5:4
3:2
R
0’h
0’h
stereo_i2s_data_
len_sel
R/W
Data Length Selection
00: 16 bits
10: 24 bits
01: 20 bits
11: 32 bits
stereo_i2s_data_
format_sel
1:0
R/W
0’h
Stereo PCM Data Format Selection
00: I2S format
01: Right justified
10: Left justified
11: PCM format
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Datasheet
8.16. Reg-36h: Extend Serial Data Port Control
(VoDAC_I2S/PCM)
Default: 0000h
Table 29. Reg-36h: Extend Serial Data Port Control (VoDAC_I2S/PCM)
Name
Bits
Read/Write Reset State Description
VoPCM_En
15
R/W
0’b
Enable PCM Interface on GPIO1, 3, 4, 5
0: GPIO function
1: VoPCM interface
Extend Serial Data Port Mode Selection
0: Master
voice_port_sel
14
R/W
0’h
1: Slave
Reserved
13:9
8
R
00’h
0’b
Reserved
voice_adc_enable
R/W
Voice ADC Enable
0b: Disable (ADC_L=ADC_R=Stereo)
1b: Enable (ADC_L=Stereo, ADC_R=Voice)
Voice I2S VBCLK Polarity Control
0: Normal
voice_vbclk_polarity_ctrl
voice_pcm_mode_sel
7
6
R/W
R/W
0’h
0’h
1: Invert
PCM Mode Select
0: Mode A
1: Mode B
Non PCM Mode Control
0: Normal VSLRCK
1: Invert VSLRCK
Reserved
Reserved
5:4
3:2
R
0’h
0’h
voice_data_len_sel
R/W
Data Length Selection
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
voice_data_format_sel
1:0
R/W
0’h
Voice Data Format Selection
00: I2S format
01: Right justified
10: Left justified
11: PCM format
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Datasheet
8.17. Reg-3Ah: Power Management Addition 1
Default: 0000h
Table 30. Reg-3Ah: Power Management Addition 1
Name
Bits Read/Write Reset State Description
depop_MONOoutb
15
14
13
R/W
R/W
R/W
0’h
0’h
0’h
Depop of MONO Out
0: Enable (De-pop Enable)
1: Disable (De-pop Disable)
Depop of HP Out
0: Enable (De-pop Enable)
1: Disable (De-pop Disable)
All Zero-Cross Detect Power Down
0: Disable
depop_hp_outb
pow_zcd
1: Enable
Reserved
12
11
R/W
R/W
0’h
0’h
Reserved
main_i2s_en
Main I2S Digital Interface Enable
0: Disable
1: Enable
Reserved
10:6
5
R/W
R/W
0’h
0’h
Reserved
pow_mic1_bias_det_ctrl
MICBIAS1 Short Current Detector Control
0: Disable
1: Enable
pow_mic2_bias_det_ctrl
4
R/W
0’h
MICBIAS2 Short Current Detector Control
0: Disable
1: Enable
pow_mic1_bias
pow_mic2_bias
pow_main_bias
pow_dac_ref
3
2
1
0
R/W
R/W
R/W
R/W
0’h
0’h
0’h
0’h
0: Disable
1: Enable microphone1 bias
0: Disable
1: Enable microphone2 bias
0: Disable
1: Enable Main bias of the ALC5620
0: Disable
1: Enable DAC reference of the ALC5620
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Datasheet
8.18. Reg-3Ch: Power Management Addition 2
Default: 0000h
Table 31. Reg-3Ch: Power Management Addition 2
Name
Bits
Read/Write
Reset State
Description
pow_thermal
15
R/W
0’h
Thermal Detect (Temp Sensor)
0: Disable
1: Enable
pow_clsab
pow_vref
pow_pll
14
13
12
R/W
R/W
R/W
0’h
0’h
0’h
Class_AB Power (All)
0: Disable
1: Enable
VREF of All Analog Circuits
0: Disable
PLL
1: Enable
0: Disable
Reserved
VoDAC Clock
0: Disable
1: Enable PLL
1: Enable
Reserved
11
10
R/W
R/W
0’h
0’h
pow_voice_dac
Note: Disabled includes Voice_I2S interface.
pow_dac_l
pow_dac_r
pow_adc_l
pow_adc_r
pow_hp_l
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
Left Stereo DAC Filter Clock
0: Disable
Right Stereo DAC Filter Clock
0: Disable 1: Enable
Left Stereo ADC Filter Clock and Input Gain
0: Disable 1: Enable
Right Stereo ADC Filter Clock and Input Gain
1: Enable
0: Disable
1: Enable
Left Headphone Mixer
0: Disable
1: Enable
pow_hp_r
Right Headphone Mixer
0: Disable
1: Enable
pow_spk
Speaker Mixer
0: Disable
1: Enable
pow_MONO
pow_adc_rec_l
pow_adc_rec_r
MONO Mixer
0: Disable
1: Enable
Left ADC Record Mixer
0: Disable
1: Enable
Right ADC Record Mixer
0: Disable
1: Enable
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Datasheet
8.19. Reg-3Eh: Power Management Addition 3
Default: 0000h
Table 32. Reg-3Eh: Power Management Addition 3
Name
Bits
15
Read/Write Reset State Description
Reserved
R
0’h
0’h
Reserved
pow_MONO_out_vol
14
R/W
MONO_OUT Volume Control (Amp)
0: Disable
SPK_OUTLN Output (Enable Class AB & Class D)
0: Disable 1: Enable
SPK_OUTRN Output (Enable Class AB & Class D)
0: Disable 1: Enable
HP_OUT_L Volume Control (Amp)
0: Disable 1: Enable
HP_OUT_R Volume Control (Amp)
0: Disable 1: Enable
SPK_OUT_L Output (Enable Class AB & Class D)
0: Disable 1: Enable
SPK_OUT_R Output (Enable Class AB & Class D)
0: Disable 1: Enable
LINE_IN Left Volume Control
0: Disable 1: Enable
LINE_IN Right Volume Control
0: Disable 1: Enable
PHONE Volume Control
1: Enable
pow_spk_outln
pow_spk_outrn
pow_hp_l_vol
pow_hp_r_vol
pow_spk_l
13
12
11
10
9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
pow_spk_r
8
pow_li_l_vol
7
pow_li_r_vol
6
pow_phone_vol
pow_phone_admixer
pow_mic1_vol
pow_mic2_vol
pow_mic1_admixer
pow_mic2_admixer
5
0: Disable
1: Enable
4
PHONE AD Mixer
0: Disable
1: Enable
1: Enable
1: Enable
3
MIC1 Volume Control
0: Disable
2
MIC2 Volume Control
0: Disable
1
MIC1 AD Mixer and Boost
0: Disable
1: Enable
0
MIC2 AD Mixer and Boost
0: Disable
1: Enable
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Datasheet
Figure 15. Power Control to MIC Input
8.20. Reg-40h: General Purpose Control Register 1
Default: 0428h
Table 33. Reg-40h: General Purpose Control Register 1
Name
Bits
Read/
Write
Reset Description
State
sel_sysclk
15
R/W
0’h Stereo SYSCLK Source Select
0: MCLK
1: PLL Output
extclk_dir
14
R/W
0’h EXTCLK Direction Control
0: Input
1: Output
Reserved
13:10
9:8
R/W
R/W
1’h Reserved
hp_amp_ctrl
0’h Headphone Amplifier VMID Ratio Control (Output Gain Control)
00: 1 01: 1.25 1x: 1.5
0’h Speaker Class D Amplifier VMID Ratio Control (Output Gain Control)
spk_ampD_ctrl
7:6
5:3
R/W
R/W
00: 1.75 Vdd
10: 1.25 Vdd
01: 1.5 Vdd
11: 1.0 Vdd
spk_ampAB_ctrl
5’h Speaker Class AB Amplifier VMID Ratio Control (Output Gain Control)
000: 2.25 Vdd
010: 1.75 Vdd
100: 1.25 Vdd
001: 2.00 Vdd
011: 1.5 Vdd
101: 1 Vdd
Others: Not allowed
Reserved
a1_status
2
1
R/W
R
0’h Reserved
0’h A1 Pin Status for I2C
0: 0
1: 1
Reserved
0
R/W
0’h Reserved
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Datasheet
8.21. Reg-42h: General Purpose Control Register 2
Default: 0000h
Table 34. Reg-42h: General Purpose Control Register 2
Name
Bits
Read/Write Reset State Description
voice_stereo_digitalpath_en
15
R/W
0’b
Voice to Stereo Digital Path Enable
0b: Disable
1b: Enable
Reserved
Reserved
14
13
R/W
R/W
0’h
0’b
se_btl_clsab
Single End & BTL of Class AB Selection:
0: Differential Mode
1: Single-End Mode
Reserved
Reserved
12:1
0
R/W
R/W
0’h
0’b
pll_pre_div
PLL Pre-Divider
0b: ÷1
1b: ÷2
8.22. Reg-44h: PLL Control
Default: 0000h
Table 35. Reg-44h: PLL Control
Read/Write Reset State Description
Name
Bits
pll_n_code
15:8
R/W
00’h
N[7:0] Code for Analog PLL
00000000: Div 2
00000001: Div 3
………..
11111111: Div 257
Bypass PLL M
0b: No bypass
1b: Bypass
pll_m_bypass
pll_k_code
7
R/W
R/W
0’h
0’h
6:4
K[2:0] Code for Analog PLL
000: Div 2
001: Div 3
…………
111: Div 9
pll_m_code
3:0
R/W
0’h
M[3:0] Code for Analog PLL
0000: Div 2
0001: Div 3
…………
1111: Div 17
Note: The PLL1 transmit formula is FOUT = (MCLK * (N+2))/((M+2) * (K+2)) {Typical K=2}
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Datasheet
8.22.1.
AC-LINK PLL Clock Setting Table (Unit: MHz)
Table 36. I2C+I2S Clock Setting Table for 48K: (Unit: MHz)
MCLK
N
66
78
94
70
80
81
78
80
78
M
7
FVCO
98.222
98.304
98.304
98.304
98.4
K
2
2
2
2
2
2
2
2
2
FOUT
24.555
24.576
24.576
24.576
24.6
13
3.6864
2.048
4.096
12
1
0
1
8
15.36
16
11
11
14
14
98.068
98.462
98.4
24.517
24.615
24.6
19.2
19.68
98.4
24.6
Table 37 I2C+I2S Clock Setting Table for 44.1K: (Unit: MHz)
MCLK
13
N
68
72
86
64
66
63
66
64
67
M
8
FVCO
91
K
2
2
2
2
2
2
2
2
2
FOUT
22.75
3.6864
2.048
4.096
12
1
90.931
90.112
90.112
90.667
90.764
90.667
90.514
90.528
22.733
22.528
22.528
22.667
22.691
22.667
22.629
22.632
0
1
7
15.36
16
9
10
12
13
19.2
19.68
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Datasheet
8.23. Reg-4Ch: GPIO Pin Configuration
Default: 2E3Eh
Table 38. Reg-4Ch: GPIO Pin Configuration
Name
Bits
15:12
11
Read/Write Reset State Description
Reserved
R
00’h
1’h
Reserved
over_temp_conf
R/W
Over-temperature Status Source Configuration
0: Bypass
1: Normal
mic1_short_det_conf
mic2_short_det_conf
10
9
R/W
R/W
1’h
1’h
MICBIAS1 Short Current Status Source Configuration
0: Bypass
1: Normal
MICBIAS2 Short Current Status Source Configuration
0: Bypass
1: Normal
Reserved
8:6
5
R
0’h
1’h
Reserved
gpio5_conf
R/W
GPIO5 Pin Configuration
0: Output
1: Input
gpio4_conf
gpio3_conf
gpio2_conf
gpio1_conf
Reserved
4
3
2
1
0
R/W
R/W
R/W
R/W
R
1’h
1’h
1’h
1’h
0’h
GPIO4 Pin Configuration
0: Output
1: Input
GPIO3 Pin Configuration
0: Output
1: Input
GPIO2 Pin Configuration
0: Output
1: Input
GPIO1 Pin Configuration
0: Output
1: Input
Reserved. Read as 0
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Datasheet
8.24. Reg-4Eh: GPIO Pin Polarity
Default: 2E3Eh
Table 39. Reg-4Eh: GPIO Pin Polarity
Read/Write Reset State Description
Name
Bits
15:12
11
Reserved
R
00’h
1’h
Reserved
over_temp_polarity
R/W
Over-temperature Polarity
0: Low Active
1: High Active
mic1_short_det_polarity
mic2_short_det_polarity
10
9
R/W
R/W
1’h
1’h
MICBIAS1 Short Current Detect Polarity
0: Low Active
1: High Active
MICBIAS2 Short Current Detect Polarity
0: Low Active
1: High Active
Reserved
8:6
5
R
0’h
1’h
Reserved. Read as 0
GPIO Pin Polarity
0: Low Active
gpio5_polarity
R/W
1: High Active
gpio4_polarity
gpio3_polarity
gpio2_polarity
gpio1_polarity
Reserved
4
3
2
1
0
R/W
R/W
R/W
R/W
R
1’h
1’h
1’h
1’h
0’h
GPIO Pin Polarity
0: Low Active
1: High Active
GPIO Pin Polarity
0: Low Active
1: High Active
GPIO Pin Polarity
0: Low Active
1: High Active
GPIO Pin Polarity
0: Low Active
1: High Active
Reserved. Read as 0
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Datasheet
8.25. Reg-50h: GPIO Pin Sticky
Default: 0000h
Table 40. Reg-50h: GPIO Pin Sticky
Read/Write Reset State Description
Name
Bits
15:12
11
Reserved
R
00’b
0’h
Reserved
over_temp_sticky_En
R/W
Over-temperature Sticky Enable
0: Not sticky
1: Sticky
mic1_short_det_sticky_En
mic2_short_det_sticky_En
10
9
R/W
R/W
0’h
0’h
MICBIAS1 Short Current Detect Sticky Enable
0: Not sticky
1: Sticky
MICBIAS2 Short Current Detect Sticky Enable
0: Not sticky
1: Sticky
Reserved
8:6
5
R
0’h
0’h
Reserved. Read as 0
GPIO5 Pin Sticky Enable
0: Not sticky
gpio5_sticky_En
R/W
1: Sticky
gpio4_sticky_En
gpio3_sticky_En
gpio2_sticky_En
gpio1_sticky_En
Reserved
4
3
2
1
0
R/W
R/W
R/W
R/W
R
0’h
0’h
0’h
0’h
0’h
GPIO4 Pin Sticky Enable
0: Not sticky
1: Sticky
GPIO3 Pin Sticky Enable
0: Not sticky
1: Sticky
GPIO2 Pin Sticky Enable
0: Not sticky
1: Sticky
GPIO1 Pin Sticky Enable
0: Not sticky
1: Sticky
Reserved. Read as 0
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Datasheet
8.26. Reg-52h: GPIO Pin Wake-Up
Default: 0000h
Table 41. Reg-52h: GPIO Pin Wake-Up
Read/Write Reset State Description
Name
Bits
15:12
11
Reserved
R
00’b
0’h
Reserved
over_temp_wakeup_en
R/W
Over-temperature Wake-up Enable
0: No wake-up
1: Wake up
mic1_short_det_wakeup
_en
10
9
R/W
R/W
0’h
0’h
MICBIAS1 Short Current Detect Wake-up Enable
0: No wake-up
1: Wake up
mic2_short_det_wakeup
_en
MICBIAS2 Short Current Detect Wake-up Enable
0: No wake-up
1: Wake up
Reserved
8:6
5
R
0’h
0’h
Reserved. Read as 0
GPIO5 Pin Wake-up Enable
0: No wake-up
gpio5_wakeup_en
R/W
1: Wake up
gpio4_wakeup_en
gpio3_wakeup_en
gpio2_wakeup_en
gpio1_wakeup_en
Reserved
4
3
2
1
0
R/W
R/W
R/W
R/W
R
0’h
0’h
0’h
0’h
0’h
GPIO4 Pin Wake-up Enable
0: No wake-up
1: Wake up
GPIO3 Pin Wake-up Enable
0: No wake-up
1: Wake up
GPIO2 Pin Wake-up Enable
0: No wake-up
1: Wake up
GPIO1 Pin Wake-up Enable
0: No wake-up
1: Wake up
Reserved. Read as 0
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Datasheet
8.27. Reg-54h: GPIO Pin Status
Default: 003Ah
Table 42. Reg-54h: GPIO Pin Status
Read/Write Reset State Description
Name
Bits
15:12
11
Reserved
R
R
00’b
0’h
Reserved
over_temp_status
Over-temperature Status
Read: Return status
Write: Writing ‘0’ clears the sticky bit
MICBIAS1 Short Current Detect Status
Read: Return status
Write: Writing ‘0’ clears the sticky bit
MICBIAS2 Short Current Detect Status
Read: Return status
mic1_short_det_status
mic2_short_det_status
10
9
R
R
0’h
0’h
Write: Writing ‘0’ clears the sticky bit
Reserved. Read as 0
Reserved
8:6
5
R
R
0’h
1’h
gpio5_status
GPIO5 Pin Status
Read: Return status of each GPIO pin
Write: Writing ‘0’ clears the sticky bit
GPIO4 Pin Status
Read: Return status of each GPIO pin
Write: Writing ‘0’ clears the sticky bit
GPIO3 Pin Status
Read: Return status of each GPIO pin
Write: Writing ‘0’ clears the sticky bit
GPIO2 Pin Status
Read: Return status of each GPIO pin
Write: Writing ‘0’ clears the sticky bit
GPIO1 Pin Status
gpio4_status
gpio3_status
gpio2_status
gpio1_status
Reserved
4
3
2
1
0
R
R
R
R
R
1’h
1’h
1’h
1’h
0’h
Read: Return status of each GPIO pin
Write: Writing ‘0’ clears the sticky bit
Reserved. Read as 0
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Datasheet
8.28. Reg-56h: Pin Sharing
Default: 0000h
Table 43. Reg-56h: Pin Sharing
Name
Bits
15:3
2
Read/Write
Reset State
0’h
Description
Reserved
Reserved
R
gpio2_pin_sharing
R/W
0’h
GPIO2 Pin Sharing
0: IRQ_Out
1: GPIO enable
Reserved
Reserved
1:0
R
0’h
Figure 16. GPIO and IRQ Logic
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Datasheet
8.29. Reg-58h: Over-Temp/Current Status
Default: 0CFFh
Table 44. Reg-58h: Over-Temp / Current Status
Name
Bits
15:12
11
Read/Write Reset State Description
Reserved
ovt_hp_status
R
R
0000’h
1’h
Reserved
Headphone Amp Over-temperature
0: Normal
1: Over-temperature
MONO Amp Over-temperature
0: Normal
1: Over-temperature
MICBIAS1 Over-current
0: Normal
ovt_MONO_status
ovc_micbias1_status
ovc_micbias2_status
rp_depop_status
rn_depop_status
lp_depop_status
ln_depop_status
ovt_rp_status
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
1’h
0’h
0’h
1’h
1’h
1’h
1’h
1’h
1’h
1’h
1’h
1: Over-current
MICBIAS2 Over-current
0: Normal
1: Over-current
RP Channel Depop Status
0: Depop ready
1: Depop finished
RN Channel Depop Status
0: Depop ready
1: Depop finished
LP Channel Depop Status
0: Depop ready
1: Depop finished
LN Channel Depop Status
0: Depop ready
1: Depop finished
RP Channel Temperature Sensor Status
0: Normal
1: Over-temperature
RN Channel Temperature Sensor Status
0: Normal
1: Over-temperature
LP Channel Temperature Sensor Status
0: Normal
1: Over-temperature
LN Channel Temperature Sensor Status
0: Normal
ovt_rn_status
ovt_lp_status
ovt_ln_status
1: Over-temperature
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Datasheet
8.30. Reg-5Ch: GPIO_Output Pin Control
Default: 0000h
Table 45. Reg-5Ch: GPIO_Output Pin Control
Name
Bits
15:6
5
Read/Write
Reset State
0000’h
0’h
Description
Reserved
R
Reserved
gpio5_out_status
R/W
GPIO5 Output Pin Control
0b: Drive Low
1b: Drive High
gpio4_out_status
gpio3_out_status
gpio2_out_status
gpio1_out_status
Reserved
4
3
2
1
0
R/W
R/W
R/W
R/W
R
0’h
0’h
0’h
0’h
0’h
GPIO4 Output Pin Control
0b: Drive Low
1b: Drive High
GPIO3 Output Pin Control
0b: Drive Low
1b: Drive High
GPIO2 Output Pin Control
0b: Drive Low
1b: Drive High
GPIO1 Output Pin Control
0b: Drive Low
1b: Drive High
Reserved. Read as 0
8.31. Reg-5Eh: MISC Control
Default: 0000h
Table 46. Reg-5Eh: MISC Control
Read/Write Reset State Description
Name
Bits
en_vref_fast
15
R/W
0’b
Enable Fast Vreg
0: Enable fast Vref
1: Disable fast Vref
Note: To improve PSRR, en_vref_fast should be
disabled before playback/record.
clsab_amp_sel
14
R/W
0’b
Class AB Output Amplifier Select
0: Strong Amp
1: Weak Amp
Note: Strong Amp, SPKVDD: 3.0V~5V and Set
index44[8:6]=100’b
Weak Amp, SPKVDD: 2.3V~5V and Set
index44[8:6]=000’b
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Name
Bits
Read/Write Reset State Description
AVC_target_sel
13:12
R/W
0’b
AVC Target Select
00: Reserved (No AVC)
01: R Channel
10: L Channel
11: Both channel
Thermal Shutdown Enable
0: Disable
thermal_shutdown_en
11
R/W
0’b
1: Enable
Reserved
10:7
6
R/W
R/W
0’h
0’h
Reserved
main_dac_l_mute
Mute Main DAC Left Input
0: On
1: Mute (-∞dB)
Mute Main DAC Right Input
0: On
main_dac_r_mute
voice_dac_mute
5
4
R/W
R/W
0’h
0’h
1: Mute (-∞dB)
Mute Voice DAC Input
0: On
1: Mute (-∞dB)
Reserved
Reserved
3:1
0
R/W
R/W
0’h
0’h
irqout_inv_ctrl
IRQOUT Inverter Control
0: Normal
1: Invert
The Jack-insert-detect pull up resister is implemented via an external circuit (see Figure 17 below).
Figure 17. Jack-Insert-Detect Pull Up Resister Implemented via an External Circuit
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8.32. Reg-60h: Stereo DAC Clock Control_1
Default: 3075h
Table 47. Reg-60h: Stereo DAC Clock Control_1
Name
Bits
Read/Write Reset State Description
stereo_i2s_sclk_div1
15:12
R/W
3’h
Stereo I2S SCLK Div1
0000b: ÷ 1
0001b: ÷ 2
0010b: ÷ 3
………….
1101b: ÷ 14
1110b: ÷ 15
1111b: ÷ 16
Reserved
Stereo I2S SCLK Div2
000b: ÷ 2
Reserved
11
R/W
R/W
0’h
0’h
stereo_i2s_sclk_div2
10:8
001b: ÷ 4
010b: ÷ 8
011b: ÷ 16
100b: ÷ 32
Others: Reserved
Stereo I2S AD WCLK Div1
0000b: ÷ 1
stereo_i2s_ad_wclk_div1
7:4
R/W
7’h
0001b: ÷ 2
0010b: ÷ 3
………….
1101b: ÷ 14
1110b: ÷ 15
1111b: ÷ 16
Stereo I2S AD WCLK Div2
000b: ÷ 2
001b: ÷ 4
010b: ÷ 8
011b: ÷ 16
100b: ÷ 32
stereo_i2s_ad_wclk_div2
stereo_i2s_da_wclk_div
3:1
R/W
R/W
010’b
Others: Reserved
Stereo I2S DA WCLK Div
0b: 32
0
1’h
1b: 64
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8.33. Reg-62h: Stereo DAC Clock Control_2
Default: 1010h
Table 48. Reg-62h: Stereo DAC Clock Control_2
Name
Bits
Read/Write Reset State Description
stereo_i2s_da_filter_div1
15:12
R/W
1’h
Stereo I2S DA Filter Div1
0000b: ÷ 1
0001b: ÷ 2
0010b: ÷ 3
…………
1101b: ÷ 14
1110b: ÷ 15
1111b: ÷ 16
Stereo I2S DA Filter Div2
000b: ÷ 2
stereo_i2s_da_filter_div2
11:9
R/W
0’h
001b: ÷ 4
010b: ÷ 8
011b: ÷ 16
100b: ÷ 32
Others: Reserved
Reserved
Stereo I2S AD Filter Div1
0000b: ÷ 1
Reserved
8
R/W
R/W
0’h
1’h
stereo_i2s_ad_filter_div1
7:4
0001b: ÷ 2
0010b: ÷ 3
…………
1101b: ÷ 14
1110b: ÷ 15
1111b: ÷ 16
Stereo I2S AD Filter Div2
000b: ÷ 2
001b: ÷ 4
010b: ÷ 8
011b: ÷ 16
100b: ÷ 32
stereo_i2s_ad_filter_div2
3:1
R/W
R/W
0’h
0’h
Others: Reserved
Reserved
Reserved
0
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8.34. Reg-64h: VoDAC_PCM Clock Control_1
Default: 2130h
Table 49. Reg-64h: VoDAC_PCM Clock Control_1
Name
Bits
Read/Write Reset State Description
voice_mclk_sel
15
R/W
R/W
R/W
0’h
0’h
1’h
Voice Master-Clock Select
0b: MCLK input
1b: PLL output
voice_sysclk_sel
14
13
Voice System-Clock Select
0b: MCLK
1b: EXTCLK
I2S Word-Clock Voice Master Select
0b: ÷32
I2s_wclk voice_master_sel
1b: ÷64
Reserved
12:11
10:8
R
0’b
1’h
Reserved
extclk_out_sel
R/W
External Clock-Out Select
000b: ÷1
001b: ÷2
010b: ÷4
011b: ÷8
100b: ÷16
Others: Reserved
I2S Bit-Clock Voice Master Select 1
0000b: ÷1
I2s_sclk_voice_master_sel_1
7:4
R/W
3’h
0001b: ÷2
0010b: ÷3
…………
1101b: ÷14
1110b: ÷15
1111b: ÷16
Reserved
3
R
0’b
0’h
Reserved
I2s_sclk_voice_master_sel_2
2:0
R/W
I2S Bit-Clock Voice Master Select 2
000b: ÷2
001b: ÷4
010b: ÷8
011b: ÷16
100b: ÷32
Others: Reserved
Note: The driver must determine the Voice AD/DA filter clock, and select the filter by setting Voice_64osr (see Table 50).
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8.35. Reg-66h: VoDAC_PCM Clock Control_2
Default: 0010h
Table 50. Reg-66h: VoDAC_PCM Clock Control_2
Name
Bits
Read/Write
Reset State
Description
sel_clk_filter_slave
15
R/W
0’h
Select Voice Clock Filter Slave
0b: ÷1
1b: ÷2
sel_clk_filter
voice_64osr
14
13
R/W
R/W
0’h
0’h
Select Voice Clock Filter Source
0b: From MCLK/EXTCLK
1b: From VBCLK
Voice DA/AD Filter Select
0b: 128x
1b: 64x
Reserved
12:8
7:4
R
0’h
1’h
Reserved
clk_filter_master_sel_1
R/W
Clock Filter Master Select 1
000b: ÷1
001b: ÷2
010b: ÷3
…………
1101b: ÷14
1110b: ÷15
1111b: ÷16
Reserved
3
R
0’h
0’h
Reserved
clk_filter_master_sel_2
2:0
R/W
Clock Filter Master Select 2
000b: ÷2
001b: ÷4
010b: ÷8
011b: ÷16
100b: ÷32
Others: Reserved
Note: The driver must determine the Voice AD/DA filter clock, and select the filter by setting Voice_64osr (see Table 50).
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8.36. Reg-68h: Pseudo Stereo and Spatial Effect Block Control
Default: 0053h
Table 51. Reg-68h: Pseudo Stereo and Spatial Effect Block Control
Name
Bits
Read/Write Reset State Description
spatial_ctrl_enable
15
R/W
0’b
Spatial Enable
0b: Disable (Clear internal state)
1b: Enable
apf_en
14
R/W
0’h
Enable All Pass Filter APF(z) (EN-APF)
0: Disable (Bypass) and reset.
1: Enable all pass filters. The coefficient a1 is loaded from
apf_parm_a1[7:0]
pseudo_stereo_en
en_3d
13
12
R/W
R/W
0’h
0’h
Enable Pseudo Stereo Block (EN-PSB)
0: Disabled
1: Enabled
Enable Stereo Expansion Block (EN-SEB)
0: Disable
1: Enabled. Load 3D Ratio from ratio_parm_3d and 3D
Gain from gain_parm_3d
Reserved
11:8
7:6
-
0’h
1’h
Reserved
gain_parm_3d
R/W
3D Gain Parameter (SEGn)
00: Gain=1.0
01: Gain=1.5
10: Gain=2.0
11: Reserved
ratio_parm_3d
5:4
R/W
1’h
3D Ratio Parameter (DPn)
00: Ratio=0.0
01: Ratio=0.66
10: Ratio=1.0
11: Reserved
Reserved
3:2
1:0
-
0’h
3’h
Reserved
apf_parm_a1
R/W
All Pass Filter parameter
00: Disable
01: Enable for 32kHz sample rate or lower
10: Enable for 44.1kHz sample rate
11: Enable for 48kHz sample rate
Note: Writes to SEGn and DPn will be ignored when the Spatial effect control bit is enabled. This means individual
Spatial coefficients cannot be modified when Spatial is enabled.
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8.37. Reg-6Ah: Index Address
Default: 0000h
Table 52. Reg-6Ah: Index Address
Name
Bits
15:7
6:0
Read/Write
Reset State Description
Reserved
index_addr
R
0’h
0’h
Reserved
R/W
Index Address
8.38. Reg-6Ch: Index Data
Default: 0000h
Table 53. Reg-6Ch: Index Data
Name
Bits
Read/Write
Reset State Description
index_data
15:0
R/W
0’h
Index Data
8.39. Reg-6Eh: EQ Status
Default: 0000h
Table 54. Reg-6Eh: EQ Status
Name
Bits
15:5
4
Read/Write
Reset State Description
Reserved
eq_hpf_status
R
R
0’h
0’h
Reserved
EQ High-Pass Filter (HPF) Status
0: Normal
1: Overflow.
This bit is set if overflow has occurred. Write 1 to clear.
EQ Band-3 (BP3) Status
eq_bpf3_status
eq_bpf2_status
eq_bpf1_status
eq_lpf_status
3
2
1
0
R
R
R
R
0’h
0’h
0’h
0’h
0: Normal
1: Overflow.
This bit is set if overflow has occurred. Write 1 to clear.
EQ Band-2 (BP2) Status
0: Normal
1: Overflow.
This bit is set if overflow has occurred. Write 1 to clear.
EQ Band-1 (BP1) Status
0: Normal
1: Overflow.
This bit is set if overflow has occurred. Write 1 to clear.
EQ Low-Pass Filter (LPF) Status
0: Normal
1: Overflow.
This bit is set if overflow has occurred. Write 1 to clear.
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8.40. Index-00h: EQ Band-0 Coefficient (LP0: a1)
Default: 0000h
Table 55. Index-00h: EQ Band-0 Coefficient (LP0: a1)
Bit
Type Function
R/W 2’s complement in 3.13 formats (The range is from –4~3.99, the a1 should be in -2 ~ 1.99)
15:0
Note: For low pass filter for Bass control – LP0 has filter coefficient a1 and gain Ho must be set (see Table 56).
8.41. Index-01h: EQ Band-0 Gain (LP0: Ho)
Default: 0000h
Table 56. Index-01h: EQ Band-0 Gain (LP0: Ho)
Bit
Type Function
15:0
R/W 2’s complement in 3.13 format (The range is from –4~3.99, the Ho should be in -4 ~ 3.99)
8.42. Index-02h: EQ Band-1 Coefficient (BP1: a1)
Default: 0000h
Table 57. Index-02h: EQ Band-1 Coefficient (BP1: a1)
Bit
Type Function
15:0
R/W 2’s complement in 3.13 format (The range is from –4~3.99, the a1 should be in -2 ~ 1.99)
8.43. Index-03h: EQ Band-1 Coefficient (BP1: a2)
Default: 0000h
Table 58. Index-03h: EQ Band-1 Coefficient (BP1: a2)
Bit
Type Function
15:0
R/W 2’s complement in 3.13 format (The range is from –4~3.99, the a1 should be in -2 ~ 1.99)
8.44. Index-04h: EQ Band-1 Gain (BP1: Ho)
Default: 0000h
Table 59. Index-04h: EQ Band-1 Gain (BP1: Ho)
Bit
Type Function
15:0
R/W 2’s complement in 3.13 format (The range is from –4~3.99, the Ho should be in -4 ~ 3.99)
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8.45. Index-05h: EQ Band-2 Coefficient (BP2: a1)
Default: 0000h
Table 60. Index-05h: EQ Band-2 Coefficient (BP2: a1)
Bit
Type Function
15:0
R/W 2’s complement in 3.13 format (The range is from –4~3.99, the a1 should be in -2 ~ 1.99)
8.46. Index-06h: EQ Band-2 Coefficient (BP2: a2)
Default: 0000h
Table 61. Index-06h: EQ Band-2 Coefficient (BP2: a2)
Bit
Type Function
15:0
R/W 2’s complement in 3.13 format (The range is from –4~3.99, the a2 should be in -2 ~ 1.99)
8.47. Index-07h: EQ Band-2 Gain (BP2: Ho)
Default: 0000h
Table 62. Index-07h: EQ Band-2 Gain (BP2: Ho)
Bit
Type Function
R/W 2’s complement in 3.13 format (The range is from –4~3.99, the Ho should be in -4 ~ 3.99)
15:0
8.48. Index-08h: EQ Band-3 Coefficient (BP3: a1)
Default: 0000h
Table 63. Index-08h: EQ Band-3 Coefficient (BP3: a1)
Bit
Type Function
15:0
R/W 2’s complement in 3.13 format (The range is from –4~3.99, the a1 should be in -2 ~ 1.99)
8.49. Index-09h: EQ Band-3 Coefficient (BP3: a2)
Default: 0000h
Table 64. Index-09h: EQ Band-3 Coefficient (BP3: a2)
Bit
Type Function
15:0
R/W 2’s complement in 3.13 format (The range is from –4~3.99, the a2 should be in -2 ~ 1.99)
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8.50. Index-0Ah: EQ Band-3 Gain (BP3: Ho)
Default: 0000h
Table 65. Index-0Ah: EQ Band-3 Gain (BP3: Ho)
Bit
Type Function
R/W 2’s complement in 3.13 format (The range is from –4~3.99, the Ho should be in -4 ~ 3.99)
15:0
8.51. Index-0Bh: EQ Band-4 Coefficient (HPF: a1)
Default: 0000h
Table 66. Index-0Bh: EQ Band-4 Coefficient (HPF: a1)
Bit
Type Function
15:0
R/W 2’s complement in 3.13 format (The range is from –4~3.99, the a1 should be in -2 ~ 1.99)
8.52. Index-0Ch: EQ Band-4 Gain (HPF: Ho)
Default: 0000h
Table 67. Index-0Ch: EQ Band-4 Gain (HPF: Ho)
Bit
Type Function
15:0
R/W 2’s complement in 3.13 format (The range is from –4~3.99, the Ho should be in -2 ~ 1.99)
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8.53. Index-10h: EQ Control and Status Register
Default: 0000h
Table 68. Index-10h: EQ Control and Status Register
Bit
Type
Function
15
R/W
EQ block Control
0b: Disable
1b: Enable
14:5
4
-
Reserved
R/W
EQ High-Pass Filter (HPF) Control
0: Disabled (bypass) and reset
1: Enabled
3
2
1
0
R/W
R/W
R/W
R/W
EQ Band-3 (BP3) Control
0: Disabled and reset
1: Enabled
EQ Band-2 (BP2) Control
0: Disabled and reset
1: Enabled
EQ Band-1 (BP1) Control
0: Disabled and reset
1: Enabled
EQ Low-Pass Filter (LPF) Control
0: Disabled and reset
1: Enabled
Note: Individual EQ coefficients cannot be modified when EQ is enabled.
8.54. Index-11h: EQ Input Volume Control
Default: 0000h
Table 69. Index-11h: EQ Input Volume Control
Bit
15:2
1:0
Type
-
Function
Reserved
R/W
7-bit Volume Unsigned Ratio EQIn-VOL-LR
00b: 0dB
01b: -6dB
10b: -12dB
11b: -18dB
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8.55. Index-12h: EQ Output Volume Control
Default: 0001h
Table 70. Index-12h: EQ Output Volume Control
Bit
15:3
2:0
Type
-
Function
Reserved
R/W
7-bit Volume Unsigned Ratio EQOut-VOL-LR
000b: -3dB
001b: 0dB
010b: 3dB
011b: 6dB
100b: 9dB
101b: 12dB
110b: 15dB
111b: 18dB
8.56. Index-20h: Auto Volume Control Register 0
Default: 0050h
Table 71. Index-20h: Auto Volume Control Register 0
Bit
Type Function
15
R/W Select the Controlled Gain Block for AVC (Default: 00b)
0: Disable AVC
1: Enable AVC to control ADC gain
14:8
7:3
-
Reserved
R/W Monitor Window Control (Unit: 2^(n+1) samples) (Default: 01010b)
00000b: 2^(1) sample
00001b: 2^(2) samples
00010b: 2^(3) samples, …
10000b: 2^(17) samples, …
Others: Reserved.
Maximum n=16
Note: The Monitor Window can only be changed after soft-reset when AVC is enabled
2:1
0
-
Reserved
R/W AVC Reference Channel Selection (Default: 0b)
0: Left Channel
1: Right Channel
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8.57. Index-21h: Auto Volume Control Register 1
Default: 2710h
Table 72. Index-21h: Auto Volume Control Register 1
Bit
15
Type Function
Reserved
R/W The Maximum PCM absolute level after AVC, Thmax (=0 ~ 2^15-1)
-
14:0
8.58. Index-22h: Auto Volume Control Register 2
Default: 0BB8h
Table 73. Index-22h: Auto Volume Control Register 2
Bit
15
Type Function
Reserved
R/W The Minimum PCM absolute level after AVC, Thmin (=0 ~ 2^15-1)
-
14:0
8.59. Index-23h: Auto Volume Control Register 3
Default: 01F4h
Table 74. Index-23h: Auto Volume Control Register 3
Bit
15
Type Function
Reserved
R/W The Non-active PCM absolute level AVC will keep analog unit gain, Thnonact (=0 ~ 2^15-1)
-
14:0
Note: Initial Index23=0001’h
8.60. Index-24h: Auto Volume Control Register 4
Default: 0190h
Table 75. Index-24h: Auto Volume Control Register 4
Bit
Type Function
15:0
R/W The CNTMAXTH1 that controls sensitivity to Gain increase (Unit:2^1)
This value should be less than CNTMAXTH2 (Max:2^17)
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8.61. Index-25h: Auto Volume Control Register 5
Default: 0200h
Table 76. Index-25h: Auto Volume Control Register 5
Bit
Type Function
15:0
R/W The CNTMAXTH2 to control the sensitivity to decrease Gain (Unit:2^1)
This value should be less than Monitor Window (Optimized: 1/2 Monitor Window)
(Max:2^17)
Note: CNTMAXTH1 < CNTMAXTH2
8.62. Index-39h: Digital Internal Register
Default: 9000h
Table 77. Index-39h: Digital Internal Register
Bit
Type
Function
15
R/W
Pad Drive Capability
0b: Weak drive
1b: Strong drive
Reserved
14:0
R/W
8.63. Index-44h: Class AB Internal Register
Default: F920h
Table 78. Index-44h: Class AB Internal Register
Bit
Type
Function
15
R/W
POW_CLSAB LP: Class_AB Left Positive Channel
0: Power Down
1: Power ON
14
13
R/W
R/W
R/W
R/W
POW_CLSAB LN: Class_AB Left Negative Channel
0: Power Down
1: Power ON
POW_CLSAB RP: Class_AB Right Positive Channel
0: Power Down
1: Power ON
12
POW_CLSAB RN: Class_AB Right Negative Channel
0: Power Down
1: Power ON
Reserved
11:0
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8.64. Index-4Ah: Class D Temperature Sensor
Default: 4444h
Table 79. Index-4Ah: Class D Temperature Sensor
Bit
15
Type
R/W
R/W
Function
Reserved
14:12
RP Channel Temp. Sensor Threshold Setting
001: 35°C
101: 95°C
Reserved
011: 65°C
111: 125°C
11
R/W
R/W
10:8
RN Channel Temp. Sensor Threshold Setting
001: 35°C
101: 95°C
Reserved
011: 65°C
111: 125°C
7
R/W
R/W
6:4
LP Channel Temp. Sensor Threshold Setting
001: 35°C
101: 95°C
Reserved
011: 65°C
111: 125°C
3
R/W
R/W
2:0
LN Channel Temp. Sensor Threshold Setting
001: 35°C
101: 95°C
011: 65°C
111: 125°C
Note: Tolerance: ± 15°C
8.65. Index-54h: AD_DA_Mixer_Internal Register
Default: 8184h
Table 80. Index-54h: AD_DA_Mixer_Internal Register
Bit
15
Type
R/W
R/W
Function
Reserved
14:13
DAC Reference Source
01: Internal DAC reference (AVDD & DAC reference cannot be bonded together)
11: External DAC reference (AVDD/AGND as DAC reference)
Others: Forbidden
12:3
2:0
R/W
R/W
Reserved
Temp. Sensor for Threshold Setting
001: 35°C
101: 95°C
011: 65°C
111: 125°C
Note: Tolerance: ± 15°C
Note: To reduce DAC power consumption, we suggest that Index54=E184’h be initialized.
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8.66. Reg-7Ch: VENDOR ID 1
Default: 10ECh
Table 81. Reg-7Ch: VENDOR ID 1
Name
Bits
Read/Write
Reset State Description
10EC’h Vendor ID=10EC
vender_id1
15:0
R
8.67. Reg-7Eh: VENDOR ID 2
Default: 2003h
Table 82. Reg-7Eh: VENDOR ID 2
Name
Bits
15:8
7:0
Read/Write
Reset State Description
vender_id
device_id2
R
R
10’h
03’h
Device ID=20
Version ID=03
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Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1.
Absolute Maximum Ratings
Table 83. Absolute Maximum Ratings
Parameter
Symbol
Min
Typ
Max
Units
Power Supplies
Digital IO Buffer
Digital Core
Analog
Touch Panel
DVDD1
DVDD2
AVDD
TPVDD
HPVDD
SPKVDD
Ta
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-25
-
-
-
-
-
-
-
-
3.63
3.63
3.63
3.63
3.63
71
V
V
V
V
V
Headphone
Speaker
V
Operating Ambient Temperature
Storage Temperature
+85
+125
oC
oC
Ts
-55
Note: SPKVDD =5V with 3.5% duty cycle Power bouncing up to SPKVDD=8V is acceptable.
9.1.2.
Recommended Operating Conditions
Table 84. Recommended Operating Conditions
Parameter
Digital IO Buffer
Digital Core
Analog
Symbol
DVDD1
DVDD2
AVDD
Min
1.81
1.8
2.3
2.3
2.3
2.3
Typ
3.3
3.3
3.3
3.3
3.3
3.3
Max
3.6
3.6
3.6
3.6
3.6
5
Units
V
V
V
Touch Panel
Headphone
Speaker
TPVDD
HPVDD
SPKVDD2
V
V
V
Note 1: Minimum DVDD1=2.3V when PLL is working.
Note 2: A 10uF Capacitor must be connected from SPKVDD to AGND, and should be placed as close as possible to the
SPKVDD pin of the ALC5620.
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Datasheet
9.1.3.
Static Characteristics
Table 85. Static Characteristics
Parameter
Symbol
Min
Typ
Max
Units
V
Input Voltage Range
VIN
-0.30
-
-
DVDD+0.30
Low Level Input Voltage
VIL
-
0.35DVDD
V
High Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
VIH
0.65DVDD
-
-
V
VOH
0.9DVDD
-
-
V
VOL
-
-1
-1
-
-
0.1DVDD
V
-
-
-
-
-
-
-
1
1
uA
uA
mA
mA
KΩ
%
Output Leakage Current (Hi-Z)
Output Buffer High Drive Current
Output Buffer Low Drive Current
VMID Internal Serial Resistor
VMID Internal Serial Resistor Ratio
-
22
10
50
100
-
-
-
25
95
75
105
Note: DVDD= 3.3V, Tambient=25°C, with 50pF external load.
9.2. Analog Performance Characteristics
Table 86. Analog Performance Characteristics
Parameter
Min
Typ
Max
Units
Full Scale Input Voltage
Line Inputs
MIC Inputs (Non-Boost)
MIC Inputs (Boost 20dB)
ADC
-
-
-
-
1.0
1.0
0.1
0.7
-
-
-
-
Vrms
Vrms
Vrms
Vrms
Full Scale Output Voltage
MONO Outputs
Headphone Amplifiers Outputs
Speaker Amplifiers Outputs
-
-
-
1.0
1.0
1.3
-
-
-
Vrms
Vrms
Vrms
S/N Ratio
(A-weighted, HPL/R or MONO with 10KΩ/50pF Load)
-
-
-
90
85
70
-
-
-
dB
dB
dB
STEREO DAC
STEREO ADC
Voice DAC
Total Harmonic Distortion + Noise
(A-weighted, HPL/R or MONO with 10KΩ/50pF Load)
STEREO DAC
STEREO ADC
Voice DAC
-
-
-
-85
-80
-60
-
-
-
dB
dB
dB
MIC Boost Amplifier
Gain=20dB
Gain=30dB
18
-
-
20
30
40
22
-
-
dB
dB
dB
Gain=40dB
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Datasheet
Parameter
Min
Typ
Max
Units
Input Impedance (Gain=0dB, ADC Mixer=On/Off)
PHONEN (Differential Mode)
MIC1N, MIC2N (Differential Mode)
MIC1P, MIC2P
-
-
-
-
16
16
16
16
-
-
-
-
KΩ
KΩ
KΩ
KΩ
PHONEP
Input Impedance (Gain=0dB, ADC Mixer=On)
LINE_IN
12.8
25.6
16
32
19.2
38.4
KΩ
KΩ
Input Impedance (Gain=0dB, ADC Mixer=Off)
LINE_IN
Output Impedance
MONO_OUT
HP_OUT
SPK_OUT (Class AB)
SPK_OUT (Class D)
-
-
-
-
2
2
1
-
-
-
Ω
Ω
Ω
Ω
0.3
0.4
MONO_OUT Amplifier Output Power (32Ω Load)
25
75
-
-
-
-
mW
mW
Single End Mode
BTL Mode
-
700
-
µA
MONO_OUT Amplifier Quiescent Current (32Ω Load)/CH
MONO_OUT Amplifier Efficiency (fIN=1kHz, 32Ω Load)
Single End Mode (Output Power=25mW)
BTL Mode (Output Power=75mW)
MONO_OUT Amplifier THD+N
Single End Mode (10KΩ Load)
Output Power=0.1mW
50
50
-
-
-
-
%
%
-
-
0.01
0.01
-
-
%
%
BTL Mode (10KΩ Load)
Output Power=0.1mW
MONO_OUT Amplifier PSRR
-
-
50
-
-
dB
mW
uA
%
31.25
Headphone Amplifier Output Power (32Ω Load)
Headphone Amplifier Quiescent Current (32Ω Load)
Headphone Amplifier Efficiency
-
700
-
-
-
50
(fIN=1kHz, 32Ω Load, Output Power=25mW)
Headphone Amplifier THD+N (32Ω Load)
Output Power=20mW
Output Power=25mW
-
-
-
-
70
70
50
1
-
-
-
-
dB
dB
dB
W
Headphone Amplifier PSRR
BTL Speaker Amplifier Output Power
(SPKVDD=5V with 8Ω Load)
BTL Speaker Amplifier Quiescent Current
Class AB_Strong (8Ω Load)
Class D
-
-
-
-
11
4
mA
mA
BTL Speaker Amplifier Efficiency
(fIN=1kHz, 8Ω Load, Output Power=700mW)
Class AB
Class D
50
-
-
82
-
-
%
%
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Datasheet
Parameter
Min
Typ
Max
Units
BTL Speaker Amplifier THD+N (8Ω Load)
Class AB_Strong (8Ω load)
Output Power=350mW
-
-
70
70
-
-
dB
dB
Output Power=600mW
Class D
-
-
70
60
-
-
dB
dB
Output Power=350mW
Output Power=600mW
BTL Speaker Amplifier THD+N
Class AB_Weak (10KΩ/50pF Load)
BTL Speaker Amplifier SNR
Class AB_Weak (10KΩ/50pF Load)
BTL Speaker Amplifier PSRR
Power Supply Current
-
-85
-
dB
-
-
-90
50
-
-
dB
dB
I
I
DDA (Analog Block)
DDD (Digital Block)
-
-
-
-
15
20
mA
mA
Power Down Current
I
I
DDA (Analog Block)
DDD (Digital Block)
-
-
-
-
10
1
µA
µA
MICBIAS1 Output Voltage
0.75*Avdd Setting
0.9*Avdd Setting
-
-
-
2.475
2.97
16
-
-
-
V
V
MICBIAS1 and MICBIAS2 Drive Current
MICBIAS2 Output Voltage
0.75*Avdd Setting
mA
-
-
-
2.475
2.97
50
-
-
-
V
V
0.9*Avdd Setting
Vref Pull Up Resistor
KΩ
Note: Standard test conditions
Tambient=25°C, DVDD=AVDD1=AVDD2=HPVDD=3.3V, SPKVDD=4.2V
1kHz input sine wave; PCM Sampling frequency=48kHz; 0dB=1Vrms, Test bench Characterization BW: 10Hz~22kHz,
0dB attenuation; EQ and 3D disabled
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Datasheet
10. Application Circuits
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Datasheet
11. Mechanical Dimensions
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Datasheet
12. Appendix A: Stereo I2S Clock Table
12.1. Master/Slave Mode
Note 1: PLL output as System Clock only supports Master Mode
Note 2: SDALRCL and SADLRCK are Output in Master Mode, and are Input in Slave Mode
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Datasheet
13. Appendix B: Voice PCM Interface
13.1. Master Mode: (voice_port_sel=0)
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Datasheet
13.2. Slave Mode: (voice_port_sel=1)
X ==> Don’t Care
– ==> forbidden
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Datasheet
14. Ordering Information
Table 87. Ordering Information
Part Number
Package
Status
ALC5620-GR
QFN-48 in ‘Green’ package
MP
Note 1: See page 5 for Green package and version identification.
Note 2: Above parts are tested under AVDD1=AVDD2 =3.3V.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-557-6047
www.realtek.com.tw
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