ALC5623-GRT [REALTEK]
I2S AUDIO CODEC HEADPHONE AMPLIFIER;
| 型号： | ALC5623-GRT |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | I2S AUDIO CODEC HEADPHONE AMPLIFIER 放大器 |
| 文件： | 总75页 (文件大小：1349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC5623-GR
ALC5623-GRT
I2S AUDIO CODEC + HEADPHONE AMPLIFIER
DATASHEET
Rev. 1.1
13 November 2008
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
ALC5623
Datasheet
COPYRIGHT
©2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC5623 Audio Codec IC.
Though every effort has been made to ensure that this document is current and accurate, more
information may have become available subsequent to the production of this guide. In that event, please
contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
Release Date
2008/04/08
2008/11/13
Summary
1.0
First release
1.1
Revised Table 3, page 8.
Revised section 10 Application Circuit, page 63.
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Datasheet
Table of Contents
1.
2.
3.
4.
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................2
SYSTEM APPLICATIONS...............................................................................................................................................3
BLOCK DIAGRAMS.........................................................................................................................................................4
4.1.
4.2.
FUNCTION BLOCK ........................................................................................................................................................4
AUDIO MIXER PATH.....................................................................................................................................................5
5.
6.
PIN ASSIGNMENTS .........................................................................................................................................................6
5.1.
GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................6
PIN DESCRIPTIONS.........................................................................................................................................................7
6.1.
DIGITAL I/O PINS.........................................................................................................................................................7
ANALOG I/O PINS ........................................................................................................................................................7
FILTER/REFERENCE......................................................................................................................................................8
POWER/GROUND..........................................................................................................................................................8
6.2.
6.3.
6.4.
7.
FUNCTIONAL DESCRIPTION.......................................................................................................................................9
7.1.
7.2.
POWER .........................................................................................................................................................................9
RESET ..........................................................................................................................................................................9
7.2.1. Power-On Reset (POR) ..........................................................................................................................................9
7.3.
CLOCKING..................................................................................................................................................................10
7.3.1. Phase-Locked Loop ..............................................................................................................................................10
7.3.2. I2S Stereo Data Interface......................................................................................................................................11
7.4.
DIGITAL DATA INTERFACE ........................................................................................................................................12
7.4.1. Stereo I2S/PCM Interface .....................................................................................................................................12
7.5.
AUDIO DATA PATH ....................................................................................................................................................15
7.5.1. Vref.......................................................................................................................................................................15
7.5.2. Stereo ADC...........................................................................................................................................................15
7.5.3. Stereo DAC...........................................................................................................................................................15
7.6.
MIXERS......................................................................................................................................................................16
7.6.1. Headphone Mixer.................................................................................................................................................16
7.6.2. MONO Mixer........................................................................................................................................................16
7.6.3. Speaker Mixer.......................................................................................................................................................17
7.6.4. ADC Record Mixer...............................................................................................................................................17
7.7.
ANALOG AUDIO INPUT PATH .....................................................................................................................................18
7.7.1. Line Input .............................................................................................................................................................18
7.7.2. AUXiliary Input ....................................................................................................................................................18
7.7.3. Microphone Input.................................................................................................................................................18
7.8.
ANALOG AUDIO OUTPUT DATA PATH .......................................................................................................................19
7.8.1. LINE Output .........................................................................................................................................................19
7.8.2. Headphone Output................................................................................................................................................20
7.8.3. MONO Output......................................................................................................................................................20
7.9.
7.10.
7.10.1.
7.10.2.
7.11.
7.11.1.
AVC CONTROL..........................................................................................................................................................21
HARDWARE SOUND EFFECTS .....................................................................................................................................23
Equalizer Block................................................................................................................................................23
Pseudo Stereo and Spatial 3D Sound ..............................................................................................................23
I2C CONTROL INTERFACE ..........................................................................................................................................24
Addressing Setting ...........................................................................................................................................24
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7.11.2.
Complete Data Transfer ..................................................................................................................................24
7.12.
7.13.
7.14.
7.15.
7.16.
ODD-ADDRESSED REGISTER ACCESS.........................................................................................................................25
POWER MANAGEMENT...............................................................................................................................................25
GPIO AND JACK DETECT FUNCTION..........................................................................................................................26
INTERNAL EVENT SIGNAL INTERRUPT .......................................................................................................................27
HEADPHONE DEPOP ...................................................................................................................................................27
8.
MIXER REGISTERS LIST.............................................................................................................................................28
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
REG-00H: RESET ........................................................................................................................................................28
REG-02H: LINE OUTPUT VOLUME..............................................................................................................................28
REG-04H: HEADPHONE OUTPUT VOLUME .................................................................................................................29
REG-06H: MONO_OUT/AUXOUT VOLUME ...........................................................................................................30
REG-08H: AUXIN VOLUME ......................................................................................................................................30
REG-0AH: LINE_IN VOLUME ...................................................................................................................................31
REG-0CH: STEREO DAC VOLUME ..........................................................................................................................31
REG-0EH: MIC VOLUME ...........................................................................................................................................32
REG-10H: MIC ROUTING CONTROL...........................................................................................................................32
REG-12H: ADC RECORD GAIN ..................................................................................................................................33
REG-14H: ADC RECORD MIXER CONTROL................................................................................................................33
REG-16H: AVOL SOFT VOLUME CONTROL TIME........................................................................................................34
REG-1CH: OUTPUT MIXER CONTROL ........................................................................................................................34
REG-22H: MICROPHONE CONTROL ............................................................................................................................35
REG-34H: DIGITAL AUDIO INTERFACE CONTROL ......................................................................................................35
REG-36AH: STEREO AD/DA CLOCK CONTROL .........................................................................................................36
REG-38H: COMPANDING CONTROL............................................................................................................................37
REG-3AH: POWER MANAGEMENT ADDITION 1..........................................................................................................37
8.9.
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
8.17.
8.18.
8.18.1.
8.18.2.
Headphone Output Amplifier Configuration ...................................................................................................38
Auxiliary Output Amplifier Configuration.......................................................................................................38
REG-3CH: POWER MANAGEMENT ADDITION 2..........................................................................................................39
REG-3EH: POWER MANAGEMENT ADDITION 3 ..........................................................................................................40
REG-40H: ADDITIONAL CONTROL REGISTER .............................................................................................................41
REG-42H: GLOBAL CLOCK CONTROL REGISTER........................................................................................................42
REG-44H: PLL CONTROL REGISTER ..........................................................................................................................42
8.19.
8.20.
8.21.
8.22.
8.23.
8.23.1.
8.23.2.
8.23.3.
Reg-44h: PLL Control Register.......................................................................................................................42
PLL Clock Setting Table for 48K: (Unit: MHz)...............................................................................................43
PLL Clock Setting Table for 44.1K: (Unit: MHz)............................................................................................43
8.24.
8.25.
8.26.
8.27.
8.28.
8.29.
8.30.
8.31.
8.32.
8.33.
8.34.
8.35.
8.36.
8.37.
8.38.
8.39.
8.40.
8.41.
8.42.
REG-4AH: GPIO_OUTPUT PIN CONTROL ..................................................................................................................43
REG-4CH: GPIO PIN CONFIGURATION.......................................................................................................................44
REG-4EH: GPIO PIN POLARITY .................................................................................................................................44
REG-50H: GPIO PIN STICKY......................................................................................................................................45
REG-52H: GPIO PIN WAKE-UP..................................................................................................................................45
REG-54H: GPIO PIN STATUS .....................................................................................................................................46
REG-56H: PIN SHARING .............................................................................................................................................46
REG-58H: OVER-CURRENT STATUS ...........................................................................................................................46
REG-5AH: JACK DETECT CONTROL REGISTER...........................................................................................................47
REG-5EH: MISC CONTROL........................................................................................................................................47
REG-60H: STEREO AND SPATIAL EFFECT BLOCK CONTROL.......................................................................................48
REG-62H: EQ CONTROL.............................................................................................................................................49
REG-66H: EQ MODE CHANGE ENABLE......................................................................................................................50
REG-68H: AVC CONTROL..........................................................................................................................................50
REG-6AH: INDEX ADDRESS .......................................................................................................................................51
REG-6CH: INDEX DATA .............................................................................................................................................51
INDEX-00H: EQ BAND-0 COEFFICIENT (LP0: A1) ......................................................................................................51
INDEX-01H: EQ BAND-0 GAIN (LP0: HO)..................................................................................................................51
INDEX-02H: EQ BAND-1 COEFFICIENT (BP1: A1)......................................................................................................51
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8.43.
8.44.
8.45.
8.46.
8.47.
8.48.
8.49.
8.50.
8.51.
8.52.
8.53.
8.54.
8.55.
8.56.
8.57.
8.58.
8.59.
8.60.
8.61.
8.62.
INDEX-03H: EQ BAND-1 COEFFICIENT (BP1: A2)......................................................................................................52
INDEX-04H: EQ BAND-1 GAIN (BP1: HO) .................................................................................................................52
INDEX-05H: EQ BAND-2 COEFFICIENT (BP2: A1)......................................................................................................52
INDEX-06H: EQ BAND-2 COEFFICIENT (BP2: A2)......................................................................................................52
INDEX-07H: EQ BAND-2 GAIN (BP2: HO) .................................................................................................................52
INDEX-08H: EQ BAND-3 COEFFICIENT (BP3: A1)......................................................................................................53
INDEX-09H: EQ BAND-3 COEFFICIENT (BP3: A2)......................................................................................................53
INDEX-0AH: EQ BAND-3 GAIN (BP3: HO).................................................................................................................53
INDEX-0BH: EQ BAND-4 COEFFICIENT (HPF: A1).....................................................................................................53
INDEX-0CH: EQ BAND-4 GAIN (HPF: HO) ................................................................................................................53
INDEX-11H: EQ INPUT VOLUME CONTROL ................................................................................................................54
INDEX-12H: EQ OUTPUT VOLUME CONTROL.............................................................................................................54
INDEX-21H: AUTO VOLUME CONTROL REGISTER 1...................................................................................................54
INDEX-22H: AUTO VOLUME CONTROL REGISTER 2...................................................................................................54
INDEX-23H: AUTO VOLUME CONTROL REGISTER 3...................................................................................................55
INDEX-24H: AUTO VOLUME CONTROL REGISTER 4...................................................................................................55
INDEX-25H: AUTO VOLUME CONTROL REGISTER 5...................................................................................................55
INDEX-39H: DIGITAL INTERNAL REGISTER ................................................................................................................56
REG-7CH: VENDOR ID 1 .........................................................................................................................................56
REG-7EH: VENDOR ID 2 .........................................................................................................................................56
9.
ELECTRICAL CHARACTERISTICS ..........................................................................................................................57
9.1.
DC CHARACTERISTICS...............................................................................................................................................57
9.1.1. Absolute Maximum Ratings..................................................................................................................................57
9.1.2. Recommended Operating Conditions...................................................................................................................57
9.1.3. Static Characteristics ...........................................................................................................................................57
9.2.
9.3.
ANALOG PERFORMANCE CHARACTERISTICS..............................................................................................................58
SIGNAL TIMING..........................................................................................................................................................60
9.3.1. I2C Control Interface............................................................................................................................................60
9.3.2. I2S Master Mode...................................................................................................................................................61
9.3.3. I2S Slave Mode......................................................................................................................................................62
10.
11.
12.
13.
APPLICATION CIRCUIT .........................................................................................................................................63
MECHANICAL DIMENSIONS.................................................................................................................................64
APPENDIX A: STEREO I2S CLOCK TABLE.........................................................................................................66
ORDERING INFORMATION...................................................................................................................................67
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List of Tables
TABLE 1. DIGITAL I/O PINS.........................................................................................................................................................7
TABLE 2. ANALOG I/O PINS ........................................................................................................................................................7
TABLE 3. FILTER/REFERENCE .....................................................................................................................................................8
TABLE 4. POWER/GROUND..........................................................................................................................................................8
TABLE 5. RESET OPERATION.......................................................................................................................................................9
TABLE 6. POWER-ON RESET VOLTAGE .......................................................................................................................................9
TABLE 7. CLOCK SETTING TABLE FOR 48K (UNIT: MHZ).........................................................................................................10
TABLE 8. CLOCK SETTING TABLE FOR 44.1K (UNIT: MHZ)......................................................................................................11
TABLE 9. MONO/AUXOUT OUTPUT SIGNAL TABLE ..............................................................................................................20
TABLE 10. ADDRESSING SETTING...............................................................................................................................................24
TABLE 11. REG-00H: RESET .......................................................................................................................................................28
TABLE 12. REG-02H: LINE OUTPUT VOLUME .............................................................................................................................28
TABLE 13. REG-04H: HEADPHONE OUTPUT VOLUME.................................................................................................................29
TABLE 14. REG-06H: MONO_OUT/AUXOUT VOLUME...........................................................................................................30
TABLE 15. REG-08H: AUXIN VOLUME......................................................................................................................................30
TABLE 16. REG-0AH: LINE_IN VOLUME...................................................................................................................................31
TABLE 17. REG-0CH: STEREO DAC VOLUME..........................................................................................................................31
TABLE 18. REG-0EH: MIC VOLUME...........................................................................................................................................32
TABLE 19. REG-10H: MIC ROUTING CONTROL ..........................................................................................................................32
TABLE 20. REG-12H: ADC RECORD GAIN..................................................................................................................................33
TABLE 21. REG-14H: ADC RECORD MIXER CONTROL ...............................................................................................................33
TABLE 22. REG-16H: AVOL SOFT VOLUME CONTROL TIME.......................................................................................................34
TABLE 23. REG-1CH: OUTPUT MIXER CONTROL........................................................................................................................34
TABLE 24. REG-22H: MICROPHONE CONTROL............................................................................................................................35
TABLE 25. REG-34H: AUDIO INTERFACE ....................................................................................................................................35
TABLE 26. REG-36H: STEREO AD/DA CLOCK CONTROL ...........................................................................................................36
TABLE 27. REG-38H: COMPANDING CONTROL ...........................................................................................................................37
TABLE 28. REG-3AH: POWER MANAGEMENT ADDITION 1 .........................................................................................................37
TABLE 29. HEADPHONE OUTPUT AMPLIFIER CONFIGURATION...................................................................................................38
TABLE 30. AUXILIARY OUTPUT AMPLIFIER CONFIGURATION ....................................................................................................38
TABLE 31. REG-3CH: POWER MANAGEMENT ADDITION 2 .........................................................................................................39
TABLE 32. REG-3EH: POWER MANAGEMENT ADDITION 3..........................................................................................................40
TABLE 33. REG-40H: ADDITIONAL CONTROL REGISTER.............................................................................................................41
TABLE 34. REG-42H: GLOBAL CLOCK CONTROL REGISTER .......................................................................................................42
TABLE 35. REG-44H: PLL CONTROL REGISTER..........................................................................................................................42
TABLE 36. PLL CLOCK SETTING TABLE FOR 48K: (UNIT: MHZ) ...............................................................................................43
TABLE 37. PLL CLOCK SETTING TABLE FOR 44.1K: (UNIT: MHZ) ............................................................................................43
TABLE 38. REG-4CH: GPIO_OUTPUT PIN CONTROL..................................................................................................................43
TABLE 39. REG-4CH: GPIO PIN CONFIGURATION......................................................................................................................44
TABLE 40. REG-4EH: GPIO PIN POLARITY.................................................................................................................................44
TABLE 41. REG-50H: GPIO PIN STICKY .....................................................................................................................................45
TABLE 42. REG-52H: GPIO PIN WAKE-UP .................................................................................................................................45
TABLE 43. REG-54H: GPIO PIN STATUS.....................................................................................................................................46
TABLE 44. REG-56H: PIN SHARING.............................................................................................................................................46
TABLE 45. REG-58H: OVER-CURRENT STATUS...........................................................................................................................46
TABLE 46. REG-5AH: JACK DETECT CONTROL REGISTER ..........................................................................................................47
TABLE 47. REG-5EH: MISC CONTROL .......................................................................................................................................47
TABLE 48. REG-60H: STEREO AND SPATIAL EFFECT BLOCK CONTROL ......................................................................................48
TABLE 49. REG-62H: EQ CONTROL ............................................................................................................................................49
TABLE 50. REG-66H: EQ MODE CHANGE ENABLE .....................................................................................................................50
TABLE 51. REG-68H: AVC CONTROL.........................................................................................................................................50
TABLE 52. REG-6AH: INDEX ADDRESS.......................................................................................................................................51
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TABLE 53. REG-6CH: INDEX DATA.............................................................................................................................................51
TABLE 54. INDEX-00H: EQ BAND-0 COEFFICIENT (LP0: A1)......................................................................................................51
TABLE 55. INDEX-01H: EQ BAND-0 GAIN (LP0: HO).................................................................................................................51
TABLE 56. INDEX-02H: EQ BAND-1 COEFFICIENT (BP1: A1) .....................................................................................................51
TABLE 57. INDEX-03H: EQ BAND-1 COEFFICIENT (BP1: A2) .....................................................................................................52
TABLE 58. INDEX-04H: EQ BAND-1 GAIN (BP1: HO).................................................................................................................52
TABLE 59. INDEX-05H: EQ BAND-2 COEFFICIENT (BP2: A1) .....................................................................................................52
TABLE 60. INDEX-06H: EQ BAND-2 COEFFICIENT (BP2: A2) .....................................................................................................52
TABLE 61. INDEX-07H: EQ BAND-2 GAIN (BP2: HO).................................................................................................................52
TABLE 62. INDEX-08H: EQ BAND-3 COEFFICIENT (BP3: A1) .....................................................................................................53
TABLE 63. INDEX-09H: EQ BAND-3 COEFFICIENT (BP3: A2) .....................................................................................................53
TABLE 64. INDEX-0AH: EQ BAND-3 GAIN (BP3: HO)................................................................................................................53
TABLE 65. INDEX-0BH: EQ BAND-4 COEFFICIENT (HPF: A1) ....................................................................................................53
TABLE 66. INDEX-0CH: EQ BAND-4 GAIN (HPF: HO)................................................................................................................53
TABLE 67. INDEX-11H: EQ INPUT VOLUME CONTROL ...............................................................................................................54
TABLE 68. INDEX-12H: EQ OUTPUT VOLUME CONTROL............................................................................................................54
TABLE 69. INDEX-21H: AUTO VOLUME CONTROL REGISTER 1 ..................................................................................................54
TABLE 70. INDEX-22H: AUTO VOLUME CONTROL REGISTER 2 ..................................................................................................54
TABLE 71. INDEX-23H: AUTO VOLUME CONTROL REGISTER 3 ..................................................................................................55
TABLE 72. INDEX-24H: AUTO VOLUME CONTROL REGISTER 4 ..................................................................................................55
TABLE 73. INDEX-25H: AUTO VOLUME CONTROL REGISTER 5 ..................................................................................................55
TABLE 74. INDEX-39H: DIGITAL INTERNAL REGISTER................................................................................................................56
TABLE 75. REG-7CH: VENDOR ID 1.........................................................................................................................................56
TABLE 76. REG-7EH: VENDOR ID 2.........................................................................................................................................56
TABLE 77. ABSOLUTE MAXIMUM RATINGS................................................................................................................................57
TABLE 78. RECOMMENDED OPERATING CONDITIONS.................................................................................................................57
TABLE 79. STATIC CHARACTERISTICS ........................................................................................................................................57
TABLE 80. ANALOG PERFORMANCE CHARACTERISTICS .............................................................................................................58
TABLE 81. I2C TIMING ................................................................................................................................................................60
TABLE 82. TIMING OF I2S MASTER MODE ..................................................................................................................................61
TABLE 83. I2S SLAVE MODE TIMING ..........................................................................................................................................62
TABLE 84. ORDERING INFORMATION..........................................................................................................................................67
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List of Figures
FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................4
FIGURE 2. AUDIO MIXER PATH ...................................................................................................................................................5
FIGURE 3. PIN ASSIGNMENTS ......................................................................................................................................................6
FIGURE 4. AUDIO SYSCLK ......................................................................................................................................................10
FIGURE 5. PCM MONO DATA MODE A FORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0, PCM_MODE_SEL=0) ......................12
FIGURE 6. PCM MONO DATA MODE A FORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=1, PCM_MODE_SEL=0) ......................12
FIGURE 7. PCM MONO DATA MODE B FORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0, PCM_MODE_SEL=1) ......................13
FIGURE 8. PCM STEREO DATA MODE A FORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0, PCM_MODE_SEL=0)....................13
FIGURE 9. PCM STEREO DATA MODE B FORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0, PCM_MODE_SEL=1) ....................13
FIGURE 10. I2S DATA FORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0)...................................................................................14
FIGURE 11. LEFT JUSTIFIED DATA FORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0)...............................................................14
FIGURE 12. RIGHT JUSTIFIED DATA FORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0).............................................................14
FIGURE 13. AUTO VOLUME CONTROL BLOCK DIAGRAM............................................................................................................22
FIGURE 14. AVC BEHAVIOR.......................................................................................................................................................22
FIGURE 15. DATA TRANSFER OVER I2C CONTROL INTERFACE ...................................................................................................24
FIGURE 16. WRITE WORD PROTOCOL .......................................................................................................................................25
FIGURE 17. READ WORD PROTOCOL.........................................................................................................................................25
FIGURE 18. GPIO IMPLEMENTATION ..........................................................................................................................................26
FIGURE 19. JACK DETECT AND IRQ LOGIC.................................................................................................................................27
FIGURE 20. POWER CONTROL TO MIC INPUT .............................................................................................................................41
FIGURE 21. I2C CONTROL INTERFACE.........................................................................................................................................60
FIGURE 22. TIMING OF I2S MASTER MODE .................................................................................................................................61
FIGURE 23. I2S SLAVE MODE TIMING.........................................................................................................................................62
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1. General Description
The ALC5623 is a highly-integrated I2S/PCM interface audio codec with multiple input/output ports and
is designed for mobile computing and communications. It provides a Stereo Hi-Fi DAC for playback and
Stereo ADC for recording via the I2S/PCM interface.
To reduce component count, the device can connect directly to:
• MONO or stereo differential analog inputs
• LINE_IN stereo Single-Ended analog inputs
• AUX_IN Single-Ended analog inputs
• Stereo Headphone Output
• Single-end stereo configurable to AUXOUT or BTL MONO_OUT
• Stereo LINE_OUT Single Ended or Bridge-Tied Load (BTL) configurable
Multiple analog input and output pins are provided for seamless integration with analog connected
wireless communication devices. Differential input/output connections efficiently reduce noise
interference, providing better sound quality. Additionally, a flexible hardware 5-band equalizer with
configurable gain, bandwidth, and center frequency, enriches the sound experience.
The ALC5623 AVDD operates at supply voltages from 2.3V to 3.6V. DVDD operates from 1.71V to
3.6V. To extend battery life, each section of the device can be powered down individually under software
control. Leakage current in maximum power saving state is less than 10µA.
The ALC5623 is available in a 5x5mm ‘Green’ QFN-32 package, making it ideal for use in handheld
portable systems.
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2. Features
Digital-to-Analog Converter with 92dB SNR and –85dB THD+N
Analog-to-Digital Converter with 85dB SNR and –80dB THD+N
Two analog stereo single-ended inputs, LINE-IN_L/R and AUXIN_L/R
Stereo differential analog microphone inputs, with boost pre-amplifiers (+20/+30dB)
One Stereo single-ended output, LINE_OUT
Stereo headphone output with on-chip 45mW headphone driver (AVDD=3.3V, 16Ω load)
Differential MONO_OUT configurable to AUXOUT (AVDD=3.3V, 32Ω load)
Audio jack insert detection and microphone switch detection
Power management and enhanced power saving
Supports digital 5-band equalizer (EQ)
Supports digital spatial sound and pseudo stereo effect
Supports pop noise suppression
Internal PLL can receive wide range of clock input
Digital power supplies from 1.71V to 3.6V;
Analog power and headphone power supplied from 2.3V to 3.6V
Supports soft-mute function
32-pin QFN package
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3. System Applications
Tablet PC system/Ultra-Mobile PC (UMPC)
Personal Digital Assistants (PDA) or PDA Phone
Multimedia Phone Applications
Portable Navigation Device (PND)
Bluetooth Headphone
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4. Block Diagrams
4.1. Function Block
Figure 1. Block Diagram
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4.2. Audio Mixer Path
Reg62[11]
Reg1C[7:6]
Reg1C[9:8]
Reg1C[11:10]
Reg62[11]
Figure 2. Audio Mixer Path
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5. Pin Assignments
Figure 3. Pin Assignments
5.1. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3. The version number is shown
in the location marked ‘V’.
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6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Characteristic Definition
Name
Type Pin Description
LRCK
IO
7
8
9
Digital Audio Synchronous Signal
Digital Audio Serial Clock
Serial ADC Data Output
Master: VOL =0.1*DVDD, VOH =0.9*DVDD
Slave: Schmitt trigger
Master: VOL =0.1*DVDD, VOH =0.9*DVDD
Slave: Schmitt trigger
VOL =0.1*DVDD, VOH =0.9*DVDD
Schmitt trigger
BCLK
IO
SADC
SDAC
MCLK
GPIO/
IRQ/
PLL_OUT
SCLK
SDA
O
I
10 Serial DAC Data Input
11 Master Clock Input
15 General Purpose Input And Output/
Interrupt Output/
I
Schmitt trigger
IO/
O/
O
I
GPIO: Input/Output
IRQOUT: Output
PLL_OUT: Output
PLL Output
16 I2C Clock
17 I2C Data
Schmitt trigger
IO
Schmitt trigger
Total: 8 Pins
6.2. Analog I/O Pins
Table 2. Analog I/O Pins
Name
Type
Pin Description
Characteristic Definition
Analog Input (1Vrms)
Analog Input (1Vrms)
Analog Input (1Vrms)
MIC1P
I
I
I
1
2
3
First Mic Positive Input
MIC1N
First Mic Negative Input
LINE_IN_L/JD1
Line Input Left Channel/Jack Detect
Input_1
MIC2P
I
I
I
4
5
6
Second Mic Positive Input
Second Mic Negative Input
Analog Input (1Vrms)
Analog Input (1Vrms)
MIC2N
LINE_IN_R/JD2
Line Input Right Channel/Jack Detect Analog Input (1Vrms)
Input_2
AUXIN_L
AUXIN_R
I
I
19
20
21
Auxiliary Input Left Channel
Auxiliary Input Right Channel
Analog Input (1Vrms)
Analog Input (1Vrms)
Analog Output (1Vrms)
AUXOUT_L/
MONO_OUT
O
Positive Mono Output/Auxiliary
Output Left Channel
AUXOUT_R/
MONO_OUT_N
O
22
Negative Mono Output/Auxiliary
Output Right Channel
Analog Output (1Vrms)
LINE_OUT
LINE_OUT_N
HP_OUT_R
HP_OUT_L
O
O
O
O
23
25
29
30
LINE Output
Analog Output(1Vrms)
Analog Output (1Vrms)
Analog Output (1Vrms)
Analog Output (1Vrms)
Total: 14 Pins
Negative LINE Output
Headphone Output Right Channel
Headphone Output Left Channel
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6.3. Filter/Reference
Table 3. Filter/Reference
Name
Type
IO
O
Pin Description
Characteristic Definition
NC/Cdepop
VREF
18
27
32
NC/De-Pop Capacitor
0.1µf capacitor to analog ground
4.7µf capacitor to analog ground
Internal Reference Voltage
MIC BIAS Voltage Output
MICBIAS
O
Programmable Analog DC output with 3mA drive
Total: 3 Pins
6.4. Power/Ground
Table 4. Power/Ground
Name
Type Pin Description
Characteristic Definition
DGND
DCVDD
DBVDD
AGND2
AVDD2
AGND
AVDD
P
P
P
P
P
P
P
12 Digital GND
13 Digital VDD
14 Digital VDD
24 Analog GND
26 Analog VDD
28 Analog GND
31 Analog VDD
-
1.71V~3.6V (Core)
1.71V~3.6V (IO Buffer)
-
2.3V~3.6V
-
2.3V~3.6V
Total: 7 Pins
Note: DBVDD ≥ DCVDD, and AVDD2 = AVDD ≥ DCVDD.
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7. Functional Description
7.1. Power
The ALC5623 has many power blocks. AVDD and AVDD2 operates between 2.3V and 3.6V. DBVDD
and DCVDD operate between 1.71V and 3.6V. The ALC5623 must handle ratio control between the
different power blocks. The power supplier limit conditions are DBVDD ≥ DCVDD, and AVDD2 ≥
AVDD ≥ DCVDD.
7.2. Reset
There are two types of reset operation: Power-On Reset (POR) and Register reset.
Table 5. Reset Operation
Reset Type
Trigger Condition
Monitor digital power supply voltage reach VPOR Power-On Reset.
Resets all hardware logic and all registers to default
CODEC Response
POR
values.
Register Reset
Write Reg-00h
Resets all registers to default values except PLL
related register
7.2.1.
Power-On Reset (POR)
When powered on, DCVDD passes through the VPOR band of the ALC5623 (VPORH ~VPORL). A Power-On
Reset (POR) will generate an internal reset signal (POR reset ‘LOW’) to reset the whole chip.
Table 6. Power-On Reset Voltage
Symbol
VPOR_ON
VPOR_OFF
Min
1.0
-
Typical
Max
1.6
-
Unit
V
-
1.3
V
Note: VPOR_OFF must be below VPOR_ON
.
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7.3. Clocking
The Audio SYSCLK can be selected from MCLK or PLL. The PLL clock source can be selected from
MCLK or BCLK. The ALC5623 only supports 256Fs or 384Fs as Audio SYSCLK (used as Stereo I2S
clock).
Figure 4. Audio SYSCLK
7.3.1.
Phase-Locked Loop
A Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz to 40MHz. Typical
choices are 2.048MHz, 4.096MHz, and 13MHz. The source of the PLL can be set to MCLK or BCLK by
setting pll_sour_sel (Reg42[14]).
The source clock of MCLK must be able to drive I2C, and F/W can setup PLL to output the desired
frequency as the SYSCLK.
The PLL transmit formula is: FOUT = (MCLK * (N+2)) / ((M+2) * (K+2)) {Typical K=2}
Table 7. Clock Setting Table for 48K (Unit: MHz)
MCLK
13
N
66
78
94
70
80
81
78
80
78
M
7
FVCO
98.222
98.304
98.304
98.304
98.4
K
2
2
2
2
2
2
2
2
2
FOUT
24.555
24.576
24.576
24.576
24.6
3.6864
2.048
4.096
12
1
0
1
8
15.36
16
11
11
14
14
98.068
98.462
98.4
24.517
24.615
24.6
19.2
19.68
98.4
24.6
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Table 8. Clock Setting Table for 44.1K (Unit: MHz)
MCLK
13
N
68
72
86
64
66
63
66
64
67
M
8
FVCO
91
K
2
2
2
2
2
2
2
2
2
FOUT
22.75
3.6864
2.048
4.096
12
1
90.931
90.112
90.112
90.667
90.764
90.667
90.514
90.528
22.733
22.528
22.528
22.667
22.691
22.667
22.629
22.632
0
1
7
15.36
16
9
10
12
13
19.2
19.68
After a Cold Reset, PLL related Registers are reset to default values, however, they are not reset to
default values after a soft-reset (write Reg00).
7.3.2.
I2S Stereo Data Interface
The ALC5623 supports the I2S digital interface for Stereo Audio. The stereo audio digital interface is
used to input data to the stereo DAC or output data from the stereo ADC. The Stereo Audio Digital
Interface can be configured as Master mode or Slave mode. For the Stereo I2S Interface, the source
system clock is always input from MCLK. Refer to section 12 Appendix A: Stereo I2S Clock Table,
page 66 for details.
Master Mode
In master mode (stereo_i2s_mode_sel=0), BCLK and LRCK are configured as output. When
sel_sysclk=0, MCLK is used as Stereo SYSCLK. When PLL is enabled and sel_sysclk=1, MCLK is
suggested to provide frequencies shown in Table 7 Clock Setting Table for 48K (Unit: MHz) and Table 8
Clock Setting Table for 44.1K (Unit: MHz). PLL can be configured to support 44.1K and 48K base
sampling rate.
Slave Mode
In slave mode (stereo_i2s_mode_sel=1), BCLK/LRCK is configured as input. MCLK should provide the
BCLK synchronized clock externally as the Stereo_SYSCLK.
Note: The ALC5623 does not support different sample rates between SDAC and SADC in
Stereo_I2S/PCM.
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7.4. Digital Data Interface
7.4.1.
Stereo I2S/PCM Interface
The stereo I2S/PCM interface can be configured as Master mode or Slave mode. Four audio data formats
are supported:
• PCM mode
• Left justified mode
• Right justified mode
• I2S mode
Figure 5. PCM Mono Data Mode A Format (stereo_i2s_bclk_polarity_ctrl=0, pcm_mode_sel=0)
1/ Fs
LRCK
BLCK
DACDAT/
1
2
n-1 n
ADCDAT
MSB
LSB
Figure 6. PCM Mono Data Mode A Format (stereo_i2s_bclk_polarity_ctrl=1, pcm_mode_sel=0)
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Figure 7. PCM Mono Data Mode B Format (stereo_i2s_bclk_polarity_ctrl=0, pcm_mode_sel=1)
Figure 8. PCM Stereo Data Mode A Format (stereo_i2s_bclk_polarity_ctrl=0, pcm_mode_sel=0)
Figure 9. PCM Stereo Data Mode B Format (stereo_i2s_bclk_polarity_ctrl=0, pcm_mode_sel=1)
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Figure 10. I2S Data Format (stereo_i2s_bclk_polarity_ctrl=0)
Figure 11. Left Justified Data Format (stereo_i2s_bclk_polarity_ctrl=0)
Figure 12. Right Justified Data Format (stereo_i2s_bclk_polarity_ctrl=0)
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7.5. Audio Data Path
7.5.1.
Vref
Vref is the reference voltage for all analog blocks. An external 1µF Capacitor connected to AGND is
required. The default status of Vref is enabled after power on. Driver can set Index-39[11]=0b in order to
enable power control bit of Reg-3C[13]:pow_vref.
7.5.2.
Stereo ADC
The stereo ADC is used for recording stereo sound. The sample rate of the stereo ADC is independent of
the stereo DAC sample rate. In order to save power, the left and right ADC can be powered down
separately by setting adc_l_vol and adc_r_vol
The sample rate of the Stereo ADC is the same as the sample rate of Stereo DAC (described in the
following section).
7.5.3.
Stereo DAC
The stereo DAC can be configured to different sample rates by driving 256Fs/384Fs into audio SYSCLK
with setting divider properly (Reg36). adda_osr is used to control the over sample rate clock divider of
the DA filter to 128Fs or 64Fs.
Performance of 128Fs is better than 64Fs but with much higher power consumption. Refer to section 12
Appendix A: Stereo I2S Clock Table, page 66 for detailed settings.
dac_l_vol & dac_r_vol can be used to control the DAC output volume.
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7.6. Mixers
The ALC5623 supports four mixers for all audio function requirements:
• Headphone mixer for 2 channels
• MONO mixer
• LINE_OUT mixer
• ADC record mixer
7.6.1.
Headphone Mixer
The headphone mixer is used to drive stereo output, including HP_OUT_L/R, LINE_OUT, and
MONO_OUT (AUXOUT_L/R). The output of the headphone mixer can be input to the ADC record
mixer.
The following signals can be mixed into the headphone mixer:
• LINE-IN_L/R (Controlled by Reg0A)
• AUXIN_L/R (Controlled by Reg08)
• MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
• Stereo DAC output (Controlled by Reg0C)
• ADC record mixer output (Controlled by Reg12 & Reg14).
When the LINE_OUT source is from the HP_mixer, LINE_OUT can be configured to L/R, L+R, and
L/LN by setting lio_outn_source. The HP mixer can be powered down by setting pow_mix_hp_l and
pow_mix_hp_r.
7.6.2.
MONO Mixer
The MONO mixer is used to drive MONO_OUT (AUXOUT_L/R) and LINE_OUT. The output of the
MONO mixer can be input to the ADC record mixer. The output of the MONO mixer is two channels
with the same signal.
The following signals can be mixed into the MONO mixer:
• LINE-IN_L/R (Controlled by Reg0A)
• AUXIN_L/R (Controlled by Reg08)
• MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
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• Stereo DAC output (Controlled by Reg0C)
• ADC record mixer output (Controlled by Reg12 & Reg14).
Note: The MONO mixer can be powered down by setting pow_mix_mono.
7.6.3.
Speaker Mixer
The speaker mixer is the same as the MONO mixer and is used to drive MONO_OUT (AUXOUT_L/R)
and LINE_OUT. The output of the speaker mixer can be input to the ADC record mixer. The output of
the speaker mixer is two channels with the same signal.
The following signals can be mixed into the speaker mixer:
• LINE-IN_L/R (Controlled by Reg0A)
• AUXIN_L/R (Controlled by Reg08)
• MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
• Stereo DAC output (Controlled by Reg0C)
Note: The speaker mixer can be powered down by setting pow_mix_spk.
7.6.4.
ADC Record Mixer
The ADC record mixer is used to mix analog signals as input to the Stereo ADC for recording. Output of
the ADC record mixer can be input to the headphone mixer, MONO mixer, and speaker mixer.
The following signals can be mixed into the ADC record mixer:
• LINE-IN_L/R (Controlled by Reg0A)
• AUXIN_L/R (Controlled by Reg08)
• MIC1P/N and MIC2P/N (Controlled by Reg22)
• Headphone mixer output
• MONO mixer output
• Speaker mixer output
Note: The ADC record mixer can be powered down by setting pow_mix_adc_rec_l &
pow_mix_adc_rec_r.
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7.7. Analog Audio Input Path
The ALC5623 supports four Analog Audio Input paths:
• Line_IN_L/R
• AUXIN_L/R
• MIC1
• MIC2
7.7.1.
Line Input
LINE_IN_L and LINE_IN_R provide 2-channel stereo single-ended input that can be mixed into any
analog output mixer and ADC record mixer.
The LINE_IN_L/R volume and mute are controlled by Reg0A.
pow_li_l_vol and pow_li_r_vol can be used to power down LINE_IN volume control.
LINE_IN_L is pin shared to JD1 and can be configured by lineinl_pin_sharing.
LINE_IN_R is pin shared to JD2 and can be configured by lineinr_pin_sharing.
7.7.2.
AUXiliary Input
AUXIN_L and AUXIN_R provide 2-channel stereo single-ended input that can be mixed into the ADC
record mixer and any analog output mixer.
AUXIN_L/R volume and mute are controlled by Reg08.
pow_auxin_l_vol and pow_auxin_r_vol can be used to power down AUXIN_L/R volume control.
7.7.3.
Microphone Input
MIC1P/N and MIC2P/N provide 2-channel stereo differential or single-ended input, via mic1_diff_ctrl
and mic2_diff_ctrl, that can be mixed into the ADC record mixer, or any analog output mixer. MIC1P
and MIC2P are main inputs when differential mode is disabled.
The ALC5623 microphone input boost provides 20/30dB boost, set by mic1_boost_ctrl (for MIC1) and
mic2_boost_ctrl (for MIC2). The MIC1/2 volume and mute are controlled by Reg0E.
pow_mic1_vol & pow_mic2_vol can be used to power down the MIC1/2 volume control path.
pow_mic1_admixer & pow_mic2_admixer can be used to power down the MIC1/2 admixer path.
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7.8. Analog Audio Output Data Path
The ALC5623 supports three Analog Audio output paths:
• LINE_OUT
• HP_OUT_L/R
• MONO_OUT (AUX_OUT_L/R).
7.8.1.
LINE Output
LINE_OUT provides one channel mono Differential output and can be configured to two-channel stereo
Single-Ended output
The LINE_OUT source is selected in lio_vol_in_sel. Sources are shown below:
• Vmid
• Headphone left mixer
• Speaker mixer
• MONO mixer
The LINE_OUT volume and mute are controlled by Reg02. Also, Reg3E[12]: pow_lineout can be used to
power down LINE output. pow_LineOut_amp (Reg3C[15]) is used to power down the Line Out
Amplifier.
LINE_OUT supports a softmute function and a zero cross detect function which can be enable at
lio_l_soft-mute_en/lio_r_soft-mute_en and lio_l_dezero/lio_r_dezero depends on the setting of
lio_vol_in_sel. If LINE_OUT is configured to differential, only lio_l_soft-mute_en and lio_l_dezero can
be used to control softmute and zero cross of LINE_OUT.
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7.8.2.
Headphone Output
HP_OUT_L/R provides stereo Single-Ended output. The source of HP_OUT_L/R can be selected from
hp_l_in_sel & hp_r_in_sel (Reg1C[9:8]).
• Vmid
• Headphone mixer
The HP_OUT_L/R volume and mute are controlled by Reg04.
pow_hp_l_vol (Reg3E[10]) and pow_hp_r_vol (Reg3E[9])can be used to power down the HP output
volume
HP_OUT supports soft-mute and zero cross detect function, which can be individually enabled at
hp_l_softmute_en/ hp_r_softmute_en and hp_l_dezero/ hp_r_dezero
7.8.3.
MONO Output
MONO_OUT provides one-channel differential MONO_OUT or stereo single-ended AUXOUT_L/R via
se_diff_auxout.
The MONO/AUXOUT source can be selected from Reg1C[7:6], mono_in_sel. Sources are shown below.
• Vmid
• Headphone mixer (L+R)
• Speaker mixer
• MONO mixer
The MONO/AUXOUT output signal depends on the setting of se_diff_auxout & mono_in_sel.
Table 9. MONO/AUXOUT Output Signal Table
mono_in_sel
se_diff_auxout
Differential Mode
Single-Ended Mode
Differential Mode
Single-Ended Mode
Differential Mode
Single-Ended Mode
Differential Mode
Single-Ended Mode
MONO/AUXOUT Output Signal
Vmid
Vmid
Vmid
HP mixer (L/R)
Speaker mixer (L+R)
MONO mixer
L/LN
L/R
(L+R)/(L+R)N
(L+R)/(L+R)
(L+R)/(L+R)N
(L+R)/(L+R)
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MONO/AUXOUT volume and mute are controlled by Reg08.
pow_aux_outl_vol (Reg3E[14]) and pow_aux_outr_vol (Reg3E[13])can be used to power down the
volume of MONO/AUXOUT.
If MONO/AUXOUT is configured to stereo Single-Ended AUXOUT, the soft-mute and zero cross detect
function of MONO/AUXOUT can be enabled at AUXO_l_softmute_en/AUXO_r_softmute_en and
AUXO_l_dezero/AUXO_r_dezero.
If MONO/AUX is configured to mono differential MONO_OUT, only AUXO_l_softmute_en and
AUXO_l_dezero can be used to control soft-mute and zero cross of MONO/AUXOUT.
7.9. AVC Control
The Automatic Volume Control (AVC) function dynamically adjusts the input signal quantized by the
ADC to an expected sound level by setting THmax, THmin, and THnonact (see Figure 14 AVC Behavior,
page 22.
When the average level of input signal is higher than THmax, the AVC will decrease the selected analog
gain to attenuate the quantized Pulse Code Modulation (PCM) signal to a lower amplitude than THmax.
When the average level of input signal is lower than THmin and higher than Thnonact., the AVC will
increase the selected analog gain to amplify the input signal. The quantized Pulse Code Modulation
(PCM) signal is then set to a higher amplitude than THmin. The quantized PCM has an average level
between THmin and THmax.
In order not to output a strong amplified signal when the gain detector input level is transiting from a very
small signal to a normal signal, the AVC block will limit the selected analog gain to unit gain (=0dB)
when the input level of the gain detector is lower than THnonact.
The AVC reference source channel and target channel can be individually set by Reg68: AVC Control.
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The AVC block diagram and behavior is shown in Figure 13 and Figure 14, respectively.
Figure 13. Auto Volume Control Block Diagram
Input Signal
THmax
THmin
THnonact
Output
Signal
Monitor Monitor
Window Window
Figure 14. AVC Behavior
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7.10. Hardware Sound Effects
The Sound Effect block is composed of Pseudo Stereo, Spatial 3D, and Equalizer blocks. The Pseudo
Stereo block is used to convert a MONO source into virtualized stereo output. The Spatial 3D block is a
surround sound generator with adjustable amplitude (Gain) and surround depth (Ratio). The Equalizer
block can be used to compensate for speaker response, or to make environment sound effects, e.g., ‘Pub’,
‘Live’, ‘Rock’,… etc..
7.10.1. Equalizer Block
The Equalizer block cascades 5 bands of equalizer to compensate for speaker response and to emulate
environment sound. One high-pass filter cascaded in the front end is used to drop low frequency tone,
which has a larger amplitude and may damage a mini speaker.
The high-pass filter can also be used to adjust Treble strength with gain control. A low-pass filter with
gain control can adjust the Bass strength. Three bands of bi-quad bandpass filters are used to emulate
environment sounds.
To avoid PCM sample saturation, a digital volume control has 0 ~18dB attenuation in the front of
equalizer is required. A –3 ~ +18dB digital gain control after equalizer is used to compensate PCM output
to suitable level.
The Equalizer source of the ALC5623 can be selected from DAC or ADC. If Equalizer parameters will be
dynamically changed, the driver should set EQ Mode Change enable and disable after the EQ parameters
have been set to new values.
7.10.2. Pseudo Stereo and Spatial 3D Sound
There are two spatial effects in post-processing; the Pseudo-Stereo Effect + Spatial Effect, and the Stereo
Expansion Effect. The Pseudo-Stereo Effect + Spatial Effect converts a MONO signal to a stereo signal
by changing the phase and amplitude of the original signal followed by enhancing the spatial effect. The
Stereo Expansion Effect enhances the spatial effect when the input signal is Stereo.
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7.11. I2C Control Interface
I2C is a 2-wire half-duplex serial communication interface, supporting only slave mode. The host must
support MCLK during register access.
7.11.1. Addressing Setting
Table 10. Addressing Setting
(MSB)
BIT
(LSB)
0
0
1
1
0
1
0
RW
7.11.2. Complete Data Transfer
Data Transfer over I2C Control Interface
Figure 15. Data Transfer Over I2C Control Interface
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Write WORD Protocol
Read WORD Protocol
Figure 16. Write WORD Protocol
1
7
1
1
8
1
7
1
8
1
8
1
1
S
Device Address Wr
A
Register Address
A
S
Device Address Rd
A
Data Byte High
A
Data Byte Low
NA
P
S: Start Condition
Slave Address: 7-bit Device Address
Wr: 0 for Write Command
A: 0 for ACK, 1 for NACK
Data Byte: 16-bit Mixer data
ꢀ: Master-to-Slave
Rd: 1 for Read Command
ꢀ: Slave-to-Master
Command Code: 8-bit Register Address
Figure 17. Read WORD Protocol
7.12. Odd-Addressed Register Access
The ALC5623 will return ‘0000h’ when odd-addressed and unimplemented registers are read.
7.13. Power Management
The ALC5623 supports a grouped power down control register (Reg26). More detailed Power
Management control is supported in Reg 3A, 3C, and 3E. Each particular block will only be active when
both Reg26 and Reg3A/3C/3E are set to ‘Enable’.
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7.14. GPIO and Jack Detect Function
The GPIO pin of the ALC5623 can be configured to PLL_OUT and IRQ_Output by setting Reg-56[1:0]:
gpio_pin_sharing.
The ALC5623 supports one GPIO that can be configured as Input/Output by Reg4C when
gpio_pin_sharing =00’b. When the GPIO is configured as Input, the status will be indicated in Reg54[1].
When the GPIO is configured as Output, Reg5C[1] is used to drive GPIO to High (1b) or Low (0b). The
status can be read in Reg54[1].
In addition, the ALC5623 supports Jack Detect (JD1/JD2) to switch ON/OFF the Analog Output
(Headphone Out, LINE Out, and AUXOUT_L/R).
JD1 and JD2 can be pin-shared from LINE_IN_R/L and are used to enable specified Analog audio output
configured in the Reg-5Ah Jack Detect Control Register.
GPIO & JD input can be configured as sticky by setting Reg50, change polarity by setting Reg4E, and
wake-up by setting Reg52 in order to generate the interrupt (IRQ). The driver can write each bit of Reg54
to ‘1’ to clear each IRQ status flag.
Figure 18. GPIO Implementation
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7.15. Internal Event Signal Interrupt
Independent of GPIOs, an Internal Event Signal (MICBIAS short detect) is handled the same as a Jack
Detect and is treated as an Interrupt source. The application of an Internal Event Signal is the same as that
of a GPIO.
Interrupt request (IRQ) can be configured as:
• Sticky by setting Reg50
• Changed polarity by setting Reg4E
• Wake-up by setting Reg52
The driver can write each bit of Reg54 to ‘1’ to clear each IRQ status flag.
Sticky (50h . n)
GPIO Status (54h . n)
0
1
0
1
ALC 206 Internal Signal
Config (4Ch. n)
Polarity (4Eh. n)
Q
S
R
0 : Active Low
1 : Active High
IRQout_ Inv
(5Eh. 0)
gpio 2_pin_ sharing
(56h . [1:0])
Sticky (50h . n)
Config (4Ch. n)
Wake (52h . n)
Write 0 ? to GPIO
Status (54h . n)
01 : Close
Others : Open
IRQ
Other 15 bits
Wake (52h . n)
Config (4Ch. n)
Sticky (50h . n)
Q
S
R
JD1/JD2
Write 0 ? to GPIO
Status (54h . n)
1
0
Polarity (4Eh. n)
0 : Active Low
1 : Active High
GPIO Status (54h . n)
1
0
Sticky (50h . n)
Config (4Ch. n)
JD
Controller
Others
JD_ sel (5Ah . 15:14)
Figure 19. Jack Detect and IRQ Logic
7.16. Headphone Depop
The ALC5623 provides a headphone depop mechanism in order to eliminate the pop noise of headphone
out. An external 1µF Capacitor is required in this application. Refer to the ALC5623 Application Note for
details.
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8. Mixer Registers List
Accessing odd numbered registers, or reading unimplemented registers, will return a 0.
8.1. Reg-00h: Reset
Default: 59B4h
Table 11. Reg-00h: Reset
Name
Bits
Read/Write
Reset State
0’h
Description
Reserved
15
R
R
R
R
R
R
R
R
R
R
R
R
Reserved. Read as 0
SE[4:0]=10110b
REG-00_b14_b10
REG-00_b9
REG-00_b8
REG-00_b7
REG-00_b6
REG-00_b5
REG-00_b4
Reserved
14:10
16’h
0’h
9
8
7
6
5
4
3
2
1
0
No Support for 20-Bit ADC
Supports 16-Bit ADC
Supports 16-Bit DAC
No Support for 18-Bit DAC
Support for Loudness
Headphone Output Support
Reserved
1’h
1’h
0’h
1’h
1’h
0’h
REG-00_b2
Reserved
1’h
Supports EQ Control
Reserved. Read as 0
0’h
REG-00_b0
0’h
Dedicated MIC PCM Input is Not Supported
Note: Writes to this register will reset all registers to their default values except PLL related registers. The written data
will be ignored.
8.2. Reg-02h: Line Output Volume
Default: 8080h
Table 12. Reg-02h: Line Output Volume
Name
Bits Read/Write Reset State Description
lio_l_mute
15
RW
RW
RW
RW
1’h
0’h
0’h
0’h
Mute LINE_OUT Left Control
0: On
1: Mute (-∞ dB)
LINE_OUT Left Zero Cross Detector Control
0: Disable
1: Enable
lio_l_dezero
lio_l_soft-mute_en
lio_l_vol
14
13
LINE_OUT Left_Softmute Enable
0: Disable
1: Enable
12:8
LINE_OUT Left Output Volume (LIOL[4:0]) in 1.5dB steps
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Name
Bits Read/Write Reset State Description
lio_r_mute
7
RW
RW
RW
RW
1’h
0’h
0’h
0’h
Mute LINE_OUT Right Control
0: On
1: Mute (-∞ dB)
Note: Not used when in differential mode (Reg1C[11:10])
lio_r_dezero
lio_r_soft-mute_en
lio_r_vol
6
LINE_OUT Right Zero Cross Detector Control
0: Disable
1:Enable
Note: Not used when in differential mode (Reg1C[11:10])
LINE_OUT Right_Softmute Enable
0: Disable
5
1: Enable
Note: Not used when in differential mode (Reg1C[11:10])
4:0
LINE_OUT Right Output Volume (LIOR[4:0]) in 1.5dB
Steps
Note: Not used when in differential mode (Reg1C[11:10])
1Fh: 46.5dB attenuation
Note: For LIOR/LIOL, 00h: 0dB attenuation
8.3. Reg-04h: Headphone Output Volume
Default: 8080h
Table 13. Reg-04h: Headphone Output Volume
Name
Bits Read/Write Reset State Description
hp_l_mute
15
14
13
RW
RW
RW
1’h
0’h
0’h
Mute HP Left Control
0: On
1: Mute Left Channel (-∞ dB)
hp_l_dezero
HP Left Zero Cross Detector Control
0: Disable 1: Enable
HP Left Channel Softmute Enable
0: Disable 1: Enable
hp_l_soft-mute_en
hp_l_vol
12:8
7
RW
RW
0’h
1’h
Headphone Output Left Volume (HPL[4:0]) in 1.5dB Steps
Mute HP Right Control
hp_r_mute
0: On
HP Right Zero Cross Detector Control
0: Disable 1: Enable
HP Right Channel Softmute Enable
0: Disable 1: Enable
1: Mute Right Channel (-∞ dB)
hp_r_dezero
hp_r_soft-mute_en
hp_r_vol
6
5
RW
RW
RW
0’h
0’h
0’h
4:0
Headphone Output Right Volume (HPR[4:0]) in 1.5dB Steps
Note: For HPR/HPL, 00h: 0dB attenuation
1Fh: 46.5dB attenuation
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8.4. Reg-06h: MONO_OUT/AUXOUT Volume
Default: 8080h
Table 14. Reg-06h: MONO_OUT/AUXOUT Volume
Name
Bits
Read/Write Reset State Description
AUXO_l_mute
15
RW
RW
RW
1’h
0’h
0’h
Mute Left Control
0: On
1: Mute Left Channel (-∞ dB)
AUXO_l_dezero
14
13
Left Zero Cross Detector Control
0: Disable 1: Enable
AUXO_l_soft-mute
_en
AUXOUT Left Channel Softmute Enable
0: Disable 1: Enable
AUXO_l_vol
12:8
7
RW
RW
0’h
1’h
AUXOUT Output Left Volume (AUXOLV[4:0]) In 1.5dB
Steps
AUXO_r_mute
Mute Right Control
0: On
1: Mute Right Channel (-∞ dB)
Note: Not used when in differential mode
Right Zero Cross Detector Control
0: Disable 1: Enable
Note: Not used when in differential mode
AUXOUT Right Channel Softmute Enable
0: Disable 1: Enable
AUXO_r_dezero
6
5
RW
RW
RW
0’h
0’h
0’h
AUXO_r_soft-mute
_en
Note: Not used when in differential mode
AUXO_r_vol
4:0
AUXOUT Output Right Volume (AUXORV[4:0]) in
1.5dB Steps
Note: Not used when in differential mode
1Fh: 46.5dB attenuation
Note: For AUXOL/R, 00h: 0dB attenuation
8.5. Reg-08h: AUXIN Volume
Default: E808h
Table 15. Reg-08h: AUXIN Volume
Bits Read/Write Reset State Description
Name
auxi2hp_mute
15
14
13
RW
RW
RW
1’h
1’h
1’h
Mute AUXIN Volume Output to Headphone Mixer Control
0: On 1: Mute
Mute AUXIN Volume Output to Speaker Mixer Control
0: On 1: Mute
Mute AUXIN Volume Output to Mono Mixer Control
0: On 1: Mute
auxi2spk_mute
auxi2mono_mute
auxi_l_vol
Reserved
12:8
7:5
RW
R
08’h
0’h
AUXIN Left Volume (AUXI LV [4:0]) in 1.5dB Steps
Reserved
auxi_r_vol
4:0
RW
8’h
AUXIN Right Volume (AUXIRV [4:0]) in 1.5dB Steps
Note: For AUXIRV/AUXI LV, 00h: +12dB gain
08h: 0dB attenuation
1Fh: 34.5dB attenuation
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Datasheet
8.6. Reg-0Ah: LINE_IN Volume
Default: E808h
Table 16. Reg-0Ah: LINE_IN Volume
Name
Bits
Read/Write
Reset State Description
li2hp_mute
15
RW
1’h
Mute LINE_IN Volume Output to Headphone Mixer
Control
0: On
1: Mute
li2spk_mute
14
13
RW
RW
1’h
1’h
Mute LINE_IN Volume Output to Speaker Mixer Control
0: On 1: Mute
Mute LINE_IN Volume Output to MONO Mixer Control
0: On 1: Mute
li2MONO_mute
li_l_vol
Reserved
li_r_vol
12:8
7:5
RW
R
08’h
0’h
LINE_IN Left Volume (NLV[4:0]) in 1.5dB Steps
Reserved
4:0
RW
8’h
LINE_IN Right Volume (NRV[4:0]) in 1.5dB Steps
Note: For NRV/NLV, 00h: +12dB gain
08h: 0dB attenuation
1Fh: 34.5dB attenuation
8.7. Reg-0Ch: STEREO DAC Volume
Default: E808h
Table 17. Reg-0Ch: STEREO DAC Volume
Name
Bits
Read/Write
Reset State Description
dac2hp_mute
15
RW
1’h
1’h
1’h
Mute DAC Volume Output to Headphone Mixer Control
0: On 1: Mute (-∞dB)
Mute DAC Volume Output to Speaker Mixer Control
0: On 1: Mute (-∞dB)
Mute DAC Volume Output to MONO Mixer Control
0: On 1: Mute (-∞dB)
dac2spk_mute
14
RW
RW
dac2MONO_mute 13
dac_l_vol
Reserved
dac_r_vol
12:8
7:5
RW
R
08’h
0’h
PCM Left DAC Volume (PLV[4:0]) in 1.5dB Steps
Reserved
4:0
RW
8’h
PCM Right DAC Volume (PRV[4:0]) in 1.5dB Steps
Note: For PRV/PLV, 00h: +12dB gain
08h: 0dB attenuation
1Fh: 34.5dB attenuation
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Datasheet
8.8. Reg-0Eh: MIC Volume
Default: 0808h
Table 18. Reg-0Eh: MIC Volume
Name
Bits
15:13
12:8
7:5
Read/Write
Reset State Description
Reserved
mic1_vol
Reserved
mic2_vol
R
RW
R
0’h
08’h
0’h
Reserved
MIC1 Volume (M1V[4:0]) in 1.5dB Steps
Reserved
4:0
RW
8’h
MIC2 Volume (M2V[4:0]) in 1.5dB Steps
Note: For M2V/M1V, 00h: +12dB gain
08h: 0dB attenuation
1Fh: 34.5dB attenuation
8.9. Reg-10h: MIC Routing Control
Default: E0E0h
Table 19. Reg-10h: MIC Routing Control
Read/Write Reset State Description
RW 1’h Mute MIC1 Volume Output to Headphone Mixer
0: On 1: Mute
Mute MIC1 Volume Output to Speaker Mixer
0: On 1: Mute
Mute MIC1 Volume Output to MONO Mixer
0: On 1: Mute
MIC1 Differential Input Control
Name
Bits
mic12hp_mute
15
mic12spk_mute
mic12MONO_mute
mic1_diff_ctrl
14
13
12
RW
RW
RW
1’h
1’h
0’h
0: Disable
Reserved
1: Enable
Reserved
11:8
7
R
0’h
1’h
mic22hp_mute
RW
Mute MIC2 Volume Output to Headphone Mixer
0: On 1: Mute
Mute MIC2 Volume Output to Speaker Mixer
0: On 1: Mute
Mute MIC2 Volume Output to MONO Mixer
0: On 1: Mute
MIC2 Differential Input Control
mic22spk_mute
mic22MONO_mute
mic2_diff_ctrl
Reserved
6
5
RW
RW
RW
R
1’h
1’h
0’h
0’h
4
0: Disable
Reserved
1: Enable
3:0
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Datasheet
8.10. Reg-12h: ADC Record Gain
Default: F58Bh
Table 20. Reg-12h: ADC Record Gain
Bits Read/Write Reset State Description
Name
adc2hp_l_mute
15
RW
RW
RW
RW
RW
1’h
Mute Left Gain Output to Headphone Mixer Control
0: On 1: Mute (-∞dB)
Mute Right Gain Output to Headphone Mixer Control
0: On 1: Mute (-∞dB)
Mute Left Gain Output to MONO Mixer Control
0: On 1: Mute (-∞dB)
Mute Right Gain Output to MONO Mixer Control
0: On 1: Mute (-∞dB)
ADC Record Gain Left Channel (LRG[4:0]) in 1.5dB Steps
adc2hp_r_mute
14
1’h
adc2MONO_l_
mute
13
1’h
adc2MONO_r_
mute
12
1’h
adc_l_vol
11:7
0B’h
00h: -16.5dB attenuation
1Fh: 30dB gain
0Bh: 0dB gain
adc_l_dezero
adc_r_dezero
adc_r_vol
6
5
RW
RW
RW
0’h
0’h
ADC_L Zero-Cross Detector Control
0: Disable
1: Enable
ADC_R Zero-Cross Detector Control
0: Disable
1: Enable
4:0
0B’h
ADC Record Gain Right Channel (RRG[4:0]) in 1.5dB Steps
00h: -16.5dB attenuation
1Fh: 30dB gain
0Bh: 0dB gain
8.11. Reg-14h: ADC Record Mixer Control
Default: 7F7Fh
Table 21. Reg-14h: ADC Record Mixer Control
Name
Bits
15
Read/Write
Reset State Description
Reserved
adcrec_l_mute
R
0’h
Reserved
14:8
RW
7F’h
Left Mixer Mute Control
0: On
Bit 14: MIC1
1: Mute (-∞dB)
Bit 13: MIC2
Bit 12: LINE_IN_L Bit 11: AUXIN_L
Bit 10: Headphone Mixer Left Channel
Bit 9: Speaker Mixer Bit 8: MONO Mixer
Reserved
7
R
0’h
Reserved
adcrec_r_mute
6:0
RW
7F’h
Right Mixer Mute Control
0: On
Bit 6: MIC1
Bit 4: LINE_IN_R
1: Mute (-∞dB)
Bit 5: MIC2
Bit 3: AUXIN_R
Bit 2: Headphone Mixer Right Channel
Bit 1: Speaker Mixer Bit 0: MONO Mixer
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Datasheet
8.12. Reg-16h: Avol Soft Volume Control Time
Default: 0000h
Table 22. Reg-16h: Avol Soft Volume Control Time
Name
Bits
15:4
3:0
Read/Write Reset State Description
Reserved
R
000’h
Reserved
soft_volume_ctrl_avol
RW
1010’b
Soft Volume Control Time (Default=1001b)
0000: 1 SVSYNC
0010: 4 SVSYNC
0100: 16 SVSYNC
0110: 64 SVSYNC
0001: 2 SVSYNC
0011: 8 SVSYNC
0101: 32 SVSYNC
0111: 128 SVSYNC
1000: 256 SVSYNC 1001: 512 SVSYNC
1010: 1024 SVSYNC Others: Reserved
Note: SVSYNC=1/Fs, Step:-1.5dBFS
8.13. Reg-1Ch: Output Mixer Control
Default: D000h
Table 23. Reg-1Ch: Output Mixer Control
Read/Write Reset State Description
Name
Bits
lio_outn_source
15:14
RW
3’h
LINE_Out_N Source Select
lio_vol_in_sel=’01’ lio_vol_in_sel=’10’ or ‘11’
00
01
10
11
RN
RP
LN
-(L+R)
L+R
-(L+R)
Vmid
Reserved
13
12
RW
RW
0’h
1’h
Reserved
line_out_amp_sel
LINE OUT Amplifier Selection
0: Test Mode
1: Normal Mode
lio_vol_in_sel
11:10
RW
00’h
LINE_OUT Volume Output Input Select
00: VMID (No input) 01: HP Mixer
10: Speaker mixer (diff out) 11: MONO Mixer (diff out)
HPL Volume Output Input Select
0: VMID (No input) 1: HP Left Mixer
HPR Volume Output Input Select
0: VMID (No input) 1: HP Right Mixer
MONO/AUX Output Volume Input Select
00: VMID (No input)
hp_l_in_sel
hp_r_in_sel
mono_in_sel
9
8
RW
RW
RW
0’h
0’h
0’h
7:6
01: HP Mixer (AUXÆL/R, MonoÆL+R)
10: Speaker mixer
Reserved
11: MONO Mixer
Reserved
5:0
R
0’h
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Datasheet
8.14. Reg-22h: Microphone Control
Default: 0000h
Table 24. Reg-22h: Microphone Control
Read/Write Reset State Description
Name
Bits
15:12
11:10
Reserved
R
0’h
0’h
Reserved
mic1_boost_ctrl
RW
MIC1 Boost Control
00: Bypass01: +20dB
10: +30dB 11: Reserved
MIC2 Boost Control
mic2_boost_ctrl
9:8
RW
0’h
00: Bypass01: +20dB
10: +30dB 11: Reserved
Reserved. Read as 0
Reserved
7:6
5
R
0’h
0’h
mic1_bias_voltage_ctrl
RW
MICBIAS1 Output Voltage Control
0: 0.9*AVDD 1: 0.75*AVDD
Reserved. Read as 0
Reserved
4:2
1:0
R
0’h
0’h
mic_bias_threshold
RW
MICBIAS1/2 Short Current Detector Threshold
00: 600µA 01: 1200µA
1x: 1800µA
8.15. Reg-34h: Digital Audio Interface Control
Default: 8000h
Table 25. Reg-34h: Audio Interface
Name
Bits
Read/Write Reset State Description
stereo_i2s_mode_sel
15
RW
1’h
Main Serial Data Port Mode Selection
0: Master 1: Slave
pcm_mode_sel
14
RW
0’h
PCM Mode Select
0: Mode A 1: Mode B
Reserved
13:8
7
RW
RW
0’h
0’h
Reserved
stereo_i2s_bclk_polarity_ctrl
Stereo I2S BCLK Polarity Control
0: Normal 1: Invert
Reserved
6
5
RW
RW
0’h
0’b
Reserved
adclrckswap
ADC Data L/R Swap
0: ADC data appear at left phase of LRCK
1: ADC data appear at right phase of LRCK
Note: Supported in I2S & PCM
DAC Data L/R Swap
daclrckswap
4
RW
0’b
0: DAC data appear at left phase of LRCK
1: DAC data appear at right phase of LRCK
Note: Supported in I2S & PCM
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Datasheet
Name
Bits
Read/Write Reset State Description
stereo_i2s_data_len_sel
3:2
RW
0’h
Data Length Selection
00: 16 bits 01: 20 bits
10: 24 bits 11: 32 bits
stereo_i2s_data_format_sel
1:0
RW
0’h
Stereo PCM Data Format Selection
00: I2S format 01: Right justified
10: Left justified 11: PCM format
8.16. Reg-36Ah: Stereo AD/DA Clock Control
Default: 166Dh
Table 26. Reg-36h: Stereo AD/DA Clock Control
Name
Bits
15
Read/Write Reset State Description
Reserved
i2s_pre_div
RW
RW
0’h
1’h
Reserved
14:12
I2S_Pre_Div
000b: ÷1
001b: ÷2
010b: ÷4
011b: ÷8
100b: ÷16
101b: ÷32
Others: Reserved
I2S_BCLK_Div
000b: ÷1 (MCLK=BCLK)
i2s_sclk_div
11:9
8:5
RW
RW
RW
011’b
0011’b
011’b
001b: ÷2
100b: ÷6
111b: ÷16
010b: ÷3
101b: ÷8
011b: ÷4
110b: ÷12
i2s_wclk_div_pre
i2s_wclk_div
I2S_WCLK_Div_pre
0000b: ÷1
………..
0001b: ÷2
0010b: ÷3
1111b: ÷16
1101b: ÷14
I2S_WCLK_Div
000b: ÷2
1110b: ÷15
4:2
001b: ÷4
010b: ÷8
011b: ÷16
100b: ÷32
Others: Reserved
adda_filter_clk
adda_osr
1
0
RW
RW
0’b
1’b
Stereo ADDA Filter Clock Select
0b: 256Fs 1b: 384Fs
Stereo ADDA Over Sample Rate Select
0b: Low
1b: High
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Datasheet
8.17. Reg-38h: Companding Control
Default: 0000h
Table 27. Reg-38h: Companding Control
Read/Write Reset State Description
Name
Bits
word_length_8
15
RW
0’b
0: OFF
1: Device works in 8 bits mode when in PCM mode B
Reserved
Reserved
14:4
3:2
RW
RW
0’h
adc_comp
00’b
ADC Companding (for ADC DAT Output)
00: OFF 01: µ-Law
10: A-Law 11: Reserved
dac_comp
1:0
RW
00’b
DAC Companding (for DAC DAT Input)
00: OFF 01: µ-Law
10: A-Law 11: Reserved
8.18. Reg-3Ah: Power Management Addition 1
Default: 0000h
Table 28. Reg-3Ah: Power Management Addition 1
Name
Bits
Read/Write Reset State Description
Main_i2s_en
15
RW
0’h
I2S Digital Interface Enable
0: Disable
1: Enable
pow_zcd
14
RW
0’h
All Zero Cross Detect Power Down
0: Disable
1: Enable
Reserved
13:12
11
RW
RW
0’h
0’h
Reserved
pow_mic1_bias
Microphone1 Bias
0: Disable
1: Enable microphone1 bias
pow_mic1_bias_det_ctrl
10
RW
0’h
MICBIAS1 Short Current Detector Control
0: Disable
1: Enable
Reserved
9
8
RW
RW
0’h
0’h
Reserved
pow_softgen
Power on Softgen
1: Power on
0: Power down
Note: Refer to the ALC5623 application note for
detailed de-pop sequence information.
Reserved
7
6
RW
RW
0’h
0’h
Reserved
pow_dpbuf_hp
Power on Headphone Depop Buffer
1: Power on
0: Power down
Note: Refer to the ALC5623 application note for
detailed de-pop sequence information.
en_hp_out_amp
5
RW
0’h
Headphone Output Amplifier Buffer
1: Enable HP Output buffer for normal loading >KΩ
0: Disable (DPOP mode)
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Datasheet
Name
Bits
Read/Write Reset State Description
en_hp_enhance_amp
4
RW
0’h
Headphone Enhance Output Buffer
1: Enable HP Output buffer for small R loading
(<100Ω)
0: Disable (DPOP mode or normal loading mode)
Reserved
Reserved
3
2
RW
RW
0’h
0’h
pow_dpbuf_aux
AUX Power on Depop Buffer
1: Power on
0: Power down
Note: Refer to the ALC5623 application note for
detailed de-pop sequence information.
en_aux_out_amp
1
0
RW
RW
0’h
0’h
AUX Output Amplifier Buffer
1: Enable AUX Output buffer for normal loading
(>KΩ)
0: Disable (DPOP mode)
en_aux_enhance_amp
Enhanced AUX Amplifier Output Buffer
1: Enable AUX Output buffer for small R loading
(<100Ω)
0: Disable (DPOP mode or normal loading mode)
8.18.1. Headphone Output Amplifier Configuration
Table 29. Headphone Output Amplifier Configuration
en_hp_out_amp
en_hp_enhance_amp
Description
0’b
0’b
1’b
1’b
0’b
1’b
0’b
1’b
HP Output OFF
Not Used
HP Output for Normal Loading (>Kohm)
HP Output for Small R Loading (<100ohm)
8.18.2. Auxiliary Output Amplifier Configuration
Table 30. Auxiliary Output Amplifier Configuration
en_aux_out_amp
en_aux_enhance_amp Description
0’b
0’b
1’b
1’b
0’b
1’b
0’b
1’b
AUX Output OFF
Not Used
AUX Output for Normal Loading (>Kohm)
AUX Output for small R Loading (<100ohm)
I2S Audio Codec +Headphone Amplifier
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Track ID: JATR-1076-21 Rev. 1.1
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Datasheet
8.19. Reg-3Ch: Power Management Addition 2
Default: 0000h
Table 31. Reg-3Ch: Power Management Addition 2
Name
Bits
Read/Write Reset State Description
pow_LineOut_amp
15
RW
0’h
Line Out Amplifier Power
0: Disable
1: Enable
Reserved
pow_vref
14
13
R/W
RW
0’b
0’h
Reserved
VREF of All Analog Circuits
0: Disable
1: Enable
Note: This bit works only if Index-39[11]=0b.
pow_pll
12
11
10
9
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
PLL
0: Disable
1: Enable
Reserved
Reserved.
Must be kept to 0.
pow_dac_ref
pow_dac_l
Power DAC Reference Circuit (Vref+/Vref-)
0: Disable 1: Enable
Left Stereo DAC Filter Clock
0: Disable 1: Enable
Right Stereo DAC Filter Clock
0: Disable 1: Enable
Left Stereo ADC Filter Clock and Input Gain
0: Disable 1: Enable
Right Stereo ADC Filter Clock and Input Gain
0: Disable 1: Enable
Left Headphone Mixer
pow_dac_r
8
pow_adc_l
7
pow_adc_r
6
pow_mix_hp_l
pow_mix_hp_r
pow_mix_spk
pow_mix_mono
pow_mix_adc_rec_l
pow_mix_adc_rec_r
5
0: Disable
1: Enable
4
Right Headphone Mixer
0: Disable
1: Enable
3
Speaker Mixer
0: Disable
1: Enable
2
MONO Mixer
0: Disable
1: Enable
1
Left ADC Record Mixer
0: Disable
1: Enable
0
Right ADC Record Mixer
0: Disable
1: Enable
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Track ID: JATR-1076-21 Rev. 1.1
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Datasheet
8.20. Reg-3Eh: Power Management Addition 3
Default: 0000h
Table 32. Reg-3Eh: Power Management Addition 3
Name
Bits
Read/Write Reset State Description
pow_main_bias
15
RW
0’h
Main Bias Analog Circuit
0: Disable 1: Enable
pow_aux_outl_vol
pow_aux_outr_vol
pow_lineout
14
13
12
RW
0’h
AUXOUT_L(Mono_P) Volume Control & AUX_L
Amplifier
0: Disable
1: Enable
RW
RW
0’h
0’h
AUXOUT_R(Mono_N) Volume Control & AUX_R
Amplifier
0: Disable
1: Enable
LINE_OUT Output
0: Disable
1: Enable
Reserved
11
10
RW
RW
0’h
0’h
Reserved
pow_hp_l_vol
HP_OUT_L Volume Control (Amp)
0: Disable 1: Enable
HP_OUT_R Volume Control (Amp)
pow_hp_r_vol
9
RW
0’h
0: Disable
Reserved
1: Enable
Reserved
8
7
RW
RW
0’h
0’h
pow_li_l_vol
LINE_IN Left Volume Control
0: Disable 1: Enable
LINE_IN Right Volume Control
0: Disable 1: Enable
AUXIN Left Volume Control
0: Disable 1: Enable
AUXIN Right Volume Control
0: Disable 1: Enable
MIC1 Boost + Differential Mixer + Volume Amp Control
0: Disable 1: Enable
MIC2 Boost+ Differential Mixer + Volume Amp Control
0: Disable 1: Enable
MIC1 AD Boost + AD Differential Mixer
0: Disable 1: Enable
MIC2 AD Boost + AD Differential Mixer
pow_li_r_vol
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
0’h
0’h
0’h
0’h
0’h
0’h
0’h
pow_auxin_l_vol
pow_auxin_r_vol
pow_mic1_vol
pow_mic2_vol
pow_mic1_admixer
pow_mic2_admixer
0: Disable
1: Enable
I2S Audio Codec +Headphone Amplifier
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Track ID: JATR-1076-21 Rev. 1.1
ALC5623
Datasheet
Figure 20. Power Control to MIC Input
8.21. Reg-40h: Additional Control Register
Default: 5300h
Table 33. Reg-40h: Additional Control Register
Name
Bits
15
Read/
Write
Reset Description
State
se_diff_auxout
lio_amp_ctrl
RW
0’b
AUXOUT Selection of Single-End or Differential Mode
0: Differential Mode 1: Single-End Mode
Line Out Amplifier VMID Ratio Control (Output Gain Control)
14:12
RW
5’h
000: 2.25 Vdd
010: 1.75 Vdd
100: 1.25 Vdd
001: 2.00 Vdd
011: 1.5 Vdd
101: 1 Vdd
Others: Not allowed
Note: Only used when AVDD does not equal to AVDD2.
Reserved
Reserved
11:10
9
R
0’h
1’h
dac_hpf_en
R/W
STEREO DAC High Pass Filter
0: Disable
1: Enable
adc_hpf_en
8
R/W
1’h
STEREO ADC High Pass Filter
0: Disable
Reserved
1: Enable
Reserved
7:6
5:4
R
0’h
0’b
digital_vol_boost
RW
Digital Volume Boost
00: 0dB
01: 6dB
10: 12dB
11: 18dB
se_btl_lio
Reserved
3
RW
RW
0’b
0’h
LINE_OUT selection of Single-End or Bridge-Tied Load (BTL).
0: Differential Mode
Reserved
1: Single-End Mode
2:0
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8.22. Reg-42h: Global Clock Control Register
Default: 0000h
Table 34. Reg-42h: Global Clock Control Register
Name
Bits
Read/Write Reset State Description
sel_sysclk
15
RW
0’h
Clock Source MUX Control
0: MCLK 1: PLL Output
PLL Source Select
pll_sour_sel
14
RW
0’h
0: From MCLK 1: From BLCK
Reserved
Reserved
13:3
2:1
RW
RW
0’h
0’b
pllout_div_ratio
PLL Output Division Ratio
(Divider of PLL Output to GPIO
00: ÷1
10: ÷4
01: ÷2
11: ÷8
pll_pre_div
0
RW
0’b
PLL Pre-Divider
0b: ÷1 1b: ÷2
8.23. Reg-44h: PLL Control Register
8.23.1. Reg-44h: PLL Control Register
Default: 0000h
Table 35. Reg-44h: PLL Control Register
Name
Bits
Read/Write
Reset State
Description
pll_n_code
15:8
RW
00’h
N[7:0] Code for Analog PLL
00000000: Div 2
00000001: Div 3
………..
11111111: Div 257
Bypass PLL M
0b: No bypass
1b: Bypass
pll_m_bypass
pll_k_code
7
RW
RW
0’h
0’h
6:4
K[2:0] Code for Analog PLL
000: Div 2
001: Div 3
…………
111: Div 9
pll_m_code
3:0
RW
0’h
M[3:0] Code for Analog PLL
0000: Div 2
0001: Div 3
…………
1111: Div 17
Note: The PLL1 transmit formula is FOUT = (MCLK * (N+2))/((M+2) * (K+2)) {Typical K=2}
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8.23.2. PLL Clock Setting Table for 48K: (Unit: MHz)
Table 36. PLL Clock Setting Table for 48K: (Unit: MHz)
MCLK
13
N
66
78
94
70
80
81
78
80
78
M
7
FVCO
98.222
98.304
98.304
98.304
98.4
K
2
2
2
2
2
2
2
2
2
FOUT
24.555
24.576
24.576
24.576
24.6
3.6864
2.048
4.096
12
1
0
1
8
15.36
16
11
11
14
14
98.068
98.462
98.4
24.517
24.615
24.6
19.2
19.68
98.4
24.6
8.23.3. PLL Clock Setting Table for 44.1K: (Unit: MHz)
Table 37. PLL Clock Setting Table for 44.1K: (Unit: MHz)
MCLK
13
N
68
72
86
64
66
63
66
64
67
M
8
FVCO
91
K
2
2
2
2
2
2
2
2
2
FOUT
22.75
3.6864
2.048
4.096
12
1
90.931
90.112
90.112
90.667
90.764
90.667
90.514
90.528
22.733
22.528
22.528
22.667
22.691
22.667
22.629
22.632
0
1
7
15.36
16
9
10
12
13
19.2
19.68
8.24. Reg-4Ah: GPIO_Output Pin Control
Default: 0000h
Table 38. Reg-4Ch: GPIO_Output Pin Control
Name
Bits
15:2
1
Read/Write Reset State Description
Reserved
R
0000’h
0’h
Reserved
gpio_out_status
RW
GPIO Output Pin Control
0b: Drive Low
1b: Drive High
Reserved
0
R
0’h
Reserved. Read as 0
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Track ID: JATR-1076-21 Rev. 1.1
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8.25. Reg-4Ch: GPIO Pin Configuration
Default: 1C0Eh
Table 39. Reg-4Ch: GPIO Pin Configuration
Name
Bits
15:11
10
Read/Write Reset State Description
Reserved
R
03’b
1’h
Reserved
mic1_short_det_conf
RW
MICBIAS Short Current Status Source Configuration
0: Bypass 1: Normal
Reserved
jd2_conf
9:4
3
R
0’h
1’h
Reserved
RW
Jack Detect 2 Status Source Configuration
0: Bypass 1: Normal
jd1_conf
gpio_conf
Reserved
2
1
0
RW
RW
R
1’h
1’h
0’h
Jack Detect 2 Status Source Configuration
0: Bypass 1: Normal
GPIO Pin Configuration
0: Bypass 1: Input
Reserved. Read as 0
8.26. Reg-4Eh: GPIO Pin Polarity
Default: 1C0Eh
Table 40. Reg-4Eh: GPIO Pin Polarity
Read/Write Reset State Description
Name
Bits
15:11
10
Reserved
R
03’b
1’h
Reserved
mic1_short_det_polarity
RW
MICBIAS Short Current Detect Polarity
0: Low Active
Reserved
1: High Active
Reserved
9:4
3
R
0’h
1’h
jd2_polarity
RW
Jack Detect 2 Pin Polarity
0: Low Active
1: High Active
jd1_polarity
gpio_polarity
Reserved
2
1
0
RW
RW
R
1’h
1’h
0’h
Jack Detect 1 Pin Polarity
0: Low Active
1: High Active
1: High Active
GPIO Pin Polarity
0: Low Active
Reserved. Read as 0
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8.27. Reg-50h: GPIO Pin Sticky
Default: 0000h
Table 41. Reg-50h: GPIO Pin Sticky
Read/Write Reset State Description
Name
Bits
15:11
10
Reserved
R
00’b
0’h
Reserved
MICBIAS Short Current Detect Sticky Enable
mic1_short_det_sticky_en
RW
0: Not sticky
Reserved
1: Sticky
Reserved
9:4
3
R
0’h
0’h
jd2_sticky_En
RW
Jack Detect 2 Pin Sticky Enable
0: Not sticky 1: Sticky
Jack Detect 1 Pin Sticky Enable
0: Not sticky 1: Sticky
GPIO Pin Sticky Enable
0: Not sticky 1: Sticky
Reserved. Read as 0
jd1_sticky_En
gpio_sticky_En
Reserved
2
1
0
RW
RW
R
0’h
0’h
0’h
8.28. Reg-52h: GPIO Pin Wake-Up
Default: 0000h
Table 42. Reg-52h: GPIO Pin Wake-Up
Read/Write Reset State Description
Name
Bits
15:11
10
Reserved
R
00’b
0’h
Reserved
mic1_short_det_wakeup_en
RW
MICBIAS Short Current Detect Wake-Up Enable
0: No wake-up
Reserved
1: Wake up
Reserved
9:4
3
R
0’h
0’h
jd2_wakeup_en
RW
Jack Detect 2 Pin Wake-Up Enable
0: No wake-up 1: Wake up
Jack Detect 1 Pin Wake-Up Enable
0: No wake-up 1: Wake up
GPIO Pin Wake-Up Enable
jd1_wakeup_en
gpio_wakeup_en
Reserved
2
1
0
RW
RW
R
0’h
0’h
0’h
0: No wake-up
1: Wake up
Reserved. Read as 0
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Track ID: JATR-1076-21 Rev. 1.1
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8.29. Reg-54h: GPIO Pin Status
Default: 0002h
Table 43. Reg-54h: GPIO Pin Status
Read/Write Reset State Description
Name
Bits
15:11
10
Reserved
R
R
00’b
0’h
Reserved
mic1_short_det_status
MICBIAS Short Current Detect Status
Read: Return status
Write: Writing ‘0’ clears the sticky bit
Reserved
jd2_status
9:4
3
R
R
0’h
0’h
Reserved
Jack Detect 2 Pin Status
Read: Returns status of JD2 pin
Write: Writing ‘0’ clears sticky bit
jd1_status
gpio_status
Reserved
2
1
0
R
R
R
0’h
1’h
0’h
Jack Detect 1 Pin Status
Read: Return status of JD1 pin
Write: Writing ‘0’ clears sticky bit
GPIO Pin Status
Read: Returns status of each GPIO pin
Write: Writing ‘0’ clears the sticky bit
Reserved. Read as 0
8.30. Reg-56h: Pin Sharing
Default: 0000h
Table 44. Reg-56h: Pin Sharing
Name
Bits
Read/Write Reset State Description
lineinl_pin_sharing
15
RW
0’b
LINE_IN_L Pin Sharing
0: LINE_IN_L
1: JD1
lineinr_pin_sharing
14
RW
0’h
LINE_IN_R Pin Sharing
0: LINE_IN_R
1: JD2
Reserved
13:2
1:0
RW
RW
000’h
00’b
Reserved
gpio_pin_sharing
GPIO Pin Sharing
00: GPIO
01: IRQ_Out
11: PLL_Out
10: Reserved
8.31. Reg-58h: Over-Current Status
Default: 0000h
Table 45. Reg-58h: Over-Current Status
Read/Write Reset State Description
Name
Bits
ovc_micbias1_status
15
R
0’h
MICBIAS Over-Current
0: Normal 1: Over-current
Reserved
14:0
R
0’h
Reserved
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8.32. Reg-5Ah: Jack Detect Control Register
Default: 0000h
Table 46. Reg-5Ah: Jack Detect Control Register
Name
Bits
Read/Write
Reset State
Description
Jack Detect Select
00: OFF
jd_sel
15:14
RW
0’h
01: GPIO
11: JD2
10: JD1
Reserved
jd_H_Out
13:12
11:8
RW
RW
0’b
0’h
Reserved
Output Enable when Selected Jack Detect is ‘High’
xxx1: Headphone Out
x1xx: AUXOUT_R
xx1x: AUXOUT_L
1xxx: Line Out
jd_L_Out
Reserved
7:4
3:0
RW
RW
0’h
0’b
Output Enable when Selected Jack Detect is ‘Low’
xxx1: Headphone Out
x1xx: AUXOUT_R
Reserved
xx1x: AUXOUT_L
1xxx: Line Out
8.33. Reg-5Eh: MISC Control
Default: 0000h
Table 47. Reg-5Eh: MISC Control
Read/Write Reset State Description
Name
Bits
en_vref_fast
15
RW
0’b
Enable Fast Vref
0: Enable fast Vref
1: Disable fast Vref
Note: To improve PSRR, en_vref_fast should be
disabled before playback/record.
Reserved
14:11
RW
RW
RW
RW
0’b
0’h
0’h
0’h
Reserved.
Must be kept to 0.
en_dp3_hp
en_dp2_hp
en_dp1_hp
10
9
Enable Depop Mode 3 of HP_Out
0: Disable 1: Enable
Enable Depop Mode 2 of HP_Out
0: Disable 1: Enable
8
Enable Depop Mode 1 of HP_Out
0: Disable 1: Enable
Reserved
7
6
RW
RW
0’h
0’h
Reserved
en_dp3_aux
Enable Depop Mode 3 of AUX_Out
0: Disable 1: Enable
en_dp2_aux
5
4
3
RW
RW
RW
0’h
0’h
0’h
Enable Depop Mode 2 of AUX_Out
0: Disable 1: Enable
en_dp1_aux
Enable Depop Mode 1 of AUX_Out
0: Disable 1: Enable
main_dac_l_mute
Mute Main DAC Left Input
0: On
1: Mute (-∞ dB)
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Datasheet
Name
Bits
Read/Write Reset State Description
main_dac_r_mute
2
RW
0’h
Mute Main DAC Right Input
0: On
1: Mute (-∞ dB)
Reserved
1
0
RW
RW
0’h
0’h
Reserved
irqout_inv_ctrl
IRQOUT Inverter Control
0: Normal 1: Invert
The Jack-insert-detect pull up resistor is implemented via an external circuit (see section 10 Application
Circuit, page 63).
8.34. Reg-60h: Stereo and Spatial Effect Block Control
Default: 0497h
Table 48. Reg-60h: Stereo and Spatial Effect Block Control
Name
Bits
Read/Write Reset State Description
spatial_ctrl_enable
15
RW
0’b
Spatial Enable
0b: Disable (clear internal state)
1b: Enable
apf_en
14
RW
0’h
Enable All Pass Filter APF(z), EN-APF
0: Disable (bypass) and reset
1: Enable all pass filter. The coefficient a1 is loaded from
REG_MX64.[7:0]
pseudo_stereo_en
en_3d
13
12
RW
RW
0’h
0’h
Enable Pseudo Stereo Block, EN-PSB
0: Disabled
1: Enabled
Enable Stereo Expansion Block , EN-SEB
0: Disable
1: Enabled. Load 3D Ratio from ratio_parm_3d, and 3D
Gain from gain_parm_3d
gain_parm_3d_l
gain_parm_3d_r
ratio_parm_3d_l
11:9
8:6
RW
RW
RW
2’h
2’h
1’h
3D Gain Parameter Left (SEG2)
000: Gain=1.0 001: Gain=1.25
010: Gain=1.5 011: Gain=1.75
100: Gain=2
Others: Reserved
3D Gain Parameter Right (SEG1)
000: Gain=1.0 001: Gain=1.25
010: Gain=1.5 011: Gain=1.75
100: Gain=2
Others: Reserved
5:4
3D Ratio Parameter Left (DP2)
00: Ratio=0.0 01: Ratio=0.66
10:Ratio=1.0
11:Reserved
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Datasheet
Name
Bits
Read/Write Reset State Description
ratio_parm_3d_r
3:2
RW
1’h
3D Ratio Parameter Right (DP1)
00: Ratio=0.0 01: Ratio=0.66
10:Ratio=1.0
11:Reserved
apf_parm_a1
1:0
RW
3’h
All Pass Filter Parameter a1 in 2’s Complement 1.7
Format (-1.0~0.99)
00: Reserved
01: 32kHz sample rate or lower
10: 44.1kHz sample rate
11: 48kHz sample rate
Note: Writes to SEGn and DPn will be ignored when the Spatial effect control bit is enabled. This means individual
Spatial coefficients cannot be modified when Spatial is enabled.
8.35. Reg-62h: EQ Control
Default: 0000h
Table 49. Reg-62h: EQ Control
Name
Bits
Read/Write Reset State Description
eq_all_en
15
RW
0’b
EQ Block Control
0b: Disable
1b: Enable
eq_HPF_mode
14
RW
0’b
EQ High Frequency Shelving Filter Mode
0: High Frequency Shelving Filter
1: -20dB/decade (HPF)
Reserved
Reserved
13:12
11
R
0’h
0’b
Eq_source
RW
EQ Source
0: DAC path
1: ADC path
Reserved
10:5
4
R
00’h
0’b
Reserved
eq_hpf_en
RW
EQ High Pass Filter (HPF) Control
0: Disabled (bypass) and reset
1: Enabled
eq_bpf3_en
eq_bpf2_en
eq_bpf1_en
eq_lpf_en
3
2
1
0
RW
RW
RW
RW
0’b
0’b
0’b
0’b
EQ Band-3 (BP3) Control
0: Disabled and reset
1: Enabled.
EQ Band-2 (BP2) Control
0: Disabled and reset
1: Enabled.
1: Enabled.
EQ Band-1 (BP1) Control
0: Disabled and reset
EQ Low Pass Filter (LPF) Control
0: Disabled and reset 1: Enabled.
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Datasheet
8.36. Reg-66h: EQ Mode Change Enable
Default: 0000h
Table 50. Reg-66h: EQ Mode Change Enable
Name
Bits
15:5
4
Read/Write Reset State Description
Reserved
RW
RW
0’h
0’b
Reserved
eq_hpf_chg_en
EQ High Pass Filter (HPF) Mode Change Enable
0: Disable 1: Enable
eq_bpf3_chg_en
eq_bpf2_chg_en
eq_bpf1_chg_en
eq_lpf_chg_en
3
2
1
0
RW
RW
RW
RW
0’b
0’b
0’b
0’b
EQ Band-3 (BP3) Mode Change Enable
0: Disable 1: Enable
EQ Band-2 (BP2) Mode Change Enable
0: Disable 1: Enable
EQ Band-1 (BP1) Mode Change Enable
0: Disable 1: Enable
EQ Low Pass Filter (LPF) Mode Change Enable
0: Disable 1: Enable
Note: To enable an EQ mode change, the driver should set the new EQ parameters (Index00~Index0C) before setting this
register to 'Enable'. After the EQ parameter has been changed, the driver should set this register to 'Disable'.
8.37. Reg-68h: AVC Control
Default: 000Bh
Table 51. Reg-68h: AVC Control
Name
Bits
Read/Write Reset State Description
avc_en
15
RW
RW
RW
0’b
0’b
0’b
Auto Volume Control (AVC) Enable
0: Disable AVC
1: Enable AVC
avc_ref_ch
14
13
AVC Reference Channel Selection
0: Left Channel
1: Right Channel
Nonact_reg_action
Gain Action of Non-Active Region
0: Keep Previous Gain
1: Unit Gain
Nonact_feedback_sel
12
RW
0’b
Non-Active Threshold Gain Feedback Selection
0: No gain feedback
Reserved
1: Gain feedback
Reserved
11:5
4:0
RW
RW
0’h
monitor_window
0B’h
Monitor Window Control (Unit: 2^(n+1) samples)
(default:01011b)
00000b: 2^(1) sample
00010b: 2^(3) samples
Others: Reserved.
00001b: 2^(2) samples
10000b: 2^(17) samples
Maximum=10000000000000000=2^17
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Datasheet
8.38. Reg-6Ah: Index Address
Default: 0000h
Table 52. Reg-6Ah: Index Address
Name
Bits
15:7
6:0
Read/Write
Reset State Description
Reserved
index_addr
R
0’h
0’h
Reserved
RW
Index Address
8.39. Reg-6Ch: Index Data
Default: 0000h
Table 53. Reg-6Ch: Index Data
Read/Write Reset State Description
RW 0’h Index Data
Name
Bits
index_data
15:0
8.40. Index-00h: EQ Band-0 Coefficient (LP0: a1)
Default: 0000h
Table 54. Index-00h: EQ Band-0 Coefficient (LP0: a1)
Bit
Type Function
RW 2’s complement in 3.13 formats (The range is from –4~3.99, the a1 should be in -2 ~ 1.99)
15:0
Note: For low pass filter for Bass control – LP0 has filter coefficient a1 and gain Ho must be set (see Table 55).
8.41. Index-01h: EQ Band-0 Gain (LP0: Ho)
Default: 0000h
Table 55. Index-01h: EQ Band-0 Gain (LP0: Ho)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from –4~3.99, the Ho should be in -4 ~ 3.99)
15:0
8.42. Index-02h: EQ Band-1 Coefficient (BP1: a1)
Default: 0000h
Table 56. Index-02h: EQ Band-1 Coefficient (BP1: a1)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from –4~3.99, the a1 should be in -2 ~ 1.99)
15:0
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Datasheet
8.43. Index-03h: EQ Band-1 Coefficient (BP1: a2)
Default: 0000h
Table 57. Index-03h: EQ Band-1 Coefficient (BP1: a2)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from –4~3.99, the a1 should be in -2 ~ 1.99)
15:0
8.44. Index-04h: EQ Band-1 Gain (BP1: Ho)
Default: 0000h
Table 58. Index-04h: EQ Band-1 Gain (BP1: Ho)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from –4~3.99, the Ho should be in -4 ~ 3.99)
15:0
8.45. Index-05h: EQ Band-2 Coefficient (BP2: a1)
Default: 0000h
Table 59. Index-05h: EQ Band-2 Coefficient (BP2: a1)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from –4~3.99, the a1 should be in -2 ~ 1.99)
15:0
8.46. Index-06h: EQ Band-2 Coefficient (BP2: a2)
Default: 0000h
Table 60. Index-06h: EQ Band-2 Coefficient (BP2: a2)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from –4~3.99, the a2 should be in -2 ~ 1.99)
15:0
8.47. Index-07h: EQ Band-2 Gain (BP2: Ho)
Default: 0000h
Table 61. Index-07h: EQ Band-2 Gain (BP2: Ho)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from –4~3.99, the Ho should be in -4 ~ 3.99)
15:0
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Datasheet
8.48. Index-08h: EQ Band-3 Coefficient (BP3: a1)
Default: 0000h
Table 62. Index-08h: EQ Band-3 Coefficient (BP3: a1)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from –4~3.99, the a1 should be in -2 ~ 1.99)
15:0
8.49. Index-09h: EQ Band-3 Coefficient (BP3: a2)
Default: 0000h
Table 63. Index-09h: EQ Band-3 Coefficient (BP3: a2)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from –4~3.99, the a2 should be in -2 ~ 1.99)
15:0
8.50. Index-0Ah: EQ Band-3 Gain (BP3: Ho)
Default: 0000h
Table 64. Index-0Ah: EQ Band-3 Gain (BP3: Ho)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from –4~3.99, the Ho should be in -4 ~ 3.99)
15:0
8.51. Index-0Bh: EQ Band-4 Coefficient (HPF: a1)
Default: 0000h
Table 65. Index-0Bh: EQ Band-4 Coefficient (HPF: a1)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from –4~3.99, the a1 should be in -2 ~ 1.99)
15:0
8.52. Index-0Ch: EQ Band-4 Gain (HPF: Ho)
Default: 0000h
Table 66. Index-0Ch: EQ Band-4 Gain (HPF: Ho)
Bit
Type
Function
2’s complement in 3.13 format (The range is from –4~3.99, the Ho should be in -2 ~ 1.99)
15:0
RW
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Datasheet
8.53. Index-11h: EQ Input Volume Control
Default: 0000h
Table 67. Index-11h: EQ Input Volume Control
Bit
15:2
1:0
Type
-
Function
Reserved
RW
7-Bit Volume Unsigned Ratio EQIn-VOL-LR
00b: 0dB
01b: -6dB
10b: -12dB
11b: -18dB
8.54. Index-12h: EQ Output Volume Control
Default: 0001h
Table 68. Index-12h: EQ Output Volume Control
Bit
15:3
2:0
Type
-
Function
Reserved
RW
7-Bit Volume Unsigned Ratio EQOut-VOL-LR
000b: -3dB
100b: 9dB
001b: 0dB
101b: 12dB
010b: 3dB
110b: 15dB
011b: 6dB
111b: 18dB
8.55. Index-21h: Auto Volume Control Register 1
Default: 0400h
Table 69. Index-21h: Auto Volume Control Register 1
Bit
15
Type
-
Function
Reserved
14:0
RW
The Maximum PCM absolute level after AVC, Thmax (=0 ~ 2^15-1)
8.56. Index-22h: Auto Volume Control Register 2
Default: 0390h
Table 70. Index-22h: Auto Volume Control Register 2
Bit
15
Type
-
Function
Reserved
14:0
RW
The Minimum PCM absolute level after AVC, Thmin (=0 ~ 2^15-1)
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Datasheet
8.57. Index-23h: Auto Volume Control Register 3
Default: 0001h
Table 71. Index-23h: Auto Volume Control Register 3
Bit
15
Type
-
Function
Reserved
14:0
RW
The Non-active PCM absolute level AVC will keep analog unit gain, Thnonact (=0 ~ 2^15-1)
Note: Initial Index23=0001’h
8.58. Index-24h: Auto Volume Control Register 4
Default: 01FFh
Table 72. Index-24h: Auto Volume Control Register 4
Bit
Type
Function
15:0
RW
CNTMAXTH1. Controls the Sensitivity to Increased Gain (unit:2^1)
This value should be less than CNTMAXTH2 (Max=11111111111111110=2^18-2)
8.59. Index-25h: Auto Volume Control Register 5
Default: 0200h
Table 73. Index-25h: Auto Volume Control Register 5
Bit
Type
Function
15:0
RW
CNTMAXTH2. Controls the Sensitivity to Decreased Gain (unit:2^1)
This value should be less than Monitor Window (Optimal: 1/2 Monitor Window)
(Max=11111111111111110=2^18-2)
Note: CNTMAXTH1 < CNTMAXTH2
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Datasheet
8.60. Index-39h: Digital Internal Register
Default: 9800h
Table 74. Index-39h: Digital Internal Register
Bit
Type
Function
15
RW
Pad Drive Capability
0b: Weak drive
Reserved
1b: Strong drive
14:13
12
RW
RW
Power Gating Enable
0: Disable
1: Enable
1: Disable
11
RW
RW
Vref Power Control Enable
0: Enable
10:0
Reserved
8.61. Reg-7Ch: VENDOR ID 1
Default: 10ECh
Table 75. Reg-7Ch: VENDOR ID 1
Name
Bits
Read/Write
Reset State
Description
vender_id1
15:0
R
10EC’h
Vendor ID=10EC
8.62. Reg-7Eh: VENDOR ID 2
Default: 2303h
Table 76. Reg-7Eh: VENDOR ID 2
Name
vender_id
device_id2
Bits
15:8
7:0
Read/Write
Reset State
23’h
Description
Device ID=23
Version ID=03
R
R
03’h
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Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1.
Absolute Maximum Ratings
Table 77. Absolute Maximum Ratings
Parameter
Symbol
Min
Typ
Max
Units
Power Supplies
Digital IO Buffer
Digital Core
Analog
Operating Ambient Temperature
Storage Temperature
DBVDD
DCVDD
AVDD, AVDD2
Ta
-0.3
-0.3
-0.3
-25
-
-
-
-
-
3.63
3.63
3.63
+85
V
V
V
oC
oC
Ts
-55
+125
9.1.2.
Recommended Operating Conditions
Table 78. Recommended Operating Conditions
Parameter
Symbol
DBVDD
DCVDD
Min
1.71*
1.71
2.3
Typ
3.3
3.3
3.3
Max
3.6
3.6
Units
V
V
Digital IO Buffer
Digital Core
Analog
AVDD, AVDD2
3.6
V
Note: ‘*’instates a 1µF Capacitor must be connected from AVDD2 to AGND, and should be placed as close as possible
to the AVDD2 pin of the ALC5623.
9.1.3.
Static Characteristics
Table 79. Static Characteristics
Parameter
Input Voltage Range
Low Level Input Voltage
High Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Symbol
VIN
VIL
VIH
VOH
VOL
Min
-0.30
-
Typ
Max
DVDD+0.30
0.35DVDD
-
Units
V
V
V
V
-
-
-
-
-
0.65DVDD
0.9DVDD
-
-
0.1DVDD
V
Note: DVDD=3.3V, Tambient=25°C, with 50pF external load.
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Datasheet
9.2. Analog Performance Characteristics
Table 80. Analog Performance Characteristics
Parameter
Min
Typ
Max
Units
Full Scale Input Voltage
Line Inputs
MIC Inputs (Non-Boost)
MIC Inputs (Boost 20dB)
ADC
-
-
-
-
1.0
1.0
0.1
0.7
-
-
-
-
Vrms
Vrms
Vrms
Vrms
Full Scale Output Voltage
MONO Outputs
Headphone Amplifiers Outputs
LINE OUT
DAC
-
-
-
-
1.0
1.0
0.9
1.0
-
-
-
-
Vrms
Vrms
Vrms
Vrms
S/N Ratio (A-Weighted, HPL/R or MONO with 10KΩ/50pF Load)
-
-
92
85
-
-
dB
dB
STEREO DAC
STEREO ADC
Total Harmonic Distortion+Noise
(A-Weighted, HPL/R or MONO with 10KΩ/50pF Load)
STEREO DAC
-
-
-85
-80
-
-
dB
dB
STEREO ADC
MIC Boost Amplifier
Gain=20dB
Gain=30dB
-
-
20
30
-
-
dB
dB
Input Impedance (Gain=0dB, ADC mixer=On/Off)
MIC1N, MIC2N (Differential Mode)
MIC1P, MIC2P
-
-
16
16
-
-
KΩ
KΩ
Input Impedance (Gain=0dB, ADC Mixer=On)
LINE_IN_L/R, AUXIN_L/R
12.8
16
19.2
KΩ
Input Impedance (Gain=0dB, ADC Mixer=Off)
LINE_IN_L/R, AUXIN_L/R
25.6
-
32
38.4
-
KΩ
µA
MONO_OUT/AUXOUT_L/R Amplifier Quiescent Current
900
(32Ω Load)
MONO_OUT/AUXOUT_L/R Amplifier Efficiency
(fIN=1KHz, 32Ω Load)
Single-End Mode (Output Power=25mW)
BTL Mode (Output Power=75mW)
50
50
-
-
-
-
%
%
LINE_OUT/MONO_OUT/AUXOUT_L/R Amplifier THD+N
Single-End Mode (10KΩ Load)
-
80
-
dB
Output Power=0.1mW
BTL Mode (10KΩ Load)
Output Power=0.1mW
-
-
-
80
-
-
31.25
-
dB
mW
dB
Headphone Amplifier Output Power (32Ω Load)
LINE_OUT/MONO_OUT/AUXOUT_L/R Amplifier PSRR
(217Hz)
50
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Datasheet
Parameter
Min
Typ
Max
Units
Headphone Amplifier Efficiency
50
-
-
%
(fIN=1KHz, 32Ω Load, Output Power=25mW)
Headphone Amplifier THD+N (32Ω Load)
Output Power=20mW
Output Power=25mW
-
-
-
70
70
50
-
-
-
dB
dB
dB
Headphone Amplifier PSRR (217Hz)
Power Supply Current
I
I
DDA (Analog Block)
DDD (Digital Block)
-
-
-
-
15
20
mA
mA
Power Down Current
I
I
DDA (Analog Block)
DDD (Digital Block)
-
-
-
-
10
1
µA
µA
MICBIAS Output Voltage
0.75*Avdd Setting
0.9*Avdd Setting
-
-
2.475
2.97
-
-
-
V
V
MICBIAS Drive Current
2
3
mA
Note: Standard test conditions
Tambient=25°C, DBVDD=DCVDD=AVDD=3.3V, AVDD2=5V
1kHz input sine wave; PCM Sampling frequency=48kHz; 0dB=1Vrms, Test bench Characterization BW: 10Hz~22kHz,
0dB attenuation; EQ and 3D disabled.
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Datasheet
9.3. Signal Timing
9.3.1.
I2C Control Interface
tw(9) tw(10)
tsp
SCLK
SDA
th(5)
th(6)
tsu(7)
tsu(8)
Figure 21. I2C Control Interface
Table 81. I2C Timing
Parameter
Symbol
tw(9)
tw(10)
f
Min
1.3
600
0
Typ
Max
Units
µs
ns
Clock Pulse Duration
Clock Pulse Duration
Clock Frequency
Start Hold Time
Data Setup Time
Data Hold Time
Rising Time
-
-
-
-
-
-
-
-
-
-
-
-
400K
-
Hz
ns
th(5)
tsu(7)
th(6)
tr
600
100
-
-
ns
900
300
300
-
ns
-
ns
Falling Time
tf
-
ns
Stop Setup Time
tsu(8)
tsp
600
0
ns
Pulse Width of Spikes Suppressed Input Filter
50
ns
Note: Condition: MCLK > 8MHz.
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Datasheet
9.3.2.
I2S Master Mode
Figure 22. Timing of I2S Master Mode
Table 82. Timing of I2S Master Mode
Parameter
Symbol
tLRD
Min
-
Typ
Max
30
30
-
Units
ns
LRCK Output to BCLK Delay
Data Output to BCLK Delay
Data Input Setup Time
-
-
-
-
tADD
-
ns
tDAS
10
10
ns
Data Input Hold Time
tDAH
-
ns
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Datasheet
9.3.3.
I2S Slave Mode
Figure 23. I2S Slave Mode Timing
Table 83. I2S Slave Mode Timing
Parameter
Symbol
tBCH
Min
20
20
30
-
Typ
Max
Units
ns
BCLK High Pulse Width
BCLK Low Pulse Width
LRCK Input Setup Time
Data Output to BCLK Delay
Data Input Setup Time
Data Input Hold Time
-
-
-
-
-
-
-
-
tBCL
ns
tLRS
-
ns
tADD
tDAS
30
-
ns
10
10
ns
tDAH
-
ns
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Datasheet
10. Application Circuit
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Datasheet
11. Mechanical Dimensions
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Datasheet
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Datasheet
12. Appendix A: Stereo I2S Clock Table
MCLK
PLL Output
Sel_sysclk
DA/AD Clock
DAC/ADC Sample Rate
(Hz)
(Hz)
Reg42[15]
Reg36
LRCK (Hz)
BCLK=64fs
BCLK=32fs
24576000
X
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0’b
1’b
0x386F
0x366D
0x366D
0x286F
0x286F
0x266D
0x266D
0x186F
0x186F
0x166D
0x166D
0x086F
0x366D
0x286F
0x266D
0x186F
0x166D
0x086F
0x3C6B
X
24576000
8000
16384000
X
0x3A69
0x3A69
0x2C6B
0x2C6B
0x2A69
0x2A69
0x1C6B
0x1C6B
0x1A69
0x1A69
0x0C6B
0x3A69
0x2C6B
0x2A69
0x1C6B
0x1A69
0x0C6B
X
16384000
24576000
X
X
24576000
12000
16000
24000
32000
48000
11025
22050
44100
18432000
X
X
18432000
24576000
X
X
24576000
16384000
X
X
16384000
24576000
X
X
24576000
18432000
X
X
18432000
24576000
X
X
24576000
16384000
X
16384000
X
X
24576000
X
24576000
X
18432000
X
18432000
X
22579200
X
22579200
X
16934400
X
16934400
X
22579200
X
16934400
X
22579200
X
16934400
X
22579200
X
22579200
X
16934400
X
16934400
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Datasheet
13. Ordering Information
Table 84. Ordering Information
Part Number
ALC5623-GR
ALC5623-GRT
Package
Status
QFN-32 in ‘Green’ Package (Tray)
Mass Production
QFN-32 in ‘Green’ Package (Tape & Reel)
Mass Production
Note 1: See page 6 for Green package and version identification.
Note 2: Above parts are tested under AVDD=AVDD2=3.3V.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
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