ALC5628-GRT [REALTEK]
I2S/PCM STEREO DAC WITH HEADPHONE;
| 型号： | ALC5628-GRT |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | I2S/PCM STEREO DAC WITH HEADPHONE PC |
| 文件： | 总45页 (文件大小：802K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC5628
I2S/PCM STEREO DAC WITH HEADPHONE
AND MONO CLASS-D SPEAKER AMPLIFIER
DATASHEET
Rev. 1.2
26 June 2009
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
ALC5628
Datasheet
COPYRIGHT
©2009 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC5628 Audio DAC IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
Release Date
Summary
1.0
-
Preliminary release.
Preliminary release.
First release.
1.1
-
1.2
2009/06/26
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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ALC5628
Datasheet
Table of Contents
1.
2.
3.
4.
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................2
SYSTEM APPLICATIONS...............................................................................................................................................3
BLOCK DIAGRAM...........................................................................................................................................................4
4.1.
4.2.
FUNCTION BLOCK ........................................................................................................................................................4
AUDIO MIXER PATH.....................................................................................................................................................5
5.
6.
PIN ASSIGNMENTS .........................................................................................................................................................6
5.1.
GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................6
PIN DESCRIPTIONS.........................................................................................................................................................7
6.1.
DIGITAL I/O.................................................................................................................................................................7
ANALOG I/O.................................................................................................................................................................7
FILTER/REFERENCE......................................................................................................................................................7
POWER/GROUND..........................................................................................................................................................8
6.2.
6.3.
6.4.
7.
FUNCTIONAL DESCRIPTION.......................................................................................................................................9
7.1.
7.2.
POWER .........................................................................................................................................................................9
RESET ..........................................................................................................................................................................9
7.2.1. Power-On Reset (POR) ..........................................................................................................................................9
7.3.
7.4.
CLOCKING..................................................................................................................................................................10
I2C CONTROL INTERFACE ..........................................................................................................................................11
7.4.1. Addressing Setting................................................................................................................................................11
7.4.2. Complete Data Transfer.......................................................................................................................................11
7.4.3. Odd-Addressed Register Access ...........................................................................................................................12
7.5.
DIGITAL DATA INTERFACE ........................................................................................................................................12
7.5.1. I2S/PCM Interface ................................................................................................................................................12
7.6.
ANALOG SIGNAL PATH ..............................................................................................................................................14
7.6.1. Line Input .............................................................................................................................................................14
7.6.2. Speaker Output.....................................................................................................................................................14
7.6.3. Headphone Output................................................................................................................................................15
7.6.4. Stereo DAC...........................................................................................................................................................15
7.6.5. Headphone Mixer.................................................................................................................................................15
7.6.6. Speaker Mixer.......................................................................................................................................................16
7.7.
7.8.
7.9.
7.10.
POWER MANAGEMENT...............................................................................................................................................16
HEADPHONE DEPOP ...................................................................................................................................................16
AVC CONTROL..........................................................................................................................................................17
ZERO CROSS ..............................................................................................................................................................18
8.
REGISTER DESCRIPTIONS.........................................................................................................................................19
8.1.
REG-00H: SOFTWARE RESET......................................................................................................................................19
REG-02H: SPEAKER OUTPUT VOLUME.......................................................................................................................19
REG-04H: HEADPHONE OUTPUT VOLUME .................................................................................................................19
REG-0A: LINE INPUT VOLUME .................................................................................................................................20
REG-0C: STEREO DAC DIGITAL VOLUME .................................................................................................................20
REG-16H: SOFT DELAY VOLUME CONTROL TIME......................................................................................................21
REG-1CH: OUTPUT MIXER CONTROL ........................................................................................................................21
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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Datasheet
8.8.
8.9.
REG-34H: STEREO AUDIO SERIAL DATA PORT CONTROL ..........................................................................................22
REG-38H: STEREO DAC CLOCK CONTROL ................................................................................................................22
REG-3AH: POWER MANAGEMENT ADDITION 1..........................................................................................................23
REG-3CH: POWER MANAGEMENT ADDITION 2..........................................................................................................24
REG-3EH: POWER MANAGEMENT ADDITION 3 ..........................................................................................................25
REG-40H: GENERAL PURPOSE CONTROL ...................................................................................................................25
REG-42H: GLOBAL CLOCK CONTROL ........................................................................................................................26
REG-44H: PLL M/N CODE CONTROL.........................................................................................................................26
REG-5AH: JACK DETECT CONTROL ...........................................................................................................................27
REG-5CH: MISC1 CONTROL......................................................................................................................................27
REG-5EH: MISC2 CONTROL......................................................................................................................................28
REG-68H: AUTOMATIC VOLUME CONTROL (AVC) CONTROL ...................................................................................29
REG-6AH: PRIVATE REGISTER INDEX ........................................................................................................................29
REG-6CH: PRIVATE REGISTER DATA .........................................................................................................................29
PRIVATE-21H: AUTO VOLUME CONTROL REGISTER 1 ...............................................................................................30
PRIVATE-22H: AUTO VOLUME CONTROL REGISTER 2 ...............................................................................................30
PRIVATE-23H: AUTO VOLUME CONTROL REGISTER 3 ...............................................................................................30
PRIVATE-24H: AUTO VOLUME CONTROL REGISTER 4 ...............................................................................................30
PRIVATE-25H: AUTO VOLUME CONTROL REGISTER 5 ...............................................................................................31
PRIVATE-39H: DIGITAL INTERNAL REGISTER ............................................................................................................31
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
8.17.
8.18.
8.19.
8.20.
8.21.
8.22.
8.23.
8.24.
8.25.
8.26.
8.27.
9.
ELECTRICAL CHARACTERISTICS ..........................................................................................................................32
9.1.
DC CHARACTERISTICS...............................................................................................................................................32
9.1.1. Absolute Maximum Ratings..................................................................................................................................32
9.1.2. Recommended Operating Conditions...................................................................................................................32
9.1.3. Static Characteristics ...........................................................................................................................................32
9.2.
9.3.
ANALOG PERFORMANCE CHARACTERISTICS..............................................................................................................33
AC TIMING CHARACTERISTICS ..................................................................................................................................34
9.3.1. I2C Control Interface............................................................................................................................................34
9.3.2. I2S/PCM Interface Master Mode ..........................................................................................................................35
9.3.3. I2S/PCM Interface Slave Mode.............................................................................................................................36
10.
11.
12.
APPLICATION CIRCUITS .......................................................................................................................................37
MECHANICAL DIMENSIONS.................................................................................................................................38
ORDERING INFORMATION...................................................................................................................................39
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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Datasheet
List of Tables
TABLE 1. DIGITAL I/O PINS.........................................................................................................................................................7
TABLE 2. ANALOG I/O PINS ........................................................................................................................................................7
TABLE 3. FILTER/REFERENCE PINS .............................................................................................................................................7
TABLE 4. POWER/GROUND PINS .................................................................................................................................................8
TABLE 5. RESET OPERATION.......................................................................................................................................................9
TABLE 6. POWER-ON RESET VOLTAGE .......................................................................................................................................9
TABLE 7. PLL CLOCK SETTING TABLE FOR 48K (UNIT: MHZ).................................................................................................10
TABLE 8. PLL CLOCK SETTING TABLE FOR 44.1K (UNIT: MHZ)..............................................................................................10
TABLE 9. MX00 SOFTWARE RESET...........................................................................................................................................19
TABLE 10. MX02 SPEAKER OUTPUT VOLUME ...........................................................................................................................19
TABLE 11. MX04 HEADPHONE OUTPUT VOLUME ......................................................................................................................19
TABLE 12. MX0A LINE INPUT VOLUME....................................................................................................................................20
TABLE 13. MX0C STEREO DAC DIGITAL VOLUME ...................................................................................................................20
TABLE 14. MX16 SOFT DELAY VOLUME CONTROL TIME ..........................................................................................................21
TABLE 15. MX1C OUTPUT MIXER CONTROL .............................................................................................................................21
TABLE 16. MX34 STEREO AUDIO SERIAL DATA PORT CONTROL...............................................................................................22
TABLE 17. MX38 STEREO DAC CLOCK CONTROL.....................................................................................................................22
TABLE 18. MX3A POWER MANAGEMENT ADDITION 1 ..............................................................................................................23
TABLE 19. HEADPHONE DRIVE ABILITY SELECTION ..................................................................................................................23
TABLE 20. MX3C POWER MANAGEMENT ADDITION 2...............................................................................................................24
TABLE 21. MX3E POWER MANAGEMENT ADDITION 3...............................................................................................................25
TABLE 22. MX40 GENERAL PURPOSE CONTROL ........................................................................................................................25
TABLE 23. MX42 GLOBAL CLOCK CONTROL .............................................................................................................................26
TABLE 24. MX44 PLL M/N CODE CONTROL .............................................................................................................................26
TABLE 25. MX5A JACK DETECT CONTROL................................................................................................................................27
TABLE 26. MX5C MISC1 CONTROL ..........................................................................................................................................27
TABLE 27. MX5E MISC2 CONTROL ..........................................................................................................................................28
TABLE 28. MX68 AUTOMATIC VOLUME CONTROL (AVC) CONTROL........................................................................................29
TABLE 29. MX6A PRIVATE REGISTER INDEX.............................................................................................................................29
TABLE 30. MX6C PRIVATE REGISTER DATA..............................................................................................................................29
TABLE 31. PR21 AUTO VOLUME CONTROL REGISTER 1 ............................................................................................................30
TABLE 32. PR22 AUTO VOLUME CONTROL REGISTER 2 ............................................................................................................30
TABLE 33. PR23 AUTO VOLUME CONTROL REGISTER 3 ............................................................................................................30
TABLE 34. PR24 AUTO VOLUME CONTROL REGISTER 4 ............................................................................................................30
TABLE 35. PR25 AUTO VOLUME CONTROL REGISTER 5 ............................................................................................................31
TABLE 36. PR39 DIGITAL INTERNAL REGISTER .........................................................................................................................31
TABLE 37. ABSOLUTE MAXIMUM RATINGS................................................................................................................................32
TABLE 38. RECOMMENDED OPERATING CONDITIONS.................................................................................................................32
TABLE 39. THRESHOLD VOLTAGE ..............................................................................................................................................32
TABLE 40. ANALOG PERFORMANCE CHARACTERISTICS .............................................................................................................33
TABLE 41. I2C CONTROL INTERFACE TIMING .............................................................................................................................34
TABLE 42. I2S MASTER MODE TIMING .......................................................................................................................................35
TABLE 43. I2S SLAVE MODE TIMING ..........................................................................................................................................36
TABLE 44. ORDERING INFORMATION..........................................................................................................................................39
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................4
FIGURE 2. AUDIO MIXER PATH ...................................................................................................................................................5
FIGURE 3. PIN ASSIGNMENTS ......................................................................................................................................................6
FIGURE 4. DATA TRANSFER OVER I2C CONTROL INTERFACE ...................................................................................................11
FIGURE 5. WRITE WORD PROTOCOL .......................................................................................................................................11
FIGURE 6. READ WORD PROTOCOL .........................................................................................................................................11
FIGURE 7. PCM STEREO DATA MODE A FORMAT (SEL_I2S_DATA_FORMAT=10’B, CTRL_I2S_BCLK_POLARITY=0’B) ............12
FIGURE 8. PCM STEREO DATA MODE A FORMAT (SEL_I2S_DATA_FORMAT=10’B, CTRL_I2S_BCLK_POLARITY=1’B) ............13
FIGURE 9. PCM STEREO DATA MODE B FORMAT (SEL_I2S_DATA_FORMAT=11’B, CTRL_I2S_BCLK_POLARITY=0’B).............13
FIGURE 10. I2S DATA FORMAT (SEL_I2S_DATA_FORMAT=00’B)................................................................................................13
FIGURE 11. LEFT-JUSTIFIED DATA FORMAT (SEL_I2S_DATA_FORMAT=01’B, CTRL_I2S_BCLK_POLARITY=0’B).......................14
FIGURE 12. AVC BLOCK OF DAC MODULE ...............................................................................................................................17
FIGURE 13. AVC BEHAVIOR.......................................................................................................................................................17
FIGURE 14. ZERO CROSS DISABLED WHEN OUTPUT MUTED.......................................................................................................18
FIGURE 15. ZERO CROSS ENABLED WHEN OUTPUT MUTED........................................................................................................18
FIGURE 16. GLOBAL CLOCK CONTROL.......................................................................................................................................26
FIGURE 17. I2C CONTROL INTERFACE WAVEFORM.....................................................................................................................34
FIGURE 18. I2S MASTER MODE WAVEFORM...............................................................................................................................35
FIGURE 19. I2S SLAVE MODE WAVEFORM..................................................................................................................................36
FIGURE 20. APPLICATION CIRCUITS............................................................................................................................................37
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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Datasheet
1. General Description
The ALC5628 is a highly-integrated I2S/PCM interface audio DAC with multiple input/output ports and
is designed for Multimedia and Communication handheld devices. It provides a Stereo Hi-Fi DAC for
playback via the I2S/PCM interface and is controlled by the I2C interface.
To reduce component count, the device can connect to:
• LINE_IN stereo Single-Ended analog inputs (can be configured to mono Differential analog input)
• Single-Ended stereo Headphone
• MONO or Stereo Bridge-Tied Load (BTL) Speaker
Multiple analog input and output pins are provided for seamless integration with analog connected
wireless communication devices. Differential input/output connections efficiently reduce noise
interference, providing better sound quality. The Class-D amplifier can be directly connected to a 2.4
Watt Mono Speaker, removing the need for an additional amplifier, further cutting both cost and required
board area.
The ALC5628 AVDD operates at supply voltages from 2.3V to 3.6V. DCVDD and DBVDD operate
from 1.8V to 3.6V, and SPKVDD operates from 2.3V to 5V. To extend battery life, each section of the
device can be powered down individually under software control. Leakage current in maximum power
saving state is less than 10µA.
The ALC5628 is available in a 4x4mm ‘Green’ QFN-24 package, making it ideal for use in handheld
portable systems.
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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Datasheet
2. Features
Digital-to-Analog Converter with 100dB SNR and –86dB THD+N at 3.3V
Two analog stereo single-ended or one stereo differential input, LINEIN_L/R
BTL (Bridge-Tied Load) Class-D Speaker output with on-chip 2.4W speaker driver (SPKVDD=5V,
4Ω load)
Supports playback soft-mute, digital volume, digital AVC
Stereo headphone output with on-chip 45mW headphone driver (AVDD=3.3V, 16Ω load)
Supports pop noise suppression with external capacitor
Digital power supplied from 1.8V to 3.6V
Analog power and headphone power supplied from 2.3V to 3.6V
Power management and enhanced power saving
Internal PLL can receive wide range of clock inputs
Supports crystal oscillator
Supports sampling rate 8KHz ~ 192KHz
Supports I2C control interface
Supports three programmable data interfaces
I2S, left justified or DSP
16/20/24-bit word lengths
Master or Slave clock mode
Speaker amplifier power supplies from 2.3V to 5V
24-pin QFN 4x4mm package for small footprint
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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Datasheet
3. System Applications
Portable media player
MP3 player
Bluetooth A2DP (Advanced Audio Distribution Profile) headsets
Portable Navigation Device (PND)
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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Datasheet
4. Block Diagram
4.1. Function Block
ALC5628
LINE_IN_L
Headphone
Amplifier
HP_OUT_L
HP_OUT_R
Headphone
Amplifier
LINE_IN_R
Output Mixer
& Gain
DACL
DACR
VREF
Class D
Speaker
Amplifier
SPK_OUT
VREF/ Depop
Cdepop
SPK_OUT_N
I 2C Control
Interface &
Register
OSC_EN
SCLK
SDA
Crystal OSC
(PLL)
I2S Interface
Figure 1. Block Diagram
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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Datasheet
4.2. Audio Mixer Path
Figure 2. Audio Mixer Path
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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Datasheet
5. Pin Assignments
18
17
16
15
14
13
SPKGND
NC
19
20
21
22
23
24
12
11
10
9
DBVDD
DCVDD
DGND
XTO
SPKVDD
VREF
AGND
8
XTI
HP_OUT_R
7
SDAC
1
2
3
4
5
6
Figure 3. Pin Assignments
5.1. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3.
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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ALC5628
Datasheet
6. Pin Descriptions
6.1. Digital I/O
Table 1. Digital I/O Pins
Pin Name
LRCK
BCLK
SDAC
XTI
Type Pin No Description
Characteristic Definition
IO
IO
I
5
6
Digital Audio Input Frame Sync
Digital Audio Serial Clock
Digital Audio Serial Data Input
Crystal Input
Schmitt Trigger Input, Output
Schmitt Trigger Input, Output
Schmitt Trigger Input
7
I
8
Schmitt Trigger Input
XTO
O
I
9
Crystal Output
Schmitt Trigger Output
Schmitt Trigger Input
SCLK
SDA
13
14
15
I2C: Clock Input
IO
I
I2C: Data Input And Output
Schmitt Trigger Input, Output
OSC_EN
Crystal Oscillator Enable Control, Connect Schmitt Trigger Input
to VDD or GND
VDD: Crystal enabled
GND: Crystal disabled
6.2. Analog I/O
Table 2. Analog I/O Pins
Pin Name
Type Pin No Description
Characteristic Definition
Analog Input
LINE_IN_L/JD1
LINE_IN_R/JD2
SPK_OUT
I
I
3
Line Input Left Channel, Jack Detect_1
Line Input Right Channel, Jack Detect_2
4
Analog Input
O
O
17
18
Speaker Out Left Channel or Positive Out Speaker Amplifier Output
SPK_OUT_N
Speaker Out Right Channel, Negative
Right Channel, or Negative Output
Speaker Amplifier Output
HP_OUT_L
HP_OUT_R
O
O
1
Headphone Out Left Channel
Headphone Out Right Channel
Analog Amplifier Output
Analog Amplifier Output
24
6.3. Filter/Reference
Table 3. Filter/Reference Pins
Pin Name
Type Pin No Description
Characteristic Definition
Cdepop
IO
16
De-Pop Capacitor, Connect 1µF Capacitor Capacitor to Analog Ground
to Analog GND
VREF
O
22
Reference Voltage Output, Connect 4.7µF Capacitor to Analog Ground
Capacitor to Analog GND
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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Datasheet
6.4. Power/Ground
Table 4. Power/Ground Pins
Description
Pin Name
DGND
Type
Pin No
10
Characteristic Definition
P
P
P
P
P
P
P
P
Digital GND
-
DCVDD
DBVDD
SPKGND
SPKVDD
AGND
11
Digital VDD
1.8V~3.6V (Core)
12
Digital VDD
1.8V~3.6V (IO Buffer)
19
Speaker Amplifier GND
Speaker Amplifier VDD
Analog GND
-
21
2.3V~5V
23
-
AVDD
2
Analog VDD
2.3V~3.6V
-
SPKGND
Exposed Pad Speaker Amplifier GND
Must be Connected to System DGND
Not Connected
NC
-
20
-
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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Datasheet
7. Functional Description
7.1. Power
The ALC5628 has many power blocks. The power supply limit conditions are DBVDD≥DCVDD and
SPKVDD≥AVDD≥DCVDD. To prevent pop noise, we suggest that DCVDD is powered on before
AVDD.
7.2. Reset
There are two types of reset operation: Power-On-Reset (POR) and Register reset.
Table 5. Reset Operation
Reset Type
Trigger Condition
Codec Response
POR
Monitor Digital Power Supply Voltage Reach
VPOR
Reset all hardware logic and all registers to default
values.
Register Reset
Write Reg00
Reset all registers to default values.
7.2.1. Power-On Reset (POR)
When power is on, DCVDD passes through the VPOR band of the ALC5628 (VPORH~VPORL). A Power-On
Reset (POR) will generate an internal reset signal (POR reset ‘LOW’) to reset the whole chip.
Table 6. Power-On Reset Voltage
Symbol
VPOR_ON
VPOR_OFF
Min
1.0
-
Typical
Max
1.6
-
Unit
V
-
1.3
V
Note: The VPOR_OFF must be below VPOR_ON
.
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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Datasheet
7.3. Clocking
The ALC5628 supports a Crystal as internal system clock. When the OSC_EN pin is kept high or floating,
the audio system clock can be selected from XTI/XTO or PLL. When a crystal is applied,
256/384/512/768Fs is required from XTI/XTO. If using internal PLL as audio internal clock, set the PLL
output to 512Fs.
A Phase-Lock Loop (PLL) is used to provide a flexible input clock from 2.048MHz (64Fs of 32kHz) to
40MHz. Typical choices are 2.048MHz, 4.096MHz, and 13MHz. The source of the PLL can be set to
XTI or BCLK by setting sel_pll_sour (Reg42[14]). Firmware can setup the PLL to output the desired
frequency for the system clock.
The PLL transmit formula is: FOUT = (XTI*(N+2)) / ((M+2)*(K+2)) (Typical K=2)
Table 7. PLL Clock Setting Table for 48K (Unit: MHz)
XTI
2.048
3.6864
4.096
12
M Code
N Code
94
Fvco
98.304
98.304
98.304
98.25
K Code
Fout
24.576
24.576
24.576
24.5625
24.57812
24.576
24.57143
24.5647
24.6
0
1
2
2
2
2
2
2
2
2
2
78
0
46
14
14
3
129
119
30
13
98.3125
98.304
98.28571
98.25882
98.4
15.36
16
5
41
19.2
19.68
15
0
85
8
Table 8. PLL Clock Setting Table for 44.1K (Unit: MHz)
XTI
2.048
3.6864
4.096
12
M Code
N Code
86
Fvco
K Code
Fout
0
90.112
2
2
2
2
2
2
2
2
2
22.528
0
47
90.3168
90.48436
90.35294
90.23529
90.35294
90.28571
90.35294
90.29647
22.5792
22.62109
22.58824
22.55882
22.58824
22.57143
22.58824
22.57412
9
241
126
116
98
15
15
15
12
15
15
13
15.36
16
77
19.2
19.68
78
76
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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ALC5628
Datasheet
7.4. I2C Control Interface
I2C is a 2-wire half-duplex serial communication interface, supporting only slave mode.
7.4.1. Addressing Setting
(MSB)
0
BIT
(LSB)
RW
0
1
1
0
0
0
7.4.2. Complete Data Transfer
Data Transfer over I2C Control Interface
Figure 4. Data Transfer Over I2C Control Interface
Write WORD Protocol
Read WORD Protocol
Figure 5. Write WORD Protocol
S: Start Condition
A: 0 for ACK, 1 for NACK
Data Byte: 16-bit Mixer data
ꢀ: Master-to-Slave
Slave Address: 7-bit Device Address
Wr: 0 for Write Command
Rd: 1 for Read Command
ꢀ: Slave-to-Master
Command Code: 8-bit Register Address
Figure 6. Read WORD Protocol
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
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ALC5628
Datasheet
7.4.3. Odd-Addressed Register Access
The ALC5628 will return ‘0000h’ when odd-addressed and unimplemented registers are read.
7.5. Digital Data Interface
7.5.1. I2S/PCM Interface
The Digital to Analog Converter (DAC) serial data is input via the SDAC pin. The serial data is shifted in
on the rising edge of BCLK (ctrl_i2s_bclk_polarity=0’b) or the falling edge (ctrl_i2s_bclk_polarity=1’b).
The Left/Right Clock (LRCK) signal is the frame sync signal. Left/Right data can be swapped by
en_dac_lrck_swap.
The ALC5628 I2S/PCM interface can be configured to Master mode or Slave mode. In Master mode
(sel_i2s_mode=0’b), BCLK and LRCK are configured as output. In Slave mode (sel_i2s_mode=1’b),
BCLK and LRCK are configured as input. The XTI provides BCLK synchronized clock externally as
Stereo System Clock.
The ALC5628 supports three independent I2S/PCM interfaces for Stereo Audio data formats:
• PCM/DSP mode
• Left justified mode
• I2S mode
Figure 7. PCM Stereo Data Mode A Format-1 (sel_i2s_data_format=10’b, ctrl_i2s_bclk_polarity=0’b)
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Mono Class-D Speaker Amplifier
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Datasheet
Figure 8. PCM Stereo Data Mode A Format-2 (sel_i2s_data_format=10’b, ctrl_i2s_bclk_polarity=1’b)
Figure 9. PCM Stereo Data Mode B Format (sel_i2s_data_format=11’b, ctrl_i2s_bclk_polarity=0’b)
Figure 10. I2S Data Format (sel_i2s_data_format=00’b)
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Datasheet
Figure 11. Left-Justified Data Format (sel_i2s_data_format=01’b, ctrl_i2s_bclk_polarity=0’b)
7.6. Analog Signal Path
7.6.1. Line Input
LINE_IN_L and LINE_IN_R provide 2-channel stereo single-ended inputs that can be mixed into any
analog output mixer. In addition, LINE_IN_L and LINE_IN_R can be configured as mono channel
differential input by Reg0A[5]: en_li_diff, which only can output to the HP mixer.
• LINE_IN_L/R volume and mute are controlled by Reg0A
• sel_li_l_vol and sel_li_r_vol can be used to power down LINE_IN volume control
• LINE_IN_L is pin shared with JD1 and can be configured by sel_jd_source
• LINE_IN_R is pin shared with JD2 and can be configured by sel_jd_source
7.6.2. Speaker Output
SPK_OUT provides one-channel differential output and can be configured to dual single-ended output.
The SPK_OUT source is selected in sel_spk_vol_in, as listed below:
• No Input (VMID
)
• Headphone mixer
• Speaker mixer
The ALC5628 Speaker-out supports a Class-D type amplifier. As the power voltage of SPKVDD is
usually higher than AVDD, it must set Class-D VMID ratio at spk_ampd_ratio_clsd in order to extend the
output level.
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Datasheet
The SPK_OUT volume and mute are controlled by Reg02. Reg3E[12]: pow_spk_vol can be used to
power down Speaker output. Reg3C[14]: pow_clsd is used to power down the Class-D amplifier.
SPK_OUT supports ‘Soft Volume Delay Mute’ and ‘Zero-Crossing Detect’ functions which can be
enabled by Reg5C[15]:en_sp_l_dezero, Reg5C[14]:en_sp_l_softvol, Reg5C[13]:en_sp_r_dezero, and
Reg5C[12]:en_sp_r_softvol.
7.6.3. Headphone Output
HP_OUT_L/R provides 2-channel single-ended output. The source of HP_OUT_L/R can be selected
from sel_hp_l_in & sel_hp_r_in as below.
• VMID
• Headphone mixer
The HP_OUT_L/R volume and mute are controlled by Reg04. Besides, Reg3E[10]: pow_hp_l_vol and
Reg3E[9]: pow_hp_r_vol can be used to power down the HP output volume.
HP_OUT supports ‘Soft Volume Delay Mute’ and ‘Zero-Crossing Detect’ functions which can be
enabled by Reg5C[11]:en_hp_l_dezero, Reg5C[10]:en_hp_l_softvol, Reg5C[9]:en_hp_r_dezero, and
Reg5C[8]:en_hp_r_softvol.
HP_OUT_L/R source can be selected from DAC Stereo output (Reg1C[1]: en_dac_hp) for high quality
performance playback.
7.6.4. Stereo DAC
The stereo DAC can be configured to different sample rates by driving 256Fs/384Fs into audio SYSCLK,
and individually set by sel_i2s_bclk_ms (Reg38[12]).
dac_l_vol & dac_r_vol can be used to control the DAC output volume.
7.6.5. Headphone Mixer
The headphone (HP) mixer is used to drive stereo output, including HP_OUT_L/R and SPK_OUT (P/N)
(SPK_OUT_L/R).
The following signals can be mixed into the headphone mixer:
• LINE_IN_L/R (Controlled by Reg0A)
• Stereo DAC output (Controlled by Reg0C)
When the SPK_OUT source is from HP mixer, SPK_OUT can be configured to stereo single-ended or
mono differential output by setting spkon_source_clsd (Reg1C[15:14]). The headphone mixer can be
powered down by setting pow_mix_hp_l (Reg3C[5]) & pow_mix_hp_r (Reg3C[4]).
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Datasheet
7.6.6. Speaker Mixer
The speaker (SPK) mixer is used to drive SPK_OUT.
The following signals can be mixed into the speaker mixer:
• LINE_IN_L/R (Controlled by Reg0A)
• Stereo DAC output (Controlled by Reg0C)
Note: The speaker mixer can be powered down by setting pow_mix_spk (Reg3C[3]).
7.7. Power Management
The ALC5628 supports detailed Power Management control registers within Reg3A, 3C, and 3E. Each
particular block will be active only when individual bits of Reg3A, 3C, and 3E are set to enable.
7.8. Headphone Depop
The ALC5628 provides a headphone depop mechanism in order to eliminate the pop noise of headphone
out. An external 1µF Capacitor is required in this application. Refer to the ALC5628 Application Notes
(separate document) for details.
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Datasheet
7.9. AVC Control
The Automatic Volume Control (AVC) function dynamically adjusts the input signal quantized by DAC
to an expected sound level by setting THmax and THmin.
When the average level of input signal quantized by DAC is higher than THmax, the AVC will decrease
the selected analog gain to attenuate the quantized Pulse Code Modulation (PCM) signal to a lower
amplitude than THmax. When the average level of input signal quantized by DAC is lower than THmin,
the AVC will increase the selected analog gain to amplify the input signal. The quantized PCM signal is
then set to a higher amplitude than THmin. The quantized PCM has an average level between THmin and
THmax.
In order to avoid outputting a strong amplified signal when the gain detector input level is transiting from
a very small signal to a normal signal, the AVC block will limit the selected analog gain to unit gain
(=0dB) when the input level of the gain detector is lower than THnonact.
Figure 12. AVC Block of DAC Module
Figure 13. AVC Behavior
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Datasheet
7.10. Zero Cross
When Zero-Cross detect is enabled, the ALC5628 will change each output volume or mute only if the
signal swing crosses the zero point. This function can avoid pop noise when volume is changed or muted.
Figure 14. Zero Cross Disabled when Output Muted
Figure 15. Zero Cross Enabled when Output Muted
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Mono Class-D Speaker Amplifier
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Datasheet
8. Register Descriptions
8.1. Reg-00h: Software Reset
Default: 0003’h
Table 9. MX00 Software Reset
Default Description
Name
id
Bits
15:8
7:0
RW
R
00’h
03’h
Chip ID
Reserved
R
Reserved
8.2. Reg-02h: Speaker Output Volume
Default: 9F9F’h
Table 10. MX02 Speaker Output Volume
Name
Bits
RW
Default Description
mute_sp_l
15
RW
1’h
Mute Speaker Output Positive/Negative
0: On
1: Mute (-∞ dB)
Reserved
14:13
12:8
7
R
0’h
1F’h
1’h
Reserved
sel_sp_l_vol
mute_sp_r
RW
RW
SPK Left Output Volume (SPKL[4:0]) in 1.5dB Steps
Mute SPK Right Channel
Reg1C[15:14] = 01’b, Mute by Reg02[15]
0: On
1: Mute (-∞ dB)
Reserved
6:5
4:0
R
0’h
Reserved
sel_sp_r_vol
RW
1F’h
SPK Right Output Volume (SPKR[4:0]) in 1.5dB Steps
Note: For SPKR/SPKL: 00h: 0dB attenuation.
1Fh: 46.5dB attenuation.
8.3. Reg-04h: Headphone Output Volume
Default: 9F9F’h
Table 11. MX04 Headphone Output Volume
Name
Bits
RW
Default Description
mute_hp_l
15
RW
1’h
Mute Left Headphone Amp Control
0: On
1: Mute Left Channel (-∞ dB)
Reserved
sel_hp_l_vol
mute_hp_r
14:13
12:8
7
R
RW
RW
0’h
1F’h
1’h
Reserved
Headphone Output Left Volume (HPL[4:0]) in 1.5dB Steps
Mute Right Headphone Amp Control
0: On
1: Mute Left Channel (-∞ dB)
Reserved
sel_hp_r_vol
6:5
4:0
R
RW
0’h
1F’h
Reserved
Headphone Output Right Volume (HPR[4:0]) in 1.5dB Steps
Note: For HPR/HPL: 00h: 0dB attenuation.
1Fh: 46.5dB attenuation.
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Datasheet
8.4. Reg-0Ah: LINE Input Volume
Default: C8C8’h
Table 12. MX0A LINE Input Volume
Bits RW Default Description
Name
mute_lil2hp
15 RW
1’h
Mute Left Volume Output to Headphone Left Mixer Control
0: On 1: Mute
Mute Left Volume Output to Speaker Mixer Control
mute_lil2spk
14 RW
1’h
0: On
1: Mute
Reserved
13
R
0’h
08’h
1’h
Reserved
sel_li_l_vol
mute_lir2hp
12:8 RW
Line-In Left Volume (NLV[4:0]) in 1.5dB Step
7
6
5
RW
RW
RW
Mute Right Volume Output to Headphone Right Mixer Control*
0: On
Mute Right Volume Output to Speaker Mixer Control*
0: On 1: Mute
Line-In Differential Input Control
1: Mute
mute_lir2spk
en_li_diff
1’h
0’h
0: Disable
1: Enable. Only output to HP left mixer
sel_li_r_vol
4:0 RW
08’h
Line-In Right Volume (NRV[4:0]) in 1.5dB Steps*
Note: For NRV/NLV: 00h: +12 dB gain
08h: 0 dB attenuation
1Fh: 34.5 dB attenuation
Note: ‘*’indicates no function when Reg-0A[5] = 1’b.
8.5. Reg-0Ch: Stereo DAC Digital Volume
Default: FFFF’h
Table 13. MX0C Stereo DAC Digital Volume
Name
Bits RW Default Description
mute_dacl2hp
15 RW
14 RW
13:8 RW
1’h
Mute DAC Left Channel Digital Volume Output to Headphone Mixer Control
0: On 1: Mute (-∞ dB)
Mute DAC Left Channel Digital Volume Output to Speaker Mixer Control
0: On 1: Mute (-∞ dB)
mute_dacl2spk
1’h
dac_l_vol
3F’h
1’h
DAC Left Channel Digital Volume (PLV[5:0]) in 0.75dB Steps
mute_dacr2hp
7
RW
Mute Right Channel DAC Digital Volume Output to Headphone Mixer
Control
0: On
Mute Right Channel DAC Digital Volume Output to Speaker Mixer Control
0: On 1: Mute (-∞ dB)
1: Mute (-∞ dB)
mute_dacr2spk
dac_r_vol
6
RW
1’h
5:0 RW
3F’h
DAC Right Channel Digital Volume (PRV[5:0]) in 0.75dB Steps
Note: For PRV/PLV: 00h: +12dB gain
10h: 0dB attenuation
3Fh: 35.25dB attenuation
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Datasheet
8.6. Reg-16h: Soft Delay Volume Control Time
Default: 0009’h
Table 14. MX16 Soft Delay Volume Control Time
Name
Bits RW Default Description
Reserved
15:4
3:0
R
0’h
Reserved
sel_sync_softvol
RW 1001’b Soft Volume Change Delay Time (Default=1001b)
0000: 1 SVSYNC
0010: 4 SVSYNC
0100: 16 SVSYNC
0110: 64 SVSYNC
1000: 256 SVSYNC
0001: 2 SVSYNC
0011: 8 SVSYNC
0101: 32 SVSYNC
0111: 128 SVSYNC
1001: 512 SVSYNC
1010: 1024 SVSYNC
Others: Reserved
Note: SVSYNC=1/Fs, Step: -1.5dBFS.
8.7. Reg-1Ch: Output Mixer Control
Default: 8004’h
Table 15. MX1C Output Mixer Control
Bits RW Default Description
Name
spkon_source_clsd
15:14 RW
2’h
Reg1C
[15:14]
Any Mixer to SPKOUT
SPK_OUT
SPK_OUT_N
Control
Register
Control
Register
Config
Config
00'b
01'b
VOL_LP Reg02[15:8] VOL_RN
VOL_LP Reg02[15:8] VOL_RP
Reg02[7:0]
Reg02[7:0]
10'b
11'b
VOL_LP Reg02[15:8] VOL_LN Reg02[15:8]
MUTE
MUTE
MUTE
MUTE
Reserved
13:12
R
0’h
Reserved
sel_spk_vol_in
11:10 RW
00’h
SPK Volume Output Source Select
00: VMID (No input)
01: HP Mixer
10: Speaker mixer (diff out)
11: Reserved
sel_hp_l_in
sel_hp_r_in
9
8
RW
RW
0’h
0’h
HPL Volume Output Source Select
0: VMID (No input)
1: HP Left Mixer
1: HP Right Mixer
HPR Volume Output Source Select
0: VMID (No input)
Reserved
7:3
2
R
0’b
1’h
Reserved
en_spk_vol_diff
RW
SPK Volume Differential Negative Signal Output Enable
0: Disable negative signal 1: Enable negative signal
DAC Direct Output to HP Amplifier Control
en_dac_hp
Reserved
1
0
RW
R
0’b
0’b
0: Normal
1: Enable direct output
Reserved
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Datasheet
8.8. Reg-34h: Stereo Audio Serial Data Port Control
Default: 8000’h
Table 16. MX34 Stereo Audio Serial Data Port Control
Name
Bits
RW
Default Description
sel_i2s_mode
15
RW
1’h
Main Serial Data Port Mode Selection
0: Master
Reserved
1: Slave
Reserved
14:8
7
R
0’h
0’h
ctrl_i2s_bclk_polarity
RW
Stereo I2S BCLK Polarity Control
0: Normal
1: Invert
Reserved
6:5
4
R
0’h
0’h
Reserved
en_dac_lrck_swap
RW
DAC Data L/R Swap
0: DAC data appears at left phase of LRCK
1: DAC data appears at right phase of LRCK
Note: Supports I2S & PCM.
Data Length Selection
sel_i2s_data_len
3:2
1:0
RW
RW
0’h
0’h
00: 16 bits
10: 24 bits
01: 20 bits
11: Reserved
sel_i2s_data_format
Stereo PCM Data Format Selection
00: I2S format
01: Left justified
10: PCM Mode A (LRCK One Plus at Master Mode)
11: PCM Mode B (LRCK One Plus at Master Mode)
8.9. Reg-38h: Stereo DAC Clock Control
Default: 2000’h
Table 17. MX38 Stereo DAC Clock Control
Name
Bits
RW
Default Description
sel_i2s_pre_div
15:13
RW
1’h
I2S Pre-Divider
000b: ÷1
001b: ÷2
011b: ÷8
101b: ÷32
010b: ÷4
100b: ÷16
Others: Reserved
sel_i2s_bclk_ms
12
RW
0’b
Master Mode Clock Relative to BCLK and LRCK
0b: 32bits (64FS)
Reserved
1b: 16bits (32FS)
Reserved
11:3
2
R
0’h
0’b
sel_dac_filter_clk
RW
Stereo DAC Filter Clock Select
0b: 256Fs
Reserved
1b: 384Fs
Reserved
1:0
R
0’h
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Datasheet
8.10. Reg-3Ah: Power Management Addition 1
Default: 0000’h
Table 18. MX3A Power Management Addition 1
Name
Bits
RW
Default Description
en_main_i2s
15
RW
0’h
I2S Digital Interface Enable
0: Disable
1: Enable
pow_zcd
14
RW
0’h
All Zero Cross Detect Power Down (Includes Digital)
0: Disable
1: Enable
Reserved
13:9
8
R
0’h
0’h
Reserved
pow_softgen
RW
Power on Softgen
1: Power on
0: Power down
Note: When pow_softgen=1, whether the HP can be driven
depends on the level on Cdepop (depneds in depop mode selection)
Reserved
7:6
5
R
0’h
0’h
Reserved
en_hp_out_amp
RW
1: Enable HP Output buffer for normal loading (used to drive High
Impedance)
0: Disable (DPOP mode)
en_hp_enhance_amp
Reserved
4
RW
R
0’h
0’h
1: Enable HP Enhance Output buffer
0: Disable (DPOP mode or normal loading mode)
Reserved
3:0
The following table describes Bit 4 & Bit 5:
Table 19. Headphone Drive Ability Selection
en_hp_enhance_amp Description
en_hp_out_amp
0’b
0’b
1’b
1’b
0’b
1’b
0’b
1’b
HP Output Off
Not Used
HP Output for High-Impedance Loading (>KOhm)
HP Output for Low-Impedance Loading (<100Ohm)
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Datasheet
8.11. Reg-3Ch: Power Management Addition 2
Default: 0000’h
Table 20. MX3C Power Management Addition 2
Name
Bits
15
RW
R
Default Description
Reserved
pow_clsd
0’h
0’b
Reserved
14
RW
0: Disable
1: Enable All Class-D Power
0: Disable
1: Enable VREF for All analog circuit (control to Vref pin)
pow_vref
pow_pll
13
12
RW
RW
0’h
0’h
0: Disable
1: Enable PLL
Reserved
11
10
RW
RW
0’h
0’h
Reserved (Must be Set to 0)
pow_dac_ref
0: Disable
1: Enable DAC reference circuit (Vref+/Vref-)
pow_dac_l
9
8
RW
RW
RW
RW
RW
RW
RW
R
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0: Disable
1: Enable left STEREO DAC and its filter clock
pow_dac_r
0: Disable
1: Enable right STEREO DAC and its filter clock
pow_dacl2mixer_direct
pow_dacr2mixer_direct
pow_mix_hp_l
pow_mix_hp_r
pow_mix_spk
Reserved
7
0: Disable
1: Enable left DAC to mixer and direct path power
6
0: Disable
1: Enable Right DAC to mixer and direct path power
5
0: Disable
1: Enable left headphone mixer
0: Disable
1: Enable right headphone mixer
0: Disable
1: Enable Speaker mixer
Reserved
4
3
2:0
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Datasheet
8.12. Reg-3Eh: Power Management Addition 3
Default: 0000’h
Table 21. MX3E Power Management Addition 3
Name
Bits
RW
Default Description
pow_main_bias
15
RW
0’h
0: Disable
1: Enable Main bias of analog circuit
Reserved
Reserved
14:13
12
R
0’h
0’h
pow_spk_vol
RW
0: Disable
1: Enable SPK_OUT output
Note: Power speaker volume controls the Class-D speaker output.
Reserved
11
10
R
0’h
0’h
Reserved
pow_hp_l_vol
RW
0: Disable
1: Enable HP_OUT_L Volume control & HP_L Amplifier
pow_hp_r_vol
9
RW
0’h
0: Disable
1: Enable HP_OUT_R Volume control & HP_R Amplifier
Reserved
Reserved
8
7
R
0’h
0’h
pow_li_l_vol
RW
0: Disable
1: Enable LINE_IN Left Volume control
0: Disable
1: Enable LINE_IN Right Volume control
Reserved (Must be set to ‘0’)
pow_li_r_vol
Reserved
6
RW
R
0’h
0’h
5:0
8.13. Reg-40h: General Purpose Control
Default: 0100’h
Table 22. MX40 General Purpose Control
Name
Bits
15:12
11:9
RW
R
Default Description
Reserved
0’h
0’h
Reserved
spk_ampd_ratio_clsd
RW
Speaker Class-D Amplifier VMID Ratio Control (Output Gain
Control)
000: 2.25Vdd
010: 1.75Vdd
100: 1.25Vdd
001: 2.00Vdd
011: 1.5Vdd
101: 1Vdd
Others: Not allowed
en_dac_hpf
Reserved
8
RW
R
1’h
0’h
STEREO DAC High Pass Filter
0: Disable
1: Enable
7:0
Reserved
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Mono Class-D Speaker Amplifier
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Datasheet
8.14. Reg-42h: Global Clock Control
Default: 0000’h
Table 23. MX42 Global Clock Control
RW Default Description
RW 0’h Clock Source MUX Control
Name
Bits
sel_sysclk
15
0: XTI
1: PLL
sel_pll_sour
14
RW
0’h
PLL Source Select
0: From XTI
Reserved
1: From BIT_CLK
Reserved
13:3
0
R
0’h
0’b
sel_pll_pre_div
RW
PLL Pre Divider
0b: ÷1
1b: ÷2
BCLK
XTI
PLL
/2
Audio SYSCLK
I2S Clock Tree
PLL & Clock Tree
Figure 16. Global Clock Control
8.15. Reg-44h: PLL M/N Code Control
Default: 0000’h
Table 24. MX44 PLL M/N Code Control
RW Default Description
RW
N[7:0] Code for Analog PLL
Name
Bits
sel_pll_n_code
15:8
00’h
00000000: Div 2
…………
00000001: Div 3
11111111: Div 257
sel_pll_m_bypass
sel_pll_k_code
7
RW
RW
0’h
0’h
Bypass PLL M
0b: No bypass
1b: Bypass
6:4
K[2:0] Code for Analog PLL
000: Div 2
…………
001: Div 3
111: Div 9
sel_pll_m_code
3:0
RW
0’h
M[3:0] Code for Analog PLL
0000: Div 2
…………
0001: Div 3
1111: Div 17
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Datasheet
8.16. Reg-5Ah: Jack Detect Control
Default: 0000’h
Table 25. MX5A Jack Detect Control
RW Default Description
RW 0’h Jack Detect Select
Name
Bits
SEL_JD_SOURCE
15:14
00: OFF
01: Reserved
10: JD1 and enable Line in Left Ch. pin share
11: JD2 and enable Line in Right Ch. pin share
Enable Jack Detect Trigger Vref
en_jd_vref
13
12
11
10
9
RW
RW
RW
RW
RW
RW
0’b
0’b
0’h
0’h
0’h
0’h
0: Disable
Selected Jack Detect Polarity Trigger Vref
0: Low trigger 1: High trigger
Enable Jack Detect Trigger HPOUT
0: Disable 1: Enable
Select Jack Detect Polarity Trigger HPOUT
0: Low trigger 1: High trigger
Enable Jack Detect Trigger SPKOUT
0: Disable 1: Enable
Select Jack Detect Polarity Trigger SPKOUT
1: Enable
polarity_jd_tri_vref
en_jd_hpout
polarity_jd_tri_hpout
en_jd_spkout
polarity_jd_tri_spkout
8
0: Low trigger
Reserved
1: High trigger
Reserved
7:4
3
R
0’b
0’h
polarity_jd_out
RW
Jack Detect Polarity
0: Normal
1: Output Invert
status_jd_internal
Reserved
2
R
R
0’h
0’b
Jack Detect Status
Read: Return status of Jack Detect Select output
Reserved
1:0
8.17. Reg-5Ch: MISC1 Control
Default: 0000’h
Table 26. MX5C MISC1 Control
Bits RW Default Description
Name
en_sp_l_dezero
15
14
13
RW
RW
RW
0’h
0’h
0’h
SPK Volume Zero Cross Detector Control
(SPK Left Volume Zero Cross Detector when Reg1C[15:14] = 01’b)
0: Disable 1: Enable
en_sp_l_softvol
en_sp_r_dezero
SPK Soft Volume Change Enable
(SPK Left Soft Volume Change Enable when Reg1C[15:14] = 01’b)
0: Disable
SPK Right Zero Cross Detector
0: Disable 1: Enable
1: Enable
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
27
Track ID: JATR-1076-21 Rev. 1.2
ALC5628
Datasheet
Name
Bits RW Default Description
en_sp_r_softvol
12
11
10
9
RW
RW
RW
RW
RW
0’h
0’h
0’h
SPK Right Soft Volume Change Enable
0: Disable 1: Enable
HP Out Left Zero Cross Detector Control
0: Disable 1: Enable
HP Out Left Soft Volume Change Control
0: Disable 1: Enable
HP Out Right Zero Cross Detector Control
0: Disable 1: Enable
HP Out Right Soft Volume Control
en_hp_l_dezero
en_hp_l_softvol
en_hp_r_dezero
en_hp_r_softvol
0’h
0’h
8
0: Disable
1: Enable
Reserved
7:4
3
R
0’h
0’b
Reserved
en_dac_zc
RW
Enable DAC Digital Volume Zero Crossing Detect
0: Disable
1: Enable
en_dac_soft_vol
Reserved
2
RW
R
0’b
0’h
Enable DAC Digital Soft Volume
0: Disable
Reserved
1: Enable
1:0
Note: When zero cross detector is enabled, change mute volume only on zero crossing or after timeout.
8.18. Reg-5Eh: MISC2 Control
Default: 0000’h
Table 27. MX5E MISC2 Control
Name
Bits
RW
Default Description
en_vref_fastb
15
RW
0’b
Enable Fast Vref (This Bit must be Disabled in Normal Use)
0: Enable fast Vref
1: Disable fast Vref
en_thermal_shutdown
14
RW
0’b
Thermal Shut Down Enable
0: Disable
1: Enable
Reserved
13:10
9
R
0’h
0’h
Reserved
en_dp2_hp
RW
Enable De-Pop Mode 2 of HP_Out
0: Disable
1: Enable
en_dp1_hp
en_smt_hp_l
en_smt_hp_r
smt_en
8
7
6
5
RW
RW
RW
RW
0’h
0’h
0’h
0’h
Enable De-Pop Mode 1 of HP_Out
0: Disable
1: Enable
Enable HP_L Mute-Unmute Depop
0: Disable
1: Enable
Enable HP_R Mute-Unmute Depop
0: Disable
1: Enable
1: Enable
Mute-Unmute Depop
0: Disable
Reserved
4
3
R
0’h
0’h
Reserved
mute_dac_l
RW
Mute Main DAC Left Input
0: On
1: Mute (-∞ dB)
mute_dac_r
Reserved
2
RW
R
0’h
0’h
Mute Main DAC Right Input
0: On
1: Mute (-∞ dB)
1:0
Reserved
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
28
Track ID: JATR-1076-21 Rev. 1.2
ALC5628
Datasheet
8.19. Reg-68h: Automatic Volume Control (AVC) Control
Default: 100B’h
Table 28. MX68 Automatic Volume Control (AVC) Control
Name
Bits RW Default Description
EN_AVC
15
14
13
RW
RW
RW
0’b
0’b
0’b
AVC Enable (Default: 00b)
0: Disable AVC
1: Enable AVC to control Digital gain
sel_avc_ref_ch
AVC Reference Channel Selection
0: Left Channel
1: Right Channel
sel_nonact_action
Gain Action of Non-active Region
0: Keep previous Gain
1: Unit Gain
Reserved
12:5
4:0
R
80’h
0B’h
Reserved
sel_monitor_window
RW
Monitor Window Control (Unit: 2^(n+1) Samples) (Default: 01011b)
00000b: 2^(1) samples
00010b: 2^(3) samples
10000b: 2^(17) samples
00001b: 2^(2) samples
………
Others: Reserved
(Maximum=10000000000000000=2^17)
8.20. Reg-6Ah: Private Register Index
Default: 0000’h
Table 29. MX6A Private Register Index
Bits RW Default Description
Name
Reserved
15:7
6:0
R
0’h
0’h
Reserved
private_reg_index
RW
Private Register Index
8.21. Reg-6Ch: Private Register Data
Default: 0000’h
Table 30. MX6C Private Register Data
Bits RW Default Description
Name
private_reg_data
15:0 RW
0’h
Private Register Data Port
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
29
Track ID: JATR-1076-21 Rev. 1.2
ALC5628
Datasheet
8.22. Private-21h: Auto Volume Control Register 1
Default: 0400’h
Table 31. PR21 Auto Volume Control Register 1
Name
Bits
15
RW
R
Default Description
0’h Reserved
0400’h The Maximum PCM Absolute Level After AVC, Thmax (=0 ~ 2^15-1)
Reserved
sel_avc_thmax
14:0
RW
8.23. Private-22h: Auto Volume Control Register 2
Default: 0390’h
Table 32. PR22 Auto Volume Control Register 2
Name
Bits
15
RW
R
Default Description
0’h Reserved
0390’h The Minimum PCM Absolute Level After AVC, Thmin (=0 ~ 2^15-1)
Reserved
sel_avc_thmin
14:0
RW
8.24. Private-23h: Auto Volume Control Register 3
Default: 0040’h
Table 33. PR23 Auto Volume Control Register 3
Name
Bits
15
RW
R
Default Description
0’h Reserved
Reserved
sel_avc_thnonact
14:0
RW
0040’h The Non-Active PCM Absolute Level AVC Will Keep Analog Unit
Gain, Thnonact (=0 ~ 2^15-1)
8.25. Private-24h: Auto Volume Control Register 4
Default: 03FF’h
Table 34. PR24 Auto Volume Control Register 4
Name
Bits
RW
Default Description
sel_avc_cntminth
15:0
RW
03FF’h CNTMAXTH1 Controls the Sensitivity to Increased Gain (unit:2^1)
This value should be less than CNTMAXTH2
(Max=11111111111111110=2^17-2)
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
30
Track ID: JATR-1076-21 Rev. 1.2
ALC5628
Datasheet
8.26. Private-25h: Auto Volume Control Register 5
Default: 0400’h
Table 35. PR25 Auto Volume Control Register 5
Name
Bits
RW
Default Description
sel_avc_cntmaxth
15:0
RW
0400’h CNTMAXTH2 Controls the Sensitivity to Decreased Gain (Unit: 2^1)
This value should be less than Monitor Window (Optimal: 1/2 Monitor
Window)
(Max=11111111111111110=2^17-2)
8.27. Private-39h: Digital Internal Register
Default: 8800’h
Table 36. PR39 Digital Internal Register
Name
Bits
RW
Default Description
sel_pad_drive
15
RW
1’h
Pad Drive Capability
0b: 5mA
1b: (5+6) 11mA
Reserved
Reserved
osc_curr
14:12
11:9
R
0’b
RW
100’b Oscillator Drive Current Control
000: 1x bias current
010: 4x
100: 16x
001: 2x
011: 8x
………..
111: 128x
Note: The oscillator startup current is set to maximum, and controlled
by osc_curr after 512 clocks. The digital clock input is enabled after
1024 clocks.
Reserved
8:0
R
0’b
Reserved
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
31
Track ID: JATR-1076-21 Rev. 1.2
ALC5628
Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 37. Absolute Maximum Ratings
Parameter
Symbol
Minimum
Typical
Maximum
Units
Power Supplies
Digital Power for Core
Digital Power for IO and PLL
Analog and HP Amplifier Power
Speaker Amplifier Power
Ambient Operating Temperature
Storage Temperature
DCVDD
DBVDD
AVDD
SPKVDD
Ta
-0.3
-0.3
-0.3
-0.3
-20
-
-
-
-
-
-
3.63
3.63
3.63
7
V
V
V
V
+85
+125
oC
oC
Ts
-40
9.1.2. Recommended Operating Conditions
Table 38. Recommended Operating Conditions
Parameter
Digital IO Buffer
Digital Core
Analog
Symbol
DBVDD
DCVDD
AVDD
Min
1.8
1.8
2.3
2.3
Typ
3.3
3.3
3.3
3.3
Max
3.6
3.6
3.6
5
Units
V
V
V
Speaker
SPKVDD*
V
Note: A 10µF Capacitor must be connected from SPKVDD to SPKGND, and should be placed as close as possible to the
SPKVDD pin of the ALC5628.
9.1.3. Static Characteristics
DBVDD= 3.3V, Tambient=25°C, with 25pF external load.
Table 39. Threshold Voltage
Parameter
Symbol
Vin
Minimum
Typical
Maximum
Units
V
Input Voltage Range
-0.30
-
-
-
-
-
-
-
DBVDD +0.30
Low Level Input Voltage
High Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Low Level Input Voltage (JD2)
High Level Input Voltage(JD2)
VIL
-
0.33*DBVDD
V
VIH
0.66*DBVDD
-
V
VOH
VOL
VIL
0.9*DBVDD
-
V
-
0.1*DBVDD
0.33*AVDD
-
V
-
V
VIH
0.66*AVDD
V
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
32
Track ID: JATR-1076-21 Rev. 1.2
ALC5628
Datasheet
9.2. Analog Performance Characteristics
• Tambient=25oC, DBVDD=DCVDD=1.8V, AVDD=3.3V, SPKVDD=5V,
1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms,
10KΩ/50pF load; Test bench Characterization BW: 10Hz~22kHz,
0dB attenuation
Standard Test Conditions
Table 40. Analog Performance Characteristics
Parameter
Minimum
Typical
Maximum
Units
Full Scale Input Voltage
LINE_IN Inputs (Gain=0dB)
-
1.0
-
Vrms
Full Scale Output Voltage
DAC Outputs
HP_OUT Outputs
SPK_OUT Outputs
-
-
-
1.0
1.0
1.5
-
-
-
Vrms
Vrms
Vrms
S/N (A Weighted)
DAC
-
-
100
95
-
-
dBFS
dBFS
Headphone Amplifier Output (RL=32Ω, PO=20mW)
THD+N
DAC
-
-
-86
-80
-50
1.5
-80
600
45
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dBFS
dBFS
dB
Headphone Amplifier Output (RL=32Ω, PO=20mW)
Power Supply Rejection (217Hz)
-
Amplifier Gain Step
-
dB
Crosstalk Between Input Channels
-
dB
-
µA
mW
mA
W
HP Amplifier Quiescent Current (RL=32Ω @ 3.3V)
HP Amplifier Output Power (RL=16Ω)
SPK Class-D Amplifier Quiescent Current (RL=8Ω @ 5V)
SPK Class-D Amplifier Output Power (RL=4Ω @ 5V, 0.1% THD+N)
SPK Class-D Amplifier Output Power (RL=8Ω @ 5V, 0.1% THD+N)
SPK Class-D Amplifier Output Power (RL=4Ω @ 5V, 1% THD+N)
SPK Class-D Amplifier Output Power (RL=8Ω @ 5V, 1% THD+N)
SPK Class-D Amplifier Output Power (RL=4Ω @ 5V, 10% THD+N)
SPK Class-D Amplifier Output Power (RL=8Ω @ 5V, 10% THD+N)
Digital Power Supply Current (Power Down Mode)
DCVDD=1.8V, DBVDD=1.8V (Include POR Circuit)
Analog Power Supply Current (DAC to Headphone Without Load)
AVDD=DCVDD=DBVDD=SPKVDD=3.3V
Analog Power Supply Current (Power Down Mode)
AVDD=3.3V
25
-
4
-
1.6
1
-
W
-
1.7
1.1
2.4
1.5
W
-
W
-
W
-
W
-
-
-
10
-
µA
8
mA
-
-
-
-
0.5
-
1
-
µA
AVDD
ms
VREF Output Voltage
VREF Rising Time at Fast Mode (C=4.7µF)
50
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
33
Track ID: JATR-1076-21 Rev. 1.2
ALC5628
Datasheet
9.3. AC Timing Characteristics
9.3.1. I2C Control Interface
Table 41. I2C Control Interface Timing
Parameter
Symbol
tw(9)
tw(10)
f
Minimum
Typical
Maximum
Units
µs
ns
Clock Pulse Duration
Clock Pulse Duration
Clock Frequency
Re-Start Setup Time
Start Hold Time
Data Setup Time
Data Hold Time
Rising Time
1.3
600
0
-
-
-
-
-
-
-
-
-
-
-
-
-
400K*
Hz
ns
tsu(6)
th(5)
tsu(7)
th(6)
tr
600
600
100
-
-
-
ns
-
ns
900
300
300
-
ns
-
ns
Falling Time
tf
-
ns
Stop Setup Time
tsu(8)
tsp
600
0
ns
Pulse Width of Spikes Suppressed
Input Filter
Note: ‘*’indicates the host must provide MCLK higher than 4MHz to the ALC5628 during I2C control interface access.
If MCLK provides 128*8KHz, the I2C clock frequency can only support 100KHz.
50
ns
Figure 17. I2C Control Interface Waveform
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
34
Track ID: JATR-1076-21 Rev. 1.2
ALC5628
Datasheet
9.3.2. I2S/PCM Interface Master Mode
Table 42. I2S Master Mode Timing
Parameter
Symbol
tLRD
Minimum
Typical
Maximum
Units
ns
LRCK Output to BCLK Delay
Data Output to BCLK Delay
Data Input Setup Time
Data Input Hold Time
-
-
-
-
-
30
30
-
tADD
-
ns
tDAS
10
10
ns
tDAH
-
ns
Figure 18. I2S Master Mode Waveform
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
35
Track ID: JATR-1076-21 Rev. 1.2
ALC5628
Datasheet
9.3.3. I2S/PCM Interface Slave Mode
Table 43. I2S Slave Mode Timing
Parameter
Symbol
tBCH
Minimum
Typical
Maximum
Units
ns
BCLK High Pulse Width
BCLK Low Pulse Width
LRCK Input Setup Time
Data Input Setup Time
Data Input Hold Time
20
20
30
10
10
-
-
-
-
-
-
-
-
-
-
tBCL
ns
tLRS
ns
tDAS
ns
tDAH
ns
Figure 19. I2S Slave Mode Waveform
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
36
Track ID: JATR-1076-21 Rev. 1.2
ALC5628
Datasheet
10. Application Circuits
Application circuits are for design reference only. System designers are suggested to visit Realtek’s web
site to download the latest application circuits. To get the best compatibility in hardware design and
software driver, Realtek should confirm modifications of application circuits.
DVDD
DBVDD
DCVDD
C1
C2
1000pF
1uF
close to IC
close to IC
AVDD
U1-1
AVDD
CA1
1uF
CA2
1000pF
LINE_IN_L
LINE_IN_R
3
4
1
24
HP_OUT_L
HP_OUT_R
SPKVDD
LINE_IN_L
LINE_IN_R
HP_OUT_L
HP_OUT_R
BCLK
LRCK
DACDAT
6
5
7
17
18
SPK_OUT
SPK_OUT_N
SPKVDD
BCLK
LRCK
DACDAT
SPK_OUT
SPK_OUT_N
CS2
CS1
10u
+
QFN24
close to IC 1000pF
16
22
Cdepop
VREF
Cdepop
VREF
C4
22p
C5
CLK_crystal1
CLK_crystal2
8
9
15
C6
1u
XTI
XTO
OSC_EN
C9
22p
C8
13
14
SCLK
SDA
0.1u
4.7u
SCLK
SDA
RGND1
0
DBVDD
RGND2
BEAD
ALC5628
DGND
AGND
POWER / GND
C18
PH3
HP_R
HP_L
1
R33
U2
1M
Crystal CLK
HP_OUT_R
HP_OUT_L
100u
2
3
4
5
C21
100
1
2
CLK_crystal2
CLK_crystal1
C19
20p
C20
20p
Crystal 24.576MHz
HPO
HP-Out
SPK_OUT
SPK_OUT
J3
LINE-IN
PH2
C12
C13
5
4
3
2
1
LI_P
1u
LINE_IN_L
SPK_OUT_N
SPK_CON
LI_N
1u
LINE_IN_R
SPK-Out
LINE_IN
Figure 20. Application Circuits
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
37
Track ID: JATR-1076-21 Rev. 1.2
ALC5628
Datasheet
11. Mechanical Dimensions
QFN-24 Package; 4x4mm Outline
Symbol
Dimension in mm
Nom
Dimension in inch
Nom
Min
0.75
0.00
-
Max
1.00
0.05
0.70
Min
0.030
0.000
-
Max
0.039
0.002
0.028
A
A1
A2
A3
b
0.85
0.034
0.02
0.001
0.65
0.026
0.20 REF
0.25
0.008 REF
0.010
0.18
2.00
0.30
0.30
2.50
0.50
0.007
0.078
0.012
0.012
0.098
0.020
D/E
D2/E2
e
4.00 BSC
2.25
0.158 BSC
0.088
0.50 BSC
0.40
0.020 BSC
0.016
L
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MO-220.
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
38
Track ID: JATR-1076-21 Rev. 1.2
ALC5628
Datasheet
12. Ordering Information
Table 44. Ordering Information
Part Number
ALC5628-GR
ALC5628-GRT
Package
Status
QFN-24 in ‘Green’ Package (Tray)
Mass Production
Mass Production
QFN-24 in ‘Green’ Package (Tape & Reel)
Note: See page 6 for package and version identification.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
I2S/PCM Audio DAC with Headphone and
Mono Class-D Speaker Amplifier
39
Track ID: JATR-1076-21 Rev. 1.2
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